2 FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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13 * then take a look at the FreeRTOS eBook *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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18 * A pdf reference manual is also available. Both are usually delivered *
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19 * to your inbox within 20 minutes to two hours when purchased between 8am *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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55 * Basic interrupt driven driver for the EMAC peripheral. This driver is not
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56 * reentrant as with uIP the buffers are only ever accessed from a single task.
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58 * The simple buffer management used within uIP allows the EMAC driver to also
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59 * be simplistic. The driver contained within the lwIP demo is more
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67 + Corrected the byte order when writing the MAC address to the MAC.
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68 + Support added for MII interfaces. Previously only RMII was supported.
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72 + The MII interface is now the default.
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73 + Modified the initialisation sequence slightly to allow auto init more
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78 + Also read the EMAC_RSR register in the EMAC ISR as a work around the
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79 the EMAC bug that can reset the RX bit in EMAC_ISR register before the
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84 + Corrected the Rx frame length mask when obtaining the length from the
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89 /* Standard includes. */
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92 /* Scheduler includes. */
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93 #include "FreeRTOS.h"
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100 /* Hardware specific includes. */
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105 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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106 to use an MII interface. */
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107 #define USE_RMII_INTERFACE 0
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109 /* The buffer addresses written into the descriptors must be aligned so the
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110 last few bits are zero. These bits have special meaning for the EMAC
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111 peripheral and cannot be used as part of the address. */
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112 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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114 /* Bit used within the address stored in the descriptor to mark the last
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115 descriptor in the array. */
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116 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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118 /* Bit used within the Tx descriptor status to indicate whether the
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119 descriptor is under the control of the EMAC or the software. */
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120 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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122 /* A short delay is used to wait for a buffer to become available, should
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123 one not be immediately available when trying to transmit a frame. */
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124 #define emacBUFFER_WAIT_DELAY ( 2 )
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125 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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127 /* Misc defines. */
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128 #define emacINTERRUPT_LEVEL ( 5 )
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129 #define emacNO_DELAY ( 0 )
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130 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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131 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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132 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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133 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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135 /* The Atmel header file only defines the TX frame length mask. */
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136 #define emacRX_LENGTH_FRAME ( 0xfff )
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138 /*-----------------------------------------------------------*/
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141 * Prototype for the EMAC interrupt asm wrapper.
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143 extern void vEMACISREntry( void );
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146 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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148 __arm void vEMACISR( void );
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151 * Initialise both the Tx and Rx descriptors used by the EMAC.
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153 static void prvSetupDescriptors(void);
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156 * Write our MAC address into the EMAC. The MAC address is set as one of the
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159 static void prvSetupMACAddress( void );
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162 * Configure the EMAC and AIC for EMAC interrupts.
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164 static void prvSetupEMACInterrupt( void );
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167 * Some initialisation functions taken from the Atmel EMAC sample code.
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169 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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170 #if USE_RMII_INTERFACE != 1
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171 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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173 static portBASE_TYPE xGetLinkSpeed( void );
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174 static portBASE_TYPE prvProbePHY( void );
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176 /*-----------------------------------------------------------*/
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178 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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179 comment above the emacADDRESS_MASK definition. */
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180 #pragma data_alignment=8
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181 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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183 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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184 above the emacADDRESS_MASK definition. */
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185 #pragma data_alignment=8
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186 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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188 /* Descriptors used to communicate between the program and the EMAC peripheral.
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189 These descriptors hold the locations and state of the Rx and Tx buffers. */
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190 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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191 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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193 /* The IP and Ethernet addresses are read from the uIP setup. */
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194 const char cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
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195 const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
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197 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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198 static xSemaphoreHandle xSemaphore = NULL;
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200 /*-----------------------------------------------------------*/
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202 xSemaphoreHandle xEMACInit( void )
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204 /* Code supplied by Atmel (modified) --------------------*/
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206 /* disable pull up on RXDV => PHY normal mode (not in test mode),
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207 PHY has internal pull down. */
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208 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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210 #if USE_RMII_INTERFACE != 1
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211 /* PHY has internal pull down : set MII mode. */
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212 AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
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215 /* clear PB18 <=> PHY powerdown. */
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216 AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
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217 AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ;
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219 /* After PHY power up, hardware reset. */
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220 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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221 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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223 /* Wait for hardware reset end. */
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224 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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230 /* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
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231 AT91F_EMAC_CfgPIO();
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233 /* Enable com between EMAC PHY.
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235 Enable management port. */
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236 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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238 /* MDC = MCK/32. */
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239 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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241 /* Wait for PHY auto init end (rather crude delay!). */
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242 vTaskDelay( emacPHY_INIT_DELAY );
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244 /* PHY configuration. */
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245 #if USE_RMII_INTERFACE != 1
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247 unsigned long ulControl;
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249 /* PHY has internal pull down : disable MII isolate. */
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250 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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251 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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252 ulControl &= ~BMCR_ISOLATE;
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253 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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257 /* Disable management port again. */
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258 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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260 #if USE_RMII_INTERFACE != 1
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261 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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262 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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264 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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266 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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269 /* End of code supplied by Atmel ------------------------*/
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271 /* Setup the buffers and descriptors. */
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272 prvSetupDescriptors();
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274 /* Load our MAC address into the EMAC. */
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275 prvSetupMACAddress();
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277 /* Try to connect. */
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278 if( prvProbePHY() )
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280 /* Enable the interrupt! */
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281 prvSetupEMACInterrupt();
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286 /*-----------------------------------------------------------*/
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288 long lEMACSend( void )
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290 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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291 portBASE_TYPE xWaitCycles = 0;
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292 long lReturn = pdPASS;
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295 /* Is a buffer available? */
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296 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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298 /* There is no room to write the Tx data to the Tx buffer. Wait a
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299 short while, then try again. */
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301 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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309 vTaskDelay( emacBUFFER_WAIT_DELAY );
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313 /* lReturn will only be pdPASS if a buffer is available. */
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314 if( lReturn == pdPASS )
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316 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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317 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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318 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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319 if( uip_len > emacTOTAL_FRAME_HEADER_SIZE )
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321 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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325 portENTER_CRITICAL();
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327 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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329 /* Fill out the necessary in the descriptor to get the data sent. */
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330 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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331 | AT91C_LAST_BUFFER
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332 | AT91C_TRANSMIT_WRAP;
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333 uxTxBufferIndex = 0;
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337 /* Fill out the necessary in the descriptor to get the data sent. */
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338 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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339 | AT91C_LAST_BUFFER;
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343 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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345 portEXIT_CRITICAL();
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350 /*-----------------------------------------------------------*/
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352 unsigned long ulEMACPoll( void )
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354 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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355 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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358 /* Skip any fragments. */
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359 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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361 /* Mark the buffer as free again. */
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362 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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364 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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366 ulNextRxBuffer = 0;
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370 /* Is there a packet ready? */
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372 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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374 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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375 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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377 if( ulSectionLength == 0 )
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379 /* The frame is longer than the buffer pointed to by this
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380 descriptor so copy the entire buffer to uIP - then move onto
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381 the next descriptor to get the rest of the frame. */
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382 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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384 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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385 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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390 /* This is the last section of the frame. Copy the section to
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392 if( ulSectionLength < UIP_BUFSIZE )
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394 /* The section length holds the length of the entire frame.
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395 ulLengthSoFar holds the length of the frame sections already
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396 copied to uIP, so the length of the final section is
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397 ulSectionLength - ulLengthSoFar; */
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398 if( ulSectionLength > ulLengthSoFar )
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400 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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404 /* Is this the last buffer for the frame? If not why? */
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405 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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408 /* Mark the buffer as free again. */
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409 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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411 /* Increment to the next buffer, wrapping if necessary. */
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413 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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415 ulNextRxBuffer = 0;
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419 /* If we obtained data but for some reason did not find the end of the
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420 frame then discard the data as it must contain an error. */
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423 ulSectionLength = 0;
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426 return ulSectionLength;
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428 /*-----------------------------------------------------------*/
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430 static void prvSetupDescriptors(void)
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432 unsigned portBASE_TYPE xIndex;
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433 unsigned long ulAddress;
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435 /* Initialise xRxDescriptors descriptor. */
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436 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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438 /* Calculate the address of the nth buffer within the array. */
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439 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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441 /* Write the buffer address into the descriptor. The DMA will place
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442 the data at this address when this descriptor is being used. Mask off
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443 the bottom bits of the address as these have special meaning. */
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444 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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447 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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448 to the first buffer. */
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449 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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451 /* Initialise xTxDescriptors. */
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452 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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454 /* Calculate the address of the nth buffer within the array. */
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455 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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457 /* Write the buffer address into the descriptor. The DMA will read
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458 data from here when the descriptor is being used. */
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459 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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460 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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463 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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464 to the first buffer. */
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465 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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467 /* Tell the EMAC where to find the descriptors. */
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468 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
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469 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
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471 /* Clear all the bits in the receive status register. */
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472 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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474 /* Enable the copy of data into the buffers, ignore broadcasts,
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475 and don't copy FCS. */
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476 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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478 /* Enable Rx and Tx, plus the stats register. */
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479 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
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481 /*-----------------------------------------------------------*/
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483 static void prvSetupMACAddress( void )
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485 /* Must be written SA1L then SA1H. */
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486 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
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487 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
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488 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
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491 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
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494 /*-----------------------------------------------------------*/
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496 static void prvSetupEMACInterrupt( void )
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498 /* Create the semaphore used to trigger the EMAC task. */
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499 vSemaphoreCreateBinary( xSemaphore );
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502 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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503 first interrupt occurs. */
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504 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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505 portENTER_CRITICAL();
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507 /* We want to interrupt on Rx events. */
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508 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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510 /* Enable the interrupts in the AIC. */
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511 AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
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512 AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
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514 portEXIT_CRITICAL();
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517 /*-----------------------------------------------------------*/
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519 __arm void vEMACISR( void )
\r
521 volatile unsigned long ulIntStatus, ulRxStatus;
\r
522 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
524 ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
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525 ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
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527 if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
\r
529 /* A frame has been received, signal the uIP task so it can process
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530 the Rx descriptors. */
\r
531 xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
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532 AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
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535 /* If a task was woken by either a character being received or a character
\r
536 being transmitted then we may need to switch to another task. */
\r
537 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
\r
539 /* Clear the interrupt. */
\r
540 AT91C_BASE_AIC->AIC_EOICR = 0;
\r
542 /*-----------------------------------------------------------*/
\r
547 * The following functions are initialisation functions taken from the Atmel
\r
548 * EMAC sample code.
\r
551 static portBASE_TYPE prvProbePHY( void )
\r
553 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
554 portBASE_TYPE xReturn = pdPASS;
\r
556 /* Code supplied by Atmel (reformatted) -----------------*/
\r
558 /* Enable management port */
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559 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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560 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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562 /* Read the PHY ID. */
\r
563 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
564 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
569 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
570 0001 stands for Rev. A, etc.
\r
572 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
574 /* Did not expect this ID. */
\r
579 ulStatus = xGetLinkSpeed();
\r
581 if( ulStatus != pdPASS )
\r
587 /* Disable management port */
\r
588 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
590 /* End of code supplied by Atmel ------------------------*/
\r
594 /*-----------------------------------------------------------*/
\r
596 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
598 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
600 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
601 | (2 << 16) | (2 << 28)
\r
602 | ((ucPHYAddress & 0x1f) << 23)
\r
603 | (ucAddress << 18);
\r
605 /* Wait until IDLE bit in Network Status register is cleared. */
\r
606 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
611 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
613 /* End of code supplied by Atmel ------------------------*/
\r
615 /*-----------------------------------------------------------*/
\r
617 #if USE_RMII_INTERFACE != 1
\r
618 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
620 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
622 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
623 | (2 << 16) | (1 << 28)
\r
624 | ((ucPHYAddress & 0x1f) << 23)
\r
625 | (ucAddress << 18))
\r
626 | (ulValue & 0xffff);
\r
628 /* Wait until IDLE bit in Network Status register is cleared */
\r
629 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
634 /* End of code supplied by Atmel ------------------------*/
\r
637 /*-----------------------------------------------------------*/
\r
639 static portBASE_TYPE xGetLinkSpeed( void )
\r
641 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
643 /* Code supplied by Atmel (reformatted) -----------------*/
\r
645 /* Link status is latched, so read twice to get current value */
\r
646 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
647 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
649 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
655 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
656 if (ulBMCR & BMCR_ANENABLE)
\r
658 /* AutoNegotiation is enabled. */
\r
659 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
661 /* Auto-negotiation in progress. */
\r
665 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
666 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
668 ulSpeed = SPEED_100;
\r
672 ulSpeed = SPEED_10;
\r
675 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
677 ulDuplex = DUPLEX_FULL;
\r
681 ulDuplex = DUPLEX_HALF;
\r
686 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
687 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
690 /* Update the MAC */
\r
691 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
692 if( ulSpeed == SPEED_100 )
\r
694 if( ulDuplex == DUPLEX_FULL )
\r
696 /* 100 Full Duplex */
\r
697 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
701 /* 100 Half Duplex */
\r
702 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
707 if (ulDuplex == DUPLEX_FULL)
\r
709 /* 10 Full Duplex */
\r
710 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
714 /* 10 Half Duplex */
\r
715 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
719 /* End of code supplied by Atmel ------------------------*/
\r