1 //*----------------------------------------------------------------------------
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2 //* ATMEL Microcontroller Software Support - ROUSSET -
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3 //*----------------------------------------------------------------------------
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4 //* The software is delivered "AS IS" without warranty or condition of any
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5 //* kind, either express, implied or statutory. This includes without
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6 //* limitation any warranty or condition with respect to merchantability or
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7 //* fitness for any particular purpose, or against the infringements of
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8 //* intellectual property rights of others.
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9 //*----------------------------------------------------------------------------
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10 //* File Name : Cstartup_SAM7.c
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11 //* Object : Low level initializations written in C for IAR
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13 //* 1.0 08/Sep/04 JPP : Creation
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14 //* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
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15 //*----------------------------------------------------------------------------
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18 // Include the board file description
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23 // The following functions must be write in ARM mode this function called directly
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24 // by exception vector
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25 extern void AT91F_Spurious_handler(void);
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26 extern void AT91F_Default_IRQ_handler(void);
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27 extern void AT91F_Default_FIQ_handler(void);
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30 //*----------------------------------------------------------------------------
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31 //* \fn AT91F_LowLevelInit
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32 //* \brief This function performs very low level HW initialization
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33 //* this function can be use a Stack, depending the compilation
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34 //* optimization mode
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35 //*----------------------------------------------------------------------------
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36 void AT91F_LowLevelInit( void);
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37 void AT91F_LowLevelInit( void ) @ "ICODE"
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40 AT91PS_PMC pPMC = AT91C_BASE_PMC;
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42 //* Set Flash Waite sate
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43 // Single Cycle Access at Up to 30 MHz, or 40
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44 // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
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45 AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
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47 //* Watchdog Disable
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48 AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
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51 // If we are running off a j-link then the PLL will have already been setup.
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52 if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) )
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54 //* Set MCK at 47 923 200
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55 // 1 Enabling the Main Oscillator:
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56 // SCK = 1/32768 = 30.51 uSeconde
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57 // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
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58 pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
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59 // Wait the startup time
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60 while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
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61 // 2 Checking the Main Oscillator Frequency (Optional)
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62 // 3 Setting PLL and divider:
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63 // - div by 5 Fin = 3,6864 =(18,432 / 5)
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64 // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
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65 // for 96 MHz the erroe is 0.16%
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66 //eld out NOT USED = 0 Fi
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67 pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
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68 (AT91C_CKGR_PLLCOUNT & (28<<8)) |
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69 (AT91C_CKGR_MUL & (25<<16)));
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71 // Wait the startup time
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72 while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
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73 // 4. Selection of Master Clock and Processor Clock
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74 // select the PLL clock divided by 2
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76 pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
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77 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
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80 pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
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81 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
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84 // Set up the default interrupts handler vectors
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85 AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
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86 for (i=1;i < 31; i++)
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88 AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
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90 AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
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