1 /*****************************************************************************
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2 * Copyright (c) 2001, 2002 Rowley Associates Limited. *
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4 * This file may be distributed under the terms of the License Agreement *
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5 * provided with this software. *
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7 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
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8 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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9 *****************************************************************************/
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11 /*****************************************************************************
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12 * Preprocessor Definitions
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13 * ------------------------
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15 * VECTORED_IRQ_INTERRUPTS
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17 * Enable vectored IRQ interrupts. If defined, the PC register will be loaded
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18 * with the contents of the VICVectAddr register on an IRQ exception.
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22 * If defined, connect PLL as processor clock source. If undefined, the
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23 * oscillator clock will be used.
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27 * Override the default PLL configuration (multiplier = 5, divider = 2)
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28 * by defining PLLCFG_VAL.
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32 * If defined then the memory accelerator module (MAM) will be enabled.
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34 * MAMCR_VAL & MAMTIM_VAL
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36 * Override the default MAM configuration (fully enabled, 3 fetch cycles)
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37 * by defining MAMCR_VAL and MAMTIM_VAL.
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41 * If defined then this value will be used to configure the VPB divider.
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45 * If defined, enable copying and re-mapping of interrupt vectors from User
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46 * FLASH to SRAM. If undefined, interrupt vectors will be mapped in User
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49 *****************************************************************************/
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52 #define PLLCFG_VAL 0x24
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60 #define MAMTIM_VAL 3
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63 #define MAMCR_OFFS 0x000
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64 #define MAMTIM_OFFS 0x004
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66 #define PLLCON_OFFS 0x080
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67 #define PLLCFG_OFFS 0x084
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68 #define PLLSTAT_OFFS 0x088
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69 #define PLLFEED_OFFS 0x08C
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71 #define VPBDIV_OFFS 0x100
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73 .section .vectors, "ax"
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77 /*****************************************************************************
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78 * Exception Vectors *
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79 *****************************************************************************/
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81 ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
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82 ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
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83 ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
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84 ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
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85 ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
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86 #ifdef VECTORED_IRQ_INTERRUPTS
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87 .word 0xB9205F84 /* boot loader checksum */
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88 ldr pc, [pc, #-0xFF0] /* irq handler */
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90 .word 0xB8A06F60 /* boot loader checksum */
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91 ldr pc, [pc, #irq_handler_address - . - 8] /* irq handler */
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93 ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */
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95 reset_handler_address:
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97 undef_handler_address:
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99 swi_handler_address:
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101 pabort_handler_address:
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102 .word pabort_handler
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103 dabort_handler_address:
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104 .word dabort_handler
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105 irq_handler_address:
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107 fiq_handler_address:
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110 .section .init, "ax"
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114 /******************************************************************************
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116 * Default exception handlers *
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118 ******************************************************************************/
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121 #if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL)
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122 ldr r0, =0xE01FC000
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124 #if defined(USE_PLL)
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125 /* Configure PLL Multiplier/Divider */
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126 ldr r1, =PLLCFG_VAL
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127 str r1, [r0, #PLLCFG_OFFS]
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130 str r1, [r0, #PLLCON_OFFS]
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132 str r1, [r0, #PLLFEED_OFFS]
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134 str r1, [r0, #PLLFEED_OFFS]
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135 /* Wait for PLL to lock */
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137 ldr r1, [r0, #PLLSTAT_OFFS]
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140 /* PLL Locked, connect PLL as clock source */
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142 str r1, [r0, #PLLCON_OFFS]
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144 str r1, [r0, #PLLFEED_OFFS]
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146 str r1, [r0, #PLLFEED_OFFS]
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149 #if defined(USE_MAM)
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151 str r1, [r0, #MAMCR_OFFS]
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152 ldr r1, =MAMTIM_VAL
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153 str r1, [r0, #MAMTIM_OFFS]
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155 str r1, [r0, #MAMCR_OFFS]
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158 #if defined(VPBDIV_VAL)
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159 ldr r1, =VPBDIV_VAL
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160 str r1, [r0, #VPBDIV_OFFS]
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163 #if defined(SRAM_EXCEPTIONS)
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164 /* Copy exception vectors into SRAM */
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165 mov r8, #0x40000000
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172 /* Re-map interrupt vectors from SRAM */
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174 mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */
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176 #endif /* SRAM_EXCEPTIONS */
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180 #ifdef SRAM_EXCEPTIONS
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185 /******************************************************************************
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187 * Default exception handlers *
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188 * These are declared weak symbols so they can be redefined in user code. *
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190 ******************************************************************************/
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210 .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler
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