1 // ----------------------------------------------------------------------------
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2 // ATMEL Microcontroller Software Support - ROUSSET -
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3 // ----------------------------------------------------------------------------
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4 // The software is delivered "AS IS" without warranty or condition of any
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5 // kind, either express, implied or statutory. This includes without
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6 // limitation any warranty or condition with respect to merchantability or
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7 // fitness for any particular purpose, or against the infringements of
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8 // intellectual property rights of others.
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9 // ----------------------------------------------------------------------------
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10 // File Name : AT91R40008.h
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11 // Object : AT91R40008 definitions
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12 // Generated : AT91 SW Application Group 02/19/2003 (11:13:31)
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14 // CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//
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15 // CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
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16 // CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
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17 // CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//
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18 // CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
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19 // CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
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20 // CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
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21 // CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
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22 // CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//
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23 // CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//
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24 // ----------------------------------------------------------------------------
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26 #ifndef AT91R40008_H
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27 #define AT91R40008_H
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29 /* AT91 Register type */
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30 typedef volatile unsigned int AT91_REG; // Hardware register definition
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31 typedef volatile unsigned int at91_reg;
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33 // *****************************************************************************
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34 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
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35 // *****************************************************************************
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36 typedef struct _AT91S_AIC {
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37 AT91_REG AIC_SMR[32]; // Source Mode egister
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38 AT91_REG AIC_SVR[32]; // Source Vector egister
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39 AT91_REG AIC_IVR; // IRQ Vector Register
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40 AT91_REG AIC_FVR; // FIQ Vector Register
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41 AT91_REG AIC_ISR; // Interrupt Status Register
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42 AT91_REG AIC_IPR; // Interrupt Pending Register
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43 AT91_REG AIC_IMR; // Interrupt Mask Register
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44 AT91_REG AIC_CISR; // Core Interrupt Status Register
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45 AT91_REG Reserved0[2]; //
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46 AT91_REG AIC_IECR; // Interrupt Enable Command Register
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47 AT91_REG AIC_IDCR; // Interrupt Disable Command egister
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48 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
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49 AT91_REG AIC_ISCR; // Interrupt Set Command Register
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50 AT91_REG AIC_EOICR; // End of Interrupt Command Register
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51 AT91_REG AIC_SPU; // Spurious Vector Register
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52 } AT91S_AIC, *AT91PS_AIC;
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54 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
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55 #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
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56 #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
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57 #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
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58 #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
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59 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
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60 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
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61 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
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62 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
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63 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
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64 #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
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65 #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
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67 // *****************************************************************************
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68 // SOFTWARE API DEFINITION FOR Watchdog Timer Interface
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69 // *****************************************************************************
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70 typedef struct _AT91S_WD {
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71 AT91_REG WD_OMR; // Overflow Mode Register
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72 AT91_REG WD_CMR; // Clock Mode Register
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73 AT91_REG WD_CR; // Control Register
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74 AT91_REG WD_SR; // Status Register
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75 } AT91S_WD, *AT91PS_WD;
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77 // -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
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78 #define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable
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79 #define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable
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80 #define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable
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81 #define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable
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82 #define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable
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83 // -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
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84 #define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection
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85 #define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32
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86 #define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128
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87 #define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
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88 #define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
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89 #define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value
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90 #define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key
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91 // -------- WD_CR : (WD Offset: 0x8) Control Register --------
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92 #define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key
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93 // -------- WD_SR : (WD Offset: 0xc) Status Register --------
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94 #define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow
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96 // *****************************************************************************
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97 // SOFTWARE API DEFINITION FOR Power Saving Controler
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98 // *****************************************************************************
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99 typedef struct _AT91S_PS {
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100 AT91_REG PS_CR; // Control Register
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101 AT91_REG PS_PCER; // Peripheral Clock Enable Register
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102 AT91_REG PS_PCDR; // Peripheral Clock Disable Register
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103 AT91_REG PS_PCSR; // Peripheral Clock Status Register
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104 } AT91S_PS, *AT91PS_PS;
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106 // -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register --------
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107 #define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock
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108 #define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock
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109 #define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock
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110 #define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock
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111 #define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock
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112 #define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock
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113 // -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register --------
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114 // -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register --------
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116 // *****************************************************************************
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117 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
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118 // *****************************************************************************
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119 typedef struct _AT91S_PIO {
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120 AT91_REG PIO_PER; // PIO Enable Register
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121 AT91_REG PIO_PDR; // PIO Disable Register
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122 AT91_REG PIO_PSR; // PIO Status Register
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123 AT91_REG Reserved0[1]; //
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124 AT91_REG PIO_OER; // Output Enable Register
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125 AT91_REG PIO_ODR; // Output Disable Registerr
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126 AT91_REG PIO_OSR; // Output Status Register
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127 AT91_REG Reserved1[1]; //
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128 AT91_REG PIO_IFER; // Input Filter Enable Register
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129 AT91_REG PIO_IFDR; // Input Filter Disable Register
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130 AT91_REG PIO_IFSR; // Input Filter Status Register
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131 AT91_REG Reserved2[1]; //
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132 AT91_REG PIO_SODR; // Set Output Data Register
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133 AT91_REG PIO_CODR; // Clear Output Data Register
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134 AT91_REG PIO_ODSR; // Output Data Status Register
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135 AT91_REG PIO_PDSR; // Pin Data Status Register
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136 AT91_REG PIO_IER; // Interrupt Enable Register
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137 AT91_REG PIO_IDR; // Interrupt Disable Register
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138 AT91_REG PIO_IMR; // Interrupt Mask Register
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139 AT91_REG PIO_ISR; // Interrupt Status Register
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140 AT91_REG PIO_MDER; // Multi-driver Enable Register
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141 AT91_REG PIO_MDDR; // Multi-driver Disable Register
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142 AT91_REG PIO_MDSR; // Multi-driver Status Register
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143 } AT91S_PIO, *AT91PS_PIO;
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146 // *****************************************************************************
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147 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
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148 // *****************************************************************************
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149 typedef struct _AT91S_TC {
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150 AT91_REG TC_CCR; // Channel Control Register
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151 AT91_REG TC_CMR; // Channel Mode Register
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152 AT91_REG Reserved0[2]; //
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153 AT91_REG TC_CV; // Counter Value
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154 AT91_REG TC_RA; // Register A
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155 AT91_REG TC_RB; // Register B
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156 AT91_REG TC_RC; // Register C
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157 AT91_REG TC_SR; // Status Register
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158 AT91_REG TC_IER; // Interrupt Enable Register
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159 AT91_REG TC_IDR; // Interrupt Disable Register
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160 AT91_REG TC_IMR; // Interrupt Mask Register
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161 } AT91S_TC, *AT91PS_TC;
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163 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
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164 #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
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165 #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
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166 #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
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167 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
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168 #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
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169 #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
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170 #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
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171 #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
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172 #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
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173 #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
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174 #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
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175 #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
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176 #define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
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177 #define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
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178 #define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
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179 #define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
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180 #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
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181 #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
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182 #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
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183 #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
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184 #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
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185 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
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186 #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
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187 #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
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188 #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
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189 #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
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190 #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
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191 #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
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192 #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
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193 #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
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194 #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
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195 #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
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196 #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
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197 #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
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198 #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
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199 #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
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200 #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
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201 #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
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202 #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
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203 #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
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204 #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
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205 #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
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206 #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
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207 #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
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208 #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
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209 #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
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210 #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
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211 #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
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212 #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
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213 #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
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214 #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
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215 #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
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216 #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
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217 #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
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218 #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
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219 #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
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220 #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
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221 #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
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222 #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
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223 #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
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224 #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
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225 #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
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226 #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
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227 #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
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228 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
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229 #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
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230 #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
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231 #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
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232 #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
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233 #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
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234 #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
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235 #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
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236 #define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
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237 #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
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238 #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
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239 #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
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240 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
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241 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
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242 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
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244 // *****************************************************************************
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245 // SOFTWARE API DEFINITION FOR Timer Counter Interface
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246 // *****************************************************************************
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247 typedef struct _AT91S_TCB {
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248 AT91S_TC TCB_TC0; // TC Channel 0
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249 AT91_REG Reserved0[4]; //
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250 AT91S_TC TCB_TC1; // TC Channel 1
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251 AT91_REG Reserved1[4]; //
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252 AT91S_TC TCB_TC2; // TC Channel 2
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253 AT91_REG Reserved2[4]; //
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254 AT91_REG TCB_BCR; // TC Block Control Register
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255 AT91_REG TCB_BMR; // TC Block Mode Register
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256 } AT91S_TCB, *AT91PS_TCB;
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258 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
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259 #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
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260 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
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261 #define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
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262 #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
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263 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
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264 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
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265 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
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266 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
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267 #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
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268 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
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269 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
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270 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
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271 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
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272 #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
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273 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
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274 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
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275 #define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
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277 // *****************************************************************************
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278 // SOFTWARE API DEFINITION FOR Peripheral Data Controller
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279 // *****************************************************************************
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280 typedef struct _AT91S_PDC {
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281 AT91_REG PDC_RPR; // Receive Pointer Register
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282 AT91_REG PDC_RCR; // Receive Counter Register
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283 AT91_REG PDC_TPR; // Transmit Pointer Register
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284 AT91_REG PDC_TCR; // Transmit Counter Register
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285 } AT91S_PDC, *AT91PS_PDC;
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288 // *****************************************************************************
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289 // SOFTWARE API DEFINITION FOR Usart
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290 // *****************************************************************************
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291 typedef struct _AT91S_USART {
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292 AT91_REG US_CR; // Control Register
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293 AT91_REG US_MR; // Mode Register
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294 AT91_REG US_IER; // Interrupt Enable Register
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295 AT91_REG US_IDR; // Interrupt Disable Register
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296 AT91_REG US_IMR; // Interrupt Mask Register
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297 AT91_REG US_CSR; // Channel Status Register
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298 AT91_REG US_RHR; // Receiver Holding Register
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299 AT91_REG US_THR; // Transmitter Holding Register
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300 AT91_REG US_BRGR; // Baud Rate Generator Register
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301 AT91_REG US_RTOR; // Receiver Time-out Register
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302 AT91_REG US_TTGR; // Transmitter Time-guard Register
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303 AT91_REG Reserved0[1]; //
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304 AT91_REG US_RPR; // Receive Pointer Register
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305 AT91_REG US_RCR; // Receive Counter Register
\r
306 AT91_REG US_TPR; // Transmit Pointer Register
\r
307 AT91_REG US_TCR; // Transmit Counter Register
\r
308 } AT91S_USART, *AT91PS_USART;
\r
310 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
\r
311 #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver
\r
312 #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter
\r
313 #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable
\r
314 #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable
\r
315 #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable
\r
316 #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable
\r
317 #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
\r
318 #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
\r
319 #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
\r
320 #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
\r
321 #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
\r
322 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
\r
323 #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
\r
324 #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
\r
325 #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
\r
326 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
\r
327 #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
\r
328 #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
\r
329 #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
\r
330 #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
\r
331 #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
\r
332 #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
\r
333 #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
\r
334 #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type
\r
335 #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity
\r
336 #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity
\r
337 #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space)
\r
338 #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark)
\r
339 #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity
\r
340 #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode
\r
341 #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
\r
342 #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
\r
343 #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
\r
344 #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
\r
345 #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode
\r
346 #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
\r
347 #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
\r
348 #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
\r
349 #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
\r
350 #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
\r
351 #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
\r
352 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
\r
353 #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt
\r
354 #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt
\r
355 #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
\r
356 #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt
\r
357 #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt
\r
358 #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt
\r
359 #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt
\r
360 #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt
\r
361 #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
\r
362 #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt
\r
363 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
\r
364 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
\r
365 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
\r
367 // *****************************************************************************
\r
368 // SOFTWARE API DEFINITION FOR Special Function Interface
\r
369 // *****************************************************************************
\r
370 typedef struct _AT91S_SF {
\r
371 AT91_REG SF_CIDR; // Chip ID Register
\r
372 AT91_REG SF_EXID; // Chip ID Extension Register
\r
373 AT91_REG SF_RSR; // Reset Status Register
\r
374 AT91_REG SF_MMR; // Memory Mode Register
\r
375 AT91_REG Reserved0[2]; //
\r
376 AT91_REG SF_PMR; // Protect Mode Register
\r
377 } AT91S_SF, *AT91PS_SF;
\r
379 // -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
\r
380 #define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip
\r
381 #define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0
\r
382 #define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1
\r
383 #define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0
\r
384 #define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size
\r
385 #define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None
\r
386 #define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes
\r
387 #define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes
\r
388 #define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes
\r
389 #define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes
\r
390 #define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
\r
391 #define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None
\r
392 #define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
\r
393 #define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None
\r
394 #define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
\r
395 #define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
\r
396 #define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
\r
397 #define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
\r
398 #define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
\r
399 #define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
\r
400 #define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
\r
401 #define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
\r
402 #define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
\r
403 #define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
\r
404 #define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series
\r
405 #define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag
\r
406 // -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
\r
407 #define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset
\r
408 #define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog
\r
409 #define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin
\r
410 // -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
\r
411 #define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection
\r
412 // -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
\r
413 #define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable
\r
414 #define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
\r
416 // *****************************************************************************
\r
417 // SOFTWARE API DEFINITION FOR External Bus Interface
\r
418 // *****************************************************************************
\r
419 typedef struct _AT91S_EBI {
\r
420 AT91_REG EBI_CSR[8]; // Chip-select Register
\r
421 AT91_REG EBI_RCR; // Remap Control Register
\r
422 AT91_REG EBI_MCR; // Memory Control Register
\r
423 } AT91S_EBI, *AT91PS_EBI;
\r
425 // -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
\r
426 #define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width
\r
427 #define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width
\r
428 #define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width
\r
429 #define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states
\r
430 #define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state
\r
431 #define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state
\r
432 #define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state
\r
433 #define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state
\r
434 #define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state
\r
435 #define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state
\r
436 #define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state
\r
437 #define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state
\r
438 #define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable
\r
439 #define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size
\r
440 #define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte
\r
441 #define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte
\r
442 #define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte
\r
443 #define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte
\r
444 #define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time
\r
445 #define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF
\r
446 #define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF
\r
447 #define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF
\r
448 #define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF
\r
449 #define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF
\r
450 #define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF
\r
451 #define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF
\r
452 #define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF
\r
453 #define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
\r
454 #define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
\r
455 #define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address
\r
456 // -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
\r
457 #define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
\r
458 // -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
\r
459 #define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable
\r
460 #define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
\r
461 #define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
\r
462 #define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
\r
463 #define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
\r
464 #define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
\r
465 #define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI)
\r
467 // *****************************************************************************
\r
468 // REGISTER ADDRESS DEFINITION FOR AT91R40008
\r
469 // *****************************************************************************
\r
470 // ========== Register definition for AIC peripheral ==========
\r
471 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
\r
472 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
\r
473 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
\r
474 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister
\r
475 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister
\r
476 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
\r
477 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
\r
478 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
\r
479 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
\r
480 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
\r
481 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
\r
482 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
\r
483 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
\r
484 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister
\r
485 // ========== Register definition for WD peripheral ==========
\r
486 #define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register
\r
487 #define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register
\r
488 #define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register
\r
489 #define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register
\r
490 // ========== Register definition for PS peripheral ==========
\r
491 #define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register
\r
492 #define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register
\r
493 #define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register
\r
494 #define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register
\r
495 // ========== Register definition for PIO peripheral ==========
\r
496 #define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register
\r
497 #define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register
\r
498 #define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register
\r
499 #define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register
\r
500 #define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register
\r
501 #define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register
\r
502 #define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register
\r
503 #define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register
\r
504 #define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register
\r
505 #define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register
\r
506 #define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register
\r
507 #define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register
\r
508 #define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register
\r
509 #define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register
\r
510 #define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register
\r
511 #define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register
\r
512 #define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register
\r
513 #define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register
\r
514 #define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register
\r
515 #define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr
\r
516 // ========== Register definition for TC2 peripheral ==========
\r
517 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register
\r
518 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register
\r
519 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B
\r
520 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value
\r
521 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register
\r
522 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register
\r
523 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register
\r
524 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C
\r
525 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A
\r
526 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register
\r
527 // ========== Register definition for TC1 peripheral ==========
\r
528 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register
\r
529 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register
\r
530 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B
\r
531 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value
\r
532 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register
\r
533 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register
\r
534 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register
\r
535 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C
\r
536 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A
\r
537 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register
\r
538 // ========== Register definition for TC0 peripheral ==========
\r
539 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register
\r
540 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register
\r
541 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B
\r
542 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value
\r
543 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register
\r
544 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register
\r
545 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register
\r
546 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C
\r
547 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A
\r
548 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register
\r
549 // ========== Register definition for TCB0 peripheral ==========
\r
550 #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register
\r
551 #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register
\r
552 // ========== Register definition for PDC_US1 peripheral ==========
\r
553 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register
\r
554 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register
\r
555 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register
\r
556 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register
\r
557 // ========== Register definition for US1 peripheral ==========
\r
558 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register
\r
559 #define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register
\r
560 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register
\r
561 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register
\r
562 #define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register
\r
563 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register
\r
564 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register
\r
565 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register
\r
566 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register
\r
567 #define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register
\r
568 #define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register
\r
569 // ========== Register definition for PDC_US0 peripheral ==========
\r
570 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register
\r
571 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register
\r
572 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register
\r
573 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register
\r
574 // ========== Register definition for US0 peripheral ==========
\r
575 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register
\r
576 #define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register
\r
577 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register
\r
578 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register
\r
579 #define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register
\r
580 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register
\r
581 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register
\r
582 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register
\r
583 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register
\r
584 #define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register
\r
585 #define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register
\r
586 // ========== Register definition for SF peripheral ==========
\r
587 #define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register
\r
588 #define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register
\r
589 #define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register
\r
590 #define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register
\r
591 #define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register
\r
592 // ========== Register definition for EBI peripheral ==========
\r
593 #define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register
\r
594 #define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register
\r
595 #define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register
\r
597 // *****************************************************************************
\r
598 // PIO DEFINITIONS FOR AT91R40008
\r
599 // *****************************************************************************
\r
600 #define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0
\r
601 #define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal
\r
602 #define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1
\r
603 #define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A
\r
604 #define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10
\r
605 #define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1
\r
606 #define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11
\r
607 #define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2
\r
608 #define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12
\r
609 #define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt
\r
610 #define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13
\r
611 #define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock
\r
612 #define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14
\r
613 #define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data
\r
614 #define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15
\r
615 #define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data
\r
616 #define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16
\r
617 #define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17
\r
618 #define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18
\r
619 #define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19
\r
620 #define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2
\r
621 #define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B
\r
622 #define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20
\r
623 #define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock
\r
624 #define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21
\r
625 #define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data
\r
626 #define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode
\r
627 #define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22
\r
628 #define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data
\r
629 #define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23
\r
630 #define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24
\r
631 #define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select
\r
632 #define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25
\r
633 #define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out
\r
634 #define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26
\r
635 #define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2
\r
636 #define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27
\r
637 #define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3
\r
638 #define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28
\r
639 #define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20
\r
640 #define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7
\r
641 #define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29
\r
642 #define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21
\r
643 #define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6
\r
644 #define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3
\r
645 #define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal
\r
646 #define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30
\r
647 #define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22
\r
648 #define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5
\r
649 #define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31
\r
650 #define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23
\r
651 #define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4
\r
652 #define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4
\r
653 #define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A
\r
654 #define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5
\r
655 #define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B
\r
656 #define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6
\r
657 #define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal
\r
658 #define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7
\r
659 #define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A
\r
660 #define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8
\r
661 #define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B
\r
662 #define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9
\r
663 #define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0
\r
665 // *****************************************************************************
\r
666 // PERIPHERAL ID DEFINITIONS FOR AT91R40008
\r
667 // *****************************************************************************
\r
668 #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
\r
669 #define AT91C_ID_SYS ((unsigned int) 1) // SWI
\r
670 #define AT91C_ID_US0 ((unsigned int) 2) // USART 0
\r
671 #define AT91C_ID_US1 ((unsigned int) 3) // USART 1
\r
672 #define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0
\r
673 #define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1
\r
674 #define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2
\r
675 #define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer
\r
676 #define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller
\r
677 #define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
\r
678 #define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
\r
679 #define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)
\r
681 // *****************************************************************************
\r
682 // BASE ADDRESS DEFINITIONS FOR AT91R40008
\r
683 // *****************************************************************************
\r
684 #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
\r
685 #define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address
\r
686 #define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address
\r
687 #define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address
\r
688 #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address
\r
689 #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address
\r
690 #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address
\r
691 #define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address
\r
692 #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address
\r
693 #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address
\r
694 #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address
\r
695 #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address
\r
696 #define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address
\r
697 #define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address
\r
699 // *****************************************************************************
\r
700 // MEMORY MAPPING DEFINITIONS FOR AT91R40008
\r
701 // *****************************************************************************
\r
702 #define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address
\r
703 #define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
\r
704 #define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address
\r
705 #define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)
\r
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