2 FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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67 /* Scheduler includes. */
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68 #include "FreeRTOS.h"
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72 /* Demo app includes. */
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73 #include "USBSample.h"
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75 #define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
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77 #define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \
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79 /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \
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80 /* STALLSENT and RX_DATA_BK1 to 1 so the */ \
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81 /* write has no effect. */ \
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82 ( * ( ( unsigned long * ) pulValueNow ) ) |= ( unsigned long ) 0x4f; \
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84 /* Clear the FORCE_STALL and TXPKTRDY bits */ \
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85 /* so the write has no effect. */ \
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86 ( * ( ( unsigned long * ) pulValueNow ) ) &= ( unsigned long ) 0xffffffcf; \
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88 /* Clear whichever bit we want clear. */ \
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89 ( * ( ( unsigned long * ) pulValueNow ) ) &= ( ~ulBit ); \
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93 /*-----------------------------------------------------------*/
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99 void vUSB_ISR_Wrapper( void ) __attribute__((naked));
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102 * Actual ISR handler. This must be separate from the entry point as the stack
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105 void vUSB_ISR_Handler( void ) __attribute__((noinline));
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107 /*-----------------------------------------------------------*/
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109 /* Array in which the USB interrupt status is passed between the ISR and task. */
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110 static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
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112 /* Queue used to pass messages between the ISR and the task. */
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113 extern xQueueHandle xUSBInterruptQueue;
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115 /*-----------------------------------------------------------*/
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117 void vUSB_ISR_Handler( void )
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119 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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120 static volatile unsigned long ulNextMessage = 0;
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121 xISRStatus *pxMessage;
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122 unsigned long ulTemp, ulRxBytes;
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124 /* To reduce the amount of time spent in this interrupt it would be
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125 possible to defer the majority of this processing to an 'interrupt task',
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126 that is a task that runs at a higher priority than any of the application
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129 /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must*
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130 be all 1's, as in 0x01, 0x03, 0x07, etc. */
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131 pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
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134 /* Take a snapshot of the current USB state for processing at the task
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136 pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
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137 pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
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139 /* Clear the interrupts from the ICR register. The bus end interrupt is
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140 cleared separately as it does not appear in the mask register. */
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141 AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
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143 /* If there are bytes in the FIFO then we have to retrieve them here.
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144 Ideally this would be done at the task level. However we need to clear the
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145 RXSETUP interrupt before leaving the ISR, and this may cause the data in
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146 the FIFO to be overwritten. Also the DIR bit has to be changed before the
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147 RXSETUP bit is cleared (as per the SAM7 manual). */
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148 ulTemp = pxMessage->ulCSR0;
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150 /* Are there any bytes in the FIFO? */
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151 ulRxBytes = ulTemp >> 16;
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152 ulRxBytes &= usbRX_COUNT_MASK;
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154 /* With this minimal implementation we are only interested in receiving
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155 setup bytes on the control end point. */
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156 if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) )
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158 /* Take off 1 for a zero based index. */
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159 while( ulRxBytes > 0 )
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162 pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
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165 /* The direction must be changed first. */
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166 usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) );
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167 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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170 /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA
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171 registers to clear the interrupts in the CSR register. */
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172 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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173 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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175 /* Also clear the interrupts in the CSR1 register. */
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176 ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
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177 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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178 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;
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180 /* The message now contains the entire state and optional data from
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181 the USB interrupt. This can now be posted on the Rx queue ready for
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182 processing at the task level. */
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183 xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, &xHigherPriorityTaskWoken );
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185 /* We may want to switch to the USB task, if this message has made
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186 it the highest priority task that is ready to execute. */
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187 if( xHigherPriorityTaskWoken )
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189 portYIELD_FROM_ISR();
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192 /* Clear the AIC ready for the next interrupt. */
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193 AT91C_BASE_AIC->AIC_EOICR = 0;
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195 /*-----------------------------------------------------------*/
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197 void vUSB_ISR_Wrapper( void )
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199 /* Save the context of the interrupted task. */
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200 portSAVE_CONTEXT();
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202 /* Call the handler itself. This must be a separate function as it uses
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204 __asm volatile ("bl vUSB_ISR_Handler");
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206 /* Restore the context of the task that is going to
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207 execute next. This might not be the same as the originally
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208 interrupted task.*/
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209 portRESTORE_CONTEXT();
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