2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* Standard includes. */
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73 /* Scheduler includes. */
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74 #include "FreeRTOS.h"
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78 /* Demo application includes. */
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79 #include "SAM7_EMAC.h"
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84 /* Hardware specific includes. */
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87 #include "AT91SAM7X256.h"
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90 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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91 to use an MII interface. */
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92 #define USE_RMII_INTERFACE 0
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94 /* The buffer addresses written into the descriptors must be aligned so the
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95 last few bits are zero. These bits have special meaning for the EMAC
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96 peripheral and cannot be used as part of the address. */
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97 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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99 /* Bit used within the address stored in the descriptor to mark the last
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100 descriptor in the array. */
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101 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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103 /* Bit used within the Tx descriptor status to indicate whether the
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104 descriptor is under the control of the EMAC or the software. */
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105 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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107 /* A short delay is used to wait for a buffer to become available, should
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108 one not be immediately available when trying to transmit a frame. */
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109 #define emacBUFFER_WAIT_DELAY ( 2 )
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110 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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112 /* Misc defines. */
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113 #define emacINTERRUPT_LEVEL ( 5 )
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114 #define emacNO_DELAY ( 0 )
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115 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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116 #define emacPHY_INIT_DELAY ( 5000 / portTICK_PERIOD_MS )
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117 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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118 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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120 /* The Atmel header file only defines the TX frame length mask. */
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121 #define emacRX_LENGTH_FRAME ( 0xfff )
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123 /* Peripheral setup for the EMAC. */
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124 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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125 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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126 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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127 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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128 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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129 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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130 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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131 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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132 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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133 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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134 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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135 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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136 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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137 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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138 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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139 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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140 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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141 ( ( unsigned long ) AT91C_PB17_ERXCK );
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143 /*-----------------------------------------------------------*/
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146 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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148 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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151 * Initialise both the Tx and Rx descriptors used by the EMAC.
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153 static void prvSetupDescriptors(void);
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156 * Write our MAC address into the EMAC. The MAC address is set as one of the
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159 static void prvSetupMACAddress( void );
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162 * Configure the EMAC and AIC for EMAC interrupts.
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164 static void prvSetupEMACInterrupt( void );
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167 * Some initialisation functions taken from the Atmel EMAC sample code.
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169 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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170 #if USE_RMII_INTERFACE != 1
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171 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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173 static portBASE_TYPE xGetLinkSpeed( void );
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174 static portBASE_TYPE prvProbePHY( void );
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176 /*-----------------------------------------------------------*/
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178 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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179 comment above the emacADDRESS_MASK definition. */
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180 #pragma data_alignment=8
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181 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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183 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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184 above the emacADDRESS_MASK definition. */
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185 #pragma data_alignment=8
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186 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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188 /* Descriptors used to communicate between the program and the EMAC peripheral.
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189 These descriptors hold the locations and state of the Rx and Tx buffers. */
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190 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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191 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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193 /* The IP and Ethernet addresses are read from the uIP setup. */
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194 const char cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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195 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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197 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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198 static SemaphoreHandle_t xSemaphore = NULL;
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200 /*-----------------------------------------------------------*/
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202 SemaphoreHandle_t xEMACInit( void )
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204 /* Code supplied by Atmel -------------------------------*/
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206 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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207 PHY has internal pull down. */
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208 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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210 #if USE_RMII_INTERFACE != 1
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211 /* PHY has internal pull down : set MII mode. */
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212 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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215 /* Clear PB18 <=> PHY powerdown. */
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216 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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217 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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218 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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220 /* After PHY power up, hardware reset. */
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221 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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222 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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224 /* Wait for hardware reset end. */
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225 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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227 __asm volatile ( "NOP" );
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229 __asm volatile ( "NOP" );
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231 /* Setup the pins. */
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232 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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233 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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235 /* Enable com between EMAC PHY.
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237 Enable management port. */
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238 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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240 /* MDC = MCK/32. */
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241 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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243 /* Wait for PHY auto init end (rather crude delay!). */
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244 vTaskDelay( emacPHY_INIT_DELAY );
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246 /* PHY configuration. */
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247 #if USE_RMII_INTERFACE != 1
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249 unsigned long ulControl;
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251 /* PHY has internal pull down : disable MII isolate. */
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252 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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253 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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254 ulControl &= ~BMCR_ISOLATE;
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255 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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259 /* Disable management port again. */
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260 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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262 #if USE_RMII_INTERFACE != 1
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263 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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264 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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266 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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268 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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271 /* End of code supplied by Atmel ------------------------*/
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273 /* Setup the buffers and descriptors. */
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274 prvSetupDescriptors();
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276 /* Load our MAC address into the EMAC. */
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277 prvSetupMACAddress();
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279 /* Are we connected? */
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280 if( prvProbePHY() )
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282 /* Enable the interrupt! */
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283 portENTER_CRITICAL();
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285 prvSetupEMACInterrupt();
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286 vPassEMACSemaphore( xSemaphore );
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288 portEXIT_CRITICAL();
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293 /*-----------------------------------------------------------*/
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295 long lEMACSend( void )
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297 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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298 portBASE_TYPE xWaitCycles = 0;
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299 long lReturn = pdPASS;
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302 /* Is a buffer available? */
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303 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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305 /* There is no room to write the Tx data to the Tx buffer. Wait a
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306 short while, then try again. */
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308 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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316 vTaskDelay( emacBUFFER_WAIT_DELAY );
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320 /* lReturn will only be pdPASS if a buffer is available. */
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321 if( lReturn == pdPASS )
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323 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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324 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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325 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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327 /* If there is room, also copy in the application data if any. */
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328 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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330 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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334 portENTER_CRITICAL();
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336 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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338 /* Fill out the necessary in the descriptor to get the data sent. */
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339 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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340 | AT91C_LAST_BUFFER
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341 | AT91C_TRANSMIT_WRAP;
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342 uxTxBufferIndex = 0;
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346 /* Fill out the necessary in the descriptor to get the data sent. */
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347 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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348 | AT91C_LAST_BUFFER;
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352 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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354 portEXIT_CRITICAL();
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359 /*-----------------------------------------------------------*/
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361 unsigned long ulEMACPoll( void )
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363 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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364 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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367 /* Skip any fragments. */
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368 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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370 /* Mark the buffer as free again. */
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371 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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373 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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375 ulNextRxBuffer = 0;
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379 /* Is there a packet ready? */
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381 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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383 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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384 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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386 if( ulSectionLength == 0 )
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388 /* The frame is longer than the buffer pointed to by this
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389 descriptor so copy the entire buffer to uIP - then move onto
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390 the next descriptor to get the rest of the frame. */
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391 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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393 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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394 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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399 /* This is the last section of the frame. Copy the section to
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401 if( ulSectionLength < UIP_BUFSIZE )
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403 /* The section length holds the length of the entire frame.
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404 ulLengthSoFar holds the length of the frame sections already
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405 copied to uIP, so the length of the final section is
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406 ulSectionLength - ulLengthSoFar; */
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407 if( ulSectionLength > ulLengthSoFar )
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409 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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413 /* Is this the last buffer for the frame? If not why? */
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414 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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417 /* Mark the buffer as free again. */
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418 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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420 /* Increment to the next buffer, wrapping if necessary. */
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422 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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424 ulNextRxBuffer = 0;
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428 /* If we obtained data but for some reason did not find the end of the
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429 frame then discard the data as it must contain an error. */
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432 ulSectionLength = 0;
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435 return ulSectionLength;
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437 /*-----------------------------------------------------------*/
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439 static void prvSetupDescriptors(void)
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441 unsigned portBASE_TYPE xIndex;
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442 unsigned long ulAddress;
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444 /* Initialise xRxDescriptors descriptor. */
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445 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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447 /* Calculate the address of the nth buffer within the array. */
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448 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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450 /* Write the buffer address into the descriptor. The DMA will place
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451 the data at this address when this descriptor is being used. Mask off
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452 the bottom bits of the address as these have special meaning. */
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453 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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456 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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457 to the first buffer. */
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458 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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460 /* Initialise xTxDescriptors. */
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461 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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463 /* Calculate the address of the nth buffer within the array. */
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464 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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466 /* Write the buffer address into the descriptor. The DMA will read
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467 data from here when the descriptor is being used. */
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468 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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469 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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472 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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473 to the first buffer. */
\r
474 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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476 /* Tell the EMAC where to find the descriptors. */
\r
477 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
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478 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
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480 /* Clear all the bits in the receive status register. */
\r
481 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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483 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
484 and don't copy FCS. */
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485 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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487 /* Enable Rx and Tx, plus the stats register. */
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488 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
490 /*-----------------------------------------------------------*/
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492 static void prvSetupMACAddress( void )
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494 /* Must be written SA1L then SA1H. */
\r
495 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
496 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
497 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
500 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
503 /*-----------------------------------------------------------*/
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505 static void prvSetupEMACInterrupt( void )
\r
507 /* Create the semaphore used to trigger the EMAC task. */
\r
508 vSemaphoreCreateBinary( xSemaphore );
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511 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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512 first interrupt occurs. */
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513 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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514 portENTER_CRITICAL();
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516 /* We want to interrupt on Rx events. */
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517 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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519 /* Enable the interrupts in the AIC. */
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520 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
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521 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
523 portEXIT_CRITICAL();
\r
526 /*-----------------------------------------------------------*/
\r
532 * The following functions are initialisation functions taken from the Atmel
\r
533 * EMAC sample code.
\r
536 static portBASE_TYPE prvProbePHY( void )
\r
538 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
539 portBASE_TYPE xReturn = pdPASS;
\r
541 /* Code supplied by Atmel (reformatted) -----------------*/
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543 /* Enable management port */
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544 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
545 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
547 /* Read the PHY ID. */
\r
548 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
549 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
554 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
555 0001 stands for Rev. A, etc.
\r
557 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
559 /* Did not expect this ID. */
\r
564 ulStatus = xGetLinkSpeed();
\r
566 if( ulStatus != pdPASS )
\r
572 /* Disable management port */
\r
573 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
575 /* End of code supplied by Atmel ------------------------*/
\r
579 /*-----------------------------------------------------------*/
\r
581 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
583 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
585 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
586 | (2 << 16) | (2 << 28)
\r
587 | ((ucPHYAddress & 0x1f) << 23)
\r
588 | (ucAddress << 18);
\r
590 /* Wait until IDLE bit in Network Status register is cleared. */
\r
591 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
596 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
598 /* End of code supplied by Atmel ------------------------*/
\r
600 /*-----------------------------------------------------------*/
\r
602 #if USE_RMII_INTERFACE != 1
\r
603 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
605 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
607 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
608 | (2 << 16) | (1 << 28)
\r
609 | ((ucPHYAddress & 0x1f) << 23)
\r
610 | (ucAddress << 18))
\r
611 | (ulValue & 0xffff);
\r
613 /* Wait until IDLE bit in Network Status register is cleared */
\r
614 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
619 /* End of code supplied by Atmel ------------------------*/
\r
622 /*-----------------------------------------------------------*/
\r
624 static portBASE_TYPE xGetLinkSpeed( void )
\r
626 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
628 /* Code supplied by Atmel (reformatted) -----------------*/
\r
630 /* Link status is latched, so read twice to get current value */
\r
631 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
632 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
634 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
640 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
641 if (ulBMCR & BMCR_ANENABLE)
\r
643 /* AutoNegotiation is enabled. */
\r
644 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
646 /* Auto-negotiation in progress. */
\r
650 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
651 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
653 ulSpeed = SPEED_100;
\r
657 ulSpeed = SPEED_10;
\r
660 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
662 ulDuplex = DUPLEX_FULL;
\r
666 ulDuplex = DUPLEX_HALF;
\r
671 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
672 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
675 /* Update the MAC */
\r
676 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
677 if( ulSpeed == SPEED_100 )
\r
679 if( ulDuplex == DUPLEX_FULL )
\r
681 /* 100 Full Duplex */
\r
682 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
686 /* 100 Half Duplex */
\r
687 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
692 if (ulDuplex == DUPLEX_FULL)
\r
694 /* 10 Full Duplex */
\r
695 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
699 /* 10 Half Duplex */
\r
700 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
704 /* End of code supplied by Atmel ------------------------*/
\r