2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
13 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
14 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
15 >>! obliged to provide the source code for proprietary components !<<
\r
16 >>! outside of the FreeRTOS kernel. !<<
\r
18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
21 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * Having a problem? Start by reading the FAQ "My application does *
\r
28 * not run, what could be wrong?". Have you defined configASSERT()? *
\r
30 * http://www.FreeRTOS.org/FAQHelp.html *
\r
32 ***************************************************************************
\r
34 ***************************************************************************
\r
36 * FreeRTOS provides completely free yet professionally developed, *
\r
37 * robust, strictly quality controlled, supported, and cross *
\r
38 * platform software that is more than just the market leader, it *
\r
39 * is the industry's de facto standard. *
\r
41 * Help yourself get started quickly while simultaneously helping *
\r
42 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
43 * tutorial book, reference manual, or both: *
\r
44 * http://www.FreeRTOS.org/Documentation *
\r
46 ***************************************************************************
\r
48 ***************************************************************************
\r
50 * Investing in training allows your team to be as productive as *
\r
51 * possible as early as possible, lowering your overall development *
\r
52 * cost, and enabling you to bring a more robust product to market *
\r
53 * earlier than would otherwise be possible. Richard Barry is both *
\r
54 * the architect and key author of FreeRTOS, and so also the world's *
\r
55 * leading authority on what is the world's most popular real time *
\r
56 * kernel for deeply embedded MCU designs. Obtaining your training *
\r
57 * from Richard ensures your team will gain directly from his in-depth *
\r
58 * product knowledge and years of usage experience. Contact Real Time *
\r
59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
\r
60 * by Richard Barry: http://www.FreeRTOS.org/contact
\r
62 ***************************************************************************
\r
64 ***************************************************************************
\r
66 * You are receiving this top quality software for free. Please play *
\r
67 * fair and reciprocate by reporting any suspected issues and *
\r
68 * participating in the community forum: *
\r
69 * http://www.FreeRTOS.org/support *
\r
73 ***************************************************************************
\r
75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
76 license and Real Time Engineers Ltd. contact details.
\r
78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
87 licenses offer ticketed support, indemnification and commercial middleware.
\r
89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
90 engineered and independently SIL3 certified version for use in safety and
\r
91 mission critical applications that require provable dependability.
\r
96 /* Standard includes. */
\r
99 /* Scheduler includes. */
\r
100 #include "FreeRTOS.h"
\r
101 #include "semphr.h"
\r
104 /* Demo application includes. */
\r
105 #include "SAM7_EMAC.h"
\r
107 /* uIP includes. */
\r
110 /* Hardware specific includes. */
\r
113 #include "AT91SAM7X256.h"
\r
116 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
\r
117 to use an MII interface. */
\r
118 #define USE_RMII_INTERFACE 0
\r
120 /* The buffer addresses written into the descriptors must be aligned so the
\r
121 last few bits are zero. These bits have special meaning for the EMAC
\r
122 peripheral and cannot be used as part of the address. */
\r
123 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
\r
125 /* Bit used within the address stored in the descriptor to mark the last
\r
126 descriptor in the array. */
\r
127 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
\r
129 /* Bit used within the Tx descriptor status to indicate whether the
\r
130 descriptor is under the control of the EMAC or the software. */
\r
131 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
\r
133 /* A short delay is used to wait for a buffer to become available, should
\r
134 one not be immediately available when trying to transmit a frame. */
\r
135 #define emacBUFFER_WAIT_DELAY ( 2 )
\r
136 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
\r
138 /* Misc defines. */
\r
139 #define emacINTERRUPT_LEVEL ( 5 )
\r
140 #define emacNO_DELAY ( 0 )
\r
141 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
\r
142 #define emacPHY_INIT_DELAY ( 5000 / portTICK_PERIOD_MS )
\r
143 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
\r
144 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
\r
146 /* The Atmel header file only defines the TX frame length mask. */
\r
147 #define emacRX_LENGTH_FRAME ( 0xfff )
\r
149 /* Peripheral setup for the EMAC. */
\r
150 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
\r
151 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
\r
152 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
\r
153 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
\r
154 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
\r
155 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
\r
156 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
\r
157 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
\r
158 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
\r
159 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
\r
160 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
\r
161 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
\r
162 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
\r
163 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
\r
164 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
\r
165 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
\r
166 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
\r
167 ( ( unsigned long ) AT91C_PB17_ERXCK );
\r
169 /*-----------------------------------------------------------*/
\r
172 * Prototype for the EMAC interrupt function - called by the asm wrapper.
\r
174 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
\r
177 * Initialise both the Tx and Rx descriptors used by the EMAC.
\r
179 static void prvSetupDescriptors(void);
\r
182 * Write our MAC address into the EMAC. The MAC address is set as one of the
\r
185 static void prvSetupMACAddress( void );
\r
188 * Configure the EMAC and AIC for EMAC interrupts.
\r
190 static void prvSetupEMACInterrupt( void );
\r
193 * Some initialisation functions taken from the Atmel EMAC sample code.
\r
195 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
\r
196 #if USE_RMII_INTERFACE != 1
\r
197 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
\r
199 static portBASE_TYPE xGetLinkSpeed( void );
\r
200 static portBASE_TYPE prvProbePHY( void );
\r
202 /*-----------------------------------------------------------*/
\r
204 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
\r
205 comment above the emacADDRESS_MASK definition. */
\r
206 #pragma data_alignment=8
\r
207 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
\r
209 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
\r
210 above the emacADDRESS_MASK definition. */
\r
211 #pragma data_alignment=8
\r
212 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
\r
214 /* Descriptors used to communicate between the program and the EMAC peripheral.
\r
215 These descriptors hold the locations and state of the Rx and Tx buffers. */
\r
216 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
\r
217 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
\r
219 /* The IP and Ethernet addresses are read from the uIP setup. */
\r
220 const char cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
\r
221 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
\r
223 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
\r
224 static SemaphoreHandle_t xSemaphore = NULL;
\r
226 /*-----------------------------------------------------------*/
\r
228 SemaphoreHandle_t xEMACInit( void )
\r
230 /* Code supplied by Atmel -------------------------------*/
\r
232 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
\r
233 PHY has internal pull down. */
\r
234 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
\r
236 #if USE_RMII_INTERFACE != 1
\r
237 /* PHY has internal pull down : set MII mode. */
\r
238 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
\r
241 /* Clear PB18 <=> PHY powerdown. */
\r
242 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
\r
243 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
\r
244 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
\r
246 /* After PHY power up, hardware reset. */
\r
247 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
\r
248 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
\r
250 /* Wait for hardware reset end. */
\r
251 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
\r
253 __asm volatile ( "NOP" );
\r
255 __asm volatile ( "NOP" );
\r
257 /* Setup the pins. */
\r
258 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
\r
259 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
\r
261 /* Enable com between EMAC PHY.
\r
263 Enable management port. */
\r
264 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
266 /* MDC = MCK/32. */
\r
267 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
269 /* Wait for PHY auto init end (rather crude delay!). */
\r
270 vTaskDelay( emacPHY_INIT_DELAY );
\r
272 /* PHY configuration. */
\r
273 #if USE_RMII_INTERFACE != 1
\r
275 unsigned long ulControl;
\r
277 /* PHY has internal pull down : disable MII isolate. */
\r
278 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
279 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
280 ulControl &= ~BMCR_ISOLATE;
\r
281 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
\r
285 /* Disable management port again. */
\r
286 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
288 #if USE_RMII_INTERFACE != 1
\r
289 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
\r
290 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
\r
292 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
\r
294 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
\r
297 /* End of code supplied by Atmel ------------------------*/
\r
299 /* Setup the buffers and descriptors. */
\r
300 prvSetupDescriptors();
\r
302 /* Load our MAC address into the EMAC. */
\r
303 prvSetupMACAddress();
\r
305 /* Are we connected? */
\r
306 if( prvProbePHY() )
\r
308 /* Enable the interrupt! */
\r
309 portENTER_CRITICAL();
\r
311 prvSetupEMACInterrupt();
\r
312 vPassEMACSemaphore( xSemaphore );
\r
314 portEXIT_CRITICAL();
\r
319 /*-----------------------------------------------------------*/
\r
321 long lEMACSend( void )
\r
323 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
\r
324 portBASE_TYPE xWaitCycles = 0;
\r
325 long lReturn = pdPASS;
\r
328 /* Is a buffer available? */
\r
329 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
\r
331 /* There is no room to write the Tx data to the Tx buffer. Wait a
\r
332 short while, then try again. */
\r
334 if( xWaitCycles > emacMAX_WAIT_CYCLES )
\r
342 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
346 /* lReturn will only be pdPASS if a buffer is available. */
\r
347 if( lReturn == pdPASS )
\r
349 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
\r
350 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
\r
351 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
\r
353 /* If there is room, also copy in the application data if any. */
\r
354 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
\r
356 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
\r
360 portENTER_CRITICAL();
\r
362 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
\r
364 /* Fill out the necessary in the descriptor to get the data sent. */
\r
365 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
366 | AT91C_LAST_BUFFER
\r
367 | AT91C_TRANSMIT_WRAP;
\r
368 uxTxBufferIndex = 0;
\r
372 /* Fill out the necessary in the descriptor to get the data sent. */
\r
373 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
374 | AT91C_LAST_BUFFER;
\r
378 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
\r
380 portEXIT_CRITICAL();
\r
385 /*-----------------------------------------------------------*/
\r
387 unsigned long ulEMACPoll( void )
\r
389 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
\r
390 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
\r
393 /* Skip any fragments. */
\r
394 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
\r
396 /* Mark the buffer as free again. */
\r
397 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
399 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
401 ulNextRxBuffer = 0;
\r
405 /* Is there a packet ready? */
\r
407 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
\r
409 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
410 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
\r
412 if( ulSectionLength == 0 )
\r
414 /* The frame is longer than the buffer pointed to by this
\r
415 descriptor so copy the entire buffer to uIP - then move onto
\r
416 the next descriptor to get the rest of the frame. */
\r
417 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
\r
419 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
\r
420 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
\r
425 /* This is the last section of the frame. Copy the section to
\r
427 if( ulSectionLength < UIP_BUFSIZE )
\r
429 /* The section length holds the length of the entire frame.
\r
430 ulLengthSoFar holds the length of the frame sections already
\r
431 copied to uIP, so the length of the final section is
\r
432 ulSectionLength - ulLengthSoFar; */
\r
433 if( ulSectionLength > ulLengthSoFar )
\r
435 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
\r
439 /* Is this the last buffer for the frame? If not why? */
\r
440 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
\r
443 /* Mark the buffer as free again. */
\r
444 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
446 /* Increment to the next buffer, wrapping if necessary. */
\r
448 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
450 ulNextRxBuffer = 0;
\r
454 /* If we obtained data but for some reason did not find the end of the
\r
455 frame then discard the data as it must contain an error. */
\r
458 ulSectionLength = 0;
\r
461 return ulSectionLength;
\r
463 /*-----------------------------------------------------------*/
\r
465 static void prvSetupDescriptors(void)
\r
467 unsigned portBASE_TYPE xIndex;
\r
468 unsigned long ulAddress;
\r
470 /* Initialise xRxDescriptors descriptor. */
\r
471 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
\r
473 /* Calculate the address of the nth buffer within the array. */
\r
474 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
\r
476 /* Write the buffer address into the descriptor. The DMA will place
\r
477 the data at this address when this descriptor is being used. Mask off
\r
478 the bottom bits of the address as these have special meaning. */
\r
479 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
482 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
483 to the first buffer. */
\r
484 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
486 /* Initialise xTxDescriptors. */
\r
487 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
489 /* Calculate the address of the nth buffer within the array. */
\r
490 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
492 /* Write the buffer address into the descriptor. The DMA will read
\r
493 data from here when the descriptor is being used. */
\r
494 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
495 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
498 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
499 to the first buffer. */
\r
500 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
502 /* Tell the EMAC where to find the descriptors. */
\r
503 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
504 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
506 /* Clear all the bits in the receive status register. */
\r
507 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
509 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
510 and don't copy FCS. */
\r
511 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
513 /* Enable Rx and Tx, plus the stats register. */
\r
514 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
516 /*-----------------------------------------------------------*/
\r
518 static void prvSetupMACAddress( void )
\r
520 /* Must be written SA1L then SA1H. */
\r
521 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
522 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
523 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
526 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
529 /*-----------------------------------------------------------*/
\r
531 static void prvSetupEMACInterrupt( void )
\r
533 /* Create the semaphore used to trigger the EMAC task. */
\r
534 vSemaphoreCreateBinary( xSemaphore );
\r
537 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
538 first interrupt occurs. */
\r
539 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
540 portENTER_CRITICAL();
\r
542 /* We want to interrupt on Rx events. */
\r
543 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
\r
545 /* Enable the interrupts in the AIC. */
\r
546 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
547 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
549 portEXIT_CRITICAL();
\r
552 /*-----------------------------------------------------------*/
\r
558 * The following functions are initialisation functions taken from the Atmel
\r
559 * EMAC sample code.
\r
562 static portBASE_TYPE prvProbePHY( void )
\r
564 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
565 portBASE_TYPE xReturn = pdPASS;
\r
567 /* Code supplied by Atmel (reformatted) -----------------*/
\r
569 /* Enable management port */
\r
570 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
571 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
573 /* Read the PHY ID. */
\r
574 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
575 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
580 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
581 0001 stands for Rev. A, etc.
\r
583 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
585 /* Did not expect this ID. */
\r
590 ulStatus = xGetLinkSpeed();
\r
592 if( ulStatus != pdPASS )
\r
598 /* Disable management port */
\r
599 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
601 /* End of code supplied by Atmel ------------------------*/
\r
605 /*-----------------------------------------------------------*/
\r
607 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
609 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
611 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
612 | (2 << 16) | (2 << 28)
\r
613 | ((ucPHYAddress & 0x1f) << 23)
\r
614 | (ucAddress << 18);
\r
616 /* Wait until IDLE bit in Network Status register is cleared. */
\r
617 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
622 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
624 /* End of code supplied by Atmel ------------------------*/
\r
626 /*-----------------------------------------------------------*/
\r
628 #if USE_RMII_INTERFACE != 1
\r
629 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
631 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
633 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
634 | (2 << 16) | (1 << 28)
\r
635 | ((ucPHYAddress & 0x1f) << 23)
\r
636 | (ucAddress << 18))
\r
637 | (ulValue & 0xffff);
\r
639 /* Wait until IDLE bit in Network Status register is cleared */
\r
640 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
645 /* End of code supplied by Atmel ------------------------*/
\r
648 /*-----------------------------------------------------------*/
\r
650 static portBASE_TYPE xGetLinkSpeed( void )
\r
652 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
654 /* Code supplied by Atmel (reformatted) -----------------*/
\r
656 /* Link status is latched, so read twice to get current value */
\r
657 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
658 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
660 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
666 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
667 if (ulBMCR & BMCR_ANENABLE)
\r
669 /* AutoNegotiation is enabled. */
\r
670 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
672 /* Auto-negotiation in progress. */
\r
676 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
677 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
679 ulSpeed = SPEED_100;
\r
683 ulSpeed = SPEED_10;
\r
686 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
688 ulDuplex = DUPLEX_FULL;
\r
692 ulDuplex = DUPLEX_HALF;
\r
697 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
698 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
701 /* Update the MAC */
\r
702 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
703 if( ulSpeed == SPEED_100 )
\r
705 if( ulDuplex == DUPLEX_FULL )
\r
707 /* 100 Full Duplex */
\r
708 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
712 /* 100 Half Duplex */
\r
713 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
718 if (ulDuplex == DUPLEX_FULL)
\r
720 /* 10 Full Duplex */
\r
721 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
725 /* 10 Half Duplex */
\r
726 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
730 /* End of code supplied by Atmel ------------------------*/
\r