2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* Standard includes. */
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78 /* Scheduler includes. */
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79 #include "FreeRTOS.h"
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83 /* Demo application includes. */
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84 #include "SAM7_EMAC.h"
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89 /* Hardware specific includes. */
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92 #include "AT91SAM7X256.h"
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95 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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96 to use an MII interface. */
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97 #define USE_RMII_INTERFACE 0
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99 /* The buffer addresses written into the descriptors must be aligned so the
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100 last few bits are zero. These bits have special meaning for the EMAC
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101 peripheral and cannot be used as part of the address. */
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102 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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104 /* Bit used within the address stored in the descriptor to mark the last
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105 descriptor in the array. */
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106 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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108 /* Bit used within the Tx descriptor status to indicate whether the
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109 descriptor is under the control of the EMAC or the software. */
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110 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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112 /* A short delay is used to wait for a buffer to become available, should
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113 one not be immediately available when trying to transmit a frame. */
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114 #define emacBUFFER_WAIT_DELAY ( 2 )
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115 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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117 /* Misc defines. */
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118 #define emacINTERRUPT_LEVEL ( 5 )
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119 #define emacNO_DELAY ( 0 )
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120 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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121 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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122 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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123 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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125 /* The Atmel header file only defines the TX frame length mask. */
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126 #define emacRX_LENGTH_FRAME ( 0xfff )
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128 /* Peripheral setup for the EMAC. */
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129 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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130 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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131 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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132 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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133 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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134 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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135 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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136 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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137 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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138 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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139 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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140 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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141 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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142 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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143 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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144 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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145 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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146 ( ( unsigned long ) AT91C_PB17_ERXCK );
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148 /*-----------------------------------------------------------*/
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151 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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153 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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156 * Initialise both the Tx and Rx descriptors used by the EMAC.
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158 static void prvSetupDescriptors(void);
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161 * Write our MAC address into the EMAC. The MAC address is set as one of the
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164 static void prvSetupMACAddress( void );
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167 * Configure the EMAC and AIC for EMAC interrupts.
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169 static void prvSetupEMACInterrupt( void );
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172 * Some initialisation functions taken from the Atmel EMAC sample code.
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174 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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175 #if USE_RMII_INTERFACE != 1
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176 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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178 static portBASE_TYPE xGetLinkSpeed( void );
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179 static portBASE_TYPE prvProbePHY( void );
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181 /*-----------------------------------------------------------*/
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183 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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184 comment above the emacADDRESS_MASK definition. */
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185 #pragma data_alignment=8
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186 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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188 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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189 above the emacADDRESS_MASK definition. */
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190 #pragma data_alignment=8
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191 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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193 /* Descriptors used to communicate between the program and the EMAC peripheral.
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194 These descriptors hold the locations and state of the Rx and Tx buffers. */
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195 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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196 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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198 /* The IP and Ethernet addresses are read from the uIP setup. */
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199 const char cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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200 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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202 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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203 static xSemaphoreHandle xSemaphore = NULL;
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205 /*-----------------------------------------------------------*/
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207 xSemaphoreHandle xEMACInit( void )
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209 /* Code supplied by Atmel -------------------------------*/
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211 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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212 PHY has internal pull down. */
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213 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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215 #if USE_RMII_INTERFACE != 1
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216 /* PHY has internal pull down : set MII mode. */
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217 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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220 /* Clear PB18 <=> PHY powerdown. */
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221 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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222 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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223 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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225 /* After PHY power up, hardware reset. */
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226 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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227 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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229 /* Wait for hardware reset end. */
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230 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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232 __asm volatile ( "NOP" );
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234 __asm volatile ( "NOP" );
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236 /* Setup the pins. */
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237 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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238 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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240 /* Enable com between EMAC PHY.
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242 Enable management port. */
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243 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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245 /* MDC = MCK/32. */
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246 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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248 /* Wait for PHY auto init end (rather crude delay!). */
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249 vTaskDelay( emacPHY_INIT_DELAY );
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251 /* PHY configuration. */
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252 #if USE_RMII_INTERFACE != 1
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254 unsigned long ulControl;
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256 /* PHY has internal pull down : disable MII isolate. */
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257 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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258 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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259 ulControl &= ~BMCR_ISOLATE;
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260 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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264 /* Disable management port again. */
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265 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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267 #if USE_RMII_INTERFACE != 1
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268 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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269 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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271 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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273 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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276 /* End of code supplied by Atmel ------------------------*/
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278 /* Setup the buffers and descriptors. */
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279 prvSetupDescriptors();
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281 /* Load our MAC address into the EMAC. */
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282 prvSetupMACAddress();
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284 /* Are we connected? */
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285 if( prvProbePHY() )
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287 /* Enable the interrupt! */
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288 portENTER_CRITICAL();
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290 prvSetupEMACInterrupt();
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291 vPassEMACSemaphore( xSemaphore );
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293 portEXIT_CRITICAL();
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298 /*-----------------------------------------------------------*/
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300 long lEMACSend( void )
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302 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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303 portBASE_TYPE xWaitCycles = 0;
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304 long lReturn = pdPASS;
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307 /* Is a buffer available? */
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308 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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310 /* There is no room to write the Tx data to the Tx buffer. Wait a
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311 short while, then try again. */
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313 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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321 vTaskDelay( emacBUFFER_WAIT_DELAY );
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325 /* lReturn will only be pdPASS if a buffer is available. */
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326 if( lReturn == pdPASS )
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328 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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329 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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330 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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332 /* If there is room, also copy in the application data if any. */
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333 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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335 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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339 portENTER_CRITICAL();
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341 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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343 /* Fill out the necessary in the descriptor to get the data sent. */
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344 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
345 | AT91C_LAST_BUFFER
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346 | AT91C_TRANSMIT_WRAP;
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347 uxTxBufferIndex = 0;
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351 /* Fill out the necessary in the descriptor to get the data sent. */
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352 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
\r
353 | AT91C_LAST_BUFFER;
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357 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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359 portEXIT_CRITICAL();
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364 /*-----------------------------------------------------------*/
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366 unsigned long ulEMACPoll( void )
\r
368 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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369 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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372 /* Skip any fragments. */
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373 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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375 /* Mark the buffer as free again. */
\r
376 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
378 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
380 ulNextRxBuffer = 0;
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384 /* Is there a packet ready? */
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386 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
\r
388 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
389 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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391 if( ulSectionLength == 0 )
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393 /* The frame is longer than the buffer pointed to by this
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394 descriptor so copy the entire buffer to uIP - then move onto
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395 the next descriptor to get the rest of the frame. */
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396 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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398 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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399 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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404 /* This is the last section of the frame. Copy the section to
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406 if( ulSectionLength < UIP_BUFSIZE )
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408 /* The section length holds the length of the entire frame.
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409 ulLengthSoFar holds the length of the frame sections already
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410 copied to uIP, so the length of the final section is
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411 ulSectionLength - ulLengthSoFar; */
\r
412 if( ulSectionLength > ulLengthSoFar )
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414 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
\r
418 /* Is this the last buffer for the frame? If not why? */
\r
419 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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422 /* Mark the buffer as free again. */
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423 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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425 /* Increment to the next buffer, wrapping if necessary. */
\r
427 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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429 ulNextRxBuffer = 0;
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433 /* If we obtained data but for some reason did not find the end of the
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434 frame then discard the data as it must contain an error. */
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437 ulSectionLength = 0;
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440 return ulSectionLength;
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442 /*-----------------------------------------------------------*/
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444 static void prvSetupDescriptors(void)
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446 unsigned portBASE_TYPE xIndex;
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447 unsigned long ulAddress;
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449 /* Initialise xRxDescriptors descriptor. */
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450 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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452 /* Calculate the address of the nth buffer within the array. */
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453 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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455 /* Write the buffer address into the descriptor. The DMA will place
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456 the data at this address when this descriptor is being used. Mask off
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457 the bottom bits of the address as these have special meaning. */
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458 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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461 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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462 to the first buffer. */
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463 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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465 /* Initialise xTxDescriptors. */
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466 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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468 /* Calculate the address of the nth buffer within the array. */
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469 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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471 /* Write the buffer address into the descriptor. The DMA will read
\r
472 data from here when the descriptor is being used. */
\r
473 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
474 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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477 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
478 to the first buffer. */
\r
479 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
481 /* Tell the EMAC where to find the descriptors. */
\r
482 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
483 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
485 /* Clear all the bits in the receive status register. */
\r
486 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
488 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
489 and don't copy FCS. */
\r
490 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
492 /* Enable Rx and Tx, plus the stats register. */
\r
493 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
495 /*-----------------------------------------------------------*/
\r
497 static void prvSetupMACAddress( void )
\r
499 /* Must be written SA1L then SA1H. */
\r
500 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
501 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
502 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
505 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
508 /*-----------------------------------------------------------*/
\r
510 static void prvSetupEMACInterrupt( void )
\r
512 /* Create the semaphore used to trigger the EMAC task. */
\r
513 vSemaphoreCreateBinary( xSemaphore );
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516 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
517 first interrupt occurs. */
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518 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
519 portENTER_CRITICAL();
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521 /* We want to interrupt on Rx events. */
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522 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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524 /* Enable the interrupts in the AIC. */
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525 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
526 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
528 portEXIT_CRITICAL();
\r
531 /*-----------------------------------------------------------*/
\r
537 * The following functions are initialisation functions taken from the Atmel
\r
538 * EMAC sample code.
\r
541 static portBASE_TYPE prvProbePHY( void )
\r
543 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
544 portBASE_TYPE xReturn = pdPASS;
\r
546 /* Code supplied by Atmel (reformatted) -----------------*/
\r
548 /* Enable management port */
\r
549 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
550 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
552 /* Read the PHY ID. */
\r
553 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
554 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
559 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
560 0001 stands for Rev. A, etc.
\r
562 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
564 /* Did not expect this ID. */
\r
569 ulStatus = xGetLinkSpeed();
\r
571 if( ulStatus != pdPASS )
\r
577 /* Disable management port */
\r
578 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
580 /* End of code supplied by Atmel ------------------------*/
\r
584 /*-----------------------------------------------------------*/
\r
586 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
588 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
590 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
591 | (2 << 16) | (2 << 28)
\r
592 | ((ucPHYAddress & 0x1f) << 23)
\r
593 | (ucAddress << 18);
\r
595 /* Wait until IDLE bit in Network Status register is cleared. */
\r
596 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
601 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
603 /* End of code supplied by Atmel ------------------------*/
\r
605 /*-----------------------------------------------------------*/
\r
607 #if USE_RMII_INTERFACE != 1
\r
608 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
610 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
612 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
613 | (2 << 16) | (1 << 28)
\r
614 | ((ucPHYAddress & 0x1f) << 23)
\r
615 | (ucAddress << 18))
\r
616 | (ulValue & 0xffff);
\r
618 /* Wait until IDLE bit in Network Status register is cleared */
\r
619 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
624 /* End of code supplied by Atmel ------------------------*/
\r
627 /*-----------------------------------------------------------*/
\r
629 static portBASE_TYPE xGetLinkSpeed( void )
\r
631 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
633 /* Code supplied by Atmel (reformatted) -----------------*/
\r
635 /* Link status is latched, so read twice to get current value */
\r
636 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
637 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
639 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
645 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
646 if (ulBMCR & BMCR_ANENABLE)
\r
648 /* AutoNegotiation is enabled. */
\r
649 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
651 /* Auto-negotiation in progress. */
\r
655 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
656 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
658 ulSpeed = SPEED_100;
\r
662 ulSpeed = SPEED_10;
\r
665 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
667 ulDuplex = DUPLEX_FULL;
\r
671 ulDuplex = DUPLEX_HALF;
\r
676 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
677 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
680 /* Update the MAC */
\r
681 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
682 if( ulSpeed == SPEED_100 )
\r
684 if( ulDuplex == DUPLEX_FULL )
\r
686 /* 100 Full Duplex */
\r
687 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
691 /* 100 Half Duplex */
\r
692 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
697 if (ulDuplex == DUPLEX_FULL)
\r
699 /* 10 Full Duplex */
\r
700 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
704 /* 10 Half Duplex */
\r
705 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
709 /* End of code supplied by Atmel ------------------------*/
\r