1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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3 ;; Part one of the system initialization code,
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4 ;; contains low-level
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7 ;; Copyright 2006 IAR Systems. All rights reserved.
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9 ;; $Revision: 10608 $
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14 ;; Forward declaration of sections.
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15 SECTION IRQ_STACK:DATA:NOROOT(3)
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16 SECTION ABT_STACK:DATA:NOROOT(3)
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17 SECTION SVC_STACK:DATA:NOROOT(3)
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18 SECTION UND_STACK:DATA:NOROOT(3)
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19 SECTION FIQ_STACK:DATA:NOROOT(3)
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20 SECTION CSTACK:DATA:NOROOT(3)
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23 ; The module in this file are included in the libraries, and may be
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24 ; replaced by any user-defined modules that define the PUBLIC symbol
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25 ; __iar_program_start or a user defined start symbol.
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27 ; To override the cstartup defined in the library, simply add your
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28 ; modified version to the workbench project.
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30 SECTION .intvec:CODE:NOROOT(2)
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33 PUBLIC __vector_0x14
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34 PUBLIC __iar_program_start
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35 EXTERN vPortYieldProcessor
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40 ldr pc,[pc,#+24] ;; Reset
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41 ldr pc,[pc,#+24] ;; Undefined instructions
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42 ;; ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
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43 b vPortYieldProcessor
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44 ldr pc,[pc,#+24] ;; Prefetch abort
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45 ldr pc,[pc,#+24] ;; Data abort
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48 ldr pc, [PC, #-0xFF0] ;; IRQ
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49 ldr pc,[pc,#+24] ;; FIQ
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51 DC32 __iar_program_start ;; Reset
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52 DC32 undef_handler ;; Undefined instructions
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53 DC32 0 ;; Software interrupt (SWI/SVC)
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54 DC32 prefetch_handler ;; Prefetch abort
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55 DC32 data_handler ;; Data abort
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58 DC32 fiq_handler ;; FIQ
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71 ; --------------------------------------------------
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72 ; ?cstartup -- low-level system initialization code.
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74 ; After a reser execution starts here, the mode is ARM, supervisor
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75 ; with interrupts disabled.
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80 SECTION .text:CODE:NOROOT(2)
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88 __iar_program_start:
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92 ; Add initialization needed before setup of stackpointers here.
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95 ; Errata MAM.1Incorrect read of data from SRAM after Reset and MAM
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96 ; is not enabled or partially enabled.
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97 ; Work-around: User code should enable the MAM after Reset and before
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99 MAMCR DEFINE 0xE01FC000 ; MAM Control Register
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100 MAMTIM DEFINE 0xE01FC004 ; MAM Timing register
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106 ldr r2,=3 ; 1 < 20 MHz; 20 MHz < 2 < 40 MHz; 40MHz > 3
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111 ; Initialize the stack pointers.
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112 ; The pattern below can be used for any of the exception stacks:
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113 ; FIQ, IRQ, SVC, ABT, UND, SYS.
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114 ; The USR mode uses the same stack as SYS.
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115 ; The stack segments must be defined in the linker command file,
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116 ; and be declared above.
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118 ; --------------------
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119 ; Mode, correspords to bits 0-5 in CPSR
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120 MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
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121 USR_MODE DEFINE 0x10 ; User mode
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122 FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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123 IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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124 SVC_MODE DEFINE 0x13 ; Supervisor mode
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125 ABT_MODE DEFINE 0x17 ; Abort mode
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126 UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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127 SYS_MODE DEFINE 0x1F ; System mode
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129 MRS r0, cpsr ; Original PSR value
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131 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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132 ORR r0, r0, #ABT_MODE ; Set ABT mode bits
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133 MSR cpsr_c, r0 ; Change the mode
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134 LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
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136 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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137 ORR r0, r0, #SVC_MODE ; Set SVC mode bits
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138 MSR cpsr_c, r0 ; Change the mode
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139 LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
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141 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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142 ORR r0, r0, #UND_MODE ; Set UND mode bits
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143 MSR cpsr_c, r0 ; Change the mode
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144 LDR sp, =SFE(UND_STACK) ; End of UND_STACK
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146 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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147 ORR r0, r0, #FIQ_MODE ; Set FIQ mode bits
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148 MSR cpsr_c, r0 ; Change the mode
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149 LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
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151 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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152 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
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153 MSR cpsr_c, r0 ; Change the mode
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154 LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
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156 BIC r0 ,r0, #MODE_BITS ; Clear the mode bits
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157 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
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158 MSR cpsr_c, r0 ; Change the mode
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159 LDR sp, =SFE(CSTACK) ; End of CSTACK
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162 ;; Enable the VFP coprocessor.
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164 MOV r0, #0x40000000 ; Set EN bit in VFP
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165 FMXR fpexc, r0 ; FPEXC, clear others.
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168 ; Disable underflow exceptions by setting flush to zero mode.
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169 ; For full IEEE 754 underflow compliance this code should be removed
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170 ; and the appropriate exception handler installed.
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173 MOV r0, #0x01000000 ; Set FZ bit in VFP
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174 FMXR fpscr, r0 ; FPSCR, clear others.
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178 ; Add more initialization here
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180 BIC r0, r0, #MODE_BITS ; Clear the mode bits
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181 ORR r0, r0, #SVC_MODE ; Set SVC mode bits
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182 MSR cpsr_c, r0 ; Change the mode
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184 ; Continue to ?main for C-level initialization.
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