2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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30 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
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33 /* Standard includes. */
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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41 /* Demo application includes. */
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44 /*-----------------------------------------------------------*/
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46 /* Constants to setup and access the UART. */
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47 #define serDLAB ( ( unsigned char ) 0x80 )
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48 #define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 )
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49 #define serNO_PARITY ( ( unsigned char ) 0x00 )
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50 #define ser1_STOP_BIT ( ( unsigned char ) 0x00 )
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51 #define ser8_BIT_CHARS ( ( unsigned char ) 0x03 )
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52 #define serFIFO_ON ( ( unsigned char ) 0x01 )
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53 #define serCLEAR_FIFO ( ( unsigned char ) 0x06 )
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54 #define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 )
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56 /* Constants to setup and access the VIC. */
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57 #define serU0VIC_CHANNEL ( ( unsigned long ) 0x0006 )
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58 #define serU0VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 )
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59 #define serU0VIC_ENABLE ( ( unsigned long ) 0x0020 )
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60 #define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
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62 /* Constants to determine the ISR source. */
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63 #define serSOURCE_THRE ( ( unsigned char ) 0x02 )
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64 #define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
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65 #define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
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66 #define serSOURCE_RX ( ( unsigned char ) 0x04 )
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67 #define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f )
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70 #define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
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71 #define serHANDLE ( ( xComPortHandle ) 1 )
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72 #define serNO_BLOCK ( ( TickType_t ) 0 )
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74 /*-----------------------------------------------------------*/
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76 /* Queues used to hold received characters, and characters waiting to be
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78 static QueueHandle_t xRxedChars;
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79 static QueueHandle_t xCharsForTx;
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80 static volatile long lTHREEmpty = pdFALSE;
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82 /*-----------------------------------------------------------*/
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84 /* The ISR. Note that this is called by a wrapper written in the file
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85 SerialISR.s79. See the WEB documentation for this port for further
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87 __arm void vSerialISR( void );
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89 /*-----------------------------------------------------------*/
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91 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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93 unsigned long ulDivisor, ulWantedClock;
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94 xComPortHandle xReturn = serHANDLE;
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95 extern void ( vSerialISREntry) ( void );
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97 /* Create the queues used to hold Rx and Tx characters. */
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98 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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99 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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101 /* Initialise the THRE empty flag. */
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102 lTHREEmpty = pdTRUE;
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105 ( xRxedChars != serINVALID_QUEUE ) &&
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106 ( xCharsForTx != serINVALID_QUEUE ) &&
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107 ( ulWantedBaud != ( unsigned long ) 0 )
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110 portENTER_CRITICAL();
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112 /* Setup the baud rate: Calculate the divisor value. */
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113 ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
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114 ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
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116 /* Set the DLAB bit so we can access the divisor. */
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119 /* Setup the divisor. */
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120 U0DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
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122 U0DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
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124 /* Turn on the FIFO's and clear the buffers. */
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125 U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
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127 /* Setup transmission format. */
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128 U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
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130 /* Setup the VIC for the UART. */
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131 VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
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132 VICIntEnable |= serU0VIC_CHANNEL_BIT;
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133 VICVectAddr1 = ( unsigned long ) vSerialISREntry;
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134 VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
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136 /* Enable UART0 interrupts. */
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137 U0IER |= serENABLE_INTERRUPTS;
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139 portEXIT_CRITICAL();
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141 xReturn = ( xComPortHandle ) 1;
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145 xReturn = ( xComPortHandle ) 0;
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150 /*-----------------------------------------------------------*/
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152 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
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154 /* The port handle is not required as this driver only supports UART0. */
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157 /* Get the next character from the buffer. Return false if no characters
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158 are available, or arrive before xBlockTime expires. */
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159 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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168 /*-----------------------------------------------------------*/
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170 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
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172 signed char *pxNext;
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174 /* NOTE: This implementation does not handle the queue being full as no
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175 block time is used! */
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177 /* The port handle is not required as this driver only supports UART0. */
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179 ( void ) usStringLength;
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181 /* Send each character in the string, one at a time. */
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182 pxNext = ( signed char * ) pcString;
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185 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
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189 /*-----------------------------------------------------------*/
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191 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
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193 signed portBASE_TYPE xReturn;
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195 /* The port handle is not required as this driver only supports UART0. */
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198 portENTER_CRITICAL();
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200 /* Is there space to write directly to the UART? */
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201 if( lTHREEmpty == ( long ) pdTRUE )
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203 /* We wrote the character directly to the UART, so was
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205 lTHREEmpty = pdFALSE;
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211 /* We cannot write directly to the UART, so queue the character.
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212 Block for a maximum of xBlockTime if there is no space in the
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213 queue. It is ok to block within a critical section as each
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214 task has it's own critical section management. */
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215 xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
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217 /* Depending on queue sizing and task prioritisation: While we
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218 were blocked waiting to post interrupts were not disabled. It is
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219 possible that the serial ISR has emptied the Tx queue, in which
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220 case we need to start the Tx off again. */
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221 if( lTHREEmpty == ( long ) pdTRUE )
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223 xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
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224 lTHREEmpty = pdFALSE;
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229 portEXIT_CRITICAL();
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233 /*-----------------------------------------------------------*/
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235 __arm void vSerialISR( void )
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238 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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240 /* What caused the interrupt? */
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241 switch( U0IIR & serINTERRUPT_SOURCE_MASK )
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243 case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
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247 case serSOURCE_THRE : /* The THRE is empty. If there is another
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248 character in the Tx queue, send it now. */
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249 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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255 /* There are no further characters
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256 queued to send so we can indicate
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257 that the THRE is available. */
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258 lTHREEmpty = pdTRUE;
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262 case serSOURCE_RX_TIMEOUT :
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263 case serSOURCE_RX : /* A character was received. Place it in
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264 the queue of received characters. */
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266 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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269 default : /* There is nothing to do, leave the ISR. */
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273 /* Exit the ISR. If a task was woken by either a character being received
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274 or transmitted then a context switch will occur. */
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275 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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277 /* Clear the ISR in the VIC. */
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278 VICVectAddr = serCLEAR_VIC_INTERRUPT;
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280 /*-----------------------------------------------------------*/
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