1 /******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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2 * File Name : 71x_map.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 05/16/2003
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5 * Description : Peripherals memory mapping and registers structures
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6 ********************************************************************************
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11 *******************************************************************************
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12 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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13 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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14 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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15 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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16 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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17 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *******************************************************************************/
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27 #include "71x_conf.h"
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28 #include "71x_type.h"
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31 /* IP registers structures */
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33 typedef volatile struct
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48 typedef volatile struct
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54 typedef volatile struct
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67 typedef volatile struct
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91 } CAN_MsgObj_TypeDef;
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93 typedef volatile struct
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109 CAN_MsgObj_TypeDef sMsgObj[2];
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129 typedef volatile struct
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144 typedef volatile struct
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156 typedef volatile struct
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166 typedef volatile struct
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174 typedef volatile struct
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186 typedef volatile struct
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205 typedef volatile struct
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216 typedef volatile struct
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231 typedef volatile struct
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254 typedef volatile struct
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273 typedef volatile struct
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296 typedef volatile struct
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321 typedef volatile struct
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338 typedef volatile struct
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359 typedef volatile struct
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361 vu32 T0TIMI_IRQHandler;
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362 vu32 FLASH_IRQHandler;
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363 vu32 RCCU_IRQHandler;
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364 vu32 RTC_IRQHandler;
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365 vu32 WDG_IRQHandler;
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366 vu32 XTI_IRQHandler;
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367 vu32 USBHP_IRQHandler;
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368 vu32 I2C0ITERR_IRQHandler;
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369 vu32 I2C1ITERR_IRQHandler;
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370 vu32 UART0_IRQHandler;
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371 vu32 UART1_IRQHandler;
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372 vu32 UART2_IRQHandler;
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373 vu32 UART3_IRQHandler;
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374 vu32 BSPI0_IRQHandler;
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375 vu32 BSPI1_IRQHandler;
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376 vu32 I2C0_IRQHandler;
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377 vu32 I2C1_IRQHandler;
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378 vu32 CAN_IRQHandler;
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379 vu32 ADC12_IRQHandler;
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380 vu32 T1TIMI_IRQHandler;
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381 vu32 T2TIMI_IRQHandler;
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382 vu32 T3TIMI_IRQHandler;
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384 vu32 HDLC_IRQHandler;
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385 vu32 USBLP_IRQHandler;
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387 vu32 T0TOI_IRQHandler;
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388 vu32 T0OC1_IRQHandler;
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389 vu32 T0OC2_IRQHandler;
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390 } IRQVectors_TypeDef;
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392 /*===================================================================*/
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394 /* Memory mapping */
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396 #define RAM_BASE 0x20000000
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398 #define FLASHR_BASE 0x40100000
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399 #define FLASHPR_BASE 0x4010DFB0
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401 #define EXTMEM_BASE 0x60000000
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402 #define RCCU_BASE 0xA0000000
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403 #define PCU_BASE 0xA0000040
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404 #define APB1_BASE 0xC0000000
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405 #define APB2_BASE 0xE0000000
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406 #define EIC_BASE 0xFFFFF800
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408 #define I2C0_BASE (APB1_BASE + 0x1000)
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409 #define I2C1_BASE (APB1_BASE + 0x2000)
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410 #define UART0_BASE (APB1_BASE + 0x4000)
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411 #define UART1_BASE (APB1_BASE + 0x5000)
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412 #define UART2_BASE (APB1_BASE + 0x6000)
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413 #define UART3_BASE (APB1_BASE + 0x7000)
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414 #define CAN_BASE (APB1_BASE + 0x9000)
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415 #define BSPI0_BASE (APB1_BASE + 0xA000)
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416 #define BSPI1_BASE (APB1_BASE + 0xB000)
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417 #define USB_BASE (APB1_BASE + 0x8800)
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419 #define XTI_BASE (APB2_BASE + 0x101C)
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420 #define GPIO0_BASE (APB2_BASE + 0x3000)
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421 #define GPIO1_BASE (APB2_BASE + 0x4000)
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422 #define GPIO2_BASE (APB2_BASE + 0x5000)
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423 #define ADC12_BASE (APB2_BASE + 0x7000)
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424 #define TIM0_BASE (APB2_BASE + 0x9000)
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425 #define TIM1_BASE (APB2_BASE + 0xA000)
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426 #define TIM2_BASE (APB2_BASE + 0xB000)
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427 #define TIM3_BASE (APB2_BASE + 0xC000)
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428 #define RTC_BASE (APB2_BASE + 0xD000)
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429 #define WDG_BASE (APB2_BASE + 0xE000)
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431 #define EMI_BASE (EXTMEM_BASE + 0x0C000000)
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433 /*===================================================================*/
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435 /* IP data access */
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438 #define ADC12 ((ADC12_TypeDef *)ADC12_BASE)
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440 #define APB1 ((APB_TypeDef *)APB1_BASE)
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441 #define APB2 ((APB_TypeDef *)APB2_BASE+0x10)
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443 #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)
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444 #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)
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446 #define CAN ((CAN_TypeDef *)CAN_BASE)
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448 #define EIC ((EIC_TypeDef *)EIC_BASE)
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450 #define EMI ((EMI_TypeDef *)EMI_BASE)
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452 #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE)
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453 #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)
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455 #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
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456 #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
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457 #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
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459 #define I2C0 ((I2C_TypeDef *)I2C0_BASE)
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460 #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
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462 #define PCU ((PCU_TypeDef *)PCU_BASE)
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464 #define RCCU ((RCCU_TypeDef *)RCCU_BASE)
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466 #define RTC ((RTC_TypeDef *)RTC_BASE)
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468 #define TIM0 ((TIM_TypeDef *)TIM0_BASE)
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469 #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
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470 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
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471 #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
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473 #define UART0 ((UART_TypeDef *)UART0_BASE)
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474 #define UART1 ((UART_TypeDef *)UART1_BASE)
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475 #define UART2 ((UART_TypeDef *)UART2_BASE)
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476 #define UART3 ((UART_TypeDef *)UART3_BASE)
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478 #define USB ((USB_TypeDef *)USB_BASE)
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480 #define WDG ((WDG_TypeDef *)WDG_BASE)
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482 #define XTI ((XTI_TypeDef *)XTI_BASE)
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484 #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)
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489 EXT ADC12_TypeDef *ADC12;
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494 EXT APB_TypeDef *APB1;
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497 EXT APB_TypeDef *APB2;
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503 EXT BSPI_TypeDef *BSPI0;
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506 EXT BSPI_TypeDef *BSPI1;
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511 EXT CAN_TypeDef *CAN;
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515 EXT EIC_TypeDef *EIC;
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519 EXT EMI_TypeDef *EMI;
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523 EXT FLASHR_TypeDef *FLASHR;
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524 EXT FLASHPR_TypeDef *FLASHPR;
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529 EXT GPIO_TypeDef *GPIO0;
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532 EXT GPIO_TypeDef *GPIO1;
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535 EXT GPIO_TypeDef *GPIO2;
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541 EXT I2C_TypeDef *I2C0;
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544 EXT I2C_TypeDef *I2C1;
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549 EXT PCU_TypeDef *PCU;
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553 EXT RCCU_TypeDef *RCCU;
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557 EXT RTC_TypeDef *RTC;
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562 EXT TIM_TypeDef *TIM0;
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565 EXT TIM_TypeDef *TIM1;
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568 EXT TIM_TypeDef *TIM2;
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571 EXT TIM_TypeDef *TIM3;
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577 EXT UART_TypeDef *UART0;
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580 EXT UART_TypeDef *UART1;
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583 EXT UART_TypeDef *UART2;
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586 EXT UART_TypeDef *UART3;
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591 EXT USB_TypeDef *USB;
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595 EXT WDG_TypeDef *WDG;
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599 EXT XTI_TypeDef *XTI;
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603 EXT IRQVectors_TypeDef *IRQVectors;
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608 #endif /* __71x_map_H */
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610 /******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/
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