1 ;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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2 ;* File Name : 91x_init.s
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3 ;* Author : MCD Application Team
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4 ;* Date First Issued : 05/18/2006 : Version 1.0
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5 ;* Description : This module performs:
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6 ;* - FLASH/RAM initialization,
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7 ;* - Stack pointer initialization for each mode ,
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8 ;* - Branches to ?main in the C library (which eventually
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11 ;* On reset, the ARM core starts up in Supervisor (SVC) mode,
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12 ;* in ARM state,with IRQ and FIQ disabled.
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13 ;*******************************************************************************
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15 ; 05/24/2006 : Version 1.1
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16 ; 05/18/2006 : Version 1.0
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17 ;*******************************************************************************
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18 ;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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19 ;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
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20 ;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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21 ;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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22 ;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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23 ;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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24 ;******************************************************************************/
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26 ; Depending in Your Application, Disable or Enable the following Define
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28 ; #define BUFFERED_Mode ; Work on Buffered mode, when enabling this define
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29 ; just enable the Buffered define on 91x_conf.h
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31 ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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39 Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
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41 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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42 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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45 ; System memory locations
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47 SRAM_Base EQU 0x04000000
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48 SRAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM
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50 SVC_Stack DEFINE SRAM_Limit ; 512 byte SVC stack at
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51 ; top of memory - used by kernel.
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52 IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack
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53 USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in
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54 ; system mode but task stacks are allocated
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55 ; when the task is created.
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56 FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack
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57 ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack
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58 UND_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack
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62 ; STR9X register specific definition
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64 FMI_BBSR_AHB_UB EQU 0x54000000
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65 FMI_BBADR_AHB_UB EQU 0x5400000C
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66 FMI_NBBSR_AHB_UB EQU 0x54000004
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67 FMI_NBBADR_AHB_UB EQU 0x54000010
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69 SCU_SCRO_APB1_UB EQU 0x4C002034
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70 SCRO_AHB_UNB EQU 0x5C002034
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74 ;---------------------------------------------------------------
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76 ;---------------------------------------------------------------
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77 MODULE ?program_start
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80 PUBLIC __program_start
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92 NOP ; execute some instructions to access CPU registers after wake
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93 NOP ; up from Reset, while waiting for OSC stabilization
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101 ldr r0,=LINK ; to include the vector table inside the final executable.
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105 ; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
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106 ; when the bank 0 is the boot bank, then enable the Bank 1.
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108 LDR R6, =0x54000000
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112 LDR R6, =0x54000004
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116 LDR R6, =0x5400000C
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120 LDR R6, =0x54000010
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124 LDR R6, =0x54000018
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128 ; --- Enable 96K RAM
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129 LDR R0, = SCRO_AHB_UNB
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134 /* Setup a stack for each mode - note that this only sets up a usable stack
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135 for system/user, SWI and IRQ modes. Also each mode is setup with
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136 interrupts initially disabled. */
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138 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
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141 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
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144 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
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147 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
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150 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
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153 MSR CPSR_c, #Mode_SYS|I_Bit|F_Bit ; No interrupts
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156 /* We want to start in supervisor mode. Operation will switch to system
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157 mode when the first task starts. */
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158 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
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161 ; --- Set bits 17-18 of the Core Configuration Control Register
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164 MCR p15,0x1,r0,c15,c1,0
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167 ; --- Now enter the C code
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168 B ?main ; Note : use B not BL, because an application will
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169 ; never return this way
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174 ;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
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