2 FreeRTOS V7.4.1 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
\r
5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
10 * Complete, revised, and edited pdf reference manuals are also *
\r
13 * Purchasing FreeRTOS documentation will not only help you, by *
\r
14 * ensuring you get running as quickly as possible and with an *
\r
15 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
16 * the FreeRTOS project to continue with its mission of providing *
\r
17 * professional grade, cross platform, de facto standard solutions *
\r
18 * for microcontrollers - completely free of charge! *
\r
20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
22 * Thank you for using FreeRTOS, and thank you for your support! *
\r
24 ***************************************************************************
\r
27 This file is part of the FreeRTOS distribution.
\r
29 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
30 the terms of the GNU General Public License (version 2) as published by the
\r
31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
\r
34 distribute a combined work that includes FreeRTOS without being obliged to
\r
35 provide the source code for proprietary components outside of the FreeRTOS
\r
38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
\r
41 details. You should have received a copy of the GNU General Public License
\r
42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
\r
43 viewed here: http://www.freertos.org/a00114.html and also obtained by
\r
44 writing to Real Time Engineers Ltd., contact details for whom are available
\r
45 on the FreeRTOS WEB site.
\r
49 ***************************************************************************
\r
51 * Having a problem? Start by reading the FAQ "My application does *
\r
52 * not run, what could be wrong?" *
\r
54 * http://www.FreeRTOS.org/FAQHelp.html *
\r
56 ***************************************************************************
\r
59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
60 license and Real Time Engineers Ltd. contact details.
\r
62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
\r
64 fully thread aware and reentrant UDP/IP stack.
\r
66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
67 Integrity Systems, who sell the code with commercial support,
\r
68 indemnification and middleware, under the OpenRTOS brand.
\r
70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
71 engineered and independently SIL3 certified version for use in safety and
\r
72 mission critical applications that require provable dependability.
\r
76 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART1.
\r
79 /* Library includes. */
\r
80 #include "91x_lib.h"
\r
82 /* Scheduler includes. */
\r
83 #include "FreeRTOS.h"
\r
87 /* Demo application includes. */
\r
89 /*-----------------------------------------------------------*/
\r
92 #define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
\r
93 #define serNO_BLOCK ( ( portTickType ) 0 )
\r
94 #define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS )
\r
96 /* Interrupt and status bit definitions. */
\r
97 #define mainTXRIS 0x20
\r
98 #define mainRXRIS 0x50
\r
99 #define serTX_FIFO_FULL 0x20
\r
100 #define serCLEAR_ALL_INTERRUPTS 0x3ff
\r
101 /*-----------------------------------------------------------*/
\r
103 /* The queue used to hold received characters. */
\r
104 static xQueueHandle xRxedChars;
\r
106 /* The semaphore used to wake a task waiting for space to become available
\r
108 static xSemaphoreHandle xTxFIFOSemaphore;
\r
110 /*-----------------------------------------------------------*/
\r
112 /* UART interrupt handler. */
\r
113 void UART1_IRQHandler( void );
\r
115 /* The interrupt service routine - called from the assembly entry point. */
\r
116 __arm void UART1_IRQHandler( void );
\r
118 /*-----------------------------------------------------------*/
\r
120 /* Flag to indicate whether or not a task is blocked waiting for space on
\r
122 static long lTaskWaiting = pdFALSE;
\r
125 * See the serial2.h header file.
\r
127 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
\r
129 xComPortHandle xReturn;
\r
130 UART_InitTypeDef xUART1_Init;
\r
131 GPIO_InitTypeDef GPIO_InitStructure;
\r
133 /* Create the queues used to hold Rx characters. */
\r
134 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
\r
136 /* Create the semaphore used to wake a task waiting for space to become
\r
137 available in the FIFO. */
\r
138 vSemaphoreCreateBinary( xTxFIFOSemaphore );
\r
140 /* If the queue/semaphore was created correctly then setup the serial port
\r
142 if( ( xRxedChars != serINVALID_QUEUE ) && ( xTxFIFOSemaphore != serINVALID_QUEUE ) )
\r
144 /* Pre take the semaphore so a task will block if it tries to access
\r
146 xSemaphoreTake( xTxFIFOSemaphore, 0 );
\r
148 /* Configure the UART. */
\r
149 xUART1_Init.UART_WordLength = UART_WordLength_8D;
\r
150 xUART1_Init.UART_StopBits = UART_StopBits_1;
\r
151 xUART1_Init.UART_Parity = UART_Parity_No;
\r
152 xUART1_Init.UART_BaudRate = ulWantedBaud;
\r
153 xUART1_Init.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
\r
154 xUART1_Init.UART_Mode = UART_Mode_Tx_Rx;
\r
155 xUART1_Init.UART_FIFO = UART_FIFO_Enable;
\r
157 /* Enable the UART1 Clock */
\r
158 SCU_APBPeriphClockConfig( __UART1, ENABLE );
\r
160 /* Enable the GPIO3 Clock */
\r
161 SCU_APBPeriphClockConfig( __GPIO3, ENABLE );
\r
163 /* Configure UART1_Rx pin GPIO3.2 */
\r
164 GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
\r
165 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
\r
166 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
\r
167 GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
\r
168 GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
\r
169 GPIO_Init( GPIO3, &GPIO_InitStructure );
\r
171 /* Configure UART1_Tx pin GPIO3.3 */
\r
172 GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
\r
173 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
\r
174 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
\r
175 GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
\r
176 GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
\r
177 GPIO_Init( GPIO3, &GPIO_InitStructure );
\r
180 portENTER_CRITICAL();
\r
182 /* Configure the UART itself. */
\r
183 UART_DeInit( UART1 );
\r
184 UART_Init( UART1, &xUART1_Init );
\r
185 UART_ITConfig( UART1, UART_IT_Receive | UART_IT_Transmit, ENABLE );
\r
186 UART1->ICR = serCLEAR_ALL_INTERRUPTS;
\r
187 UART_LoopBackConfig( UART1, DISABLE );
\r
188 UART_IrDACmd( IrDA1, DISABLE );
\r
190 /* Configure the VIC for the UART interrupts. */
\r
191 VIC_Config( UART1_ITLine, VIC_IRQ, 9 );
\r
192 VIC_ITCmd( UART1_ITLine, ENABLE );
\r
194 UART_Cmd( UART1, ENABLE );
\r
195 lTaskWaiting = pdFALSE;
\r
197 portEXIT_CRITICAL();
\r
201 xReturn = ( xComPortHandle ) 0;
\r
204 /* This demo file only supports a single port but we have to return
\r
205 something to comply with the standard demo header file. */
\r
208 /*-----------------------------------------------------------*/
\r
210 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
\r
212 /* The port handle is not required as this driver only supports one port. */
\r
215 /* Get the next character from the buffer. Return false if no characters
\r
216 are available, or arrive before xBlockTime expires. */
\r
217 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
\r
226 /*-----------------------------------------------------------*/
\r
228 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
\r
230 signed char *pxNext;
\r
232 /* A couple of parameters that this port does not use. */
\r
233 ( void ) usStringLength;
\r
236 /* NOTE: This implementation does not handle the queue being full as no
\r
237 block time is used! */
\r
239 /* The port handle is not required as this driver only supports UART1. */
\r
242 /* Send each character in the string, one at a time. */
\r
243 pxNext = ( signed char * ) pcString;
\r
246 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
\r
250 /*-----------------------------------------------------------*/
\r
252 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
\r
254 portBASE_TYPE xReturn;
\r
256 portENTER_CRITICAL();
\r
258 /* Can we write to the FIFO? */
\r
259 if( UART1->FR & serTX_FIFO_FULL )
\r
261 /* Wait for the interrupt letting us know there is space on the
\r
262 FIFO. It is ok to block in a critical section, interrupts will be
\r
263 enabled for other tasks once we force a switch. */
\r
264 lTaskWaiting = pdTRUE;
\r
266 /* Just to be a bit different this driver uses a semaphore to
\r
267 block the sending task when the FIFO is full. The standard COMTest
\r
268 task assumes a queue of adequate length exists so does not use
\r
269 a block time. For this demo the block time is therefore hard
\r
271 xReturn = xSemaphoreTake( xTxFIFOSemaphore, serTX_BLOCK_TIME );
\r
274 UART1->DR = cOutChar;
\r
279 UART1->DR = cOutChar;
\r
283 portEXIT_CRITICAL();
\r
287 /*-----------------------------------------------------------*/
\r
289 void vSerialClose( xComPortHandle xPort )
\r
291 /* Not supported as not required by the demo application. */
\r
293 /*-----------------------------------------------------------*/
\r
295 void UART1_IRQHandler( void )
\r
298 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
300 while( UART1->RIS & mainRXRIS )
\r
302 /* The interrupt was caused by a character being received. Grab the
\r
303 character from the DR and place it in the queue of received
\r
306 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
\r
309 if( UART1->RIS & mainTXRIS )
\r
311 if( lTaskWaiting == pdTRUE )
\r
313 /* This interrupt was caused by space becoming available on the Tx
\r
314 FIFO, wake any task that is waiting to post (if any). */
\r
315 xSemaphoreGiveFromISR( xTxFIFOSemaphore, &xHigherPriorityTaskWoken );
\r
316 lTaskWaiting = pdFALSE;
\r
319 UART1->ICR = mainTXRIS;
\r
322 /* If a task was woken by either a character being received or a character
\r
323 being transmitted then we may need to switch to another task. */
\r
324 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
\r