1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief GPIO header for AVR32 UC3.
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6 * This file contains basic GPIO driver functions.
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8 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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9 * - Supported devices: All AVR32 devices with a GPIO module can be used.
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12 * \author Atmel Corporation: http://www.atmel.com \n
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13 * Support and FAQ: http://support.atmel.no/
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15 *****************************************************************************/
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17 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
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19 * Redistribution and use in source and binary forms, with or without
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20 * modification, are permitted provided that the following conditions are met:
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22 * 1. Redistributions of source code must retain the above copyright notice,
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23 * this list of conditions and the following disclaimer.
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25 * 2. Redistributions in binary form must reproduce the above copyright notice,
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26 * this list of conditions and the following disclaimer in the documentation
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27 * and/or other materials provided with the distribution.
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29 * 3. The name of ATMEL may not be used to endorse or promote products derived
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30 * from this software without specific prior written permission.
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32 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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33 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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34 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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35 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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36 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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48 #include <avr32/io.h>
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51 /*! \name Return Values of the GPIO API
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54 #define GPIO_SUCCESS 0 //!< Function successfully completed.
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55 #define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range.
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59 /*! \name Interrupt Trigger Modes
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62 #define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change.
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63 #define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge.
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64 #define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge.
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68 //! A type definition of pins and modules connectivity.
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71 unsigned char pin; //!< Module pin.
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72 unsigned char function; //!< Module function.
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76 /*! \brief Enables specific module modes for a set of pins.
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78 * \param gpiomap The pin map.
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79 * \param size The number of pins in \a gpiomap.
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81 * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
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83 extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
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85 /*! \brief Enables a specific module mode for a pin.
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87 * \param pin The pin number.\n
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88 * Refer to the product header file `uc3x.h' (where x is the part
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89 * number; e.g. x = a0512) for module pins. E.g., to enable a PWM
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90 * channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM
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92 * \param function The pin function.\n
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93 * Refer to the product header file `uc3x.h' (where x is the
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94 * part number; e.g. x = a0512) for module pin functions. E.g.,
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95 * to enable a PWM channel output, the pin function can be
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96 * AVR32_PWM_PWM_3_FUNCTION for PWM channel 3.
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98 * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
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100 extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);
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102 /*! \brief Enables the GPIO mode of a set of pins.
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104 * \param gpiomap The pin map.
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105 * \param size The number of pins in \a gpiomap.
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107 extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
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109 /*! \brief Enables the GPIO mode of a pin.
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111 * \param pin The pin number.\n
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112 * Refer to the product header file `uc3x.h' (where x is the part
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113 * number; e.g. x = a0512) for pin definitions. E.g., to enable the
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114 * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
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115 * AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release
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116 * module pins for GPIO.
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118 extern void gpio_enable_gpio_pin(unsigned int pin);
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120 /*! \brief Enables the open-drain mode of a pin.
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122 * \param pin The pin number.
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124 extern void gpio_enable_pin_open_drain(unsigned int pin);
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126 /*! \brief Disables the open-drain mode of a pin.
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128 * \param pin The pin number.
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130 extern void gpio_disable_pin_open_drain(unsigned int pin);
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132 /*! \brief Enables the pull-up resistor of a pin.
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134 * \param pin The pin number.
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136 extern void gpio_enable_pin_pull_up(unsigned int pin);
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138 /*! \brief Disables the pull-up resistor of a pin.
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140 * \param pin The pin number.
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142 extern void gpio_disable_pin_pull_up(unsigned int pin);
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144 /*! \brief Returns the value of a pin.
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146 * \param pin The pin number.
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148 * \return The pin value.
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150 extern int gpio_get_pin_value(unsigned int pin);
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152 /*! \brief Returns the output value set for a GPIO pin.
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154 * \param pin The pin number.
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156 * \return The pin output value.
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158 extern int gpio_get_gpio_pin_output_value(unsigned int pin);
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160 /*! \brief Drives a GPIO pin to 1.
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162 * \param pin The pin number.
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164 extern void gpio_set_gpio_pin(unsigned int pin);
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166 /*! \brief Drives a GPIO pin to 0.
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168 * \param pin The pin number.
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170 extern void gpio_clr_gpio_pin(unsigned int pin);
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172 /*! \brief Toggles a GPIO pin.
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174 * \param pin The pin number.
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176 extern void gpio_tgl_gpio_pin(unsigned int pin);
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178 /*! \brief Enables the glitch filter of a pin.
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180 * When the glitch filter is enabled, a glitch with duration of less than 1
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181 * clock cycle is automatically rejected, while a pulse with duration of 2 clock
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182 * cycles or more is accepted. For pulse durations between 1 clock cycle and 2
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183 * clock cycles, the pulse may or may not be taken into account, depending on
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184 * the precise timing of its occurrence. Thus for a pulse to be guaranteed
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185 * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
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186 * filtered out, its duration must not exceed 1 clock cycle. The filter
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187 * introduces 2 clock cycles latency.
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189 * \param pin The pin number.
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191 extern void gpio_enable_pin_glitch_filter(unsigned int pin);
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193 /*! \brief Disables the glitch filter of a pin.
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195 * \param pin The pin number.
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197 extern void gpio_disable_pin_glitch_filter(unsigned int pin);
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199 /*! \brief Enables the interrupt of a pin with the specified settings.
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201 * \param pin The pin number.
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202 * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
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203 * \ref GPIO_FALLING_EDGE).
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205 * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
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207 extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);
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209 /*! \brief Disables the interrupt of a pin.
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211 * \param pin The pin number.
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213 extern void gpio_disable_pin_interrupt(unsigned int pin);
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215 /*! \brief Gets the interrupt flag of a pin.
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217 * \param pin The pin number.
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219 * \return The pin interrupt flag.
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221 extern int gpio_get_pin_interrupt_flag(unsigned int pin);
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223 /*! \brief Clears the interrupt flag of a pin.
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225 * \param pin The pin number.
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227 extern void gpio_clear_pin_interrupt_flag(unsigned int pin);
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