2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * NOTE: Currently only timer 1 and timer 2 are used -
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31 * This file initialises two timers as follows:
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33 * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ
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34 * standard demo tasks, which test interrupt nesting and using queues from
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35 * interrupts. Both these interrupts operate below the maximum syscall
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36 * interrupt priority.
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38 * Timer 2 is a much higher frequency timer that tests the nesting of interrupts
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39 * that execute above the maximum syscall interrupt priority.
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41 * All the timers can nest with the tick interrupt - creating a maximum
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42 * interrupt nesting depth of 4.
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44 * For convenience, the high frequency timer is also used to provide the time
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45 * base for the run time stats.
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48 /* Scheduler includes. */
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49 #include "FreeRTOS.h"
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51 /* Demo includes. */
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52 #include "IntQueueTimer.h"
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53 #include "IntQueue.h"
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55 /* Xilinx includes. */
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57 #include "xscugic.h"
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59 /* The frequencies at which the first two timers expire are slightly offset to
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60 ensure they don't remain synchronised. The frequency of the interrupt that
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61 operates above the max syscall interrupt priority is 10 times faster so really
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62 hammers the interrupt entry and exit code. */
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63 #define tmrTIMERS_USED 3
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64 #define tmrTIMER_0_FREQUENCY ( 100UL )
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65 #define tmrTIMER_1_FREQUENCY ( 111UL )
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66 #define tmrTIMER_2_FREQUENCY ( 20000UL )
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68 /*-----------------------------------------------------------*/
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71 * The single interrupt service routines that is used to service all three
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74 static void prvTimerHandler( void *CallBackRef );
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76 /*-----------------------------------------------------------*/
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78 /* Hardware constants. */
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79 static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };
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80 static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };
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82 /* Timer configuration settings. */
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85 uint32_t OutputHz; /* Output frequency. */
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86 uint16_t Interval; /* Interval value. */
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87 uint8_t Prescaler; /* Prescaler value. */
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88 uint16_t Options; /* Option settings. */
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91 static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =
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93 { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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94 { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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95 { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }
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98 /* Lower priority number means higher logical priority, so
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99 configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call
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100 interrupt priority. */
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101 static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =
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103 configMAX_API_CALL_INTERRUPT_PRIORITY + 1,
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104 configMAX_API_CALL_INTERRUPT_PRIORITY,
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105 configMAX_API_CALL_INTERRUPT_PRIORITY - 1
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108 static XTtcPs xTimerInstances[ tmrTIMERS_USED ];
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110 /* Used to provide a means of ensuring the intended interrupt nesting depth is
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111 actually being reached. */
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112 extern uint64_t ullPortInterruptNesting;
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113 static volatile uint32_t ulMaxRecordedNesting = 1;
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115 /* Used to ensure the high frequency timer is running at the expected
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117 static volatile uint32_t ulHighFrequencyTimerCounts = 0;
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119 /*-----------------------------------------------------------*/
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121 void vInitialiseTimerForIntQueueTest( void )
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123 BaseType_t xStatus;
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124 TmrCntrSetup *pxTimerSettings;
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125 extern XScuGic xInterruptController;
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127 XTtcPs *pxTimerInstance;
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128 XTtcPs_Config *pxTimerConfiguration;
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129 const uint8_t ucRisingEdge = 3;
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131 /*_RB_ Currently only timer 1 and timer 2 are used. */
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132 for( xTimer = 0; xTimer < ( tmrTIMERS_USED - 1 ); xTimer++ )
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134 /* Look up the timer's configuration. */
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135 pxTimerInstance = &( xTimerInstances[ xTimer ] );
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136 pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
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137 configASSERT( pxTimerConfiguration );
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139 pxTimerSettings = &( xTimerSettings[ xTimer ] );
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141 /* Initialise the device. */
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142 xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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143 if( xStatus != XST_SUCCESS )
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145 /* Not sure how to do this before XTtcPs_CfgInitialize is called
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146 as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
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147 XTtcPs_Stop( pxTimerInstance );
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148 xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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149 configASSERT( xStatus == XST_SUCCESS );
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152 /* Set the options. */
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153 XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
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155 /* The timer frequency is preset in the pxTimerSettings structure.
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156 Derive the values for the other structure members. */
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157 XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
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159 /* Set the interval and prescale. */
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160 XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
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161 XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
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163 /* The priority must be the lowest possible. */
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164 XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
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166 /* Connect to the interrupt controller. */
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167 xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
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168 configASSERT( xStatus == XST_SUCCESS);
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170 /* Enable the interrupt in the GIC. */
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171 XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
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173 /* Enable the interrupts in the timer. */
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174 XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
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176 /* Start the timer. */
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177 XTtcPs_Start( pxTimerInstance );
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180 /*-----------------------------------------------------------*/
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182 static void prvTimerHandler( void *pvCallBackRef )
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184 uint32_t ulInterruptStatus;
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185 XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;
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186 BaseType_t xYieldRequired;
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188 /* Read the interrupt status, then write it back to clear the interrupt. */
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189 ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );
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190 XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus );
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191 __asm volatile( "DSB SY" );
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192 __asm volatile( "ISB SY" );
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195 /* Now the interrupt has been cleared, interrupts can be re-enabled. */
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196 portENABLE_INTERRUPTS();
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198 /* Only one interrupt event type is expected. */
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199 configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );
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201 /* Check the device ID to know which IntQueue demo to call. */
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202 if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )
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204 xYieldRequired = xFirstTimerHandler();
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206 else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )
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208 xYieldRequired = xSecondTimerHandler();
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212 /* Used to check the timer is running at the expected frequency. */
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213 ulHighFrequencyTimerCounts++;
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214 xYieldRequired = pdFALSE;
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217 /* Latch the highest interrupt nesting count detected. */
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218 if( ullPortInterruptNesting > ulMaxRecordedNesting )
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220 ulMaxRecordedNesting = ullPortInterruptNesting;
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223 /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()
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224 or xSecondTimerHandler() resulted in a task leaving the blocked state and
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225 the task that left the blocked state had a priority higher than the currently
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226 running task (the task this interrupt interrupted) - so a context switch
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227 should be performed so the interrupt returns directly to the higher priority
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228 task. xYieldRequired is tested inside the following macro. */
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229 portYIELD_FROM_ISR( xYieldRequired );
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