1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
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9 /* Description : Cortex-A53 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
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17 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
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18 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
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20 /* Define Memories in the system */
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24 psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x7FF00000
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25 psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
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26 psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
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27 psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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30 /* Specify the default entry point to the program */
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32 ENTRY(_vector_table)
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34 /* Define the sections, and where they are mapped in memory */
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43 *(.gnu.linkonce.t.*)
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46 *(.gcc_execpt_table)
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50 *(.gnu.linkonce.armextab.*)
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53 .init (ALIGN(64)) : {
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57 .fini (ALIGN(64)) : {
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66 KEEP (*(.note-ABI-tag))
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74 *(.gnu.linkonce.r.*)
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80 __rodata1_start = .;
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91 *(.gnu.linkonce.s2.*)
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100 *(.gnu.linkonce.sb2.*)
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102 } > psu_ddr_0_MEM_0
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109 *(.gnu.linkonce.d.*)
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114 } > psu_ddr_0_MEM_0
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122 } > psu_ddr_0_MEM_0
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126 } > psu_ddr_0_MEM_0
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130 } > psu_ddr_0_MEM_0
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134 } > psu_ddr_0_MEM_0
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139 ___CTORS_LIST___ = .;
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140 KEEP (*crtbegin.o(.ctors))
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141 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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142 KEEP (*(SORT(.ctors.*)))
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145 ___CTORS_END___ = .;
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146 } > psu_ddr_0_MEM_0
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151 ___DTORS_LIST___ = .;
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152 KEEP (*crtbegin.o(.dtors))
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153 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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154 KEEP (*(SORT(.dtors.*)))
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157 ___DTORS_END___ = .;
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158 } > psu_ddr_0_MEM_0
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164 } > psu_ddr_0_MEM_0
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168 } > psu_ddr_0_MEM_0
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171 __eh_framehdr_start = .;
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173 __eh_framehdr_end = .;
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174 } > psu_ddr_0_MEM_0
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176 .gcc_except_table : {
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177 *(.gcc_except_table)
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178 } > psu_ddr_0_MEM_0
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180 .mmu_tbl0 (ALIGN(4096)) : {
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181 __mmu_tbl0_start = .;
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183 __mmu_tbl0_end = .;
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184 } > psu_ddr_0_MEM_0
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186 .mmu_tbl1 (ALIGN(4096)) : {
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187 __mmu_tbl1_start = .;
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189 __mmu_tbl1_end = .;
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190 } > psu_ddr_0_MEM_0
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192 .mmu_tbl2 (ALIGN(4096)) : {
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193 __mmu_tbl2_start = .;
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195 __mmu_tbl2_end = .;
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196 } > psu_ddr_0_MEM_0
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201 *(.gnu.linkonce.armexidix.*.*)
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203 } > psu_ddr_0_MEM_0
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207 __preinit_array_start = .;
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208 KEEP (*(SORT(.preinit_array.*)))
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209 KEEP (*(.preinit_array))
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210 __preinit_array_end = .;
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211 } > psu_ddr_0_MEM_0
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215 __init_array_start = .;
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216 KEEP (*(SORT(.init_array.*)))
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217 KEEP (*(.init_array))
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218 __init_array_end = .;
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219 } > psu_ddr_0_MEM_0
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223 __fini_array_start = .;
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224 KEEP (*(SORT(.fini_array.*)))
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225 KEEP (*(.fini_array))
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226 __fini_array_end = .;
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227 } > psu_ddr_0_MEM_0
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229 .ARM.attributes : {
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230 __ARM.attributes_start = .;
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232 __ARM.attributes_end = .;
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233 } > psu_ddr_0_MEM_0
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240 *(.gnu.linkonce.s.*)
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242 } > psu_ddr_0_MEM_0
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249 *(.gnu.linkonce.sb.*)
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252 } > psu_ddr_0_MEM_0
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259 *(.gnu.linkonce.td.*)
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261 } > psu_ddr_0_MEM_0
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268 *(.gnu.linkonce.tb.*)
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270 } > psu_ddr_0_MEM_0
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277 *(.gnu.linkonce.b.*)
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281 } > psu_ddr_0_MEM_0
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283 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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285 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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287 /* Generate Stack and Heap definitions */
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297 } > psu_ddr_0_MEM_0
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299 .stack (NOLOAD) : {
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301 _el3_stack_end = .;
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304 _el2_stack_end = .;
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305 . += _EL2_STACK_SIZE;
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308 _el1_stack_end = .;
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309 . += _EL1_STACK_SIZE;
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312 _el0_stack_end = .;
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313 . += _EL0_STACK_SIZE;
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316 } > psu_ddr_0_MEM_0
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