1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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9 /* Description : Cortex-A53 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
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17 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
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18 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
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20 /* Define Memories in the system */
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24 psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
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25 psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x80000000
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26 psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
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27 psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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28 psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
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29 psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
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30 psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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33 /* Specify the default entry point to the program */
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35 ENTRY(_vector_table)
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37 /* Define the sections, and where they are mapped in memory */
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46 *(.gnu.linkonce.t.*)
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49 *(.gcc_execpt_table)
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53 *(.gnu.linkonce.armextab.*)
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54 } > psu_ddr_0_S_AXI_BASEADDR
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56 .init (ALIGN(64)) : {
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58 } > psu_ddr_0_S_AXI_BASEADDR
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60 .fini (ALIGN(64)) : {
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62 } > psu_ddr_0_S_AXI_BASEADDR
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66 } > psu_ddr_0_S_AXI_BASEADDR
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69 KEEP (*(.note-ABI-tag))
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70 } > psu_ddr_0_S_AXI_BASEADDR
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77 *(.gnu.linkonce.r.*)
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79 } > psu_ddr_0_S_AXI_BASEADDR
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83 __rodata1_start = .;
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87 } > psu_ddr_0_S_AXI_BASEADDR
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94 *(.gnu.linkonce.s2.*)
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96 } > psu_ddr_0_S_AXI_BASEADDR
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103 *(.gnu.linkonce.sb2.*)
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105 } > psu_ddr_0_S_AXI_BASEADDR
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112 *(.gnu.linkonce.d.*)
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117 } > psu_ddr_0_S_AXI_BASEADDR
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125 } > psu_ddr_0_S_AXI_BASEADDR
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129 } > psu_ddr_0_S_AXI_BASEADDR
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133 } > psu_ddr_0_S_AXI_BASEADDR
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137 } > psu_ddr_0_S_AXI_BASEADDR
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142 ___CTORS_LIST___ = .;
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143 KEEP (*crtbegin.o(.ctors))
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144 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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145 KEEP (*(SORT(.ctors.*)))
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148 ___CTORS_END___ = .;
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149 } > psu_ddr_0_S_AXI_BASEADDR
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154 ___DTORS_LIST___ = .;
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155 KEEP (*crtbegin.o(.dtors))
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156 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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157 KEEP (*(SORT(.dtors.*)))
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160 ___DTORS_END___ = .;
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161 } > psu_ddr_0_S_AXI_BASEADDR
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167 } > psu_ddr_0_S_AXI_BASEADDR
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171 } > psu_ddr_0_S_AXI_BASEADDR
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174 __eh_framehdr_start = .;
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176 __eh_framehdr_end = .;
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177 } > psu_ddr_0_S_AXI_BASEADDR
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179 .gcc_except_table : {
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180 *(.gcc_except_table)
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181 } > psu_ddr_0_S_AXI_BASEADDR
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183 .mmu_tbl0 (ALIGN(4096)) : {
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184 __mmu_tbl0_start = .;
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186 __mmu_tbl0_end = .;
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187 } > psu_ddr_0_S_AXI_BASEADDR
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189 .mmu_tbl1 (ALIGN(4096)) : {
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190 __mmu_tbl1_start = .;
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192 __mmu_tbl1_end = .;
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193 } > psu_ddr_0_S_AXI_BASEADDR
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195 .mmu_tbl2 (ALIGN(4096)) : {
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196 __mmu_tbl2_start = .;
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198 __mmu_tbl2_end = .;
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199 } > psu_ddr_0_S_AXI_BASEADDR
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204 *(.gnu.linkonce.armexidix.*.*)
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206 } > psu_ddr_0_S_AXI_BASEADDR
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210 __preinit_array_start = .;
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211 KEEP (*(SORT(.preinit_array.*)))
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212 KEEP (*(.preinit_array))
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213 __preinit_array_end = .;
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214 } > psu_ddr_0_S_AXI_BASEADDR
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218 __init_array_start = .;
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219 KEEP (*(SORT(.init_array.*)))
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220 KEEP (*(.init_array))
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221 __init_array_end = .;
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222 } > psu_ddr_0_S_AXI_BASEADDR
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226 __fini_array_start = .;
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227 KEEP (*(SORT(.fini_array.*)))
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228 KEEP (*(.fini_array))
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229 __fini_array_end = .;
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230 } > psu_ddr_0_S_AXI_BASEADDR
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232 .ARM.attributes : {
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233 __ARM.attributes_start = .;
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235 __ARM.attributes_end = .;
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236 } > psu_ddr_0_S_AXI_BASEADDR
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243 *(.gnu.linkonce.s.*)
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245 } > psu_ddr_0_S_AXI_BASEADDR
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252 *(.gnu.linkonce.sb.*)
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255 } > psu_ddr_0_S_AXI_BASEADDR
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262 *(.gnu.linkonce.td.*)
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264 } > psu_ddr_0_S_AXI_BASEADDR
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271 *(.gnu.linkonce.tb.*)
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273 } > psu_ddr_0_S_AXI_BASEADDR
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280 *(.gnu.linkonce.b.*)
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284 } > psu_ddr_0_S_AXI_BASEADDR
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286 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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288 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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290 /* Generate Stack and Heap definitions */
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300 } > psu_ddr_0_S_AXI_BASEADDR
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302 .stack (NOLOAD) : {
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304 _el3_stack_end = .;
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307 _el2_stack_end = .;
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308 . += _EL2_STACK_SIZE;
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311 _el1_stack_end = .;
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312 . += _EL1_STACK_SIZE;
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315 _el0_stack_end = .;
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316 . += _EL0_STACK_SIZE;
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319 } > psu_ddr_0_S_AXI_BASEADDR
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