1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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9 /* Description : Cortex-A53 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
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17 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
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18 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
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20 /* Define Memories in the system */
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24 psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
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25 psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x80000000
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26 psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
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27 psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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28 psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
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29 psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
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30 psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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33 /* Specify the default entry point to the program */
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35 ENTRY(_vector_table)
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37 /* Define the sections, and where they are mapped in memory */
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43 KEEP (*(.freertos_vectors))
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47 *(.gnu.linkonce.t.*)
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50 *(.gcc_execpt_table)
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54 *(.gnu.linkonce.armextab.*)
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55 } > psu_ddr_0_S_AXI_BASEADDR
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57 .init (ALIGN(64)) : {
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59 } > psu_ddr_0_S_AXI_BASEADDR
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61 .fini (ALIGN(64)) : {
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63 } > psu_ddr_0_S_AXI_BASEADDR
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67 } > psu_ddr_0_S_AXI_BASEADDR
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70 KEEP (*(.note-ABI-tag))
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71 } > psu_ddr_0_S_AXI_BASEADDR
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78 *(.gnu.linkonce.r.*)
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80 } > psu_ddr_0_S_AXI_BASEADDR
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84 __rodata1_start = .;
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88 } > psu_ddr_0_S_AXI_BASEADDR
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95 *(.gnu.linkonce.s2.*)
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97 } > psu_ddr_0_S_AXI_BASEADDR
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104 *(.gnu.linkonce.sb2.*)
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106 } > psu_ddr_0_S_AXI_BASEADDR
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113 *(.gnu.linkonce.d.*)
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118 } > psu_ddr_0_S_AXI_BASEADDR
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126 } > psu_ddr_0_S_AXI_BASEADDR
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130 } > psu_ddr_0_S_AXI_BASEADDR
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134 } > psu_ddr_0_S_AXI_BASEADDR
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138 } > psu_ddr_0_S_AXI_BASEADDR
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143 ___CTORS_LIST___ = .;
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144 KEEP (*crtbegin.o(.ctors))
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145 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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146 KEEP (*(SORT(.ctors.*)))
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149 ___CTORS_END___ = .;
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150 } > psu_ddr_0_S_AXI_BASEADDR
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155 ___DTORS_LIST___ = .;
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156 KEEP (*crtbegin.o(.dtors))
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157 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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158 KEEP (*(SORT(.dtors.*)))
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161 ___DTORS_END___ = .;
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162 } > psu_ddr_0_S_AXI_BASEADDR
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168 } > psu_ddr_0_S_AXI_BASEADDR
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172 } > psu_ddr_0_S_AXI_BASEADDR
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175 __eh_framehdr_start = .;
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177 __eh_framehdr_end = .;
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178 } > psu_ddr_0_S_AXI_BASEADDR
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180 .gcc_except_table : {
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181 *(.gcc_except_table)
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182 } > psu_ddr_0_S_AXI_BASEADDR
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184 .mmu_tbl0 (ALIGN(4096)) : {
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185 __mmu_tbl0_start = .;
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187 __mmu_tbl0_end = .;
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188 } > psu_ddr_0_S_AXI_BASEADDR
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190 .mmu_tbl1 (ALIGN(4096)) : {
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191 __mmu_tbl1_start = .;
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193 __mmu_tbl1_end = .;
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194 } > psu_ddr_0_S_AXI_BASEADDR
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196 .mmu_tbl2 (ALIGN(4096)) : {
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197 __mmu_tbl2_start = .;
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199 __mmu_tbl2_end = .;
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200 } > psu_ddr_0_S_AXI_BASEADDR
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205 *(.gnu.linkonce.armexidix.*.*)
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207 } > psu_ddr_0_S_AXI_BASEADDR
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211 __preinit_array_start = .;
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212 KEEP (*(SORT(.preinit_array.*)))
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213 KEEP (*(.preinit_array))
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214 __preinit_array_end = .;
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215 } > psu_ddr_0_S_AXI_BASEADDR
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219 __init_array_start = .;
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220 KEEP (*(SORT(.init_array.*)))
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221 KEEP (*(.init_array))
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222 __init_array_end = .;
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223 } > psu_ddr_0_S_AXI_BASEADDR
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227 __fini_array_start = .;
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228 KEEP (*(SORT(.fini_array.*)))
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229 KEEP (*(.fini_array))
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230 __fini_array_end = .;
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231 } > psu_ddr_0_S_AXI_BASEADDR
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233 .ARM.attributes : {
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234 __ARM.attributes_start = .;
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236 __ARM.attributes_end = .;
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237 } > psu_ddr_0_S_AXI_BASEADDR
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244 *(.gnu.linkonce.s.*)
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246 } > psu_ddr_0_S_AXI_BASEADDR
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253 *(.gnu.linkonce.sb.*)
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256 } > psu_ddr_0_S_AXI_BASEADDR
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263 *(.gnu.linkonce.td.*)
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265 } > psu_ddr_0_S_AXI_BASEADDR
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272 *(.gnu.linkonce.tb.*)
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274 } > psu_ddr_0_S_AXI_BASEADDR
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281 *(.gnu.linkonce.b.*)
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285 } > psu_ddr_0_S_AXI_BASEADDR
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287 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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289 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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291 /* Generate Stack and Heap definitions */
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301 } > psu_ddr_0_S_AXI_BASEADDR
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303 .stack (NOLOAD) : {
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305 _el3_stack_end = .;
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308 _el2_stack_end = .;
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309 . += _EL2_STACK_SIZE;
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312 _el1_stack_end = .;
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313 . += _EL1_STACK_SIZE;
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316 _el0_stack_end = .;
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317 . += _EL0_STACK_SIZE;
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320 } > psu_ddr_0_S_AXI_BASEADDR
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