1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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9 /* Description : Cortex-A53 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
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17 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
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18 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
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20 /* Define Memories in the system */
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24 psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
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25 psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000
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26 psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
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27 psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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28 psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
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29 psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
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30 psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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31 psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000
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32 psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000
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33 psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000
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34 psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000
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35 psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000
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36 psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000
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37 psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000
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40 /* Specify the default entry point to the program */
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42 ENTRY(_vector_table)
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44 /* Define the sections, and where they are mapped in memory */
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53 *(.gnu.linkonce.t.*)
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56 *(.gcc_execpt_table)
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60 *(.gnu.linkonce.armextab.*)
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61 } > psu_r5_ddr_0_S_AXI_BASEADDR
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63 .init (ALIGN(64)) : {
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65 } > psu_r5_ddr_0_S_AXI_BASEADDR
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67 .fini (ALIGN(64)) : {
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69 } > psu_r5_ddr_0_S_AXI_BASEADDR
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73 } > psu_r5_ddr_0_S_AXI_BASEADDR
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76 KEEP (*(.note-ABI-tag))
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77 } > psu_r5_ddr_0_S_AXI_BASEADDR
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84 *(.gnu.linkonce.r.*)
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86 } > psu_r5_ddr_0_S_AXI_BASEADDR
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90 __rodata1_start = .;
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94 } > psu_r5_ddr_0_S_AXI_BASEADDR
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101 *(.gnu.linkonce.s2.*)
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103 } > psu_r5_ddr_0_S_AXI_BASEADDR
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110 *(.gnu.linkonce.sb2.*)
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112 } > psu_r5_ddr_0_S_AXI_BASEADDR
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119 *(.gnu.linkonce.d.*)
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124 } > psu_r5_ddr_0_S_AXI_BASEADDR
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132 } > psu_r5_ddr_0_S_AXI_BASEADDR
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136 } > psu_r5_ddr_0_S_AXI_BASEADDR
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140 } > psu_r5_ddr_0_S_AXI_BASEADDR
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144 } > psu_r5_ddr_0_S_AXI_BASEADDR
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149 ___CTORS_LIST___ = .;
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150 KEEP (*crtbegin.o(.ctors))
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151 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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152 KEEP (*(SORT(.ctors.*)))
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155 ___CTORS_END___ = .;
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156 } > psu_r5_ddr_0_S_AXI_BASEADDR
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161 ___DTORS_LIST___ = .;
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162 KEEP (*crtbegin.o(.dtors))
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163 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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164 KEEP (*(SORT(.dtors.*)))
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167 ___DTORS_END___ = .;
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168 } > psu_r5_ddr_0_S_AXI_BASEADDR
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174 } > psu_r5_ddr_0_S_AXI_BASEADDR
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178 } > psu_r5_ddr_0_S_AXI_BASEADDR
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181 __eh_framehdr_start = .;
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183 __eh_framehdr_end = .;
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184 } > psu_r5_ddr_0_S_AXI_BASEADDR
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186 .gcc_except_table : {
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187 *(.gcc_except_table)
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188 } > psu_r5_ddr_0_S_AXI_BASEADDR
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190 .mmu_tbl0 (ALIGN(4096)) : {
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191 __mmu_tbl0_start = .;
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193 __mmu_tbl0_end = .;
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194 } > psu_r5_ddr_0_S_AXI_BASEADDR
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196 .mmu_tbl1 (ALIGN(4096)) : {
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197 __mmu_tbl1_start = .;
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199 __mmu_tbl1_end = .;
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200 } > psu_r5_ddr_0_S_AXI_BASEADDR
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202 .mmu_tbl2 (ALIGN(4096)) : {
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203 __mmu_tbl2_start = .;
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205 __mmu_tbl2_end = .;
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206 } > psu_r5_ddr_0_S_AXI_BASEADDR
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211 *(.gnu.linkonce.armexidix.*.*)
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213 } > psu_r5_ddr_0_S_AXI_BASEADDR
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217 __preinit_array_start = .;
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218 KEEP (*(SORT(.preinit_array.*)))
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219 KEEP (*(.preinit_array))
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220 __preinit_array_end = .;
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221 } > psu_r5_ddr_0_S_AXI_BASEADDR
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225 __init_array_start = .;
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226 KEEP (*(SORT(.init_array.*)))
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227 KEEP (*(.init_array))
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228 __init_array_end = .;
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229 } > psu_r5_ddr_0_S_AXI_BASEADDR
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233 __fini_array_start = .;
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234 KEEP (*(SORT(.fini_array.*)))
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235 KEEP (*(.fini_array))
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236 __fini_array_end = .;
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237 } > psu_r5_ddr_0_S_AXI_BASEADDR
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239 .ARM.attributes : {
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240 __ARM.attributes_start = .;
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242 __ARM.attributes_end = .;
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243 } > psu_r5_ddr_0_S_AXI_BASEADDR
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250 *(.gnu.linkonce.s.*)
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252 } > psu_r5_ddr_0_S_AXI_BASEADDR
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259 *(.gnu.linkonce.sb.*)
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262 } > psu_r5_ddr_0_S_AXI_BASEADDR
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269 *(.gnu.linkonce.td.*)
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271 } > psu_r5_ddr_0_S_AXI_BASEADDR
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278 *(.gnu.linkonce.tb.*)
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280 } > psu_r5_ddr_0_S_AXI_BASEADDR
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287 *(.gnu.linkonce.b.*)
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291 } > psu_r5_ddr_0_S_AXI_BASEADDR
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293 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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295 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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297 /* Generate Stack and Heap definitions */
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307 } > psu_r5_ddr_0_S_AXI_BASEADDR
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309 .stack (NOLOAD) : {
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311 _el3_stack_end = .;
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314 _el2_stack_end = .;
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315 . += _EL2_STACK_SIZE;
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318 _el1_stack_end = .;
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319 . += _EL1_STACK_SIZE;
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322 _el0_stack_end = .;
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323 . += _EL0_STACK_SIZE;
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326 } > psu_r5_ddr_0_S_AXI_BASEADDR
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