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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
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  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
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  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xnandpsu.h
  36 *
  37 * This file implements a driver to support Arasan NAND controller
  38 * present in Zynq Ultrascale Mp.
  39 *
  40 * <b>Driver Initialization</b>
  41 *
  42 * The function call XNandPsu_CfgInitialize() should be called by the application
  43 * before any other function in the driver. The initialization function takes
  44 * device specific data (like device id, instance id, and base address) and
  45 * initializes the XNandPsu instance with the device specific data.
  46 *
  47 * <b>Device Geometry</b>
  48 *
  49 * NAND flash device is memory device and it is segmented into areas called
  50 * Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
  51 * can have multiple LUN. LUN is sequential raw of multiple blocks of the same
  52 * size. A block is the smallest erasable unit of data within the Flash array of
  53 * a LUN. The size of each block is based on a power of 2. There is no
  54 * restriction on the number of blocks within the LUN. A block contains a number
  55 * of pages. A page is the smallest addressable unit for read and program
  56 * operations. The arrangement of LUN, blocks, and pages is referred to by this
  57 * module as the part's geometry.
  58 *
  59 * The cells within the part can be programmed from a logic 1 to a logic 0
  60 * and not the other way around. To change a cell back to a logic 1, the
  61 * entire block containing that cell must be erased. When a block is erased
  62 * all bytes contain the value 0xFF. The number of times a block can be
  63 * erased is finite. Eventually the block will wear out and will no longer
  64 * be capable of erasure. As of this writing, the typical flash block can
  65 * be erased 100,000 or more times.
  66 *
  67 * The jobs done by this driver typically are:
  68 *       - 8-bit operational mode
  69 *       - Read, Write, and Erase operation
  70 *
  71 * <b>Write Operation</b>
  72 *
  73 * The write call can be used to write a minimum of one byte and a maximum
  74 * entire flash. If the address offset specified to write is out of flash or if
  75 * the number of bytes specified from the offset exceed flash boundaries
  76 * an error is reported back to the user. The write is blocking in nature in that
  77 * the control is returned back to user only after the write operation is
  78 * completed successfully or an error is reported.
  79 *
  80 * <b>Read Operation</b>
  81 *
  82 * The read call can be used to read a minimum of one byte and maximum of
  83 * entire flash. If the address offset specified to read is out of flash or if
  84 * the number of bytes specified from the offset exceed flash boundaries
  85 * an error is reported back to the user. The read is blocking in nature in that
  86 * the control is returned back to user only after the read operation is
  87 * completed successfully or an error is reported.
  88 *
  89 * <b>Erase Operation</b>
  90 *
  91 * The erase operations are provided to erase a Block in the Flash memory. The
  92 * erase call is blocking in nature in that the control is returned back to user
  93 * only after the erase operation is completed successfully or an error is
  94 * reported.
  95 *
  96 * @note         Driver has been renamed to nandpsu after change in
  97 *               naming convention.
  98 *
  99 * This driver is intended to be RTOS and processor independent. It works with
 100 * physical addresses only. Any needs for dynamic memory management, threads,
 101 * mutual exclusion, virtual memory, cache control, or HW write protection
 102 * management must be satisfied by the layer above this driver.
 103 *
 104 * <pre>
 105 * MODIFICATION HISTORY:
 106 *
 107 * Ver   Who    Date        Changes
 108 * ----- ----   ----------  -----------------------------------------------
 109 * 1.0   nm     05/06/2014  First release
 110 * 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
 111 *                          as parameter to Read API's
 112 *                          - XNandPsu_Read()
 113 *                          - XNandPsu_ReadPage
 114 *                          Modified
 115 *                          - XNandPsu_SetFeature()
 116 *                          - XNandPsu_GetFeature()
 117 *                          and made them public.
 118 *                          Removed Failure Return for BCF Error check in
 119 *                          XNandPsu_ReadPage() and added BCH_Error counter
 120 *                          in the instance pointer structure.
 121 *                          Added XNandPsu_Prepare_Cmd API
 122 *                          Replaced
 123 *                          - XNandPsu_IntrStsEnable
 124 *                          - XNandPsu_IntrStsClear
 125 *                          - XNandPsu_IntrClear
 126 *                          - XNandPsu_SetProgramReg
 127 *                          with XNandPsu_WriteReg call
 128 *                          Modified xnandpsu.c file API's with above changes.
 129 *                          Corrected the program command for Set Feature API.
 130 *                          Modified
 131 *                          - XNandPsu_OnfiReadStatus
 132 *                          - XNandPsu_GetFeature
 133 *                          - XNandPsu_SetFeature
 134 *                          to add support for DDR mode.
 135 *                          Changed Convention for SLC/MLC
 136 *                          SLC --> HAMMING
 137 *                          MLC --> BCH
 138 *                          SlcMlc --> IsBCH
 139 *                          Added support for writing BBT signature and version
 140 *                          in page section by enabling XNANDPSU_BBT_NO_OOB.
 141 *                          Removed extra DMA mode initialization from
 142 *                          the XNandPsu_CfgInitialize API.
 143 *                          Modified
 144 *                          - XNandPsu_SetEccAddrSize
 145 *                          ECC address now is calculated based upon the
 146 *                          size of spare area
 147 *                          Modified Block Erase API, removed clearing of
 148 *                          packet register before erase.
 149 *                          Clearing Data Interface Register before
 150 *                          XNandPsu_OnfiReset call.
 151 *                          Modified XNandPsu_ChangeTimingMode API supporting
 152 *                          SDR and NVDDR interface for timing modes 0 to 5.
 153 *                          Modified Bbt Signature and Version Offset value for
 154 *                          Oob and No-Oob region.
 155 * </pre>
 156 *
 157 ******************************************************************************/
 158
 159 #ifndef XNANDPSU_H              /* prevent circular inclusions */
 160 #define XNANDPSU_H              /* by using protection macros */
 161
 162 #ifdef __cplusplus
 163 extern "C" {
 164 #endif
 165
 166 /***************************** Include Files *********************************/
 167 #include "xil_types.h"
 168 #include <string.h>
 169 #include "xstatus.h"
 170 #include "xil_assert.h"
 171 #include "xnandpsu_hw.h"
 172 #include "xnandpsu_onfi.h"
 173 #include "xil_cache.h"
 174 /************************** Constant Definitions *****************************/
 175
 176 #define XNANDPSU_DEBUG
 177
 178 #define XNANDPSU_MAX_TARGETS            1U      /**< ce_n0, ce_n1 */
 179 #define XNANDPSU_MAX_PKT_SIZE           0x7FFU  /**< Max packet size */
 180 #define XNANDPSU_MAX_PKT_COUNT          0xFFFU  /**< Max packet count */
 181
 182 #define XNANDPSU_PAGE_SIZE_512          512U    /**< 512 bytes page */
 183 #define XNANDPSU_PAGE_SIZE_2K           2048U   /**< 2K bytes page */
 184 #define XNANDPSU_PAGE_SIZE_4K           4096U   /**< 4K bytes page */
 185 #define XNANDPSU_PAGE_SIZE_8K           8192U   /**< 8K bytes page */
 186 #define XNANDPSU_PAGE_SIZE_16K          16384U  /**< 16K bytes page */
 187 #define XNANDPSU_PAGE_SIZE_1K_16BIT     1024U   /**< 16-bit 2K bytes page */
 188 #define XNANDPSU_MAX_PAGE_SIZE          16384U  /**< Max page size supported */
 189
 190 #define XNANDPSU_BUS_WIDTH_8            0U      /**< 8-bit bus width */
 191 #define XNANDPSU_BUS_WIDTH_16           1U      /**< 16-bit bus width */
 192
 193 #define XNANDPSU_HAMMING                0x1U    /**< Hamming Flash */
 194 #define XNANDPSU_BCH                    0x2U    /**< BCH Flash */
 195
 196 #define XNANDPSU_MAX_BLOCKS             32768U  /**< Max number of Blocks */
 197 #define XNANDPSU_MAX_SPARE_SIZE         0x800U  /**< Max spare bytes of a NAND
 198                                                   flash page of 16K */
 199
 200 #define XNANDPSU_INTR_POLL_TIMEOUT      10000U
 201
 202 #define XNANDPSU_SDR_CLK                ((u16)100U * (u16)1000U * (u16)1000U)
 203 #define XNANDPSU_NVDDR_CLK_0            ((u16)20U * (u16)1000U * (u16)1000U)
 204 #define XNANDPSU_NVDDR_CLK_1            ((u16)33U * (u16)1000U * (u16)1000U)
 205 #define XNANDPSU_NVDDR_CLK_2            ((u16)50U * (u16)1000U * (u16)1000U)
 206 #define XNANDPSU_NVDDR_CLK_3            ((u16)66U * (u16)1000U * (u16)1000U)
 207 #define XNANDPSU_NVDDR_CLK_4            ((u16)83U * (u16)1000U * (u16)1000U)
 208 #define XNANDPSU_NVDDR_CLK_5            ((u16)100U * (u16)1000U * (u16)1000U)
 209
 210 /**
 211  * The XNandPsu_Config structure contains configuration information for NAND
 212  * controller.
 213  */
 214 typedef struct {
 215         u16 DeviceId;           /**< Instance ID of NAND flash controller */
 216         u32 BaseAddress;        /**< Base address of NAND flash controller */
 217 } XNandPsu_Config;
 218
 219 /**
 220  * The XNandPsu_DataInterface enum contains flash operating mode.
 221  */
 222 typedef enum {
 223         XNANDPSU_SDR = 0U,              /**< Single Data Rate */
 224         XNANDPSU_NVDDR                  /**< Double Data Rate */
 225 } XNandPsu_DataInterface;
 226
 227 /**
 228  * XNandPsu_TimingMode enum contains timing modes.
 229  */
 230 typedef enum {
 231         XNANDPSU_SDR0 = 0U,
 232         XNANDPSU_SDR1,
 233         XNANDPSU_SDR2,
 234         XNANDPSU_SDR3,
 235         XNANDPSU_SDR4,
 236         XNANDPSU_SDR5,
 237         XNANDPSU_NVDDR0,
 238         XNANDPSU_NVDDR1,
 239         XNANDPSU_NVDDR2,
 240         XNANDPSU_NVDDR3,
 241         XNANDPSU_NVDDR4,
 242         XNANDPSU_NVDDR5
 243 } XNandPsu_TimingMode;
 244
 245 /**
 246  * The XNandPsu_SWMode enum contains the driver operating mode.
 247  */
 248 typedef enum {
 249         XNANDPSU_POLLING = 0,           /**< Polling */
 250         XNANDPSU_INTERRUPT              /**< Interrupt */
 251 } XNandPsu_SWMode;
 252
 253 /**
 254  * The XNandPsu_DmaMode enum contains the controller MDMA mode.
 255  */
 256 typedef enum {
 257         XNANDPSU_PIO = 0,               /**< PIO Mode */
 258         XNANDPSU_SDMA,                  /**< SDMA Mode */
 259         XNANDPSU_MDMA                   /**< MDMA Mode */
 260 } XNandPsu_DmaMode;
 261
 262 /**
 263  * The XNandPsu_EccMode enum contains ECC functionality.
 264  */
 265 typedef enum {
 266         XNANDPSU_NONE = 0,
 267         XNANDPSU_HWECC,
 268         XNANDPSU_EZNAND,
 269         XNANDPSU_ONDIE
 270 } XNandPsu_EccMode;
 271
 272 /**
 273  * The XNandPsu_BbtOption enum contains the BBT storage option.
 274  */
 275 typedef enum {
 276         XNANDPSU_BBT_OOB = 0,           /**< OOB area */
 277         XNANDPSU_BBT_NO_OOB,            /**< No OOB i.e page area */
 278 } XNandPsu_BbtOption;
 279
 280 /**
 281  * Bad block table descriptor
 282  */
 283 typedef struct {
 284         u32 PageOffset[XNANDPSU_MAX_TARGETS];
 285                                 /**< Page offset where BBT resides */
 286         u32 SigOffset;          /**< Signature offset in Spare area */
 287         u32 VerOffset;          /**< Offset of BBT version */
 288         u32 SigLength;          /**< Length of the signature */
 289         u32 MaxBlocks;          /**< Max blocks to search for BBT */
 290         char Signature[4];      /**< BBT signature */
 291         u8 Version[XNANDPSU_MAX_TARGETS];
 292                                 /**< BBT version */
 293         u32 Valid;              /**< BBT descriptor is valid or not */
 294         XNandPsu_BbtOption Option;      /**< BBT Oob option enabled/disabled */
 295 } XNandPsu_BbtDesc;
 296
 297 /**
 298  * Bad block pattern
 299  */
 300 typedef struct {
 301         u32 Options;            /**< Options to search the bad block pattern */
 302         u32 Offset;             /**< Offset to search for specified pattern */
 303         u32 Length;             /**< Number of bytes to check the pattern */
 304         u8 Pattern[2];          /**< Pattern format to search for */
 305 } XNandPsu_BadBlockPattern;
 306
 307 /**
 308  * The XNandPsu_Geometry structure contains the ONFI geometry information.
 309  */
 310 typedef struct {
 311         /*
 312          * Parameter page information
 313          */
 314         u32 BytesPerPage;       /**< Number of bytes per page */
 315         u16 SpareBytesPerPage;  /**< Number of spare bytes per page */
 316         u32 PagesPerBlock;      /**< Number of pages per block */
 317         u32 BlocksPerLun;       /**< Number of blocks per LUN */
 318         u8 NumLuns;             /**< Number of LUN's */
 319         u8 RowAddrCycles;       /**< Row address cycles */
 320         u8 ColAddrCycles;       /**< Column address cycles */
 321         u8 NumBitsPerCell;      /**< Number of bits per cell (Hamming/BCH) */
 322         u8 NumBitsECC;          /**< Number of bits ECC correctability */
 323         u32 EccCodeWordSize;    /**< ECC codeword size */
 324         /*
 325          * Driver specific information
 326          */
 327         u32 BlockSize;          /**< Block size */
 328         u32 NumTargetPages;     /**< Total number of pages in a Target */
 329         u32 NumTargetBlocks;    /**< Total number of blocks in a Target */
 330         u64 TargetSize;         /**< Target size in bytes */
 331         u8 NumTargets;          /**< Number of targets present */
 332         u32 NumPages;           /**< Total number of pages */
 333         u32 NumBlocks;          /**< Total number of blocks */
 334         u64 DeviceSize;         /**< Total flash size in bytes */
 335 } XNandPsu_Geometry;
 336
 337 /**
 338  * The XNandPsu_Features structure contains the ONFI features information.
 339  */
 340 typedef struct {
 341         u32 BusWidth;
 342         u32 NvDdr;
 343         u32 EzNand;
 344         u32 OnDie;
 345         u32 ExtPrmPage;
 346 } XNandPsu_Features;
 347
 348 /**
 349  * The XNandPsu_EccMatrix structure contains ECC features information.
 350  */
 351 typedef struct {
 352         u16 PageSize;
 353         u16 CodeWordSize;
 354         u8 NumEccBits;
 355         u8 IsBCH;
 356         u16 EccAddr;
 357         u16 EccSize;
 358 } XNandPsu_EccMatrix;
 359
 360 /**
 361  * The XNandPsu_EccCfg structure contains ECC configuration.
 362  */
 363 typedef struct {
 364         u16 EccAddr;
 365         u16 EccSize;
 366         u16 CodeWordSize;
 367         u8 NumEccBits;
 368         u8 IsBCH;
 369 } XNandPsu_EccCfg;
 370
 371 /**
 372  * The XNandPsu structure contains the driver instance data. The user is
 373  * required to allocate a variable of this type for the NAND controller.
 374  * A pointer to a variable of this type is then passed to the driver API
 375  * functions.
 376  */
 377 typedef struct {
 378         u32 IsReady;            /**< Device is initialized and ready */
 379         XNandPsu_Config Config;
 380         u16 Ecc_Stat_PerPage_flips;     /**< Ecc Correctable Error Counter for Current Page */
 381         u32 Ecc_Stats_total_flips;     /**< Total Ecc Errors Corrected */
 382         XNandPsu_DataInterface DataInterface;
 383         XNandPsu_TimingMode TimingMode;
 384         XNandPsu_SWMode Mode;           /**< Driver operating mode */
 385         XNandPsu_DmaMode DmaMode;       /**< MDMA mode enabled/disabled */
 386         XNandPsu_EccMode EccMode;       /**< ECC Mode */
 387         XNandPsu_EccCfg EccCfg;         /**< ECC configuration */
 388         XNandPsu_Geometry Geometry;     /**< Flash geometry */
 389         XNandPsu_Features Features;     /**< ONFI features */
 390         u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
 391                                         /**< Partial read/write buffer */
 392         /* Bad block table definitions */
 393         XNandPsu_BbtDesc BbtDesc;       /**< Bad block table descriptor */
 394         XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */
 395         XNandPsu_BadBlockPattern BbPattern;     /**< Bad block pattern to
 396                                                   search */
 397         u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];       /**< Bad block table array */
 398 } XNandPsu;
 399
 400 /******************* Macro Definitions (Inline Functions) *******************/
 401
 402 /*****************************************************************************/
 403 /**
 404  * This macro sets the bitmask in the register.
 405  *
 406  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 407  *              controller.
 408  * @param       RegOffset is the register offset.
 409  * @param       BitMask is the bitmask.
 410  *
 411  * @note        C-style signature:
 412  *              void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
 413  *                                                      u32 BitMask)
 414  *
 415  *****************************************************************************/
 416 #define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)               \
 417         XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
 418                 (RegOffset),                                            \
 419         ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,      \
 420                 (RegOffset)) | (BitMask))))
 421
 422 /*****************************************************************************/
 423 /**
 424  * This macro clears the bitmask in the register.
 425  *
 426  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 427  *              controller.
 428  * @param       RegOffset is the register offset.
 429  * @param       BitMask is the bitmask.
 430  *
 431  * @note        C-style signature:
 432  *              void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
 433  *                                                      u32 BitMask)
 434  *
 435  *****************************************************************************/
 436 #define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)               \
 437         XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
 438                 (RegOffset),                                            \
 439         ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,      \
 440                 (RegOffset)) & ~(BitMask))))
 441
 442 /*****************************************************************************/
 443 /**
 444  * This macro clears and updates the bitmask in the register.
 445  *
 446  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 447  *              controller.
 448  * @param       RegOffset is the register offset.
 449  * @param       Mask is the bitmask.
 450  * @param       Value is the register value to write.
 451  *
 452  * @note        C-style signature:
 453  *              void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
 454  *                                      u32 RegOffset, u32 Mask, u32 Val)
 455  *
 456  *****************************************************************************/
 457 #define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)   \
 458         XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,            \
 459                 (RegOffset),                                            \
 460         ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
 461                 (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
 462
 463 /*****************************************************************************/
 464 /**
 465  * This macro enables bitmask in Interrupt Signal Enable register.
 466  *
 467  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 468  *              controller.
 469  * @param       Mask is the bitmask.
 470  *
 471  * @note        C-style signature:
 472  *              void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
 473  *
 474  *****************************************************************************/
 475 #define XNandPsu_IntrSigEnable(InstancePtr, Mask)                       \
 476                 XNandPsu_SetBits((InstancePtr),                         \
 477                         XNANDPSU_INTR_SIG_EN_OFFSET,                    \
 478                         (Mask))
 479
 480 /*****************************************************************************/
 481 /**
 482  * This macro clears bitmask in Interrupt Signal Enable register.
 483  *
 484  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 485  *              controller.
 486  * @param       Mask is the bitmask.
 487  *
 488  * @note        C-style signature:
 489  *              void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
 490  *
 491  *****************************************************************************/
 492 #define XNandPsu_IntrSigClear(InstancePtr, Mask)                        \
 493                 XNandPsu_ClrBits((InstancePtr),                         \
 494                         XNANDPSU_INTR_SIG_EN_OFFSET,                    \
 495                         (Mask))
 496
 497 /*****************************************************************************/
 498 /**
 499  * This macro enables bitmask in Interrupt Status Enable register.
 500  *
 501  * @param       InstancePtr is a pointer to the XNandPsu instance of the
 502  *              controller.
 503  * @param       Mask is the bitmask.
 504  *
 505  * @note        C-style signature:
 506  *              void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
 507  *
 508  *****************************************************************************/
 509 #define XNandPsu_IntrStsEnable(InstancePtr, Mask)                       \
 510                 XNandPsu_SetBits((InstancePtr),                         \
 511                         XNANDPSU_INTR_STS_EN_OFFSET,                    \
 512                         (Mask))
 513
 514 /*****************************************************************************/
 515 /**
 516  * This macro checks for the ONFI ID.
 517  *
 518  * @param       Buff is the buffer holding ONFI ID
 519  *
 520  * @note        none.
 521  *
 522  *****************************************************************************/
 523 #define IS_ONFI(Buff)                                   \
 524         (Buff[0] == (u8)'O') && (Buff[1] == (u8)'N') && \
 525         (Buff[2] == (u8)'F') && (Buff[3] == (u8)'I')
 526
 527 /************************** Function Prototypes *****************************/
 528
 529 s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 530                                 u32 EffectiveAddr);
 531
 532 s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
 533
 534 s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
 535                                                         u8 *SrcBuf);
 536
 537 s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
 538                                                         u8 *DestBuf);
 539
 540 s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
 541
 542 s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 543
 544 s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 545
 546 s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 547                                 XNandPsu_DataInterface NewIntf,
 548                                 XNandPsu_TimingMode NewMode);
 549
 550 s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 551                                                                 u8 *Buf);
 552
 553 s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 554                                                                 u8 *Buf);
 555
 556 s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
 557
 558 s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
 559
 560 void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
 561
 562 void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
 563
 564 void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
 565
 566 void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
 567
 568 void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
 569                         u8 DmaMode, u8 AddrCycles);
 570
 571 void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr);
 572
 573 void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr);
 574 /*
 575  * XNandPsu_LookupConfig in xnandpsu_sinit.c
 576  */
 577 XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID);
 578
 579
 580 #ifdef __cplusplus
 581 }
 582 #endif
 583
 584 #endif /* XNANDPSU_H end of protection macro */