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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
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  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
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  27 * Except as contained in this notice, the name of the Xilinx shall not be used
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  29 * this Software without prior written authorization from Xilinx.
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  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xnandpsu_onfi.h
  36 *
  37 * This file defines all the ONFI 3.1 specific commands and values.
  38 *
  39 * @note         None
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who    Date        Changes
  45 * ----- ----   ----------  -----------------------------------------------
  46 * 1.0   nm     05/06/2014  First release
  47 * </pre>
  48 *
  49 ******************************************************************************/
  50 #ifndef XNANDPSU_ONFI_H         /* prevent circular inclusions */
  51 #define XNANDPSU_ONFI_H         /* by using protection macros */
  52
  53 #ifdef __cplusplus
  54 extern "C" {
  55 #endif
  56
  57 /***************************** Include Files *********************************/
  58 #include "xil_types.h"
  59
  60 /************************** Constant Definitions *****************************/
  61 /*
  62  * Standard ONFI 3.1 Commands
  63  */
  64 /*
  65  * ONFI 3.1 Mandatory Commands
  66  */
  67 #define ONFI_CMD_RD1                    0x00U   /**< Read (1st cycle) */
  68 #define ONFI_CMD_RD2                    0x30U   /**< Read (2nd cycle) */
  69 #define ONFI_CMD_CHNG_RD_COL1           0x05U   /**< Change Read Column
  70                                                   (1st cycle) */
  71 #define ONFI_CMD_CHNG_RD_COL2           0xE0U   /**< Change Read Column
  72                                                   (2nd cycle) */
  73 #define ONFI_CMD_BLK_ERASE1             0x60U   /**< Block Erase (1st cycle) */
  74 #define ONFI_CMD_BLK_ERASE2             0xD0U   /**< Block Erase (2nd cycle) */
  75 #define ONFI_CMD_RD_STS                 0x70U   /**< Read Status */
  76 #define ONFI_CMD_PG_PROG1               0x80U   /**< Page Program(1st cycle) */
  77 #define ONFI_CMD_PG_PROG2               0x10U   /**< Page Program(2nd cycle) */
  78 #define ONFI_CMD_CHNG_WR_COL            0x85U   /**< Change Write Column */
  79 #define ONFI_CMD_RD_ID                  0x90U   /**< Read ID */
  80 #define ONFI_CMD_RD_PRM_PG              0xECU   /**< Read Parameter Page */
  81 #define ONFI_CMD_RST                    0xFFU   /**< Reset */
  82 /*
  83  * ONFI 3.1 Optional Commands
  84  */
  85 #define ONFI_CMD_MUL_RD1                0x00U   /**< Multiplane Read
  86                                                   (1st cycle) */
  87 #define ONFI_CMD_MUL_RD2                0x32U   /**< Multiplane Read
  88                                                   (2nd cycle) */
  89 #define ONFI_CMD_CPBK_RD1               0x00U   /**< Copyback Read
  90                                                   (1st cycle) */
  91 #define ONFI_CMD_CPBK_RD2               0x35U   /**< Copyback Read
  92                                                   (2nd cycle) */
  93 #define ONFI_CMD_CHNG_RD_COL_ENHCD1     0x06U   /**< Change Read Column
  94                                                   Enhanced (1st cycle) */
  95 #define ONFI_CMD_CHNG_RD_COL_ENHCD2     0xE0U   /**< Change Read Column
  96                                                   Enhanced (2nd cycle) */
  97 #define ONFI_CMD_RD_CACHE_RND1          0x00U   /**< Read Cache Random
  98                                                   (1st cycle) */
  99 #define ONFI_CMD_RD_CACHE_RND2          0x31U   /**< Read Cache Random
 100                                                   (2nd cycle) */
 101 #define ONFI_CMD_RD_CACHE_SEQ           0x31U   /**< Read Cache Sequential */
 102 #define ONFI_CMD_RD_CACHE_END           0x3FU   /**< Read Cache End */
 103 #define ONFI_CMD_MUL_BLK_ERASE1         0x60U   /**< Multiplane Block Erase
 104                                                   (1st cycle) */
 105 #define ONFI_CMD_MUL_BLK_ERASE2         0xD1U   /**< Multiplane Block Erase
 106                                                   (2nd cycle) */
 107 #define ONFI_CMD_RD_STS_ENHCD           0x78U   /**< Read Status Enhanced */
 108 #define ONFI_CMD_BLK_ERASE_INTRLVD2     0xD1U   /**< Block Erase Interleaved
 109                                                   (2nd cycle) */
 110 #define ONFI_CMD_MUL_PG_PROG1           0x80U   /**< Multiplane Page Program
 111                                                   (1st cycle) */
 112 #define ONFI_CMD_MUL_PG_PROG2           0x11U   /**< Multiplane Page Program
 113                                                   (2nd cycle) */
 114 #define ONFI_CMD_PG_CACHE_PROG1         0x80U   /**< Page Cache Program
 115                                                   (1st cycle) */
 116 #define ONFI_CMD_PG_CACHE_PROG2         0x15U   /**< Page Cache Program
 117                                                   (2nd cycle) */
 118 #define ONFI_CMD_CPBK_PROG1             0x85U   /**< Copyback Program
 119                                                   (1st cycle) */
 120 #define ONFI_CMD_CPBK_PROG2             0x10U   /**< Copyback Program
 121                                                   (2nd cycle) */
 122 #define ONFI_CMD_MUL_CPBK_PROG1         0x85U   /**< Multiplane Copyback
 123                                                   Program (1st cycle) */
 124 #define ONFI_CMD_MUL_CPBK_PROG2         0x10U   /**< Multiplane Copyback
 125                                                   Program (2nd cycle) */
 126 #define ONFI_CMD_SMALL_DATA_MV1         0x85U   /**< Small Data Move
 127                                                   (1st cycle) */
 128 #define ONFI_CMD_SMALL_DATA_MV2         0x10U   /**< Small Data Move
 129                                                   (2nd cycle) */
 130 #define ONFI_CMD_CHNG_ROW_ADDR          0x85U   /**< Change Row Address */
 131 #define ONFI_CMD_VOL_SEL                0xE1U   /**< Volume Select */
 132 #define ONFI_CMD_ODT_CONF               0xE2U   /**< ODT Configure */
 133 #define ONFI_CMD_RD_UNIQID              0xEDU   /**< Read Unique ID */
 134 #define ONFI_CMD_GET_FEATURES           0xEEU   /**< Get Features */
 135 #define ONFI_CMD_SET_FEATURES           0xEFU   /**< Set Features */
 136 #define ONFI_CMD_LUN_GET_FEATURES       0xD4U   /**< LUN Get Features */
 137 #define ONFI_CMD_LUN_SET_FEATURES       0xD5U   /**< LUN Set Features */
 138 #define ONFI_CMD_RST_LUN                0xFAU   /**< Reset LUN */
 139 #define ONFI_CMD_SYN_RST                0xFCU   /**< Synchronous Reset */
 140
 141 /*
 142  * ONFI Status Register bit offsets
 143  */
 144 #define ONFI_STS_FAIL                   0x01U   /**< FAIL */
 145 #define ONFI_STS_FAILC                  0x02U   /**< FAILC */
 146 #define ONFI_STS_CSP                    0x08U   /**< CSP */
 147 #define ONFI_STS_VSP                    0x10U   /**< VSP */
 148 #define ONFI_STS_ARDY                   0x20U   /**< ARDY */
 149 #define ONFI_STS_RDY                    0x40U   /**< RDY */
 150 #define ONFI_STS_WP                     0x80U   /**< WP_n */
 151
 152 /*
 153  * ONFI constants
 154  */
 155 #define ONFI_CRC_LEN                    254U    /**< ONFI CRC Buf Length */
 156 #define ONFI_PRM_PG_LEN                 256U    /**< Parameter Page Length */
 157 #define ONFI_MND_PRM_PGS                3U      /**< Number of mandatory
 158                                                   parameter pages */
 159 #define ONFI_SIG_LEN                    4U      /**< Signature Length */
 160 #define ONFI_CMD_INVALID                0x00U   /**< Invalid Command */
 161
 162 #define ONFI_READ_ID_LEN                4U      /**< ONFI ID length */
 163 #define ONFI_READ_ID_ADDR               0x20U   /**< ONFI Read ID Address */
 164 #define ONFI_READ_ID_ADDR_CYCLES        1U      /**< ONFI Read ID Address
 165                                                   cycles */
 166
 167 #define ONFI_PRM_PG_ADDR_CYCLES         1U      /**< ONFI Read Parameter page
 168                                                   address cycles */
 169
 170 /**
 171  * This enum defines the ONFI 3.1 commands.
 172  */
 173 enum OnfiCommandList {
 174         READ=0,                         /**< Read */
 175         MULTIPLANE_READ,                /**< Multiplane Read */
 176         COPYBACK_READ,                  /**< Copyback Read */
 177         CHANGE_READ_COLUMN,             /**< Change Read Column */
 178         CHANGE_READ_COLUMN_ENHANCED,    /**< Change Read Column Enhanced */
 179         READ_CACHE_RANDOM,              /**< Read Cache Random */
 180         READ_CACHE_SEQUENTIAL,          /**< Read Cache Sequential */
 181         READ_CACHE_END,                 /**< Read Cache End */
 182         BLOCK_ERASE,                    /**< Block Erase */
 183         MULTIPLANE_BLOCK_ERASE,         /**< Multiplane Block Erase */
 184         READ_STATUS,                    /**< Read Status */
 185         READ_STATUS_ENHANCED,           /**< Read Status Enhanced */
 186         PAGE_PROGRAM,                   /**< Page Program */
 187         MULTIPLANE_PAGE_PROGRAM,        /**< Multiplane Page Program */
 188         PAGE_CACHE_PROGRAM,             /**< Page Cache Program */
 189         COPYBACK_PROGRAM,               /**< Copyback Program */
 190         MULTIPLANE_COPYBACK_PROGRAM,    /**< Multiplance Copyback Program */
 191         SMALL_DATA_MOVE,                /**< Small Data Move */
 192         CHANGE_WRITE_COLUMN,            /**< Change Write Column */
 193         CHANGE_ROW_ADDR,                /**< Change Row Address */
 194         READ_ID,                        /**< Read ID */
 195         VOLUME_SELECT,                  /**< Volume Select */
 196         ODT_CONFIGURE,                  /**< ODT Configure */
 197         READ_PARAM_PAGE,                /**< Read Parameter Page */
 198         READ_UNIQUE_ID,                 /**< Read Unique ID */
 199         GET_FEATURES,                   /**< Get Features */
 200         SET_FEATURES,                   /**< Set Features */
 201         LUN_GET_FEATURES,               /**< LUN Get Features */
 202         LUN_SET_FEATURES,               /**< LUN Set Features */
 203         RESET_LUN,                      /**< Reset LUN */
 204         SYN_RESET,                      /**< Synchronous Reset */
 205         RESET,                          /**< Reset */
 206         MAX_CMDS                        /**< Dummy Command */
 207 };
 208
 209 /**************************** Type Definitions *******************************/
 210 /*
 211  * Parameter page structure of ONFI 3.1 specification.
 212  */
 213 typedef struct {
 214         /*
 215          * Revision information and features block
 216          */
 217         u8 Signature[4];                /**< Parameter page signature */
 218         u16 Revision;                   /**< Revision Number */
 219         u16 Features;                   /**< Features supported */
 220         u16 OptionalCmds;               /**< Optional commands supported */
 221         u8 JedecJtgPrmAdvCmd;           /**< ONFI JEDEC JTG primary advanced
 222                                           command support */
 223         u8 Reserved0;                   /**< Reserved (11) */
 224         u16 ExtParamPageLen;            /**< Extended Parameter Page Length */
 225         u8 NumOfParamPages;             /**< Number of Parameter Pages */
 226         u8 Reserved1[17];               /**< Reserved (15-31) */
 227         /*
 228          * Manufacturer information block
 229          */
 230         u8 DeviceManufacturer[12];      /**< Device manufacturer */
 231         u8 DeviceModel[20];             /**< Device model */
 232         u8 JedecManufacturerId;         /**< JEDEC Manufacturer ID */
 233         u8 DateCode[2];                 /**< Date code */
 234         u8 Reserved2[13];               /**< Reserved (67-79) */
 235         /*
 236          * Memory organization block
 237         */
 238         u32 BytesPerPage;               /**< Number of data bytes per page */
 239         u16 SpareBytesPerPage;          /**< Number of spare bytes per page */
 240         u32 BytesPerPartialPage;        /**< Number of data bytes per
 241                                           partial page */
 242         u16 SpareBytesPerPartialPage;   /**< Number of spare bytes per
 243                                           partial page */
 244         u32 PagesPerBlock;              /**< Number of pages per block */
 245         u32 BlocksPerLun;               /**< Number of blocks per LUN */
 246         u8 NumLuns;                     /**< Number of LUN's */
 247         u8 AddrCycles;                  /**< Number of address cycles */
 248         u8 BitsPerCell;                 /**< Number of bits per cell */
 249         u16 MaxBadBlocksPerLun;         /**< Bad blocks maximum per LUN */
 250         u16 BlockEndurance;             /**< Block endurance */
 251         u8 GuaranteedValidBlock;        /**< Guaranteed valid blocks at
 252                                           beginning of target */
 253         u16 BlockEnduranceGVB;          /**< Block endurance for guaranteed
 254                                           valid block */
 255         u8 ProgramsPerPage;             /**< Number of programs per page */
 256         u8 PartialProgAttr;             /**< Partial programming attributes */
 257         u8 EccBits;                     /**< Number of bits ECC
 258                                           correctability */
 259         u8 PlaneAddrBits;               /**< Number of plane address bits */
 260         u8 PlaneOperationAttr;          /**< Multi-plane operation
 261                                           attributes */
 262         u8 EzNandSupport;               /**< EZ NAND support */
 263         u8 Reserved3[12];               /**< Reserved (116 - 127) */
 264         /*
 265          * Electrical parameters block
 266         */
 267         u8 IOPinCapacitance;            /**< I/O pin capacitance, maximum */
 268         u16 SDRTimingMode;              /**< SDR Timing mode support */
 269         u16 SDRPagecacheTimingMode;     /**< SDR Program cache timing mode */
 270         u16 TProg;                      /**< Maximum page program time */
 271         u16 TBers;                      /**< Maximum block erase time */
 272         u16 TR;                         /**< Maximum page read time */
 273         u16 TCcs;                       /**< Maximum change column setup
 274                                           time */
 275         u8 NVDDRTimingMode;             /**< NVDDR timing mode support */
 276         u8 NVDDR2TimingMode;            /**< NVDDR2 timing mode support */
 277         u8 SynFeatures;                 /**< NVDDR/NVDDR2 features */
 278         u16 ClkInputPinCap;             /**< CLK input pin capacitance */
 279         u16 IOPinCap;                   /**< I/O pin capacitance */
 280         u16 InputPinCap;                /**< Input pin capacitance typical */
 281         u8 InputPinCapMax;              /**< Input pin capacitance maximum */
 282         u8 DrvStrength;                 /**< Driver strength support */
 283         u16 TMr;                        /**< Maximum multi-plane read time */
 284         u16 TAdl;                       /**< Program page register clear
 285                                           enhancement value */
 286         u16 TEr;                        /**< Typical page read time for
 287                                           EZ NAND */
 288         u8 NVDDR2Features;              /**< NVDDR2 Features */
 289         u8 NVDDR2WarmupCycles;          /**< NVDDR2 Warmup Cycles */
 290         u8 Reserved4[4];                /**< Reserved (160 - 163) */
 291         /*
 292          * Vendor block
 293          */
 294         u16 VendorRevisionNum;          /**< Vendor specific revision number */
 295         u8 VendorSpecific[88];          /**< Vendor specific */
 296         u16 Crc;                        /**< Integrity CRC */
 297 }__attribute__((packed))OnfiParamPage;
 298
 299 /*
 300  * ONFI extended parameter page structure.
 301  */
 302 typedef struct {
 303         u16 Crc;
 304         u8 Sig[4];
 305         u8 Reserved1[10];
 306         u8 Section0Type;
 307         u8 Section0Len;
 308         u8 Section1Type;
 309         u8 Section1Len;
 310         u8 ResSection[12];
 311         u8 SectionData[256];
 312 }__attribute__((packed))OnfiExtPrmPage;
 313
 314 /*
 315  * Driver extended parameter page information.
 316  */
 317 typedef struct {
 318         u8 NumBitsEcc;
 319         u8 CodeWordSize;
 320         u16 MaxBadBlocks;
 321         u16 BlockEndurance;
 322         u16 Reserved;
 323 }__attribute__((packed))OnfiExtEccBlock;
 324
 325 typedef struct {
 326         u8 Command1;                    /**< Command Cycle 1 */
 327         u8 Command2;                    /**< Command Cycle 2 */
 328 } OnfiCmdFormat;
 329
 330 extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
 331
 332 /************************** Function Prototypes ******************************/
 333
 334 u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
 335
 336 #ifdef __cplusplus
 337 }
 338 #endif
 339
 340 #endif /* XNANDPSU_ONFI_H end of protection macro */