1 /******************************************************************************
3 * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
33 /*****************************************************************************/
38 * This file defines the functions implemented by the DPDMA driver present
39 * in the Zynq Ultrascale MP.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ---- ----- -------- ----------------------------------------------------
48 * 1.0 aad 04/12/16 Initial release.
50 *****************************************************************************/
54 /* Prevent circular inclusions by using protection macros. */
61 /***************************** Include Files **********************************/
63 #include "xdpdma_hw.h"
66 #include "xil_assert.h"
69 /************************** Constant Definitions ******************************/
71 /* Alignment for DPDMA Descriptor and Payload */
72 #define XDPDMA_DESCRIPTOR_ALIGN 256
73 /* DPDMA preamble field */
74 #define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5
75 /**************************** Type Definitions ********************************/
78 * This typedef describes the DPDMA descriptor structure and its internals
79 * which will be used when fetching data from a nonlive path
82 u32 Control; /**< [7:0] Descriptor Preamble
83 [8] Enable completion Interrupt
84 [9] Enable descriptor update
92 [21] Last descriptor frame
94 u32 DSCR_ID; /**< [15:0] Descriptor ID
96 u32 XFER_SIZE; /**< Size of transfer in bytes */
97 u32 LINE_SIZE_STRIDE; /**< [17:0] Horizontal Resolution
99 u32 LSB_Timestamp; /**< LSB of the Timestamp */
100 u32 MSB_Timestamp; /**< MSB of the Timestamp */
101 u32 ADDR_EXT; /**< [15:0] Next descriptor
103 [31:16] SRC address extemsion */
104 u32 NEXT_DESR; /**< Address of next descriptor */
105 u32 SRC_ADDR; /**< Source Address */
106 u32 ADDR_EXT_23; /**< [15:0] Address extension for SRC
108 [31:16] Address extension for
110 u32 ADDR_EXT_45; /**< [15:0] Address extension for SRC
112 [31:16] Address extension for
114 u32 SRC_ADDR2; /**< Source address of 2nd page */
115 u32 SRC_ADDR3; /**< Source address of 3rd page */
116 u32 SRC_ADDR4; /**< Source address of 4th page */
117 u32 SRC_ADDR5; /**< Source address of 5th page */
118 u32 CRC; /**< Reserved */
120 } XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN)));
123 * This typedef contains configuration information for the DPDMA.
126 u16 DeviceId; /**< Device ID */
127 u32 BaseAddr; /**< Base Address */
131 * The following data structure enumerates the types of
139 } XDpDma_ChannelType;
142 * This typedef lists the channel status.
149 } XDpDma_ChannelState;
152 * This typedef is the information needed to transfer video info.
159 } XDpDma_FrameBuffer;
161 * This typedef is the information needed to transfer audio info.
166 } XDpDma_AudioBuffer;
169 * This typedef defines the Video/Graphics Channel attributes.
172 XDpDma_Descriptor Descriptor0;
173 XDpDma_Descriptor Descriptor1;
174 XDpDma_Descriptor *Current;
178 * This typedef defines the Video Channel attributes.
181 XDpDma_Channel Channel[3];
184 XAVBuf_VideoAttribute *VideoInfo;
185 XDpDma_FrameBuffer *FrameBuffer[3];
186 } XDpDma_VideoChannel;
189 * This typedef defines the Graphics Channel attributes.
192 XDpDma_Channel Channel;
195 XAVBuf_VideoAttribute *VideoInfo;
196 XDpDma_FrameBuffer *FrameBuffer;
200 * This typedef defines the Audio Channel attributes.
203 XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2;
204 XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5;
205 XDpDma_Descriptor Descriptor6, Descriptor7;
206 XDpDma_Descriptor *Current;
208 XDpDma_AudioBuffer *Buffer;
210 } XDpDma_AudioChannel;
211 /*************************************************************************/
213 * This callback type represents the handler for a DPDMA VSync interrupt.
215 * @param InstancePtr is a pointer to the XDpDma instance.
219 **************************************************************************/
220 typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr);
222 /*************************************************************************/
224 * This callback type represents the handler for a DPDMA Done interrupt.
226 * @param InstancePtr is a pointer to the XDpDma instance.
230 **************************************************************************/
231 typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr);
234 * The XDpDma driver instance data representing the DPDMA operation.
237 XDpDma_Config Config;
238 XDpDma_VideoChannel Video;
239 XDpDma_GfxChannel Gfx;
240 XDpDma_AudioChannel Audio[2];
241 XVidC_VideoTiming *Timing;
244 XDpDma_VSyncInterruptHandler VSyncHandler;
245 void * VSyncInterruptHandler;
247 XDpDma_DoneInterruptHandler DoneHandler;
248 void * DoneInterruptHandler;
252 void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr);
253 XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId);
254 int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
255 XDpDma_ChannelState ChannelState);
256 void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS);
257 void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
258 int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
259 int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
260 void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing);
261 int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
262 int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
263 void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask);
264 void XDpDma_InterruptHandler(XDpDma *InstancePtr);
265 void XDpDma_VSyncHandler(XDpDma *InstancePtr);
266 void XDpDma_DoneHandler(XDpDma *InstancePtr);
267 void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
268 XDpDma_FrameBuffer *FrameBuffer);
269 void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
270 XDpDma_FrameBuffer *Plane1,
271 XDpDma_FrameBuffer *Plane2,
272 XDpDma_FrameBuffer *Plane3);
273 void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
274 XDpDma_FrameBuffer *Plane);
275 void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
276 XDpDma_AudioBuffer *AudioBuffer);
277 int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
283 #endif /* _XDPDMA_H_ */