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  13 * all copies or substantial portions of the Software.
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  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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  29 * this Software without prior written authorization from Xilinx.
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  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xemacps_intr.c
  36 *
  37 * Functions in this file implement general purpose interrupt processing related
  38 * functionality. See xemacps.h for a detailed description of the driver.
  39 *
  40 * <pre>
  41 * MODIFICATION HISTORY:
  42 *
  43 * Ver   Who  Date     Changes
  44 * ----- ---- -------- -------------------------------------------------------
  45 * 1.00a wsy  01/10/10 First release
  46 * 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
  47 *                     Rx errors. Under heavy Rx traffic, there will be a large
  48 *                     number of errors related to receive buffer not available.
  49 *                     Because of a HW bug (SI #692601), under such heavy errors,
  50 *                     the Rx data path can become unresponsive. To reduce the
  51 *                     probabilities for hitting this HW bug, the SW writes to
  52 *                     bit 18 to flush a packet from Rx DPRAM immediately. The
  53 *                     changes for it are done in the function
  54 *                     XEmacPs_IntrHandler.
  55 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
  56 *                      and 64-bit changes.
  57 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
  58 * </pre>
  59 ******************************************************************************/
  60
  61 /***************************** Include Files *********************************/
  62
  63 #include "xemacps.h"
  64
  65 /************************** Constant Definitions *****************************/
  66
  67
  68 /**************************** Type Definitions *******************************/
  69
  70
  71 /***************** Macros (Inline Functions) Definitions *********************/
  72
  73
  74 /************************** Function Prototypes ******************************/
  75
  76
  77 /************************** Variable Definitions *****************************/
  78
  79
  80 /*****************************************************************************/
  81 /**
  82  * Install an asynchronious handler function for the given HandlerType:
  83  *
  84  * @param InstancePtr is a pointer to the instance to be worked on.
  85  * @param HandlerType indicates what interrupt handler type is.
  86  *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
  87  *        XEMACPS_HANDLER_ERROR.
  88  * @param FuncPointer is the pointer to the callback function
  89  * @param CallBackRef is the upper layer callback reference passed back when
  90  *        when the callback function is invoked.
  91  *
  92  * @return
  93  *
  94  * None.
  95  *
  96  * @note
  97  * There is no assert on the CallBackRef since the driver doesn't know what
  98  * it is.
  99  *
 100  *****************************************************************************/
 101 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
 102                         void *FuncPointer, void *CallBackRef)
 103 {
 104         LONG Status;
 105         Xil_AssertNonvoid(InstancePtr != NULL);
 106         Xil_AssertNonvoid(FuncPointer != NULL);
 107         Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 108
 109         switch (HandlerType) {
 110         case XEMACPS_HANDLER_DMASEND:
 111                 Status = (LONG)(XST_SUCCESS);
 112                 InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
 113                 InstancePtr->SendRef = CallBackRef;
 114                 break;
 115         case XEMACPS_HANDLER_DMARECV:
 116                 Status = (LONG)(XST_SUCCESS);
 117                 InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
 118                 InstancePtr->RecvRef = CallBackRef;
 119                 break;
 120         case XEMACPS_HANDLER_ERROR:
 121                 Status = (LONG)(XST_SUCCESS);
 122                 InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
 123                 InstancePtr->ErrorRef = CallBackRef;
 124                 break;
 125         default:
 126                 Status = (LONG)(XST_INVALID_PARAM);
 127                 break;
 128         }
 129         return Status;
 130 }
 131
 132 /*****************************************************************************/
 133 /**
 134 * Master interrupt handler for EMAC driver. This routine will query the
 135 * status of the device, bump statistics, and invoke user callbacks.
 136 *
 137 * This routine must be connected to an interrupt controller using OS/BSP
 138 * specific methods.
 139 *
 140 * @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
 141 *        interrupt.
 142 *
 143 ******************************************************************************/
 144 void XEmacPs_IntrHandler(void *XEmacPsPtr)
 145 {
 146         u32 RegISR;
 147         u32 RegSR;
 148         u32 RegCtrl;
 149         u32 RegQ1ISR = 0U;
 150         XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
 151
 152         Xil_AssertVoid(InstancePtr != NULL);
 153         Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 154
 155         /* This ISR will try to handle as many interrupts as it can in a single
 156          * call. However, in most of the places where the user's error handler
 157          * is called, this ISR exits because it is expected that the user will
 158          * reset the device in nearly all instances.
 159          */
 160         RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 161                                    XEMACPS_ISR_OFFSET);
 162
 163         /* Read Transmit Q1 ISR */
 164
 165         if (InstancePtr->Version > 2)
 166                 RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 167                                    XEMACPS_INTQ1_STS_OFFSET);
 168
 169         /* Clear the interrupt status register */
 170         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 171                            RegISR);
 172
 173         /* Receive complete interrupt */
 174         if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
 175                 /* Clear RX status register RX complete indication but preserve
 176                  * error bits if there is any */
 177                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 178                                    XEMACPS_RXSR_OFFSET,
 179                                    ((u32)XEMACPS_RXSR_FRAMERX_MASK |
 180                                    (u32)XEMACPS_RXSR_BUFFNA_MASK));
 181                 InstancePtr->RecvHandler(InstancePtr->RecvRef);
 182         }
 183
 184         /* Transmit Q1 complete interrupt */
 185         if ((InstancePtr->Version > 2) &&
 186                         ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 187                 /* Clear TX status register TX complete indication but preserve
 188                  * error bits if there is any */
 189                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 190                                    XEMACPS_INTQ1_STS_OFFSET,
 191                                    XEMACPS_INTQ1SR_TXCOMPL_MASK);
 192                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 193                                    XEMACPS_TXSR_OFFSET,
 194                                    ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 195                                    (u32)XEMACPS_TXSR_USEDREAD_MASK));
 196                 InstancePtr->SendHandler(InstancePtr->SendRef);
 197         }
 198
 199         /* Transmit complete interrupt */
 200         if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
 201                 /* Clear TX status register TX complete indication but preserve
 202                  * error bits if there is any */
 203                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 204                                    XEMACPS_TXSR_OFFSET,
 205                                    ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 206                                    (u32)XEMACPS_TXSR_USEDREAD_MASK));
 207                 InstancePtr->SendHandler(InstancePtr->SendRef);
 208         }
 209
 210         /* Receive error conditions interrupt */
 211         if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
 212                 /* Clear RX status register */
 213                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 214                                           XEMACPS_RXSR_OFFSET);
 215                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 216                                    XEMACPS_RXSR_OFFSET, RegSR);
 217
 218                 /* Fix for CR # 692702. Write to bit 18 of net_ctrl
 219                  * register to flush a packet out of Rx SRAM upon
 220                  * an error for receive buffer not available. */
 221                 if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
 222                         RegCtrl =
 223                         XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 224                                                 XEMACPS_NWCTRL_OFFSET);
 225                         RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
 226                         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 227                                         XEMACPS_NWCTRL_OFFSET, RegCtrl);
 228                 }
 229                 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
 230                                           RegSR);
 231         }
 232
 233         /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
 234          * will be asserted the same time.
 235          * Have to distinguish this bit to handle the real error condition.
 236          */
 237         /* Transmit Q1 error conditions interrupt */
 238         if ((InstancePtr->Version > 2) &&
 239                         ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
 240             ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 241                         /* Clear Interrupt Q1 status register */
 242                         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 243                                    XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
 244                         InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 245                                           RegQ1ISR);
 246            }
 247
 248         /* Transmit error conditions interrupt */
 249         if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
 250             (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
 251                 /* Clear TX status register */
 252                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 253                                           XEMACPS_TXSR_OFFSET);
 254                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 255                                    XEMACPS_TXSR_OFFSET, RegSR);
 256                 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 257                                           RegSR);
 258         }
 259
 260 }