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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xgpiops_hw.c
  36 *
  37 * This file contains low level GPIO functions.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who  Date     Changes
  43 * ----- ---- -------- -----------------------------------------------
  44 * 1.02a hk   08/22/13 First Release
  45 * 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
  46 *
  47 * </pre>
  48 *
  49 ******************************************************************************/
  50
  51 /***************************** Include Files *********************************/
  52
  53 #include "xgpiops_hw.h"
  54 #include "xgpiops.h"
  55
  56 /************************** Constant Definitions *****************************/
  57
  58 /**************************** Type Definitions *******************************/
  59
  60 /***************** Macros (Inline Functions) Definitions *********************/
  61
  62 /************************** Variable Definitions *****************************/
  63
  64 /************************** Function Prototypes ******************************/
  65
  66
  67 /*****************************************************************************/
  68 /*
  69 *
  70 * This function resets the GPIO module by writing reset values to
  71 * all registers
  72 *
  73 * @param        Base address of GPIO module
  74 *
  75 * @return       None
  76 *
  77 * @note         None.
  78 *
  79 ******************************************************************************/
  80 void XGpioPs_ResetHw(u32 BaseAddress)
  81 {
  82         u32 BankCount;
  83
  84         /*
  85          * Write reset values to all mask data registers
  86          */
  87         for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
  88
  89                 XGpioPs_WriteReg(BaseAddress,
  90                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
  91                                  XGPIOPS_DATA_LSW_OFFSET), 0x0U);
  92                 XGpioPs_WriteReg(BaseAddress,
  93                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
  94                                  XGPIOPS_DATA_MSW_OFFSET), 0x0U);
  95         }
  96         /*
  97          * Write reset values to all output data registers
  98          */
  99         for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
 100
 101                 XGpioPs_WriteReg(BaseAddress,
 102                                 ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
 103                                  XGPIOPS_DATA_OFFSET), 0x0U);
 104         }
 105
 106         /*
 107          * Reset all registers of all 4 banks
 108          */
 109         for(BankCount = 0U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
 110
 111                 XGpioPs_WriteReg(BaseAddress,
 112                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 113                                  XGPIOPS_DIRM_OFFSET), 0x0U);
 114                 XGpioPs_WriteReg(BaseAddress,
 115                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 116                                  XGPIOPS_OUTEN_OFFSET), 0x0U);
 117                 XGpioPs_WriteReg(BaseAddress,
 118                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 119                                  XGPIOPS_INTMASK_OFFSET), 0x0U);
 120                 XGpioPs_WriteReg(BaseAddress,
 121                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 122                                  XGPIOPS_INTEN_OFFSET), 0x0U);
 123                 XGpioPs_WriteReg(BaseAddress,
 124                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 125                                  XGPIOPS_INTDIS_OFFSET), 0x0U);
 126                 XGpioPs_WriteReg(BaseAddress,
 127                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 128                                  XGPIOPS_INTSTS_OFFSET), 0x0U);
 129                 XGpioPs_WriteReg(BaseAddress,
 130                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 131                                  XGPIOPS_INTPOL_OFFSET), 0x0U);
 132                 XGpioPs_WriteReg(BaseAddress,
 133                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 134                                  XGPIOPS_INTANY_OFFSET), 0x0U);
 135         }
 136
 137         /*
 138          * Bank 0 Int type
 139          */
 140         XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
 141                         XGPIOPS_INTTYPE_BANK0_RESET);
 142         /*
 143          * Bank 1 Int type
 144          */
 145         XGpioPs_WriteReg(BaseAddress,
 146                         ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
 147                         XGPIOPS_INTTYPE_BANK1_RESET);
 148         /*
 149          * Bank 2 Int type
 150          */
 151         XGpioPs_WriteReg(BaseAddress,
 152                         (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 153                         XGPIOPS_INTTYPE_BANK2_RESET);
 154         /*
 155          * Bank 3 Int type
 156          */
 157         XGpioPs_WriteReg(BaseAddress,
 158                         (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 159                         XGPIOPS_INTTYPE_BANK3_RESET);
 160 #ifdef XPAR_PSU_GPIO_0_BASEADDR
 161         /*
 162          * Bank 4 Int type
 163          */
 164         XGpioPs_WriteReg(BaseAddress,
 165                         (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 166                         XGPIOPS_INTTYPE_BANK4_RESET);
 167         /*
 168          * Bank 5 Int type
 169          */
 170         XGpioPs_WriteReg(BaseAddress,
 171                         (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 172                         XGPIOPS_INTTYPE_BANK5_RESET);
 173 #endif
 174
 175 }