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32 /*****************************************************************************/
36 * @addtogroup gpiops_v3_1
40 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
43 * The GPIO Controller supports the following features:
45 * - Masked writes (There are no masked reads)
47 * - Configurable Interrupts (Level/Edge)
49 * This driver is intended to be RTOS and processor independent. Any needs for
50 * dynamic memory management, threads or thread mutual exclusion, virtual
51 * memory, or cache control must be satisfied by the layer above this driver.
53 * This driver supports all the features listed above, if applicable.
55 * <b>Driver Description</b>
57 * The device driver enables higher layer software (e.g., an application) to
58 * communicate to the GPIO.
62 * The driver provides interrupt management functions and an interrupt handler.
63 * Users of this driver need to provide callback functions. An interrupt handler
64 * example is available with the driver.
68 * This driver is not thread safe. Any needs for threads or thread mutual
69 * exclusion must be satisfied by the layer above this driver.
73 * Asserts are used within all Xilinx drivers to enforce constraints on argument
74 * values. Asserts can be turned off on a system-wide basis by defining, at
75 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
76 * is recommended that users leave asserts on during development.
78 * <b>Building the driver</b>
80 * The XGpioPs driver is composed of several source files. This allows the user
81 * to build and link only those parts of the driver that are necessary.
85 * MODIFICATION HISTORY:
87 * Ver Who Date Changes
88 * ----- ---- -------- -----------------------------------------------
89 * 1.00a sv 01/15/10 First Release
90 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
91 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
92 * relevant to Zynq device.The interrupts are disabled
93 * for output pins on all banks during initialization.
94 * 1.02a hk 08/22/13 Added low level reset API
95 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
96 * 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
97 * passed to APIs. CR# 822636
98 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
99 * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
103 ******************************************************************************/
104 #ifndef XGPIOPS_H /* prevent circular inclusions */
105 #define XGPIOPS_H /* by using protection macros */
111 /***************************** Include Files *********************************/
114 #include "xgpiops_hw.h"
115 #include "xplatform_info.h"
117 /************************** Constant Definitions *****************************/
119 /** @name Interrupt types
121 * The following constants define the interrupt types that can be set for each
124 #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
125 #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
126 #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
127 #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
128 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
131 #define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
132 #define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
133 #define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
134 #define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
135 #define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
137 #ifdef XPAR_PSU_GPIO_0_BASEADDR
138 #define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
139 #define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
142 #define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
143 * Zynq Ultrascale+ MP GPIO device
145 #define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
147 #define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
148 * Zynq Ultrascale+ MP GPIO device
156 #define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
163 /**************************** Type Definitions *******************************/
165 /****************************************************************************/
167 * This handler data type allows the user to define a callback function to
168 * handle the interrupts for the GPIO device. The application using this
169 * driver is expected to define a handler of this type, to support interrupt
170 * driven mode. The handler executes in an interrupt context such that minimal
171 * processing should be performed.
173 * @param CallBackRef is a callback reference passed in by the upper layer
174 * when setting the callback functions for a GPIO bank. It is
175 * passed back to the upper layer when the callback is invoked. Its
176 * type is not important to the driver component, so it is a void
178 * @param Bank is the bank for which the interrupt status has changed.
179 * @param Status is the Interrupt status of the GPIO bank.
181 *****************************************************************************/
182 typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
185 * This typedef contains configuration information for a device.
188 u16 DeviceId; /**< Unique ID of device */
189 u32 BaseAddr; /**< Register base address */
193 * The XGpioPs driver instance data. The user is required to allocate a
194 * variable of this type for the GPIO device in the system. A pointer
195 * to a variable of this type is then passed to the driver API functions.
198 XGpioPs_Config GpioConfig; /**< Device configuration */
199 u32 IsReady; /**< Device is initialized and ready */
200 XGpioPs_Handler Handler; /**< Status handlers for all banks */
201 void *CallBackRef; /**< Callback ref for bank handlers */
202 u32 Platform; /**< Platform data */
203 u32 MaxPinNum; /**< Max pins in the GPIO device */
204 u8 MaxBanks; /**< Max banks in a GPIO device */
207 /***************** Macros (Inline Functions) Definitions *********************/
209 /************************** Function Prototypes ******************************/
211 /* Functions in xgpiops.c */
212 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
215 /* Bank APIs in xgpiops.c */
216 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
217 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
218 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
219 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
220 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
221 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
222 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
224 /* Pin APIs in xgpiops.c */
225 u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
226 void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
227 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
228 u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
229 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
230 u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
232 /* Diagnostic functions in xgpiops_selftest.c */
233 s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
235 /* Functions in xgpiops_intr.c */
236 /* Bank APIs in xgpiops_intr.c */
237 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
238 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
239 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
240 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
241 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
242 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
243 u32 IntrPolarity, u32 IntrOnAny);
244 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
245 u32 *IntrPolarity, u32 *IntrOnAny);
246 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
247 XGpioPs_Handler FuncPointer);
248 void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
250 /* Pin APIs in xgpiops_intr.c */
251 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
252 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
254 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
255 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
256 u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
257 u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
258 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
260 /* Functions in xgpiops_sinit.c */
261 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
267 #endif /* end of protection macro */