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33 /*****************************************************************************/
37 * @addtogroup gpiops_v3_3
41 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
44 * The GPIO Controller supports the following features:
46 * - Masked writes (There are no masked reads)
48 * - Configurable Interrupts (Level/Edge)
50 * This driver is intended to be RTOS and processor independent. Any needs for
51 * dynamic memory management, threads or thread mutual exclusion, virtual
52 * memory, or cache control must be satisfied by the layer above this driver.
54 * This driver supports all the features listed above, if applicable.
56 * <b>Driver Description</b>
58 * The device driver enables higher layer software (e.g., an application) to
59 * communicate to the GPIO.
63 * The driver provides interrupt management functions and an interrupt handler.
64 * Users of this driver need to provide callback functions. An interrupt handler
65 * example is available with the driver.
69 * This driver is not thread safe. Any needs for threads or thread mutual
70 * exclusion must be satisfied by the layer above this driver.
74 * Asserts are used within all Xilinx drivers to enforce constraints on argument
75 * values. Asserts can be turned off on a system-wide basis by defining, at
76 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
77 * is recommended that users leave asserts on during development.
79 * <b>Building the driver</b>
81 * The XGpioPs driver is composed of several source files. This allows the user
82 * to build and link only those parts of the driver that are necessary.
86 * MODIFICATION HISTORY:
88 * Ver Who Date Changes
89 * ----- ---- -------- -----------------------------------------------
90 * 1.00a sv 01/15/10 First Release
91 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
92 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
93 * relevant to Zynq device.The interrupts are disabled
94 * for output pins on all banks during initialization.
95 * 1.02a hk 08/22/13 Added low level reset API
96 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
97 * 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
98 * passed to APIs. CR# 822636
99 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
100 * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
101 * ms 03/17/17 Added readme.txt file in examples folder for doxygen
103 * ms 04/05/17 Added tabspace for return statements in functions of
104 * gpiops examples for proper documentation while
105 * generating doxygen.
106 * 3.3 ms 04/17/17 Added notes about gpio input and output pin description
107 * for zcu102 and zc702 boards in polled and interrupt
108 * example, configured Interrupt pin to input pin for
109 * proper functioning of interrupt example.
112 ******************************************************************************/
113 #ifndef XGPIOPS_H /* prevent circular inclusions */
114 #define XGPIOPS_H /* by using protection macros */
120 /***************************** Include Files *********************************/
123 #include "xgpiops_hw.h"
124 #include "xplatform_info.h"
126 /************************** Constant Definitions *****************************/
128 /** @name Interrupt types
130 * The following constants define the interrupt types that can be set for each
133 #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
134 #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
135 #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
136 #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
137 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
140 #define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
141 #define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
142 #define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
143 #define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
144 #define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
146 #ifdef XPAR_PSU_GPIO_0_BASEADDR
147 #define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
148 #define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
151 #define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
152 * Zynq Ultrascale+ MP GPIO device
154 #define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
156 #define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
157 * Zynq Ultrascale+ MP GPIO device
165 #define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
172 /**************************** Type Definitions *******************************/
174 /****************************************************************************/
176 * This handler data type allows the user to define a callback function to
177 * handle the interrupts for the GPIO device. The application using this
178 * driver is expected to define a handler of this type, to support interrupt
179 * driven mode. The handler executes in an interrupt context such that minimal
180 * processing should be performed.
182 * @param CallBackRef is a callback reference passed in by the upper layer
183 * when setting the callback functions for a GPIO bank. It is
184 * passed back to the upper layer when the callback is invoked. Its
185 * type is not important to the driver component, so it is a void
187 * @param Bank is the bank for which the interrupt status has changed.
188 * @param Status is the Interrupt status of the GPIO bank.
190 *****************************************************************************/
191 typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
194 * This typedef contains configuration information for a device.
197 u16 DeviceId; /**< Unique ID of device */
198 u32 BaseAddr; /**< Register base address */
202 * The XGpioPs driver instance data. The user is required to allocate a
203 * variable of this type for the GPIO device in the system. A pointer
204 * to a variable of this type is then passed to the driver API functions.
207 XGpioPs_Config GpioConfig; /**< Device configuration */
208 u32 IsReady; /**< Device is initialized and ready */
209 XGpioPs_Handler Handler; /**< Status handlers for all banks */
210 void *CallBackRef; /**< Callback ref for bank handlers */
211 u32 Platform; /**< Platform data */
212 u32 MaxPinNum; /**< Max pins in the GPIO device */
213 u8 MaxBanks; /**< Max banks in a GPIO device */
216 /***************** Macros (Inline Functions) Definitions *********************/
218 /************************** Function Prototypes ******************************/
220 /* Functions in xgpiops.c */
221 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
224 /* Bank APIs in xgpiops.c */
225 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
226 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
227 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
228 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
229 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
230 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
231 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
233 /* Pin APIs in xgpiops.c */
234 u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
235 void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
236 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
237 u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
238 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
239 u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
241 /* Diagnostic functions in xgpiops_selftest.c */
242 s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
244 /* Functions in xgpiops_intr.c */
245 /* Bank APIs in xgpiops_intr.c */
246 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
247 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
248 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
249 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
250 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
251 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
252 u32 IntrPolarity, u32 IntrOnAny);
253 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
254 u32 *IntrPolarity, u32 *IntrOnAny);
255 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
256 XGpioPs_Handler FuncPointer);
257 void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
259 /* Pin APIs in xgpiops_intr.c */
260 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
261 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
263 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
264 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
265 u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
266 u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
267 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
269 /* Functions in xgpiops_sinit.c */
270 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
276 #endif /* end of protection macro */