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32 /*****************************************************************************/
35 * @addtogroup ipipsu_v2_3
39 * This is the header file for implementation of IPIPSU driver.
40 * Inter Processor Interrupt (IPI) is used for communication between
41 * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
42 * and Observation registers for communication between processors. Each IPI path
43 * has a 32 byte buffer associated with it and these buffers are located in the
44 * XPPU RAM. This driver supports the following operations:
46 * - Trigger IPIs to CPUs on the SoC
47 * - Write and Read Message buffers
48 * - Read the status of Observation Register to get status of Triggered IPI
49 * - Enable/Disable IPIs from selected Masters
50 * - Read the Status register to get the source of an incoming IPI
52 * <b>Initialization</b>
53 * The config data for the driver is loaded and is based on the HW build. The
54 * XIpiPsu_Config data structure contains all the data related to the
55 * IPI driver instance and also teh available Target CPUs.
57 * <b>Sending an IPI</b>
58 * The following steps can be followed to send an IPI:
59 * - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
60 * - Trigger IPI using XIpiPsu_TriggerIpi()
61 * - Wait for Ack using XIpiPsu_PollForAck()
62 * - Read response using XIpiPsu_ReadMessage()
64 * @note XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
65 * previous IPI was serviced by the target
67 * <b>Receiving an IPI</b>
68 * To receive an IPI, the following sequence can be followed:
69 * - Register an interrupt handler for the IPIs interrupt ID
70 * - Enable the required sources using XIpiPsu_InterruptEnable()
71 * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
72 * - Read the message form source using XIpiPsu_ReadMessage()
73 * - Write the response using XIpiPsu_WriteMessage()
74 * - Ack the IPI using XIpiPsu_ClearInterruptStatus()
76 * @note XIpiPsu_Reset can be used at startup to clear the status and
80 * MODIFICATION HISTORY:
82 * Ver Who Date Changes
83 * ---- --- -------- --------------------------------------------------
84 * 2.2 ms 01/23/17 Modified xil_printf statement in main function for all
85 * examples to ensure that "Successfully ran" and "Failed"
86 * strings are available in all examples. This is a fix
88 * kvn 02/17/17 Add support for updating ConfigTable at run time
89 * ms 03/17/17 Added readme.txt file in examples folder for doxygen
91 * 2.3 ms 04/11/17 Modified tcl file to add suffix U for all macro
92 * definitions of ipipsu in xparameters.h
95 *****************************************************************************/
96 /*****************************************************************************/
101 /***************************** Include Files *********************************/
104 #include "xipipsu_hw.h"
106 /************************** Constant Definitions *****************************/
107 #define XIPIPSU_BUF_TYPE_MSG (0x00000001U)
108 #define XIPIPSU_BUF_TYPE_RESP (0x00000002U)
109 #define XIPIPSU_MAX_MSG_LEN XIPIPSU_MSG_BUF_SIZE
110 /**************************** Type Definitions *******************************/
112 * Data structure used to refer IPI Targets
115 u32 Mask; /**< Bit Mask for the target */
116 u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
120 * This typedef contains configuration information for the device.
123 u32 DeviceId; /**< Unique ID of device */
124 u32 BaseAddress; /**< Base address of the device */
125 u32 BitMask; /**< BitMask to be used to identify this CPU */
126 u32 BufferIndex; /**< Index of the IPI Message Buffer */
127 u32 IntId; /**< Interrupt ID on GIC **/
128 u32 TargetCount; /**< Number of available IPI Targets */
129 XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
133 * The XIpiPsu driver instance data. The user is required to allocate a
134 * variable of this type for each IPI device in the system. A pointer
135 * to a variable of this type is then passed to the driver API functions.
138 XIpiPsu_Config Config; /**< Configuration structure */
139 u32 IsReady; /**< Device is initialized and ready */
140 u32 Options; /**< Options set in the device */
143 /***************** Macros (Inline Functions) Definitions *********************/
146 * Read the register specified by the base address and offset
148 * @param BaseAddress is the base address of the IPI instance
149 * @param RegOffset is the offset of the register relative to base
151 * @return Value of the specified register
154 * u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
156 *****************************************************************************/
158 #define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
159 Xil_In32((BaseAddress) + (RegOffset))
161 /****************************************************************************/
164 * Write a value into a register specified by base address and offset
166 * @param BaseAddress is the base address of the IPI instance
167 * @param RegOffset is the offset of the register relative to base
168 * @param Data is a 32-bit value that is to be written into the specified register
172 * void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
174 *****************************************************************************/
176 #define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
177 Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
179 /****************************************************************************/
182 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
183 * each bit set to 1 in <i>Mask</i>, will be enabled.
185 * @param InstancePtr is a pointer to the instance to be worked on.
186 * @param Mask contains a bit mask of interrupts to enable. The mask can
187 * be formed using a set of bitwise or'd values of individual CPU masks
191 * void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
193 *****************************************************************************/
194 #define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
195 XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
196 XIPIPSU_IER_OFFSET, \
197 ((Mask) & XIPIPSU_ALL_MASK));
199 /****************************************************************************/
202 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
203 * each bit set to 1 in <i>Mask</i>, will be disabled.
205 * @param InstancePtr is a pointer to the instance to be worked on.
206 * @param Mask contains a bit mask of interrupts to disable. The mask can
207 * be formed using a set of bitwise or'd values of individual CPU masks
211 * void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
213 *****************************************************************************/
214 #define XIpiPsu_InterruptDisable(InstancePtr, Mask) \
215 XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
216 XIPIPSU_IDR_OFFSET, \
217 ((Mask) & XIPIPSU_ALL_MASK));
218 /****************************************************************************/
221 * Get the <i>STATUS REGISTER</i> of the current IPI instance.
223 * @param InstancePtr is a pointer to the instance to be worked on.
224 * @return Returns the Interrupt Status register(ISR) contents
225 * @note User needs to parse this 32-bit value to check the source CPU
227 * u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
229 *****************************************************************************/
230 #define XIpiPsu_GetInterruptStatus(InstancePtr) \
231 XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
233 /****************************************************************************/
236 * Clear the <i>STATUS REGISTER</i> of the current IPI instance.
237 * The corresponding interrupt status for
238 * each bit set to 1 in <i>Mask</i>, will be cleared
240 * @param InstancePtr is a pointer to the instance to be worked on.
241 * @param Mask corresponding to the source CPU*
243 * @note This function should be used after handling the IPI.
244 * Clearing the status will automatically clear the corresponding bit in
245 * OBSERVATION register of Source CPU
247 * void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
249 *****************************************************************************/
251 #define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask) \
252 XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
253 XIPIPSU_ISR_OFFSET, \
254 ((Mask) & XIPIPSU_ALL_MASK));
255 /****************************************************************************/
258 * Get the <i>OBSERVATION REGISTER</i> of the current IPI instance.
260 * @param InstancePtr is a pointer to the instance to be worked on.
261 * @return Returns the Observation register(OBS) contents
262 * @note User needs to parse this 32-bit value to check the status of
265 * u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
267 *****************************************************************************/
268 #define XIpiPsu_GetObsStatus(InstancePtr) \
269 XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
271 /****************************************************************************/
272 /************************** Function Prototypes *****************************/
274 /* Static lookup function implemented in xipipsu_sinit.c */
276 XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
278 /* Interface Functions implemented in xipipsu.c */
280 XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
281 UINTPTR EffectiveAddress);
283 void XIpiPsu_Reset(XIpiPsu *InstancePtr);
285 XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
287 XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
290 XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
291 u32 MsgLength, u8 BufferType);
293 XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
294 u32 MsgLength, u8 BufferType);
295 void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr);
297 #endif /* XIPIPSU_H_ */