1 /******************************************************************************
3 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
35 * @file xsysmonpsu_hw.h
37 * This header file contains the identifiers and basic driver functions (or
38 * macros) that can be used to access the device. Other driver functions
39 * are defined in xsysmonpsu.h.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ----- -------- -----------------------------------------------
46 * 1.0 kvn 12/15/15 First release
47 * 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
48 * SEQ_CH2 and SEQ_AVG2 offsets and bit masks
49 * 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset.
53 ******************************************************************************/
55 #ifndef XSYSMONPSU_HW_H__
56 #define XSYSMONPSU_HW_H__
63 /***************************** Include Files ********************************/
65 #include "xil_types.h"
66 #include "xil_assert.h"
68 #include "xparameters.h"
71 * XSysmonPsu Base Address
73 #define XSYSMONPSU_BASEADDR 0xFFA50000U
76 * Register: XSysmonPsuMisc
78 #define XSYSMONPSU_MISC_OFFSET 0x00000000U
79 #define XSYSMONPSU_MISC_RSTVAL 0x00000000U
81 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_SHIFT 1U
82 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_WIDTH 1U
83 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_MASK 0x00000002U
85 #define XSYSMONPSU_MISC_SLVERR_EN_SHIFT 0U
86 #define XSYSMONPSU_MISC_SLVERR_EN_WIDTH 1U
87 #define XSYSMONPSU_MISC_SLVERR_EN_MASK 0x00000001U
90 * Register: XSysmonPsuIsr0
92 #define XSYSMONPSU_ISR_0_OFFSET 0x00000010U
93 #define XSYSMONPSU_ISR_0_MASK 0xffffffffU
94 #define XSYSMONPSU_ISR_0_RSTVAL 0x00000000U
96 #define XSYSMONPSU_ISR_0_PL_ALM_15_SHIFT 31U
97 #define XSYSMONPSU_ISR_0_PL_ALM_15_WIDTH 1U
98 #define XSYSMONPSU_ISR_0_PL_ALM_15_MASK 0x80000000U
100 #define XSYSMONPSU_ISR_0_PL_ALM_14_SHIFT 30U
101 #define XSYSMONPSU_ISR_0_PL_ALM_14_WIDTH 1U
102 #define XSYSMONPSU_ISR_0_PL_ALM_14_MASK 0x40000000U
104 #define XSYSMONPSU_ISR_0_PL_ALM_13_SHIFT 29U
105 #define XSYSMONPSU_ISR_0_PL_ALM_13_WIDTH 1U
106 #define XSYSMONPSU_ISR_0_PL_ALM_13_MASK 0x20000000U
108 #define XSYSMONPSU_ISR_0_PL_ALM_12_SHIFT 28U
109 #define XSYSMONPSU_ISR_0_PL_ALM_12_WIDTH 1U
110 #define XSYSMONPSU_ISR_0_PL_ALM_12_MASK 0x10000000U
112 #define XSYSMONPSU_ISR_0_PL_ALM_11_SHIFT 27U
113 #define XSYSMONPSU_ISR_0_PL_ALM_11_WIDTH 1U
114 #define XSYSMONPSU_ISR_0_PL_ALM_11_MASK 0x08000000U
116 #define XSYSMONPSU_ISR_0_PL_ALM_10_SHIFT 26U
117 #define XSYSMONPSU_ISR_0_PL_ALM_10_WIDTH 1U
118 #define XSYSMONPSU_ISR_0_PL_ALM_10_MASK 0x04000000U
120 #define XSYSMONPSU_ISR_0_PL_ALM_9_SHIFT 25U
121 #define XSYSMONPSU_ISR_0_PL_ALM_9_WIDTH 1U
122 #define XSYSMONPSU_ISR_0_PL_ALM_9_MASK 0x02000000U
124 #define XSYSMONPSU_ISR_0_PL_ALM_8_SHIFT 24U
125 #define XSYSMONPSU_ISR_0_PL_ALM_8_WIDTH 1U
126 #define XSYSMONPSU_ISR_0_PL_ALM_8_MASK 0x01000000U
128 #define XSYSMONPSU_ISR_0_PL_ALM_7_SHIFT 23U
129 #define XSYSMONPSU_ISR_0_PL_ALM_7_WIDTH 1U
130 #define XSYSMONPSU_ISR_0_PL_ALM_7_MASK 0x00800000U
132 #define XSYSMONPSU_ISR_0_PL_ALM_6_SHIFT 22U
133 #define XSYSMONPSU_ISR_0_PL_ALM_6_WIDTH 1U
134 #define XSYSMONPSU_ISR_0_PL_ALM_6_MASK 0x00400000U
136 #define XSYSMONPSU_ISR_0_PL_ALM_5_SHIFT 21U
137 #define XSYSMONPSU_ISR_0_PL_ALM_5_WIDTH 1U
138 #define XSYSMONPSU_ISR_0_PL_ALM_5_MASK 0x00200000U
140 #define XSYSMONPSU_ISR_0_PL_ALM_4_SHIFT 20U
141 #define XSYSMONPSU_ISR_0_PL_ALM_4_WIDTH 1U
142 #define XSYSMONPSU_ISR_0_PL_ALM_4_MASK 0x00100000U
144 #define XSYSMONPSU_ISR_0_PL_ALM_3_SHIFT 19U
145 #define XSYSMONPSU_ISR_0_PL_ALM_3_WIDTH 1U
146 #define XSYSMONPSU_ISR_0_PL_ALM_3_MASK 0x00080000U
148 #define XSYSMONPSU_ISR_0_PL_ALM_2_SHIFT 18U
149 #define XSYSMONPSU_ISR_0_PL_ALM_2_WIDTH 1U
150 #define XSYSMONPSU_ISR_0_PL_ALM_2_MASK 0x00040000U
152 #define XSYSMONPSU_ISR_0_PL_ALM_1_SHIFT 17U
153 #define XSYSMONPSU_ISR_0_PL_ALM_1_WIDTH 1U
154 #define XSYSMONPSU_ISR_0_PL_ALM_1_MASK 0x00020000U
156 #define XSYSMONPSU_ISR_0_PL_ALM_0_SHIFT 16U
157 #define XSYSMONPSU_ISR_0_PL_ALM_0_WIDTH 1U
158 #define XSYSMONPSU_ISR_0_PL_ALM_0_MASK 0x00010000U
160 #define XSYSMONPSU_ISR_0_PS_ALM_15_SHIFT 15U
161 #define XSYSMONPSU_ISR_0_PS_ALM_15_WIDTH 1U
162 #define XSYSMONPSU_ISR_0_PS_ALM_15_MASK 0x00008000U
164 #define XSYSMONPSU_ISR_0_PS_ALM_14_SHIFT 14U
165 #define XSYSMONPSU_ISR_0_PS_ALM_14_WIDTH 1U
166 #define XSYSMONPSU_ISR_0_PS_ALM_14_MASK 0x00004000U
168 #define XSYSMONPSU_ISR_0_PS_ALM_13_SHIFT 13U
169 #define XSYSMONPSU_ISR_0_PS_ALM_13_WIDTH 1U
170 #define XSYSMONPSU_ISR_0_PS_ALM_13_MASK 0x00002000U
172 #define XSYSMONPSU_ISR_0_PS_ALM_12_SHIFT 12U
173 #define XSYSMONPSU_ISR_0_PS_ALM_12_WIDTH 1U
174 #define XSYSMONPSU_ISR_0_PS_ALM_12_MASK 0x00001000U
176 #define XSYSMONPSU_ISR_0_PS_ALM_11_SHIFT 11U
177 #define XSYSMONPSU_ISR_0_PS_ALM_11_WIDTH 1U
178 #define XSYSMONPSU_ISR_0_PS_ALM_11_MASK 0x00000800U
180 #define XSYSMONPSU_ISR_0_PS_ALM_10_SHIFT 10U
181 #define XSYSMONPSU_ISR_0_PS_ALM_10_WIDTH 1U
182 #define XSYSMONPSU_ISR_0_PS_ALM_10_MASK 0x00000400U
184 #define XSYSMONPSU_ISR_0_PS_ALM_9_SHIFT 9U
185 #define XSYSMONPSU_ISR_0_PS_ALM_9_WIDTH 1U
186 #define XSYSMONPSU_ISR_0_PS_ALM_9_MASK 0x00000200U
188 #define XSYSMONPSU_ISR_0_PS_ALM_8_SHIFT 8U
189 #define XSYSMONPSU_ISR_0_PS_ALM_8_WIDTH 1U
190 #define XSYSMONPSU_ISR_0_PS_ALM_8_MASK 0x00000100U
192 #define XSYSMONPSU_ISR_0_PS_ALM_7_SHIFT 7U
193 #define XSYSMONPSU_ISR_0_PS_ALM_7_WIDTH 1U
194 #define XSYSMONPSU_ISR_0_PS_ALM_7_MASK 0x00000080U
196 #define XSYSMONPSU_ISR_0_PS_ALM_6_SHIFT 6U
197 #define XSYSMONPSU_ISR_0_PS_ALM_6_WIDTH 1U
198 #define XSYSMONPSU_ISR_0_PS_ALM_6_MASK 0x00000040U
200 #define XSYSMONPSU_ISR_0_PS_ALM_5_SHIFT 5U
201 #define XSYSMONPSU_ISR_0_PS_ALM_5_WIDTH 1U
202 #define XSYSMONPSU_ISR_0_PS_ALM_5_MASK 0x00000020U
204 #define XSYSMONPSU_ISR_0_PS_ALM_4_SHIFT 4U
205 #define XSYSMONPSU_ISR_0_PS_ALM_4_WIDTH 1U
206 #define XSYSMONPSU_ISR_0_PS_ALM_4_MASK 0x00000010U
208 #define XSYSMONPSU_ISR_0_PS_ALM_3_SHIFT 3U
209 #define XSYSMONPSU_ISR_0_PS_ALM_3_WIDTH 1U
210 #define XSYSMONPSU_ISR_0_PS_ALM_3_MASK 0x00000008U
212 #define XSYSMONPSU_ISR_0_PS_ALM_2_SHIFT 2U
213 #define XSYSMONPSU_ISR_0_PS_ALM_2_WIDTH 1U
214 #define XSYSMONPSU_ISR_0_PS_ALM_2_MASK 0x00000004U
216 #define XSYSMONPSU_ISR_0_PS_ALM_1_SHIFT 1U
217 #define XSYSMONPSU_ISR_0_PS_ALM_1_WIDTH 1U
218 #define XSYSMONPSU_ISR_0_PS_ALM_1_MASK 0x00000002U
220 #define XSYSMONPSU_ISR_0_PS_ALM_0_SHIFT 0U
221 #define XSYSMONPSU_ISR_0_PS_ALM_0_WIDTH 1U
222 #define XSYSMONPSU_ISR_0_PS_ALM_0_MASK 0x00000001U
225 * Register: XSysmonPsuIsr1
227 #define XSYSMONPSU_ISR_1_OFFSET 0x00000014U
228 #define XSYSMONPSU_ISR_1_MASK 0xe000001fU
229 #define XSYSMONPSU_ISR_1_RSTVAL 0x00000000U
231 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_SHIFT 31U
232 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_WIDTH 1U
233 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_MASK 0x80000000U
235 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
236 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
237 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
239 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
240 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
241 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
243 #define XSYSMONPSU_ISR_1_EOS_SHIFT 4U
244 #define XSYSMONPSU_ISR_1_EOS_WIDTH 1U
245 #define XSYSMONPSU_ISR_1_EOS_MASK 0x00000010U
247 #define XSYSMONPSU_ISR_1_EOC_SHIFT 3U
248 #define XSYSMONPSU_ISR_1_EOC_WIDTH 1U
249 #define XSYSMONPSU_ISR_1_EOC_MASK 0x00000008U
251 #define XSYSMONPSU_ISR_1_PL_OT_SHIFT 2U
252 #define XSYSMONPSU_ISR_1_PL_OT_WIDTH 1U
253 #define XSYSMONPSU_ISR_1_PL_OT_MASK 0x00000004U
255 #define XSYSMONPSU_ISR_1_PS_LPD_OT_SHIFT 1U
256 #define XSYSMONPSU_ISR_1_PS_LPD_OT_WIDTH 1U
257 #define XSYSMONPSU_ISR_1_PS_LPD_OT_MASK 0x00000002U
259 #define XSYSMONPSU_ISR_1_PS_FPD_OT_SHIFT 0U
260 #define XSYSMONPSU_ISR_1_PS_FPD_OT_WIDTH 1U
261 #define XSYSMONPSU_ISR_1_PS_FPD_OT_MASK 0x00000001U
264 * Register: XSysmonPsuImr0
266 #define XSYSMONPSU_IMR_0_OFFSET 0x00000018U
267 #define XSYSMONPSU_IMR_0_RSTVAL 0xffffffffU
269 #define XSYSMONPSU_IMR_0_PL_ALM_15_SHIFT 31U
270 #define XSYSMONPSU_IMR_0_PL_ALM_15_WIDTH 1U
271 #define XSYSMONPSU_IMR_0_PL_ALM_15_MASK 0x80000000U
273 #define XSYSMONPSU_IMR_0_PL_ALM_14_SHIFT 30U
274 #define XSYSMONPSU_IMR_0_PL_ALM_14_WIDTH 1U
275 #define XSYSMONPSU_IMR_0_PL_ALM_14_MASK 0x40000000U
277 #define XSYSMONPSU_IMR_0_PL_ALM_13_SHIFT 29U
278 #define XSYSMONPSU_IMR_0_PL_ALM_13_WIDTH 1U
279 #define XSYSMONPSU_IMR_0_PL_ALM_13_MASK 0x20000000U
281 #define XSYSMONPSU_IMR_0_PL_ALM_12_SHIFT 28U
282 #define XSYSMONPSU_IMR_0_PL_ALM_12_WIDTH 1U
283 #define XSYSMONPSU_IMR_0_PL_ALM_12_MASK 0x10000000U
285 #define XSYSMONPSU_IMR_0_PL_ALM_11_SHIFT 27U
286 #define XSYSMONPSU_IMR_0_PL_ALM_11_WIDTH 1U
287 #define XSYSMONPSU_IMR_0_PL_ALM_11_MASK 0x08000000U
289 #define XSYSMONPSU_IMR_0_PL_ALM_10_SHIFT 26U
290 #define XSYSMONPSU_IMR_0_PL_ALM_10_WIDTH 1U
291 #define XSYSMONPSU_IMR_0_PL_ALM_10_MASK 0x04000000U
293 #define XSYSMONPSU_IMR_0_PL_ALM_9_SHIFT 25U
294 #define XSYSMONPSU_IMR_0_PL_ALM_9_WIDTH 1U
295 #define XSYSMONPSU_IMR_0_PL_ALM_9_MASK 0x02000000U
297 #define XSYSMONPSU_IMR_0_PL_ALM_8_SHIFT 24U
298 #define XSYSMONPSU_IMR_0_PL_ALM_8_WIDTH 1U
299 #define XSYSMONPSU_IMR_0_PL_ALM_8_MASK 0x01000000U
301 #define XSYSMONPSU_IMR_0_PL_ALM_7_SHIFT 23U
302 #define XSYSMONPSU_IMR_0_PL_ALM_7_WIDTH 1U
303 #define XSYSMONPSU_IMR_0_PL_ALM_7_MASK 0x00800000U
305 #define XSYSMONPSU_IMR_0_PL_ALM_6_SHIFT 22U
306 #define XSYSMONPSU_IMR_0_PL_ALM_6_WIDTH 1U
307 #define XSYSMONPSU_IMR_0_PL_ALM_6_MASK 0x00400000U
309 #define XSYSMONPSU_IMR_0_PL_ALM_5_SHIFT 21U
310 #define XSYSMONPSU_IMR_0_PL_ALM_5_WIDTH 1U
311 #define XSYSMONPSU_IMR_0_PL_ALM_5_MASK 0x00200000U
313 #define XSYSMONPSU_IMR_0_PL_ALM_4_SHIFT 20U
314 #define XSYSMONPSU_IMR_0_PL_ALM_4_WIDTH 1U
315 #define XSYSMONPSU_IMR_0_PL_ALM_4_MASK 0x00100000U
317 #define XSYSMONPSU_IMR_0_PL_ALM_3_SHIFT 19U
318 #define XSYSMONPSU_IMR_0_PL_ALM_3_WIDTH 1U
319 #define XSYSMONPSU_IMR_0_PL_ALM_3_MASK 0x00080000U
321 #define XSYSMONPSU_IMR_0_PL_ALM_2_SHIFT 18U
322 #define XSYSMONPSU_IMR_0_PL_ALM_2_WIDTH 1U
323 #define XSYSMONPSU_IMR_0_PL_ALM_2_MASK 0x00040000U
325 #define XSYSMONPSU_IMR_0_PL_ALM_1_SHIFT 17U
326 #define XSYSMONPSU_IMR_0_PL_ALM_1_WIDTH 1U
327 #define XSYSMONPSU_IMR_0_PL_ALM_1_MASK 0x00020000U
329 #define XSYSMONPSU_IMR_0_PL_ALM_0_SHIFT 16U
330 #define XSYSMONPSU_IMR_0_PL_ALM_0_WIDTH 1U
331 #define XSYSMONPSU_IMR_0_PL_ALM_0_MASK 0x00010000U
333 #define XSYSMONPSU_IMR_0_PS_ALM_15_SHIFT 15U
334 #define XSYSMONPSU_IMR_0_PS_ALM_15_WIDTH 1U
335 #define XSYSMONPSU_IMR_0_PS_ALM_15_MASK 0x00008000U
337 #define XSYSMONPSU_IMR_0_PS_ALM_14_SHIFT 14U
338 #define XSYSMONPSU_IMR_0_PS_ALM_14_WIDTH 1U
339 #define XSYSMONPSU_IMR_0_PS_ALM_14_MASK 0x00004000U
341 #define XSYSMONPSU_IMR_0_PS_ALM_13_SHIFT 13U
342 #define XSYSMONPSU_IMR_0_PS_ALM_13_WIDTH 1U
343 #define XSYSMONPSU_IMR_0_PS_ALM_13_MASK 0x00002000U
345 #define XSYSMONPSU_IMR_0_PS_ALM_12_SHIFT 12U
346 #define XSYSMONPSU_IMR_0_PS_ALM_12_WIDTH 1U
347 #define XSYSMONPSU_IMR_0_PS_ALM_12_MASK 0x00001000U
349 #define XSYSMONPSU_IMR_0_PS_ALM_11_SHIFT 11U
350 #define XSYSMONPSU_IMR_0_PS_ALM_11_WIDTH 1U
351 #define XSYSMONPSU_IMR_0_PS_ALM_11_MASK 0x00000800U
353 #define XSYSMONPSU_IMR_0_PS_ALM_10_SHIFT 10U
354 #define XSYSMONPSU_IMR_0_PS_ALM_10_WIDTH 1U
355 #define XSYSMONPSU_IMR_0_PS_ALM_10_MASK 0x00000400U
357 #define XSYSMONPSU_IMR_0_PS_ALM_9_SHIFT 9U
358 #define XSYSMONPSU_IMR_0_PS_ALM_9_WIDTH 1U
359 #define XSYSMONPSU_IMR_0_PS_ALM_9_MASK 0x00000200U
361 #define XSYSMONPSU_IMR_0_PS_ALM_8_SHIFT 8U
362 #define XSYSMONPSU_IMR_0_PS_ALM_8_WIDTH 1U
363 #define XSYSMONPSU_IMR_0_PS_ALM_8_MASK 0x00000100U
365 #define XSYSMONPSU_IMR_0_PS_ALM_7_SHIFT 7U
366 #define XSYSMONPSU_IMR_0_PS_ALM_7_WIDTH 1U
367 #define XSYSMONPSU_IMR_0_PS_ALM_7_MASK 0x00000080U
369 #define XSYSMONPSU_IMR_0_PS_ALM_6_SHIFT 6U
370 #define XSYSMONPSU_IMR_0_PS_ALM_6_WIDTH 1U
371 #define XSYSMONPSU_IMR_0_PS_ALM_6_MASK 0x00000040U
373 #define XSYSMONPSU_IMR_0_PS_ALM_5_SHIFT 5U
374 #define XSYSMONPSU_IMR_0_PS_ALM_5_WIDTH 1U
375 #define XSYSMONPSU_IMR_0_PS_ALM_5_MASK 0x00000020U
377 #define XSYSMONPSU_IMR_0_PS_ALM_4_SHIFT 4U
378 #define XSYSMONPSU_IMR_0_PS_ALM_4_WIDTH 1U
379 #define XSYSMONPSU_IMR_0_PS_ALM_4_MASK 0x00000010U
381 #define XSYSMONPSU_IMR_0_PS_ALM_3_SHIFT 3U
382 #define XSYSMONPSU_IMR_0_PS_ALM_3_WIDTH 1U
383 #define XSYSMONPSU_IMR_0_PS_ALM_3_MASK 0x00000008U
385 #define XSYSMONPSU_IMR_0_PS_ALM_2_SHIFT 2U
386 #define XSYSMONPSU_IMR_0_PS_ALM_2_WIDTH 1U
387 #define XSYSMONPSU_IMR_0_PS_ALM_2_MASK 0x00000004U
389 #define XSYSMONPSU_IMR_0_PS_ALM_1_SHIFT 1U
390 #define XSYSMONPSU_IMR_0_PS_ALM_1_WIDTH 1U
391 #define XSYSMONPSU_IMR_0_PS_ALM_1_MASK 0x00000002U
393 #define XSYSMONPSU_IMR_0_PS_ALM_0_SHIFT 0U
394 #define XSYSMONPSU_IMR_0_PS_ALM_0_WIDTH 1U
395 #define XSYSMONPSU_IMR_0_PS_ALM_0_MASK 0x00000001U
398 * Register: XSysmonPsuImr1
400 #define XSYSMONPSU_IMR_1_OFFSET 0x0000001CU
401 #define XSYSMONPSU_IMR_1_RSTVAL 0xe000001fU
403 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_SHIFT 31U
404 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_WIDTH 1U
405 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_MASK 0x80000000U
407 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
408 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
409 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
411 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
412 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
413 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
415 #define XSYSMONPSU_IMR_1_EOS_SHIFT 4U
416 #define XSYSMONPSU_IMR_1_EOS_WIDTH 1U
417 #define XSYSMONPSU_IMR_1_EOS_MASK 0x00000010U
419 #define XSYSMONPSU_IMR_1_EOC_SHIFT 3U
420 #define XSYSMONPSU_IMR_1_EOC_WIDTH 1U
421 #define XSYSMONPSU_IMR_1_EOC_MASK 0x00000008U
423 #define XSYSMONPSU_IMR_1_PL_OT_SHIFT 2U
424 #define XSYSMONPSU_IMR_1_PL_OT_WIDTH 1U
425 #define XSYSMONPSU_IMR_1_PL_OT_MASK 0x00000004U
427 #define XSYSMONPSU_IMR_1_PS_LPD_OT_SHIFT 1U
428 #define XSYSMONPSU_IMR_1_PS_LPD_OT_WIDTH 1U
429 #define XSYSMONPSU_IMR_1_PS_LPD_OT_MASK 0x00000002U
431 #define XSYSMONPSU_IMR_1_PS_FPD_OT_SHIFT 0U
432 #define XSYSMONPSU_IMR_1_PS_FPD_OT_WIDTH 1U
433 #define XSYSMONPSU_IMR_1_PS_FPD_OT_MASK 0x00000001U
436 * Register: XSysmonPsuIer0
438 #define XSYSMONPSU_IER_0_OFFSET 0x00000020U
439 #define XSYSMONPSU_IXR_0_MASK 0xFFFFFFFFU
440 #define XSYSMONPSU_IER_0_RSTVAL 0x00000000U
442 #define XSYSMONPSU_IER_0_PL_ALM_15_SHIFT 31U
443 #define XSYSMONPSU_IER_0_PL_ALM_15_WIDTH 1U
444 #define XSYSMONPSU_IER_0_PL_ALM_15_MASK 0x80000000U
446 #define XSYSMONPSU_IER_0_PL_ALM_14_SHIFT 30U
447 #define XSYSMONPSU_IER_0_PL_ALM_14_WIDTH 1U
448 #define XSYSMONPSU_IER_0_PL_ALM_14_MASK 0x40000000U
450 #define XSYSMONPSU_IER_0_PL_ALM_13_SHIFT 29U
451 #define XSYSMONPSU_IER_0_PL_ALM_13_WIDTH 1U
452 #define XSYSMONPSU_IER_0_PL_ALM_13_MASK 0x20000000U
454 #define XSYSMONPSU_IER_0_PL_ALM_12_SHIFT 28U
455 #define XSYSMONPSU_IER_0_PL_ALM_12_WIDTH 1U
456 #define XSYSMONPSU_IER_0_PL_ALM_12_MASK 0x10000000U
458 #define XSYSMONPSU_IER_0_PL_ALM_11_SHIFT 27U
459 #define XSYSMONPSU_IER_0_PL_ALM_11_WIDTH 1U
460 #define XSYSMONPSU_IER_0_PL_ALM_11_MASK 0x08000000U
462 #define XSYSMONPSU_IER_0_PL_ALM_10_SHIFT 26U
463 #define XSYSMONPSU_IER_0_PL_ALM_10_WIDTH 1U
464 #define XSYSMONPSU_IER_0_PL_ALM_10_MASK 0x04000000U
466 #define XSYSMONPSU_IER_0_PL_ALM_9_SHIFT 25U
467 #define XSYSMONPSU_IER_0_PL_ALM_9_WIDTH 1U
468 #define XSYSMONPSU_IER_0_PL_ALM_9_MASK 0x02000000U
470 #define XSYSMONPSU_IER_0_PL_ALM_8_SHIFT 24U
471 #define XSYSMONPSU_IER_0_PL_ALM_8_WIDTH 1U
472 #define XSYSMONPSU_IER_0_PL_ALM_8_MASK 0x01000000U
474 #define XSYSMONPSU_IER_0_PL_ALM_7_SHIFT 23U
475 #define XSYSMONPSU_IER_0_PL_ALM_7_WIDTH 1U
476 #define XSYSMONPSU_IER_0_PL_ALM_7_MASK 0x00800000U
478 #define XSYSMONPSU_IER_0_PL_ALM_6_SHIFT 22U
479 #define XSYSMONPSU_IER_0_PL_ALM_6_WIDTH 1U
480 #define XSYSMONPSU_IER_0_PL_ALM_6_MASK 0x00400000U
482 #define XSYSMONPSU_IER_0_PL_ALM_5_SHIFT 21U
483 #define XSYSMONPSU_IER_0_PL_ALM_5_WIDTH 1U
484 #define XSYSMONPSU_IER_0_PL_ALM_5_MASK 0x00200000U
486 #define XSYSMONPSU_IER_0_PL_ALM_4_SHIFT 20U
487 #define XSYSMONPSU_IER_0_PL_ALM_4_WIDTH 1U
488 #define XSYSMONPSU_IER_0_PL_ALM_4_MASK 0x00100000U
490 #define XSYSMONPSU_IER_0_PL_ALM_3_SHIFT 19U
491 #define XSYSMONPSU_IER_0_PL_ALM_3_WIDTH 1U
492 #define XSYSMONPSU_IER_0_PL_ALM_3_MASK 0x00080000U
494 #define XSYSMONPSU_IER_0_PL_ALM_2_SHIFT 18U
495 #define XSYSMONPSU_IER_0_PL_ALM_2_WIDTH 1U
496 #define XSYSMONPSU_IER_0_PL_ALM_2_MASK 0x00040000U
498 #define XSYSMONPSU_IER_0_PL_ALM_1_SHIFT 17U
499 #define XSYSMONPSU_IER_0_PL_ALM_1_WIDTH 1U
500 #define XSYSMONPSU_IER_0_PL_ALM_1_MASK 0x00020000U
502 #define XSYSMONPSU_IER_0_PL_ALM_0_SHIFT 16U
503 #define XSYSMONPSU_IER_0_PL_ALM_0_WIDTH 1U
504 #define XSYSMONPSU_IER_0_PL_ALM_0_MASK 0x00010000U
506 #define XSYSMONPSU_IER_0_PS_ALM_15_SHIFT 15U
507 #define XSYSMONPSU_IER_0_PS_ALM_15_WIDTH 1U
508 #define XSYSMONPSU_IER_0_PS_ALM_15_MASK 0x00008000U
510 #define XSYSMONPSU_IER_0_PS_ALM_14_SHIFT 14U
511 #define XSYSMONPSU_IER_0_PS_ALM_14_WIDTH 1U
512 #define XSYSMONPSU_IER_0_PS_ALM_14_MASK 0x00004000U
514 #define XSYSMONPSU_IER_0_PS_ALM_13_SHIFT 13U
515 #define XSYSMONPSU_IER_0_PS_ALM_13_WIDTH 1U
516 #define XSYSMONPSU_IER_0_PS_ALM_13_MASK 0x00002000U
518 #define XSYSMONPSU_IER_0_PS_ALM_12_SHIFT 12U
519 #define XSYSMONPSU_IER_0_PS_ALM_12_WIDTH 1U
520 #define XSYSMONPSU_IER_0_PS_ALM_12_MASK 0x00001000U
522 #define XSYSMONPSU_IER_0_PS_ALM_11_SHIFT 11U
523 #define XSYSMONPSU_IER_0_PS_ALM_11_WIDTH 1U
524 #define XSYSMONPSU_IER_0_PS_ALM_11_MASK 0x00000800U
526 #define XSYSMONPSU_IER_0_PS_ALM_10_SHIFT 10U
527 #define XSYSMONPSU_IER_0_PS_ALM_10_WIDTH 1U
528 #define XSYSMONPSU_IER_0_PS_ALM_10_MASK 0x00000400U
530 #define XSYSMONPSU_IER_0_PS_ALM_9_SHIFT 9U
531 #define XSYSMONPSU_IER_0_PS_ALM_9_WIDTH 1U
532 #define XSYSMONPSU_IER_0_PS_ALM_9_MASK 0x00000200U
534 #define XSYSMONPSU_IER_0_PS_ALM_8_SHIFT 8U
535 #define XSYSMONPSU_IER_0_PS_ALM_8_WIDTH 1U
536 #define XSYSMONPSU_IER_0_PS_ALM_8_MASK 0x00000100U
538 #define XSYSMONPSU_IER_0_PS_ALM_7_SHIFT 7U
539 #define XSYSMONPSU_IER_0_PS_ALM_7_WIDTH 1U
540 #define XSYSMONPSU_IER_0_PS_ALM_7_MASK 0x00000080U
542 #define XSYSMONPSU_IER_0_PS_ALM_6_SHIFT 6U
543 #define XSYSMONPSU_IER_0_PS_ALM_6_WIDTH 1U
544 #define XSYSMONPSU_IER_0_PS_ALM_6_MASK 0x00000040U
546 #define XSYSMONPSU_IER_0_PS_ALM_5_SHIFT 5U
547 #define XSYSMONPSU_IER_0_PS_ALM_5_WIDTH 1U
548 #define XSYSMONPSU_IER_0_PS_ALM_5_MASK 0x00000020U
550 #define XSYSMONPSU_IER_0_PS_ALM_4_SHIFT 4U
551 #define XSYSMONPSU_IER_0_PS_ALM_4_WIDTH 1U
552 #define XSYSMONPSU_IER_0_PS_ALM_4_MASK 0x00000010U
554 #define XSYSMONPSU_IER_0_PS_ALM_3_SHIFT 3U
555 #define XSYSMONPSU_IER_0_PS_ALM_3_WIDTH 1U
556 #define XSYSMONPSU_IER_0_PS_ALM_3_MASK 0x00000008U
558 #define XSYSMONPSU_IER_0_PS_ALM_2_SHIFT 2U
559 #define XSYSMONPSU_IER_0_PS_ALM_2_WIDTH 1U
560 #define XSYSMONPSU_IER_0_PS_ALM_2_MASK 0x00000004U
562 #define XSYSMONPSU_IER_0_PS_ALM_1_SHIFT 1U
563 #define XSYSMONPSU_IER_0_PS_ALM_1_WIDTH 1U
564 #define XSYSMONPSU_IER_0_PS_ALM_1_MASK 0x00000002U
566 #define XSYSMONPSU_IER_0_PS_ALM_0_SHIFT 0U
567 #define XSYSMONPSU_IER_0_PS_ALM_0_WIDTH 1U
568 #define XSYSMONPSU_IER_0_PS_ALM_0_MASK 0x00000001U
571 * Register: XSysmonPsuIer1
573 #define XSYSMONPSU_IER_1_OFFSET 0x00000024U
574 #define XSYSMONPSU_IXR_1_MASK 0xE000001FU
575 #define XSYSMONPSU_IER_1_RSTVAL 0x00000000U
577 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_SHIFT 31U
578 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_WIDTH 1U
579 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_MASK 0x80000000U
581 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
582 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
583 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
585 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
586 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
587 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
589 #define XSYSMONPSU_IER_1_EOS_SHIFT 4U
590 #define XSYSMONPSU_IER_1_EOS_WIDTH 1U
591 #define XSYSMONPSU_IER_1_EOS_MASK 0x00000010U
593 #define XSYSMONPSU_IER_1_EOC_SHIFT 3U
594 #define XSYSMONPSU_IER_1_EOC_WIDTH 1U
595 #define XSYSMONPSU_IER_1_EOC_MASK 0x00000008U
597 #define XSYSMONPSU_IER_1_PL_OT_SHIFT 2U
598 #define XSYSMONPSU_IER_1_PL_OT_WIDTH 1U
599 #define XSYSMONPSU_IER_1_PL_OT_MASK 0x00000004U
601 #define XSYSMONPSU_IER_1_PS_LPD_OT_SHIFT 1U
602 #define XSYSMONPSU_IER_1_PS_LPD_OT_WIDTH 1U
603 #define XSYSMONPSU_IER_1_PS_LPD_OT_MASK 0x00000002U
605 #define XSYSMONPSU_IER_1_PS_FPD_OT_SHIFT 0U
606 #define XSYSMONPSU_IER_1_PS_FPD_OT_WIDTH 1U
607 #define XSYSMONPSU_IER_1_PS_FPD_OT_MASK 0x00000001U
609 #define XSYSMONPSU_IXR_1_SHIFT 32U
612 * Register: XSysmonPsuIdr0
614 #define XSYSMONPSU_IDR_0_OFFSET 0x00000028U
615 #define XSYSMONPSU_IDR_0_RSTVAL 0x00000000U
617 #define XSYSMONPSU_IDR_0_PL_ALM_15_SHIFT 31U
618 #define XSYSMONPSU_IDR_0_PL_ALM_15_WIDTH 1U
619 #define XSYSMONPSU_IDR_0_PL_ALM_15_MASK 0x80000000U
621 #define XSYSMONPSU_IDR_0_PL_ALM_14_SHIFT 30U
622 #define XSYSMONPSU_IDR_0_PL_ALM_14_WIDTH 1U
623 #define XSYSMONPSU_IDR_0_PL_ALM_14_MASK 0x40000000U
625 #define XSYSMONPSU_IDR_0_PL_ALM_13_SHIFT 29U
626 #define XSYSMONPSU_IDR_0_PL_ALM_13_WIDTH 1U
627 #define XSYSMONPSU_IDR_0_PL_ALM_13_MASK 0x20000000U
629 #define XSYSMONPSU_IDR_0_PL_ALM_12_SHIFT 28U
630 #define XSYSMONPSU_IDR_0_PL_ALM_12_WIDTH 1U
631 #define XSYSMONPSU_IDR_0_PL_ALM_12_MASK 0x10000000U
633 #define XSYSMONPSU_IDR_0_PL_ALM_11_SHIFT 27U
634 #define XSYSMONPSU_IDR_0_PL_ALM_11_WIDTH 1U
635 #define XSYSMONPSU_IDR_0_PL_ALM_11_MASK 0x08000000U
637 #define XSYSMONPSU_IDR_0_PL_ALM_10_SHIFT 26U
638 #define XSYSMONPSU_IDR_0_PL_ALM_10_WIDTH 1U
639 #define XSYSMONPSU_IDR_0_PL_ALM_10_MASK 0x04000000U
641 #define XSYSMONPSU_IDR_0_PL_ALM_9_SHIFT 25U
642 #define XSYSMONPSU_IDR_0_PL_ALM_9_WIDTH 1U
643 #define XSYSMONPSU_IDR_0_PL_ALM_9_MASK 0x02000000U
645 #define XSYSMONPSU_IDR_0_PL_ALM_8_SHIFT 24U
646 #define XSYSMONPSU_IDR_0_PL_ALM_8_WIDTH 1U
647 #define XSYSMONPSU_IDR_0_PL_ALM_8_MASK 0x01000000U
649 #define XSYSMONPSU_IDR_0_PL_ALM_7_SHIFT 23U
650 #define XSYSMONPSU_IDR_0_PL_ALM_7_WIDTH 1U
651 #define XSYSMONPSU_IDR_0_PL_ALM_7_MASK 0x00800000U
653 #define XSYSMONPSU_IDR_0_PL_ALM_6_SHIFT 22U
654 #define XSYSMONPSU_IDR_0_PL_ALM_6_WIDTH 1U
655 #define XSYSMONPSU_IDR_0_PL_ALM_6_MASK 0x00400000U
657 #define XSYSMONPSU_IDR_0_PL_ALM_5_SHIFT 21U
658 #define XSYSMONPSU_IDR_0_PL_ALM_5_WIDTH 1U
659 #define XSYSMONPSU_IDR_0_PL_ALM_5_MASK 0x00200000U
661 #define XSYSMONPSU_IDR_0_PL_ALM_4_SHIFT 20U
662 #define XSYSMONPSU_IDR_0_PL_ALM_4_WIDTH 1U
663 #define XSYSMONPSU_IDR_0_PL_ALM_4_MASK 0x00100000U
665 #define XSYSMONPSU_IDR_0_PL_ALM_3_SHIFT 19U
666 #define XSYSMONPSU_IDR_0_PL_ALM_3_WIDTH 1U
667 #define XSYSMONPSU_IDR_0_PL_ALM_3_MASK 0x00080000U
669 #define XSYSMONPSU_IDR_0_PL_ALM_2_SHIFT 18U
670 #define XSYSMONPSU_IDR_0_PL_ALM_2_WIDTH 1U
671 #define XSYSMONPSU_IDR_0_PL_ALM_2_MASK 0x00040000U
673 #define XSYSMONPSU_IDR_0_PL_ALM_1_SHIFT 17U
674 #define XSYSMONPSU_IDR_0_PL_ALM_1_WIDTH 1U
675 #define XSYSMONPSU_IDR_0_PL_ALM_1_MASK 0x00020000U
677 #define XSYSMONPSU_IDR_0_PL_ALM_0_SHIFT 16U
678 #define XSYSMONPSU_IDR_0_PL_ALM_0_WIDTH 1U
679 #define XSYSMONPSU_IDR_0_PL_ALM_0_MASK 0x00010000U
681 #define XSYSMONPSU_IDR_0_PS_ALM_15_SHIFT 15U
682 #define XSYSMONPSU_IDR_0_PS_ALM_15_WIDTH 1U
683 #define XSYSMONPSU_IDR_0_PS_ALM_15_MASK 0x00008000U
685 #define XSYSMONPSU_IDR_0_PS_ALM_14_SHIFT 14U
686 #define XSYSMONPSU_IDR_0_PS_ALM_14_WIDTH 1U
687 #define XSYSMONPSU_IDR_0_PS_ALM_14_MASK 0x00004000U
689 #define XSYSMONPSU_IDR_0_PS_ALM_13_SHIFT 13U
690 #define XSYSMONPSU_IDR_0_PS_ALM_13_WIDTH 1U
691 #define XSYSMONPSU_IDR_0_PS_ALM_13_MASK 0x00002000U
693 #define XSYSMONPSU_IDR_0_PS_ALM_12_SHIFT 12U
694 #define XSYSMONPSU_IDR_0_PS_ALM_12_WIDTH 1U
695 #define XSYSMONPSU_IDR_0_PS_ALM_12_MASK 0x00001000U
697 #define XSYSMONPSU_IDR_0_PS_ALM_11_SHIFT 11U
698 #define XSYSMONPSU_IDR_0_PS_ALM_11_WIDTH 1U
699 #define XSYSMONPSU_IDR_0_PS_ALM_11_MASK 0x00000800U
701 #define XSYSMONPSU_IDR_0_PS_ALM_10_SHIFT 10U
702 #define XSYSMONPSU_IDR_0_PS_ALM_10_WIDTH 1U
703 #define XSYSMONPSU_IDR_0_PS_ALM_10_MASK 0x00000400U
705 #define XSYSMONPSU_IDR_0_PS_ALM_9_SHIFT 9U
706 #define XSYSMONPSU_IDR_0_PS_ALM_9_WIDTH 1U
707 #define XSYSMONPSU_IDR_0_PS_ALM_9_MASK 0x00000200U
709 #define XSYSMONPSU_IDR_0_PS_ALM_8_SHIFT 8U
710 #define XSYSMONPSU_IDR_0_PS_ALM_8_WIDTH 1U
711 #define XSYSMONPSU_IDR_0_PS_ALM_8_MASK 0x00000100U
713 #define XSYSMONPSU_IDR_0_PS_ALM_7_SHIFT 7U
714 #define XSYSMONPSU_IDR_0_PS_ALM_7_WIDTH 1U
715 #define XSYSMONPSU_IDR_0_PS_ALM_7_MASK 0x00000080U
717 #define XSYSMONPSU_IDR_0_PS_ALM_6_SHIFT 6U
718 #define XSYSMONPSU_IDR_0_PS_ALM_6_WIDTH 1U
719 #define XSYSMONPSU_IDR_0_PS_ALM_6_MASK 0x00000040U
721 #define XSYSMONPSU_IDR_0_PS_ALM_5_SHIFT 5U
722 #define XSYSMONPSU_IDR_0_PS_ALM_5_WIDTH 1U
723 #define XSYSMONPSU_IDR_0_PS_ALM_5_MASK 0x00000020U
725 #define XSYSMONPSU_IDR_0_PS_ALM_4_SHIFT 4U
726 #define XSYSMONPSU_IDR_0_PS_ALM_4_WIDTH 1U
727 #define XSYSMONPSU_IDR_0_PS_ALM_4_MASK 0x00000010U
729 #define XSYSMONPSU_IDR_0_PS_ALM_3_SHIFT 3U
730 #define XSYSMONPSU_IDR_0_PS_ALM_3_WIDTH 1U
731 #define XSYSMONPSU_IDR_0_PS_ALM_3_MASK 0x00000008U
733 #define XSYSMONPSU_IDR_0_PS_ALM_2_SHIFT 2U
734 #define XSYSMONPSU_IDR_0_PS_ALM_2_WIDTH 1U
735 #define XSYSMONPSU_IDR_0_PS_ALM_2_MASK 0x00000004U
737 #define XSYSMONPSU_IDR_0_PS_ALM_1_SHIFT 1U
738 #define XSYSMONPSU_IDR_0_PS_ALM_1_WIDTH 1U
739 #define XSYSMONPSU_IDR_0_PS_ALM_1_MASK 0x00000002U
741 #define XSYSMONPSU_IDR_0_PS_ALM_0_SHIFT 0U
742 #define XSYSMONPSU_IDR_0_PS_ALM_0_WIDTH 1U
743 #define XSYSMONPSU_IDR_0_PS_ALM_0_MASK 0x00000001U
746 * Register: XSysmonPsuIdr1
748 #define XSYSMONPSU_IDR_1_OFFSET 0x0000002CU
749 #define XSYSMONPSU_IDR_1_RSTVAL 0x00000000U
751 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_SHIFT 31U
752 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_WIDTH 1U
753 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_MASK 0x80000000U
755 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
756 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
757 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
759 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
760 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
761 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
763 #define XSYSMONPSU_IDR_1_EOS_SHIFT 4U
764 #define XSYSMONPSU_IDR_1_EOS_WIDTH 1U
765 #define XSYSMONPSU_IDR_1_EOS_MASK 0x00000010U
767 #define XSYSMONPSU_IDR_1_EOC_SHIFT 3U
768 #define XSYSMONPSU_IDR_1_EOC_WIDTH 1U
769 #define XSYSMONPSU_IDR_1_EOC_MASK 0x00000008U
771 #define XSYSMONPSU_IDR_1_PL_OT_SHIFT 2U
772 #define XSYSMONPSU_IDR_1_PL_OT_WIDTH 1U
773 #define XSYSMONPSU_IDR_1_PL_OT_MASK 0x00000004U
775 #define XSYSMONPSU_IDR_1_PS_LPD_OT_SHIFT 1U
776 #define XSYSMONPSU_IDR_1_PS_LPD_OT_WIDTH 1U
777 #define XSYSMONPSU_IDR_1_PS_LPD_OT_MASK 0x00000002U
779 #define XSYSMONPSU_IDR_1_PS_FPD_OT_SHIFT 0U
780 #define XSYSMONPSU_IDR_1_PS_FPD_OT_WIDTH 1U
781 #define XSYSMONPSU_IDR_1_PS_FPD_OT_MASK 0x00000001U
784 * Register: XSysmonPsuPsSysmonSts
786 #define XSYSMONPSU_PS_SYSMON_CSTS_OFFSET 0x00000040U
787 #define XSYSMONPSU_PS_SYSMON_CSTS_RSTVAL 0x00000000U
789 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_SHIFT 24U
790 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_WIDTH 4U
791 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_MASK 0x0f000000U
793 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_SHIFT 16U
794 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_WIDTH 1U
795 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_MASK 0x00010000U
797 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_SHIFT 3U
798 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_WIDTH 1U
799 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK 0x00000008U
801 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_SHIFT 2U
802 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_WIDTH 1U
803 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK 0x00000004U
805 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_SHIFT 1U
806 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_WIDTH 1U
807 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_MASK 0x00000002U
809 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_SHIFT 0U
810 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_WIDTH 1U
811 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_MASK 0x00000001U
813 #define XSYSMONPSU_PS_SYSMON_READY 0x08010000U
816 * Register: XSysmonPsuPlSysmonSts
818 #define XSYSMONPSU_PL_SYSMON_CSTS_OFFSET 0x00000044U
819 #define XSYSMONPSU_PL_SYSMON_CSTS_RSTVAL 0x00000000U
821 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_SHIFT 0U
822 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_WIDTH 1U
823 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK 0x00000001U
826 * Register: XSysmonPsuMonSts
828 #define XSYSMONPSU_MON_STS_OFFSET 0x00000050U
829 #define XSYSMONPSU_MON_STS_RSTVAL 0x00000000U
831 #define XSYSMONPSU_MON_STS_JTAG_LCKD_SHIFT 23U
832 #define XSYSMONPSU_MON_STS_JTAG_LCKD_WIDTH 1U
833 #define XSYSMONPSU_MON_STS_JTAG_LCKD_MASK 0x00800000U
835 #define XSYSMONPSU_MON_STS_BSY_SHIFT 22U
836 #define XSYSMONPSU_MON_STS_BSY_WIDTH 1U
837 #define XSYSMONPSU_MON_STS_BSY_MASK 0x00400000U
839 #define XSYSMONPSU_MON_STS_CH_SHIFT 16U
840 #define XSYSMONPSU_MON_STS_CH_WIDTH 6U
841 #define XSYSMONPSU_MON_STS_CH_MASK 0x003f0000U
843 #define XSYSMONPSU_MON_STS_DATA_SHIFT 0U
844 #define XSYSMONPSU_MON_STS_DATA_WIDTH 16U
845 #define XSYSMONPSU_MON_STS_DATA_MASK 0x0000ffffU
848 * Register: XSysmonPsuVccPspll0
850 #define XSYSMONPSU_VCC_PSPLL0_OFFSET 0x00000060U
851 #define XSYSMONPSU_VCC_PSPLL0_RSTVAL 0x00000000U
853 #define XSYSMONPSU_VCC_PSPLL0_VAL_SHIFT 0U
854 #define XSYSMONPSU_VCC_PSPLL0_VAL_WIDTH 16U
855 #define XSYSMONPSU_VCC_PSPLL0_VAL_MASK 0x0000ffffU
858 * Register: XSysmonPsuVccPspll1
860 #define XSYSMONPSU_VCC_PSPLL1_OFFSET 0x00000064U
861 #define XSYSMONPSU_VCC_PSPLL1_RSTVAL 0x00000000U
863 #define XSYSMONPSU_VCC_PSPLL1_VAL_SHIFT 0U
864 #define XSYSMONPSU_VCC_PSPLL1_VAL_WIDTH 16U
865 #define XSYSMONPSU_VCC_PSPLL1_VAL_MASK 0x0000ffffU
868 * Register: XSysmonPsuVccPspll2
870 #define XSYSMONPSU_VCC_PSPLL2_OFFSET 0x00000068U
871 #define XSYSMONPSU_VCC_PSPLL2_RSTVAL 0x00000000U
873 #define XSYSMONPSU_VCC_PSPLL2_VAL_SHIFT 0U
874 #define XSYSMONPSU_VCC_PSPLL2_VAL_WIDTH 16U
875 #define XSYSMONPSU_VCC_PSPLL2_VAL_MASK 0x0000ffffU
878 * Register: XSysmonPsuVccPspll3
880 #define XSYSMONPSU_VCC_PSPLL3_OFFSET 0x0000006CU
881 #define XSYSMONPSU_VCC_PSPLL3_RSTVAL 0x00000000U
883 #define XSYSMONPSU_VCC_PSPLL3_VAL_SHIFT 0U
884 #define XSYSMONPSU_VCC_PSPLL3_VAL_WIDTH 16U
885 #define XSYSMONPSU_VCC_PSPLL3_VAL_MASK 0x0000ffffU
888 * Register: XSysmonPsuVccPspll4
890 #define XSYSMONPSU_VCC_PSPLL4_OFFSET 0x00000070U
891 #define XSYSMONPSU_VCC_PSPLL4_RSTVAL 0x00000000U
893 #define XSYSMONPSU_VCC_PSPLL4_VAL_SHIFT 0U
894 #define XSYSMONPSU_VCC_PSPLL4_VAL_WIDTH 16U
895 #define XSYSMONPSU_VCC_PSPLL4_VAL_MASK 0x0000ffffU
898 * Register: XSysmonPsuVccPsbatt
900 #define XSYSMONPSU_VCC_PSBATT_OFFSET 0x00000074U
901 #define XSYSMONPSU_VCC_PSBATT_RSTVAL 0x00000000U
903 #define XSYSMONPSU_VCC_PSBATT_VAL_SHIFT 0U
904 #define XSYSMONPSU_VCC_PSBATT_VAL_WIDTH 16U
905 #define XSYSMONPSU_VCC_PSBATT_VAL_MASK 0x0000ffffU
908 * Register: XSysmonPsuVccint
910 #define XSYSMONPSU_VCCINT_OFFSET 0x00000078U
911 #define XSYSMONPSU_VCCINT_RSTVAL 0x00000000U
913 #define XSYSMONPSU_VCCINT_VAL_SHIFT 0U
914 #define XSYSMONPSU_VCCINT_VAL_WIDTH 16U
915 #define XSYSMONPSU_VCCINT_VAL_MASK 0x0000ffffU
918 * Register: XSysmonPsuVccbram
920 #define XSYSMONPSU_VCCBRAM_OFFSET 0x0000007CU
921 #define XSYSMONPSU_VCCBRAM_RSTVAL 0x00000000U
923 #define XSYSMONPSU_VCCBRAM_VAL_SHIFT 0U
924 #define XSYSMONPSU_VCCBRAM_VAL_WIDTH 16U
925 #define XSYSMONPSU_VCCBRAM_VAL_MASK 0x0000ffffU
928 * Register: XSysmonPsuVccaux
930 #define XSYSMONPSU_VCCAUX_OFFSET 0x00000080U
931 #define XSYSMONPSU_VCCAUX_RSTVAL 0x00000000U
933 #define XSYSMONPSU_VCCAUX_VAL_SHIFT 0U
934 #define XSYSMONPSU_VCCAUX_VAL_WIDTH 16U
935 #define XSYSMONPSU_VCCAUX_VAL_MASK 0x0000ffffU
938 * Register: XSysmonPsuVccPsddrpll
940 #define XSYSMONPSU_VCC_PSDDRPLL_OFFSET 0x00000084U
941 #define XSYSMONPSU_VCC_PSDDRPLL_RSTVAL 0x00000000U
943 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_SHIFT 0U
944 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_WIDTH 16U
945 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_MASK 0x0000ffffU
948 * Register: XSysmonPsuDdrphyVref
950 #define XSYSMONPSU_DDRPHY_VREF_OFFSET 0x00000088U
951 #define XSYSMONPSU_DDRPHY_VREF_RSTVAL 0x00000000U
953 #define XSYSMONPSU_DDRPHY_VREF_VAL_SHIFT 0U
954 #define XSYSMONPSU_DDRPHY_VREF_VAL_WIDTH 16U
955 #define XSYSMONPSU_DDRPHY_VREF_VAL_MASK 0x0000ffffU
958 * Register: XSysmonPsuDdrphyAto
960 #define XSYSMONPSU_DDRPHY_ATO_OFFSET 0x0000008CU
961 #define XSYSMONPSU_DDRPHY_ATO_RSTVAL 0x00000000U
963 #define XSYSMONPSU_DDRPHY_ATO_VAL_SHIFT 0U
964 #define XSYSMONPSU_DDRPHY_ATO_VAL_WIDTH 16U
965 #define XSYSMONPSU_DDRPHY_ATO_VAL_MASK 0x0000ffffU
968 * Register: XSysmonPsuPsgtAt0
970 #define XSYSMONPSU_PSGT_AT0_OFFSET 0x00000090U
971 #define XSYSMONPSU_PSGT_AT0_RSTVAL 0x00000000U
973 #define XSYSMONPSU_PSGT_AT0_VAL_SHIFT 0U
974 #define XSYSMONPSU_PSGT_AT0_VAL_WIDTH 16U
975 #define XSYSMONPSU_PSGT_AT0_VAL_MASK 0x0000ffffU
978 * Register: XSysmonPsuPsgtAt1
980 #define XSYSMONPSU_PSGT_AT1_OFFSET 0x00000094U
981 #define XSYSMONPSU_PSGT_AT1_RSTVAL 0x00000000U
983 #define XSYSMONPSU_PSGT_AT1_VAL_SHIFT 0U
984 #define XSYSMONPSU_PSGT_AT1_VAL_WIDTH 16U
985 #define XSYSMONPSU_PSGT_AT1_VAL_MASK 0x0000ffffU
988 * Register: XSysmonPsuReserve0
990 #define XSYSMONPSU_RESERVE0_OFFSET 0x00000098U
991 #define XSYSMONPSU_RESERVE0_RSTVAL 0x00000000U
993 #define XSYSMONPSU_RESERVE0_VAL_SHIFT 0U
994 #define XSYSMONPSU_RESERVE0_VAL_WIDTH 16U
995 #define XSYSMONPSU_RESERVE0_VAL_MASK 0x0000ffffU
998 * Register: XSysmonPsuReserve1
1000 #define XSYSMONPSU_RESERVE1_OFFSET 0x0000009CU
1001 #define XSYSMONPSU_RESERVE1_RSTVAL 0x00000000U
1003 #define XSYSMONPSU_RESERVE1_VAL_SHIFT 0U
1004 #define XSYSMONPSU_RESERVE1_VAL_WIDTH 16U
1005 #define XSYSMONPSU_RESERVE1_VAL_MASK 0x0000ffffU
1008 * Register: XSysmonPsuTemp
1010 #define XSYSMONPSU_TEMP_OFFSET 0x00000000U
1011 #define XSYSMONPSU_TEMP_RSTVAL 0x00000000U
1013 #define XSYSMONPSU_TEMP_SHIFT 0U
1014 #define XSYSMONPSU_TEMP_WIDTH 16U
1015 #define XSYSMONPSU_TEMP_MASK 0x0000ffffU
1018 * Register: XSysmonPsuSup1
1020 #define XSYSMONPSU_SUP1_OFFSET 0x00000004U
1021 #define XSYSMONPSU_SUP1_RSTVAL 0x00000000U
1023 #define XSYSMONPSU_SUP1_SUP_VAL_SHIFT 0U
1024 #define XSYSMONPSU_SUP1_SUP_VAL_WIDTH 16U
1025 #define XSYSMONPSU_SUP1_SUP_VAL_MASK 0x0000ffffU
1028 * Register: XSysmonPsuSup2
1030 #define XSYSMONPSU_SUP2_OFFSET 0x00000008U
1031 #define XSYSMONPSU_SUP2_RSTVAL 0x00000000U
1033 #define XSYSMONPSU_SUP2_SUP_VAL_SHIFT 0U
1034 #define XSYSMONPSU_SUP2_SUP_VAL_WIDTH 16U
1035 #define XSYSMONPSU_SUP2_SUP_VAL_MASK 0x0000ffffU
1038 * Register: XSysmonPsuVpVn
1040 #define XSYSMONPSU_VP_VN_OFFSET 0x0000000CU
1041 #define XSYSMONPSU_VP_VN_RSTVAL 0x00000000U
1043 #define XSYSMONPSU_VP_VN_SHIFT 0U
1044 #define XSYSMONPSU_VP_VN_WIDTH 16U
1045 #define XSYSMONPSU_VP_VN_MASK 0x0000ffffU
1048 * Register: XSysmonPsuVrefp
1050 #define XSYSMONPSU_VREFP_OFFSET 0x00000010U
1051 #define XSYSMONPSU_VREFP_RSTVAL 0x00000000U
1053 #define XSYSMONPSU_VREFP_SUP_VAL_SHIFT 0U
1054 #define XSYSMONPSU_VREFP_SUP_VAL_WIDTH 16U
1055 #define XSYSMONPSU_VREFP_SUP_VAL_MASK 0x0000ffffU
1058 * Register: XSysmonPsuVrefn
1060 #define XSYSMONPSU_VREFN_OFFSET 0x00000014U
1061 #define XSYSMONPSU_VREFN_RSTVAL 0x00000000U
1063 #define XSYSMONPSU_VREFN_SUP_VAL_SHIFT 0U
1064 #define XSYSMONPSU_VREFN_SUP_VAL_WIDTH 16U
1065 #define XSYSMONPSU_VREFN_SUP_VAL_MASK 0x0000ffffU
1068 * Register: XSysmonPsuSup3
1070 #define XSYSMONPSU_SUP3_OFFSET 0x00000018U
1071 #define XSYSMONPSU_SUP3_RSTVAL 0x00000000U
1073 #define XSYSMONPSU_SUP3_SUP_VAL_SHIFT 0U
1074 #define XSYSMONPSU_SUP3_SUP_VAL_WIDTH 16U
1075 #define XSYSMONPSU_SUP3_SUP_VAL_MASK 0x0000ffffU
1078 * Register: XSysmonPsuCalSupOff
1080 #define XSYSMONPSU_CAL_SUP_OFF_OFFSET 0x00000020U
1081 #define XSYSMONPSU_CAL_SUP_OFF_RSTVAL 0x00000000U
1083 #define XSYSMONPSU_CAL_SUP_OFF_VAL_SHIFT 0U
1084 #define XSYSMONPSU_CAL_SUP_OFF_VAL_WIDTH 16U
1085 #define XSYSMONPSU_CAL_SUP_OFF_VAL_MASK 0x0000ffffU
1088 * Register: XSysmonPsuCalAdcBiplrOff
1090 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_OFFSET 0x00000024U
1091 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_RSTVAL 0x00000000U
1093 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_SHIFT 0U
1094 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_WIDTH 16U
1095 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_MASK 0x0000ffffU
1098 * Register: XSysmonPsuCalGainErr
1100 #define XSYSMONPSU_CAL_GAIN_ERR_OFFSET 0x00000028U
1101 #define XSYSMONPSU_CAL_GAIN_ERR_RSTVAL 0x00000000U
1103 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_SHIFT 0U
1104 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_WIDTH 16U
1105 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_MASK 0x0000ffffU
1108 * Register: XSysmonPsuSup4
1110 #define XSYSMONPSU_SUP4_OFFSET 0x00000034U
1111 #define XSYSMONPSU_SUP4_RSTVAL 0x00000000U
1113 #define XSYSMONPSU_SUP4_SUP_VAL_SHIFT 0U
1114 #define XSYSMONPSU_SUP4_SUP_VAL_WIDTH 16U
1115 #define XSYSMONPSU_SUP4_SUP_VAL_MASK 0x0000ffffU
1118 * Register: XSysmonPsuSup5
1120 #define XSYSMONPSU_SUP5_OFFSET 0x00000038U
1121 #define XSYSMONPSU_SUP5_RSTVAL 0x00000000U
1123 #define XSYSMONPSU_SUP5_SUP_VAL_SHIFT 0U
1124 #define XSYSMONPSU_SUP5_SUP_VAL_WIDTH 16U
1125 #define XSYSMONPSU_SUP5_SUP_VAL_MASK 0x0000ffffU
1128 * Register: XSysmonPsuSup6
1130 #define XSYSMONPSU_SUP6_OFFSET 0x0000003CU
1131 #define XSYSMONPSU_SUP6_RSTVAL 0x00000000U
1133 #define XSYSMONPSU_SUP6_SUP_VAL_SHIFT 0U
1134 #define XSYSMONPSU_SUP6_SUP_VAL_WIDTH 16U
1135 #define XSYSMONPSU_SUP6_SUP_VAL_MASK 0x0000ffffU
1138 * Register: XSysmonPsuVaux00
1140 #define XSYSMONPSU_VAUX00_OFFSET 0x00000040U
1141 #define XSYSMONPSU_VAUX00_RSTVAL 0x00000000U
1143 #define XSYSMONPSU_VAUX00_VAUX_VAL_SHIFT 0U
1144 #define XSYSMONPSU_VAUX00_VAUX_VAL_WIDTH 16U
1145 #define XSYSMONPSU_VAUX00_VAUX_VAL_MASK 0x0000ffffU
1148 * Register: XSysmonPsuVaux01
1150 #define XSYSMONPSU_VAUX01_OFFSET 0x00000044U
1151 #define XSYSMONPSU_VAUX01_RSTVAL 0x00000000U
1153 #define XSYSMONPSU_VAUX01_VAUX_VAL_SHIFT 0U
1154 #define XSYSMONPSU_VAUX01_VAUX_VAL_WIDTH 16U
1155 #define XSYSMONPSU_VAUX01_VAUX_VAL_MASK 0x0000ffffU
1158 * Register: XSysmonPsuVaux02
1160 #define XSYSMONPSU_VAUX02_OFFSET 0x00000048U
1161 #define XSYSMONPSU_VAUX02_RSTVAL 0x00000000U
1163 #define XSYSMONPSU_VAUX02_VAUX_VAL_SHIFT 0U
1164 #define XSYSMONPSU_VAUX02_VAUX_VAL_WIDTH 16U
1165 #define XSYSMONPSU_VAUX02_VAUX_VAL_MASK 0x0000ffffU
1168 * Register: XSysmonPsuVaux03
1170 #define XSYSMONPSU_VAUX03_OFFSET 0x0000004CU
1171 #define XSYSMONPSU_VAUX03_RSTVAL 0x00000000U
1173 #define XSYSMONPSU_VAUX03_VAUX_VAL_SHIFT 0U
1174 #define XSYSMONPSU_VAUX03_VAUX_VAL_WIDTH 16U
1175 #define XSYSMONPSU_VAUX03_VAUX_VAL_MASK 0x0000ffffU
1178 * Register: XSysmonPsuVaux04
1180 #define XSYSMONPSU_VAUX04_OFFSET 0x00000050U
1181 #define XSYSMONPSU_VAUX04_RSTVAL 0x00000000U
1183 #define XSYSMONPSU_VAUX04_VAUX_VAL_SHIFT 0U
1184 #define XSYSMONPSU_VAUX04_VAUX_VAL_WIDTH 16U
1185 #define XSYSMONPSU_VAUX04_VAUX_VAL_MASK 0x0000ffffU
1188 * Register: XSysmonPsuVaux05
1190 #define XSYSMONPSU_VAUX05_OFFSET 0x00000054U
1191 #define XSYSMONPSU_VAUX05_RSTVAL 0x00000000U
1193 #define XSYSMONPSU_VAUX05_VAUX_VAL_SHIFT 0U
1194 #define XSYSMONPSU_VAUX05_VAUX_VAL_WIDTH 16U
1195 #define XSYSMONPSU_VAUX05_VAUX_VAL_MASK 0x0000ffffU
1198 * Register: XSysmonPsuVaux06
1200 #define XSYSMONPSU_VAUX06_OFFSET 0x00000058U
1201 #define XSYSMONPSU_VAUX06_RSTVAL 0x00000000U
1203 #define XSYSMONPSU_VAUX06_VAUX_VAL_SHIFT 0U
1204 #define XSYSMONPSU_VAUX06_VAUX_VAL_WIDTH 16U
1205 #define XSYSMONPSU_VAUX06_VAUX_VAL_MASK 0x0000ffffU
1208 * Register: XSysmonPsuVaux07
1210 #define XSYSMONPSU_VAUX07_OFFSET 0x0000005CU
1211 #define XSYSMONPSU_VAUX07_RSTVAL 0x00000000U
1213 #define XSYSMONPSU_VAUX07_VAUX_VAL_SHIFT 0U
1214 #define XSYSMONPSU_VAUX07_VAUX_VAL_WIDTH 16U
1215 #define XSYSMONPSU_VAUX07_VAUX_VAL_MASK 0x0000ffffU
1218 * Register: XSysmonPsuVaux08
1220 #define XSYSMONPSU_VAUX08_OFFSET 0x00000060U
1221 #define XSYSMONPSU_VAUX08_RSTVAL 0x00000000U
1223 #define XSYSMONPSU_VAUX08_VAUX_VAL_SHIFT 0U
1224 #define XSYSMONPSU_VAUX08_VAUX_VAL_WIDTH 16U
1225 #define XSYSMONPSU_VAUX08_VAUX_VAL_MASK 0x0000ffffU
1228 * Register: XSysmonPsuVaux09
1230 #define XSYSMONPSU_VAUX09_OFFSET 0x00000064U
1231 #define XSYSMONPSU_VAUX09_RSTVAL 0x00000000U
1233 #define XSYSMONPSU_VAUX09_VAUX_VAL_SHIFT 0U
1234 #define XSYSMONPSU_VAUX09_VAUX_VAL_WIDTH 16U
1235 #define XSYSMONPSU_VAUX09_VAUX_VAL_MASK 0x0000ffffU
1238 * Register: XSysmonPsuVaux0a
1240 #define XSYSMONPSU_VAUX0A_OFFSET 0x00000068U
1241 #define XSYSMONPSU_VAUX0A_RSTVAL 0x00000000U
1243 #define XSYSMONPSU_VAUX0A_VAUX_VAL_SHIFT 0U
1244 #define XSYSMONPSU_VAUX0A_VAUX_VAL_WIDTH 16U
1245 #define XSYSMONPSU_VAUX0A_VAUX_VAL_MASK 0x0000ffffU
1248 * Register: XSysmonPsuVaux0b
1250 #define XSYSMONPSU_VAUX0B_OFFSET 0x0000006CU
1251 #define XSYSMONPSU_VAUX0B_RSTVAL 0x00000000U
1253 #define XSYSMONPSU_VAUX0B_VAUX_VAL_SHIFT 0U
1254 #define XSYSMONPSU_VAUX0B_VAUX_VAL_WIDTH 16U
1255 #define XSYSMONPSU_VAUX0B_VAUX_VAL_MASK 0x0000ffffU
1258 * Register: XSysmonPsuVaux0c
1260 #define XSYSMONPSU_VAUX0C_OFFSET 0x00000070U
1261 #define XSYSMONPSU_VAUX0C_RSTVAL 0x00000000U
1263 #define XSYSMONPSU_VAUX0C_VAUX_VAL_SHIFT 0U
1264 #define XSYSMONPSU_VAUX0C_VAUX_VAL_WIDTH 16U
1265 #define XSYSMONPSU_VAUX0C_VAUX_VAL_MASK 0x0000ffffU
1268 * Register: XSysmonPsuVaux0d
1270 #define XSYSMONPSU_VAUX0D_OFFSET 0x00000074U
1271 #define XSYSMONPSU_VAUX0D_RSTVAL 0x00000000U
1273 #define XSYSMONPSU_VAUX0D_VAUX_VAL_SHIFT 0U
1274 #define XSYSMONPSU_VAUX0D_VAUX_VAL_WIDTH 16U
1275 #define XSYSMONPSU_VAUX0D_VAUX_VAL_MASK 0x0000ffffU
1278 * Register: XSysmonPsuVaux0e
1280 #define XSYSMONPSU_VAUX0E_OFFSET 0x00000078U
1281 #define XSYSMONPSU_VAUX0E_RSTVAL 0x00000000U
1283 #define XSYSMONPSU_VAUX0E_VAUX_VAL_SHIFT 0U
1284 #define XSYSMONPSU_VAUX0E_VAUX_VAL_WIDTH 16U
1285 #define XSYSMONPSU_VAUX0E_VAUX_VAL_MASK 0x0000ffffU
1288 * Register: XSysmonPsuVaux0f
1290 #define XSYSMONPSU_VAUX0F_OFFSET 0x0000007CU
1291 #define XSYSMONPSU_VAUX0F_RSTVAL 0x00000000U
1293 #define XSYSMONPSU_VAUX0F_VAUX_VAL_SHIFT 0U
1294 #define XSYSMONPSU_VAUX0F_VAUX_VAL_WIDTH 16U
1295 #define XSYSMONPSU_VAUX0F_VAUX_VAL_MASK 0x0000ffffU
1298 * Register: XSysmonPsuMaxTemp
1300 #define XSYSMONPSU_MAX_TEMP_OFFSET 0x00000080U
1301 #define XSYSMONPSU_MAX_TEMP_RSTVAL 0x00000000U
1303 #define XSYSMONPSU_MAX_TEMP_SHIFT 0U
1304 #define XSYSMONPSU_MAX_TEMP_WIDTH 16U
1305 #define XSYSMONPSU_MAX_TEMP_MASK 0x0000ffffU
1308 * Register: XSysmonPsuMaxSup1
1310 #define XSYSMONPSU_MAX_SUP1_OFFSET 0x00000084U
1311 #define XSYSMONPSU_MAX_SUP1_RSTVAL 0x00000000U
1313 #define XSYSMONPSU_MAX_SUP1_VAL_SHIFT 0U
1314 #define XSYSMONPSU_MAX_SUP1_VAL_WIDTH 16U
1315 #define XSYSMONPSU_MAX_SUP1_VAL_MASK 0x0000ffffU
1318 * Register: XSysmonPsuMaxSup2
1320 #define XSYSMONPSU_MAX_SUP2_OFFSET 0x00000088U
1321 #define XSYSMONPSU_MAX_SUP2_RSTVAL 0x00000000U
1323 #define XSYSMONPSU_MAX_SUP2_VAL_SHIFT 0U
1324 #define XSYSMONPSU_MAX_SUP2_VAL_WIDTH 16U
1325 #define XSYSMONPSU_MAX_SUP2_VAL_MASK 0x0000ffffU
1328 * Register: XSysmonPsuMaxSup3
1330 #define XSYSMONPSU_MAX_SUP3_OFFSET 0x0000008CU
1331 #define XSYSMONPSU_MAX_SUP3_RSTVAL 0x00000000U
1333 #define XSYSMONPSU_MAX_SUP3_VAL_SHIFT 0U
1334 #define XSYSMONPSU_MAX_SUP3_VAL_WIDTH 16U
1335 #define XSYSMONPSU_MAX_SUP3_VAL_MASK 0x0000ffffU
1338 * Register: XSysmonPsuMinTemp
1340 #define XSYSMONPSU_MIN_TEMP_OFFSET 0x00000090U
1341 #define XSYSMONPSU_MIN_TEMP_RSTVAL 0x0000ffffU
1343 #define XSYSMONPSU_MIN_TEMP_SHIFT 0U
1344 #define XSYSMONPSU_MIN_TEMP_WIDTH 16U
1345 #define XSYSMONPSU_MIN_TEMP_MASK 0x0000ffffU
1348 * Register: XSysmonPsuMinSup1
1350 #define XSYSMONPSU_MIN_SUP1_OFFSET 0x00000094U
1351 #define XSYSMONPSU_MIN_SUP1_RSTVAL 0x0000ffffU
1353 #define XSYSMONPSU_MIN_SUP1_VAL_SHIFT 0U
1354 #define XSYSMONPSU_MIN_SUP1_VAL_WIDTH 16U
1355 #define XSYSMONPSU_MIN_SUP1_VAL_MASK 0x0000ffffU
1358 * Register: XSysmonPsuMinSup2
1360 #define XSYSMONPSU_MIN_SUP2_OFFSET 0x00000098U
1361 #define XSYSMONPSU_MIN_SUP2_RSTVAL 0x0000ffffU
1363 #define XSYSMONPSU_MIN_SUP2_VAL_SHIFT 0U
1364 #define XSYSMONPSU_MIN_SUP2_VAL_WIDTH 16U
1365 #define XSYSMONPSU_MIN_SUP2_VAL_MASK 0x0000ffffU
1368 * Register: XSysmonPsuMinSup3
1370 #define XSYSMONPSU_MIN_SUP3_OFFSET 0x0000009CU
1371 #define XSYSMONPSU_MIN_SUP3_RSTVAL 0x0000ffffU
1373 #define XSYSMONPSU_MIN_SUP3_VAL_SHIFT 0U
1374 #define XSYSMONPSU_MIN_SUP3_VAL_WIDTH 16U
1375 #define XSYSMONPSU_MIN_SUP3_VAL_MASK 0x0000ffffU
1378 * Register: XSysmonPsuMaxSup4
1380 #define XSYSMONPSU_MAX_SUP4_OFFSET 0x000000A0U
1381 #define XSYSMONPSU_MAX_SUP4_RSTVAL 0x00000000U
1383 #define XSYSMONPSU_MAX_SUP4_VAL_SHIFT 0U
1384 #define XSYSMONPSU_MAX_SUP4_VAL_WIDTH 16U
1385 #define XSYSMONPSU_MAX_SUP4_VAL_MASK 0x0000ffffU
1388 * Register: XSysmonPsuMaxSup5
1390 #define XSYSMONPSU_MAX_SUP5_OFFSET 0x000000A4U
1391 #define XSYSMONPSU_MAX_SUP5_RSTVAL 0x00000000U
1393 #define XSYSMONPSU_MAX_SUP5_VAL_SHIFT 0U
1394 #define XSYSMONPSU_MAX_SUP5_VAL_WIDTH 16U
1395 #define XSYSMONPSU_MAX_SUP5_VAL_MASK 0x0000ffffU
1398 * Register: XSysmonPsuMaxSup6
1400 #define XSYSMONPSU_MAX_SUP6_OFFSET 0x000000A8U
1401 #define XSYSMONPSU_MAX_SUP6_RSTVAL 0x00000000U
1403 #define XSYSMONPSU_MAX_SUP6_VAL_SHIFT 0U
1404 #define XSYSMONPSU_MAX_SUP6_VAL_WIDTH 16U
1405 #define XSYSMONPSU_MAX_SUP6_VAL_MASK 0x0000ffffU
1408 * Register: XSysmonPsuMinSup4
1410 #define XSYSMONPSU_MIN_SUP4_OFFSET 0x000000B0U
1411 #define XSYSMONPSU_MIN_SUP4_RSTVAL 0x0000ffffU
1413 #define XSYSMONPSU_MIN_SUP4_VAL_SHIFT 0U
1414 #define XSYSMONPSU_MIN_SUP4_VAL_WIDTH 16U
1415 #define XSYSMONPSU_MIN_SUP4_VAL_MASK 0x0000ffffU
1418 * Register: XSysmonPsuMinSup5
1420 #define XSYSMONPSU_MIN_SUP5_OFFSET 0x000000B4U
1421 #define XSYSMONPSU_MIN_SUP5_RSTVAL 0x0000ffffU
1423 #define XSYSMONPSU_MIN_SUP5_VAL_SHIFT 0U
1424 #define XSYSMONPSU_MIN_SUP5_VAL_WIDTH 16U
1425 #define XSYSMONPSU_MIN_SUP5_VAL_MASK 0x0000ffffU
1428 * Register: XSysmonPsuMinSup6
1430 #define XSYSMONPSU_MIN_SUP6_OFFSET 0x000000B8U
1431 #define XSYSMONPSU_MIN_SUP6_RSTVAL 0x0000ffffU
1433 #define XSYSMONPSU_MIN_SUP6_VAL_SHIFT 0U
1434 #define XSYSMONPSU_MIN_SUP6_VAL_WIDTH 16U
1435 #define XSYSMONPSU_MIN_SUP6_VAL_MASK 0x0000ffffU
1438 * Register: XSysmonPsuStsFlag
1440 #define XSYSMONPSU_STS_FLAG_OFFSET 0x000000FCU
1441 #define XSYSMONPSU_STS_FLAG_RSTVAL 0x00000000U
1443 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_SHIFT 15U
1444 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_WIDTH 1U
1445 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_MASK 0x00008000U
1447 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_SHIFT 14U
1448 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_WIDTH 1U
1449 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_MASK 0x00004000U
1451 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_SHIFT 11U
1452 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_WIDTH 1U
1453 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_MASK 0x00000800U
1455 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_SHIFT 10U
1456 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_WIDTH 1U
1457 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_MASK 0x00000400U
1459 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_SHIFT 9U
1460 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_WIDTH 1U
1461 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_MASK 0x00000200U
1463 #define XSYSMONPSU_STS_FLAG_DISD_SHIFT 8U
1464 #define XSYSMONPSU_STS_FLAG_DISD_WIDTH 1U
1465 #define XSYSMONPSU_STS_FLAG_DISD_MASK 0x00000100U
1467 #define XSYSMONPSU_STS_FLAG_ALM_6_3_SHIFT 4U
1468 #define XSYSMONPSU_STS_FLAG_ALM_6_3_WIDTH 4U
1469 #define XSYSMONPSU_STS_FLAG_ALM_6_3_MASK 0x000000f0U
1471 #define XSYSMONPSU_STS_FLAG_OT_SHIFT 3U
1472 #define XSYSMONPSU_STS_FLAG_OT_WIDTH 1U
1473 #define XSYSMONPSU_STS_FLAG_OT_MASK 0x00000008U
1475 #define XSYSMONPSU_STS_FLAG_ALM_2_0_SHIFT 0U
1476 #define XSYSMONPSU_STS_FLAG_ALM_2_0_WIDTH 3U
1477 #define XSYSMONPSU_STS_FLAG_ALM_2_0_MASK 0x00000007U
1480 * Register: XSysmonPsuCfgReg0
1482 #define XSYSMONPSU_CFG_REG0_OFFSET 0x00000100U
1483 #define XSYSMONPSU_CFG_REG0_RSTVAL 0x00000000U
1485 #define XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT 12U
1486 #define XSYSMONPSU_CFG_REG0_AVRGNG_WIDTH 2U
1487 #define XSYSMONPSU_CFG_REG0_AVRGNG_MASK 0x00003000U
1489 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_SHIFT 11U
1490 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_WIDTH 1U
1491 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK 0x00000800U
1493 #define XSYSMONPSU_CFG_REG0_BU_SHIFT 10U
1494 #define XSYSMONPSU_CFG_REG0_BU_WIDTH 1U
1495 #define XSYSMONPSU_CFG_REG0_BU_MASK 0x00000400U
1497 #define XSYSMONPSU_CFG_REG0_EC_SHIFT 9U
1498 #define XSYSMONPSU_CFG_REG0_EC_WIDTH 1U
1499 #define XSYSMONPSU_CFG_REG0_EC_MASK 0x00000200U
1501 #define XSYSMONPSU_EVENT_MODE 1
1502 #define XSYSMONPSU_CONTINUOUS_MODE 2
1504 #define XSYSMONPSU_CFG_REG0_ACQ_SHIFT 8U
1505 #define XSYSMONPSU_CFG_REG0_ACQ_WIDTH 1U
1506 #define XSYSMONPSU_CFG_REG0_ACQ_MASK 0x00000100U
1508 #define XSYSMONPSU_CFG_REG0_MUX_CH_SHIFT 0U
1509 #define XSYSMONPSU_CFG_REG0_MUX_CH_WIDTH 6U
1510 #define XSYSMONPSU_CFG_REG0_MUX_CH_MASK 0x0000003fU
1513 * Register: XSysmonPsuCfgReg1
1515 #define XSYSMONPSU_CFG_REG1_OFFSET 0x00000104U
1516 #define XSYSMONPSU_CFG_REG1_RSTVAL 0x00000000U
1518 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT 12U
1519 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_WIDTH 4U
1520 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK 0x0000f000U
1522 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_SHIFT 8U
1523 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_WIDTH 4U
1524 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_MASK 0x00000f00U
1526 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_SHIFT 1U
1527 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_WIDTH 3U
1528 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_MASK 0x0000000eU
1530 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_SHIFT 0U
1531 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_WIDTH 1U
1532 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_MASK 0x00000001U
1534 #define XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK 0x00000f0fU
1535 #define XSYSMONPSU_CFR_REG1_ALRM_SUP6_MASK 0x0800U
1536 #define XSYSMONPSU_CFR_REG1_ALRM_SUP5_MASK 0x0400U
1537 #define XSYSMONPSU_CFR_REG1_ALRM_SUP4_MASK 0x0200U
1538 #define XSYSMONPSU_CFR_REG1_ALRM_SUP3_MASK 0x0100U
1539 #define XSYSMONPSU_CFR_REG1_ALRM_SUP2_MASK 0x0008U
1540 #define XSYSMONPSU_CFR_REG1_ALRM_SUP1_MASK 0x0004U
1541 #define XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK 0x0002U
1542 #define XSYSMONPSU_CFR_REG1_ALRM_OT_MASK 0x0001U
1545 * Register: XSysmonPsuCfgReg2
1547 #define XSYSMONPSU_CFG_REG2_OFFSET 0x00000108U
1548 #define XSYSMONPSU_CFG_REG2_RSTVAL 0x00000000U
1550 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT 8U
1551 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_WIDTH 8U
1552 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK 0x0000ff00U
1554 #define XSYSMONPSU_CLK_DVDR_MIN_VAL 0U
1555 #define XSYSMONPSU_CLK_DVDR_MAX_VAL 255U
1557 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT 4U
1558 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_WIDTH 4U
1559 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK 0x000000f0U
1561 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_SHIFT 2U
1562 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_WIDTH 1U
1563 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_MASK 0x00000004U
1565 #define XSYSMONPSU_CFG_REG2_TST_MDE_SHIFT 0U
1566 #define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH 2U
1567 #define XSYSMONPSU_CFG_REG2_TST_MDE_MASK 0x00000003U
1569 /* Register: XSysmonPsuCfgReg3 */
1570 #define XSYSMONPSU_CFG_REG3_OFFSET 0x0000010CU
1571 #define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK 0x0000003FU
1573 #define XSM_CFG_ALARM_SHIFT 16U
1575 /* Register: XSysmonPsuSeqCh2 */
1576 #define XSYSMONPSU_SEQ_CH2_OFFSET 0x00000118U
1578 #define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT 5U
1579 #define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK 0x00000020U
1581 #define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT 4U
1582 #define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK 0x00000010U
1584 #define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT 3U
1585 #define XSYSMONPSU_SEQ_CH2_SUP10_MASK 0x00000008U
1587 #define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT 2U
1588 #define XSYSMONPSU_SEQ_CH2_SUP9_MASK 0x00000004U
1590 #define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT 1U
1591 #define XSYSMONPSU_SEQ_CH2_SUP8_MASK 0x00000002U
1593 #define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT 0U
1594 #define XSYSMONPSU_SEQ_CH2_SUP7_MASK 0x00000001U
1596 #define XSYSMONPSU_SEQ_CH2_VALID_MASK 0x0000003FU
1598 /* Register: XSysmonPsuSeqAverage0 */
1599 #define XSYSMONPSU_SEQ_AVERAGE2_OFFSET 0x0000011CU
1600 #define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
1601 #define XSYSMONPSU_SEQ_AVERAGE2_MASK 0x0000003FU
1604 * Register: XSysmonPsuSeqCh0
1606 #define XSYSMONPSU_SEQ_CH0_OFFSET 0x00000120U
1607 #define XSYSMONPSU_SEQ_CH0_RSTVAL 0x00000000U
1609 #define XSYSMONPSU_SEQ_CH0_CUR_MON_SHIFT 15U
1610 #define XSYSMONPSU_SEQ_CH0_CUR_MON_WIDTH 1U
1611 #define XSYSMONPSU_SEQ_CH0_CUR_MON_MASK 0x00008000U
1613 #define XSYSMONPSU_SEQ_CH0_SUP3_SHIFT 14U
1614 #define XSYSMONPSU_SEQ_CH0_SUP3_WIDTH 1U
1615 #define XSYSMONPSU_SEQ_CH0_SUP3_MASK 0x00004000U
1617 #define XSYSMONPSU_SEQ_CH0_VREFN_SHIFT 13U
1618 #define XSYSMONPSU_SEQ_CH0_VREFN_WIDTH 1U
1619 #define XSYSMONPSU_SEQ_CH0_VREFN_MASK 0x00002000U
1621 #define XSYSMONPSU_SEQ_CH0_VREFP_SHIFT 12U
1622 #define XSYSMONPSU_SEQ_CH0_VREFP_WIDTH 1U
1623 #define XSYSMONPSU_SEQ_CH0_VREFP_MASK 0x00001000U
1625 #define XSYSMONPSU_SEQ_CH0_VP_VN_SHIFT 11U
1626 #define XSYSMONPSU_SEQ_CH0_VP_VN_WIDTH 1U
1627 #define XSYSMONPSU_SEQ_CH0_VP_VN_MASK 0x00000800U
1629 #define XSYSMONPSU_SEQ_CH0_SUP2_SHIFT 10U
1630 #define XSYSMONPSU_SEQ_CH0_SUP2_WIDTH 1U
1631 #define XSYSMONPSU_SEQ_CH0_SUP2_MASK 0x00000400U
1633 #define XSYSMONPSU_SEQ_CH0_SUP1_SHIFT 9U
1634 #define XSYSMONPSU_SEQ_CH0_SUP1_WIDTH 1U
1635 #define XSYSMONPSU_SEQ_CH0_SUP1_MASK 0x00000200U
1637 #define XSYSMONPSU_SEQ_CH0_TEMP_SHIFT 8U
1638 #define XSYSMONPSU_SEQ_CH0_TEMP_WIDTH 1U
1639 #define XSYSMONPSU_SEQ_CH0_TEMP_MASK 0x00000100U
1641 #define XSYSMONPSU_SEQ_CH0_SUP6_SHIFT 7U
1642 #define XSYSMONPSU_SEQ_CH0_SUP6_WIDTH 1U
1643 #define XSYSMONPSU_SEQ_CH0_SUP6_MASK 0x00000080U
1645 #define XSYSMONPSU_SEQ_CH0_SUP5_SHIFT 6U
1646 #define XSYSMONPSU_SEQ_CH0_SUP5_WIDTH 1U
1647 #define XSYSMONPSU_SEQ_CH0_SUP5_MASK 0x00000040U
1649 #define XSYSMONPSU_SEQ_CH0_SUP4_SHIFT 5U
1650 #define XSYSMONPSU_SEQ_CH0_SUP4_WIDTH 1U
1651 #define XSYSMONPSU_SEQ_CH0_SUP4_MASK 0x00000020U
1653 #define XSYSMONPSU_SEQ_CH0_TST_CH_SHIFT 3U
1654 #define XSYSMONPSU_SEQ_CH0_TST_CH_WIDTH 1U
1655 #define XSYSMONPSU_SEQ_CH0_TST_CH_MASK 0x00000008U
1657 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_SHIFT 0U
1658 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_WIDTH 1U
1659 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_MASK 0x00000001U
1661 #define XSYSMONPSU_SEQ_CH0_VALID_MASK 0x0000FFE9U
1664 * Register: XSysmonPsuSeqCh1
1666 #define XSYSMONPSU_SEQ_CH1_OFFSET 0x00000124U
1667 #define XSYSMONPSU_SEQ_CH1_VALID_MASK 0x0000FFFFU
1668 #define XSYSMONPSU_SEQ_CH1_RSTVAL 0x00000000U
1670 #define XSYSMONPSU_SEQ_CH1_VAUX0F_SHIFT 15U
1671 #define XSYSMONPSU_SEQ_CH1_VAUX0F_WIDTH 1U
1672 #define XSYSMONPSU_SEQ_CH1_VAUX0F_MASK 0x00008000U
1674 #define XSYSMONPSU_SEQ_CH1_VAUX0E_SHIFT 14U
1675 #define XSYSMONPSU_SEQ_CH1_VAUX0E_WIDTH 1U
1676 #define XSYSMONPSU_SEQ_CH1_VAUX0E_MASK 0x00004000U
1678 #define XSYSMONPSU_SEQ_CH1_VAUX0D_SHIFT 13U
1679 #define XSYSMONPSU_SEQ_CH1_VAUX0D_WIDTH 1U
1680 #define XSYSMONPSU_SEQ_CH1_VAUX0D_MASK 0x00002000U
1682 #define XSYSMONPSU_SEQ_CH1_VAUX0C_SHIFT 12U
1683 #define XSYSMONPSU_SEQ_CH1_VAUX0C_WIDTH 1U
1684 #define XSYSMONPSU_SEQ_CH1_VAUX0C_MASK 0x00001000U
1686 #define XSYSMONPSU_SEQ_CH1_VAUX0B_SHIFT 11U
1687 #define XSYSMONPSU_SEQ_CH1_VAUX0B_WIDTH 1U
1688 #define XSYSMONPSU_SEQ_CH1_VAUX0B_MASK 0x00000800U
1690 #define XSYSMONPSU_SEQ_CH1_VAUX0A_SHIFT 10U
1691 #define XSYSMONPSU_SEQ_CH1_VAUX0A_WIDTH 1U
1692 #define XSYSMONPSU_SEQ_CH1_VAUX0A_MASK 0x00000400U
1694 #define XSYSMONPSU_SEQ_CH1_VAUX09_SHIFT 9U
1695 #define XSYSMONPSU_SEQ_CH1_VAUX09_WIDTH 1U
1696 #define XSYSMONPSU_SEQ_CH1_VAUX09_MASK 0x00000200U
1698 #define XSYSMONPSU_SEQ_CH1_VAUX08_SHIFT 8U
1699 #define XSYSMONPSU_SEQ_CH1_VAUX08_WIDTH 1U
1700 #define XSYSMONPSU_SEQ_CH1_VAUX08_MASK 0x00000100U
1702 #define XSYSMONPSU_SEQ_CH1_VAUX07_SHIFT 7U
1703 #define XSYSMONPSU_SEQ_CH1_VAUX07_WIDTH 1U
1704 #define XSYSMONPSU_SEQ_CH1_VAUX07_MASK 0x00000080U
1706 #define XSYSMONPSU_SEQ_CH1_VAUX06_SHIFT 6U
1707 #define XSYSMONPSU_SEQ_CH1_VAUX06_WIDTH 1U
1708 #define XSYSMONPSU_SEQ_CH1_VAUX06_MASK 0x00000040U
1710 #define XSYSMONPSU_SEQ_CH1_VAUX05_SHIFT 5U
1711 #define XSYSMONPSU_SEQ_CH1_VAUX05_WIDTH 1U
1712 #define XSYSMONPSU_SEQ_CH1_VAUX05_MASK 0x00000020U
1714 #define XSYSMONPSU_SEQ_CH1_VAUX04_SHIFT 4U
1715 #define XSYSMONPSU_SEQ_CH1_VAUX04_WIDTH 1U
1716 #define XSYSMONPSU_SEQ_CH1_VAUX04_MASK 0x00000010U
1718 #define XSYSMONPSU_SEQ_CH1_VAUX03_SHIFT 3U
1719 #define XSYSMONPSU_SEQ_CH1_VAUX03_WIDTH 1U
1720 #define XSYSMONPSU_SEQ_CH1_VAUX03_MASK 0x00000008U
1722 #define XSYSMONPSU_SEQ_CH1_VAUX02_SHIFT 2U
1723 #define XSYSMONPSU_SEQ_CH1_VAUX02_WIDTH 1U
1724 #define XSYSMONPSU_SEQ_CH1_VAUX02_MASK 0x00000004U
1726 #define XSYSMONPSU_SEQ_CH1_VAUX01_SHIFT 1U
1727 #define XSYSMONPSU_SEQ_CH1_VAUX01_WIDTH 1U
1728 #define XSYSMONPSU_SEQ_CH1_VAUX01_MASK 0x00000002U
1730 #define XSYSMONPSU_SEQ_CH1_VAUX00_SHIFT 0U
1731 #define XSYSMONPSU_SEQ_CH1_VAUX00_WIDTH 1U
1732 #define XSYSMONPSU_SEQ_CH1_VAUX00_MASK 0x00000001U
1734 #define XSM_SEQ_CH_SHIFT 16U
1735 #define XSM_SEQ_CH2_SHIFT 32U
1738 * Register: XSysmonPsuSeqAverage0
1740 #define XSYSMONPSU_SEQ_AVERAGE0_OFFSET 0x00000128U
1741 #define XSYSMONPSU_SEQ_AVERAGE0_RSTVAL 0x00000000U
1743 #define XSYSMONPSU_SEQ_AVERAGE0_SHIFT 0U
1744 #define XSYSMONPSU_SEQ_AVERAGE0_WIDTH 16U
1745 #define XSYSMONPSU_SEQ_AVERAGE0_MASK 0x0000ffffU
1748 * Register: XSysmonPsuSeqAverage1
1750 #define XSYSMONPSU_SEQ_AVERAGE1_OFFSET 0x0000012CU
1751 #define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
1753 #define XSYSMONPSU_SEQ_AVERAGE1_SHIFT 0U
1754 #define XSYSMONPSU_SEQ_AVERAGE1_WIDTH 16U
1755 #define XSYSMONPSU_SEQ_AVERAGE1_MASK 0x0000ffffU
1758 * Register: XSysmonPsuSeqInputMde0
1760 #define XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET 0x00000130U
1761 #define XSYSMONPSU_SEQ_INPUT_MDE0_RSTVAL 0x00000000U
1763 #define XSYSMONPSU_SEQ_INPUT_MDE0_SHIFT 0U
1764 #define XSYSMONPSU_SEQ_INPUT_MDE0_WIDTH 16U
1765 #define XSYSMONPSU_SEQ_INPUT_MDE0_MASK 0x0000ffffU
1768 * Register: XSysmonPsuSeqInputMde1
1770 #define XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET 0x00000134U
1771 #define XSYSMONPSU_SEQ_INPUT_MDE1_RSTVAL 0x00000000U
1773 #define XSYSMONPSU_SEQ_INPUT_MDE1_SHIFT 0U
1774 #define XSYSMONPSU_SEQ_INPUT_MDE1_WIDTH 16U
1775 #define XSYSMONPSU_SEQ_INPUT_MDE1_MASK 0x0000ffffU
1778 * Register: XSysmonPsuSeqAcq0
1780 #define XSYSMONPSU_SEQ_ACQ0_OFFSET 0x00000138U
1781 #define XSYSMONPSU_SEQ_ACQ0_RSTVAL 0x00000000U
1783 #define XSYSMONPSU_SEQ_ACQ0_SHIFT 0U
1784 #define XSYSMONPSU_SEQ_ACQ0_WIDTH 16U
1785 #define XSYSMONPSU_SEQ_ACQ0_MASK 0x0000ffffU
1788 * Register: XSysmonPsuSeqAcq1
1790 #define XSYSMONPSU_SEQ_ACQ1_OFFSET 0x0000013CU
1791 #define XSYSMONPSU_SEQ_ACQ1_RSTVAL 0x00000000U
1793 #define XSYSMONPSU_SEQ_ACQ1_SHIFT 0U
1794 #define XSYSMONPSU_SEQ_ACQ1_WIDTH 16U
1795 #define XSYSMONPSU_SEQ_ACQ1_MASK 0x0000ffffU
1798 * Register: XSysmonPsuAlrmTempUpr
1800 #define XSYSMONPSU_ALRM_TEMP_UPR_OFFSET 0x00000140U
1801 #define XSYSMONPSU_ALRM_TEMP_UPR_RSTVAL 0x00000000U
1803 #define XSYSMONPSU_ALRM_TEMP_UPR_SHIFT 0U
1804 #define XSYSMONPSU_ALRM_TEMP_UPR_WIDTH 16U
1805 #define XSYSMONPSU_ALRM_TEMP_UPR_MASK 0x0000ffffU
1808 * Register: XSysmonPsuAlrmSup1Upr
1810 #define XSYSMONPSU_ALRM_SUP1_UPR_OFFSET 0x00000144U
1811 #define XSYSMONPSU_ALRM_SUP1_UPR_RSTVAL 0x00000000U
1813 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_SHIFT 0U
1814 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_WIDTH 16U
1815 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_MASK 0x0000ffffU
1818 * Register: XSysmonPsuAlrmSup2Upr
1820 #define XSYSMONPSU_ALRM_SUP2_UPR_OFFSET 0x00000148U
1821 #define XSYSMONPSU_ALRM_SUP2_UPR_RSTVAL 0x00000000U
1823 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_SHIFT 0U
1824 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_WIDTH 16U
1825 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_MASK 0x0000ffffU
1828 * Register: XSysmonPsuAlrmOtUpr
1830 #define XSYSMONPSU_ALRM_OT_UPR_OFFSET 0x0000014CU
1831 #define XSYSMONPSU_ALRM_OT_UPR_RSTVAL 0x00000000U
1833 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_SHIFT 0U
1834 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_WIDTH 16U
1835 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_MASK 0x0000ffffU
1838 * Register: XSysmonPsuAlrmTempLwr
1840 #define XSYSMONPSU_ALRM_TEMP_LWR_OFFSET 0x00000150U
1841 #define XSYSMONPSU_ALRM_TEMP_LWR_RSTVAL 0x00000000U
1843 #define XSYSMONPSU_ALRM_TEMP_LWR_SHIFT 1U
1844 #define XSYSMONPSU_ALRM_TEMP_LWR_WIDTH 15U
1845 #define XSYSMONPSU_ALRM_TEMP_LWR_MASK 0x0000fffeU
1847 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_SHIFT 0U
1848 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_WIDTH 1U
1849 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_MASK 0x00000001U
1852 * Register: XSysmonPsuAlrmSup1Lwr
1854 #define XSYSMONPSU_ALRM_SUP1_LWR_OFFSET 0x00000154U
1855 #define XSYSMONPSU_ALRM_SUP1_LWR_RSTVAL 0x00000000U
1857 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_SHIFT 0U
1858 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_WIDTH 16U
1859 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_MASK 0x0000ffffU
1862 * Register: XSysmonPsuAlrmSup2Lwr
1864 #define XSYSMONPSU_ALRM_SUP2_LWR_OFFSET 0x00000158U
1865 #define XSYSMONPSU_ALRM_SUP2_LWR_RSTVAL 0x00000000U
1867 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_SHIFT 0U
1868 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_WIDTH 16U
1869 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_MASK 0x0000ffffU
1872 * Register: XSysmonPsuAlrmOtLwr
1874 #define XSYSMONPSU_ALRM_OT_LWR_OFFSET 0x0000015CU
1875 #define XSYSMONPSU_ALRM_OT_LWR_RSTVAL 0x00000000U
1877 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_SHIFT 1U
1878 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_WIDTH 15U
1879 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_MASK 0x0000fffeU
1881 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_SHIFT 0U
1882 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_WIDTH 1U
1883 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_MASK 0x00000001U
1886 * Register: XSysmonPsuAlrmSup3Upr
1888 #define XSYSMONPSU_ALRM_SUP3_UPR_OFFSET 0x00000160U
1889 #define XSYSMONPSU_ALRM_SUP3_UPR_RSTVAL 0x00000000U
1891 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_SHIFT 0U
1892 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_WIDTH 16U
1893 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_MASK 0x0000ffffU
1896 * Register: XSysmonPsuAlrmSup4Upr
1898 #define XSYSMONPSU_ALRM_SUP4_UPR_OFFSET 0x00000164U
1899 #define XSYSMONPSU_ALRM_SUP4_UPR_RSTVAL 0x00000000U
1901 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_SHIFT 0U
1902 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_WIDTH 16U
1903 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_MASK 0x0000ffffU
1906 * Register: XSysmonPsuAlrmSup5Upr
1908 #define XSYSMONPSU_ALRM_SUP5_UPR_OFFSET 0x00000168U
1909 #define XSYSMONPSU_ALRM_SUP5_UPR_RSTVAL 0x00000000U
1911 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_SHIFT 0U
1912 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_WIDTH 16U
1913 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_MASK 0x0000ffffU
1916 * Register: XSysmonPsuAlrmSup6Upr
1918 #define XSYSMONPSU_ALRM_SUP6_UPR_OFFSET 0x0000016CU
1919 #define XSYSMONPSU_ALRM_SUP6_UPR_RSTVAL 0x00000000U
1921 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_SHIFT 0U
1922 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_WIDTH 16U
1923 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_MASK 0x0000ffffU
1926 * Register: XSysmonPsuAlrmSup3Lwr
1928 #define XSYSMONPSU_ALRM_SUP3_LWR_OFFSET 0x00000170U
1929 #define XSYSMONPSU_ALRM_SUP3_LWR_RSTVAL 0x00000000U
1931 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_SHIFT 0U
1932 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_WIDTH 16U
1933 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_MASK 0x0000ffffU
1936 * Register: XSysmonPsuAlrmSup4Lwr
1938 #define XSYSMONPSU_ALRM_SUP4_LWR_OFFSET 0x00000174U
1939 #define XSYSMONPSU_ALRM_SUP4_LWR_RSTVAL 0x00000000U
1941 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_SHIFT 0U
1942 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_WIDTH 16U
1943 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_MASK 0x0000ffffU
1946 * Register: XSysmonPsuAlrmSup5Lwr
1948 #define XSYSMONPSU_ALRM_SUP5_LWR_OFFSET 0x00000178U
1949 #define XSYSMONPSU_ALRM_SUP5_LWR_RSTVAL 0x00000000U
1951 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_SHIFT 0U
1952 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_WIDTH 16U
1953 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_MASK 0x0000ffffU
1956 * Register: XSysmonPsuAlrmSup6Lwr
1958 #define XSYSMONPSU_ALRM_SUP6_LWR_OFFSET 0x0000017CU
1959 #define XSYSMONPSU_ALRM_SUP6_LWR_RSTVAL 0x00000000U
1961 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_SHIFT 0U
1962 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_WIDTH 16U
1963 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_MASK 0x0000ffffU
1966 * Register: XSysmonPsuAlrmSup7Upr
1968 #define XSYSMONPSU_ALRM_SUP7_UPR_OFFSET 0x00000180U
1969 #define XSYSMONPSU_ALRM_SUP7_UPR_RSTVAL 0x00000000U
1971 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_SHIFT 0U
1972 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_WIDTH 16U
1973 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_MASK 0x0000ffffU
1976 * Register: XSysmonPsuAlrmSup8Upr
1978 #define XSYSMONPSU_ALRM_SUP8_UPR_OFFSET 0x00000184U
1979 #define XSYSMONPSU_ALRM_SUP8_UPR_RSTVAL 0x00000000U
1981 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_SHIFT 0U
1982 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_WIDTH 16U
1983 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_MASK 0x0000ffffU
1986 * Register: XSysmonPsuAlrmSup9Upr
1988 #define XSYSMONPSU_ALRM_SUP9_UPR_OFFSET 0x00000188U
1989 #define XSYSMONPSU_ALRM_SUP9_UPR_RSTVAL 0x00000000U
1991 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_SHIFT 0U
1992 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_WIDTH 16U
1993 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_MASK 0x0000ffffU
1996 * Register: XSysmonPsuAlrmSup10Upr
1998 #define XSYSMONPSU_ALRM_SUP10_UPR_OFFSET 0x0000018CU
1999 #define XSYSMONPSU_ALRM_SUP10_UPR_RSTVAL 0x00000000U
2001 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_SHIFT 0U
2002 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_WIDTH 16U
2003 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_MASK 0x0000ffffU
2006 * Register: XSysmonPsuAlrmVccamsUpr
2008 #define XSYSMONPSU_ALRM_VCCAMS_UPR_OFFSET 0x00000190U
2009 #define XSYSMONPSU_ALRM_VCCAMS_UPR_RSTVAL 0x00000000U
2011 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_SHIFT 0U
2012 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_WIDTH 16U
2013 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_MASK 0x0000ffffU
2016 * Register: XSysmonPsuAlrmTremoteUpr
2018 #define XSYSMONPSU_ALRM_TREMOTE_UPR_OFFSET 0x00000194U
2019 #define XSYSMONPSU_ALRM_TREMOTE_UPR_RSTVAL 0x00000000U
2021 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_SHIFT 0U
2022 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_WIDTH 16U
2023 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_MASK 0x0000ffffU
2026 * Register: XSysmonPsuAlrmSup7Lwr
2028 #define XSYSMONPSU_ALRM_SUP7_LWR_OFFSET 0x000001A0U
2029 #define XSYSMONPSU_ALRM_SUP7_LWR_RSTVAL 0x00000000U
2031 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_SHIFT 0U
2032 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_WIDTH 16U
2033 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_MASK 0x0000ffffU
2036 * Register: XSysmonPsuAlrmSup8Lwr
2038 #define XSYSMONPSU_ALRM_SUP8_LWR_OFFSET 0x000001A4U
2039 #define XSYSMONPSU_ALRM_SUP8_LWR_RSTVAL 0x00000000U
2041 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_SHIFT 0U
2042 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_WIDTH 16U
2043 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_MASK 0x0000ffffU
2046 * Register: XSysmonPsuAlrmSup9Lwr
2048 #define XSYSMONPSU_ALRM_SUP9_LWR_OFFSET 0x000001A8U
2049 #define XSYSMONPSU_ALRM_SUP9_LWR_RSTVAL 0x00000000U
2051 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_SHIFT 0U
2052 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_WIDTH 16U
2053 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_MASK 0x0000ffffU
2056 * Register: XSysmonPsuAlrmSup10Lwr
2058 #define XSYSMONPSU_ALRM_SUP10_LWR_OFFSET 0x000001ACU
2059 #define XSYSMONPSU_ALRM_SUP10_LWR_RSTVAL 0x00000000U
2061 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_SHIFT 0U
2062 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_WIDTH 16U
2063 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_MASK 0x0000ffffU
2066 * Register: XSysmonPsuAlrmVccamsLwr
2068 #define XSYSMONPSU_ALRM_VCCAMS_LWR_OFFSET 0x000001B0U
2069 #define XSYSMONPSU_ALRM_VCCAMS_LWR_RSTVAL 0x00000000U
2071 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_SHIFT 0U
2072 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_WIDTH 16U
2073 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_MASK 0x0000ffffU
2076 * Register: XSysmonPsuAlrmTremoteLwr
2078 #define XSYSMONPSU_ALRM_TREMOTE_LWR_OFFSET 0x000001B4U
2079 #define XSYSMONPSU_ALRM_TREMOTE_LWR_RSTVAL 0x00000000U
2081 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_SHIFT 1U
2082 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_WIDTH 15U
2083 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_MASK 0x0000fffeU
2085 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_SHIFT 0U
2086 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH 1U
2087 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK 0x00000001U
2089 /* Register: XSysmonPsuSeqInputMde2 */
2090 #define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET 0x000001E0U
2091 #define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL 0x00000000U
2093 #define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT 0U
2094 #define XSYSMONPSU_SEQ_INPUT_MDE2_MASK 0x0000003FU
2097 * Register: XSysmonPsuSeqAcq2
2099 #define XSYSMONPSU_SEQ_ACQ2_OFFSET 0x000001E4U
2100 #define XSYSMONPSU_SEQ_ACQ2_RSTVAL 0x00000000U
2102 #define XSYSMONPSU_SEQ_ACQ2_SHIFT 0U
2103 #define XSYSMONPSU_SEQ_ACQ2_MASK 0x0000003FU
2106 * Register: XSysmonPsuSup7
2108 #define XSYSMONPSU_SUP7_OFFSET 0x00000200U
2109 #define XSYSMONPSU_SUP7_RSTVAL 0x00000000U
2111 #define XSYSMONPSU_SUP7_SUP_VAL_SHIFT 0U
2112 #define XSYSMONPSU_SUP7_SUP_VAL_WIDTH 16U
2113 #define XSYSMONPSU_SUP7_SUP_VAL_MASK 0x0000ffffU
2116 * Register: XSysmonPsuSup8
2118 #define XSYSMONPSU_SUP8_OFFSET 0x00000204U
2119 #define XSYSMONPSU_SUP8_RSTVAL 0x00000000U
2121 #define XSYSMONPSU_SUP8_SUP_VAL_SHIFT 0U
2122 #define XSYSMONPSU_SUP8_SUP_VAL_WIDTH 16U
2123 #define XSYSMONPSU_SUP8_SUP_VAL_MASK 0x0000ffffU
2126 * Register: XSysmonPsuSup9
2128 #define XSYSMONPSU_SUP9_OFFSET 0x00000208U
2129 #define XSYSMONPSU_SUP9_RSTVAL 0x00000000U
2131 #define XSYSMONPSU_SUP9_SUP_VAL_SHIFT 0U
2132 #define XSYSMONPSU_SUP9_SUP_VAL_WIDTH 16U
2133 #define XSYSMONPSU_SUP9_SUP_VAL_MASK 0x0000ffffU
2136 * Register: XSysmonPsuSup10
2138 #define XSYSMONPSU_SUP10_OFFSET 0x0000020CU
2139 #define XSYSMONPSU_SUP10_RSTVAL 0x00000000U
2141 #define XSYSMONPSU_SUP10_SUP_VAL_SHIFT 0U
2142 #define XSYSMONPSU_SUP10_SUP_VAL_WIDTH 16U
2143 #define XSYSMONPSU_SUP10_SUP_VAL_MASK 0x0000ffffU
2146 * Register: XSysmonPsuVccams
2148 #define XSYSMONPSU_VCCAMS_OFFSET 0x00000210U
2149 #define XSYSMONPSU_VCCAMS_RSTVAL 0x00000000U
2151 #define XSYSMONPSU_VCCAMS_SUP_VAL_SHIFT 0U
2152 #define XSYSMONPSU_VCCAMS_SUP_VAL_WIDTH 16U
2153 #define XSYSMONPSU_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2156 * Register: XSysmonPsuTempRemte
2158 #define XSYSMONPSU_TEMP_REMTE_OFFSET 0x00000214U
2159 #define XSYSMONPSU_TEMP_REMTE_RSTVAL 0x00000000U
2161 #define XSYSMONPSU_TEMP_REMTE_SHIFT 0U
2162 #define XSYSMONPSU_TEMP_REMTE_WIDTH 16U
2163 #define XSYSMONPSU_TEMP_REMTE_MASK 0x0000ffffU
2166 * Register: XSysmonPsuMaxSup7
2168 #define XSYSMONPSU_MAX_SUP7_OFFSET 0x00000280U
2169 #define XSYSMONPSU_MAX_SUP7_RSTVAL 0x00000000U
2171 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_SHIFT 0U
2172 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_WIDTH 16U
2173 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_MASK 0x0000ffffU
2176 * Register: XSysmonPsuMaxSup8
2178 #define XSYSMONPSU_MAX_SUP8_OFFSET 0x00000284U
2179 #define XSYSMONPSU_MAX_SUP8_RSTVAL 0x00000000U
2181 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_SHIFT 0U
2182 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_WIDTH 16U
2183 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_MASK 0x0000ffffU
2186 * Register: XSysmonPsuMaxSup9
2188 #define XSYSMONPSU_MAX_SUP9_OFFSET 0x00000288U
2189 #define XSYSMONPSU_MAX_SUP9_RSTVAL 0x00000000U
2191 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_SHIFT 0U
2192 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_WIDTH 16U
2193 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_MASK 0x0000ffffU
2196 * Register: XSysmonPsuMaxSup10
2198 #define XSYSMONPSU_MAX_SUP10_OFFSET 0x0000028CU
2199 #define XSYSMONPSU_MAX_SUP10_RSTVAL 0x00000000U
2201 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_SHIFT 0U
2202 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_WIDTH 16U
2203 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_MASK 0x0000ffffU
2206 * Register: XSysmonPsuMaxVccams
2208 #define XSYSMONPSU_MAX_VCCAMS_OFFSET 0x00000290U
2209 #define XSYSMONPSU_MAX_VCCAMS_RSTVAL 0x00000000U
2211 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_SHIFT 0U
2212 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_WIDTH 16U
2213 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2216 * Register: XSysmonPsuMaxTempRemte
2218 #define XSYSMONPSU_MAX_TEMP_REMTE_OFFSET 0x00000294U
2219 #define XSYSMONPSU_MAX_TEMP_REMTE_RSTVAL 0x00000000U
2221 #define XSYSMONPSU_MAX_TEMP_REMTE_SHIFT 0U
2222 #define XSYSMONPSU_MAX_TEMP_REMTE_WIDTH 16U
2223 #define XSYSMONPSU_MAX_TEMP_REMTE_MASK 0x0000ffffU
2226 * Register: XSysmonPsuMinSup7
2228 #define XSYSMONPSU_MIN_SUP7_OFFSET 0x000002A0U
2229 #define XSYSMONPSU_MIN_SUP7_RSTVAL 0x0000ffffU
2231 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_SHIFT 0U
2232 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_WIDTH 16U
2233 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_MASK 0x0000ffffU
2236 * Register: XSysmonPsuMinSup8
2238 #define XSYSMONPSU_MIN_SUP8_OFFSET 0x000002A4U
2239 #define XSYSMONPSU_MIN_SUP8_RSTVAL 0x0000ffffU
2241 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_SHIFT 0U
2242 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_WIDTH 16U
2243 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_MASK 0x0000ffffU
2246 * Register: XSysmonPsuMinSup9
2248 #define XSYSMONPSU_MIN_SUP9_OFFSET 0x000002A8U
2249 #define XSYSMONPSU_MIN_SUP9_RSTVAL 0x0000ffffU
2251 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_SHIFT 0U
2252 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_WIDTH 16U
2253 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_MASK 0x0000ffffU
2256 * Register: XSysmonPsuMinSup10
2258 #define XSYSMONPSU_MIN_SUP10_OFFSET 0x000002ACU
2259 #define XSYSMONPSU_MIN_SUP10_RSTVAL 0x0000ffffU
2261 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_SHIFT 0U
2262 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_WIDTH 16U
2263 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_MASK 0x0000ffffU
2266 * Register: XSysmonPsuMinVccams
2268 #define XSYSMONPSU_MIN_VCCAMS_OFFSET 0x000002B0U
2269 #define XSYSMONPSU_MIN_VCCAMS_RSTVAL 0x0000ffffU
2271 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_SHIFT 0U
2272 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_WIDTH 16U
2273 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2276 * Register: XSysmonPsuMinTempRemte
2278 #define XSYSMONPSU_MIN_TEMP_REMTE_OFFSET 0x000002B4U
2279 #define XSYSMONPSU_MIN_TEMP_REMTE_RSTVAL 0x0000ffffU
2281 #define XSYSMONPSU_MIN_TEMP_REMTE_SHIFT 0U
2282 #define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH 16U
2283 #define XSYSMONPSU_MIN_TEMP_REMTE_MASK 0x0000ffffU
2285 #define CSU_BASEADDR 0xFFCA0000U
2286 #define PCAP_STATUS_OFFSET 0x00003010U
2287 #define PL_CFG_RESET_MASK 0x00000040U
2288 #define PL_CFG_RESET_SHIFT 6U
2290 /***************** Macros (Inline Functions) Definitions *********************/
2292 /****************************************************************************/
2295 * This macro reads the given register.
2297 * @param RegisterAddr is the register address in the address
2298 * space of the SYSMONPSU device.
2300 * @return The 32-bit value of the register
2304 *****************************************************************************/
2305 #define XSysmonPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
2307 /****************************************************************************/
2310 * This macro writes the given register.
2312 * @param RegisterAddr is the register address in the address
2313 * space of the SYSMONPSU device.
2314 * @param Data is the 32-bit value to write to the register.
2320 *****************************************************************************/
2321 #define XSysmonPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
2327 #endif /* XSYSMONPSU_HW_H__ */