1 /******************************************************************************
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31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup usbpsu_v1_0
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- ----- -------- -----------------------------------------------------
45 * 1.0 sg 06/06/16 First release
49 *****************************************************************************/
51 #ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
52 #define XUSBPSU_HW_H /* by using protection macros */
58 /***************************** Include Files ********************************/
60 /************************** Constant Definitions ****************************/
62 /**@name Register offsets
64 * The following constants provide access to each of the registers of the
70 #define XUSBPSU_PORTSC_30 0x430
71 #define XUSBPSU_PORTMSC_30 0x434
73 /* XUSBPSU registers memory space boundries */
74 #define XUSBPSU_GLOBALS_REGS_START 0xc100
75 #define XUSBPSU_GLOBALS_REGS_END 0xc6ff
76 #define XUSBPSU_DEVICE_REGS_START 0xc700
77 #define XUSBPSU_DEVICE_REGS_END 0xcbff
78 #define XUSBPSU_OTG_REGS_START 0xcc00
79 #define XUSBPSU_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define XUSBPSU_GSBUSCFG0 0xc100
83 #define XUSBPSU_GSBUSCFG1 0xc104
84 #define XUSBPSU_GTXTHRCFG 0xc108
85 #define XUSBPSU_GRXTHRCFG 0xc10c
86 #define XUSBPSU_GCTL 0xc110
87 #define XUSBPSU_GEVTEN 0xc114
88 #define XUSBPSU_GSTS 0xc118
89 #define XUSBPSU_GSNPSID 0xc120
90 #define XUSBPSU_GGPIO 0xc124
91 #define XUSBPSU_GUID 0xc128
92 #define XUSBPSU_GUCTL 0xc12c
93 #define XUSBPSU_GBUSERRADDR0 0xc130
94 #define XUSBPSU_GBUSERRADDR1 0xc134
95 #define XUSBPSU_GPRTBIMAP0 0xc138
96 #define XUSBPSU_GPRTBIMAP1 0xc13c
97 #define XUSBPSU_GHWPARAMS0_OFFSET 0xc140U
98 #define XUSBPSU_GHWPARAMS1_OFFSET 0xc144U
99 #define XUSBPSU_GHWPARAMS2_OFFSET 0xc148U
100 #define XUSBPSU_GHWPARAMS3_OFFSET 0xc14cU
101 #define XUSBPSU_GHWPARAMS4_OFFSET 0xc150U
102 #define XUSBPSU_GHWPARAMS5_OFFSET 0xc154U
103 #define XUSBPSU_GHWPARAMS6_OFFSET 0xc158U
104 #define XUSBPSU_GHWPARAMS7_OFFSET 0xc15cU
105 #define XUSBPSU_GDBGFIFOSPACE 0xc160
106 #define XUSBPSU_GDBGLTSSM 0xc164
107 #define XUSBPSU_GPRTBIMAP_HS0 0xc180
108 #define XUSBPSU_GPRTBIMAP_HS1 0xc184
109 #define XUSBPSU_GPRTBIMAP_FS0 0xc188
110 #define XUSBPSU_GPRTBIMAP_FS1 0xc18c
112 #define XUSBPSU_GUSB2PHYCFG(n) ((u32)0xc200 + ((u32)(n) * (u32)0x04))
113 #define XUSBPSU_GUSB2I2CCTL(n) ((u32)0xc240 + ((u32)(n) * (u32)0x04))
115 #define XUSBPSU_GUSB2PHYACC(n) ((u32)0xc280 + ((u32)(n) * (u32)0x04))
117 #define XUSBPSU_GUSB3PIPECTL(n) ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
119 #define XUSBPSU_GTXFIFOSIZ(n) ((u32)0xc300 + ((u32)(n) * (u32)0x04))
120 #define XUSBPSU_GRXFIFOSIZ(n) ((u32)0xc380 + ((u32)(n) * (u32)0x04))
122 #define XUSBPSU_GEVNTADRLO(n) ((u32)0xc400 + ((u32)(n) * (u32)0x10))
123 #define XUSBPSU_GEVNTADRHI(n) ((u32)0xc404 + ((u32)(n) * (u32)0x10))
124 #define XUSBPSU_GEVNTSIZ(n) ((u32)0xc408 + ((u32)(n) * (u32)0x10))
125 #define XUSBPSU_GEVNTCOUNT(n) ((u32)0xc40c + ((u32)(n) * (u32)0x10))
127 #define XUSBPSU_GHWPARAMS8 0x0000c600U
129 /* Device Registers */
130 #define XUSBPSU_DCFG 0x0000c700U
131 #define XUSBPSU_DCTL 0x0000c704U
132 #define XUSBPSU_DEVTEN 0x0000c708U
133 #define XUSBPSU_DSTS 0x0000c70cU
134 #define XUSBPSU_DGCMDPAR 0x0000c710U
135 #define XUSBPSU_DGCMD 0x0000c714U
136 #define XUSBPSU_DALEPENA 0x0000c720U
137 #define XUSBPSU_DEPCMDPAR2(n) ((u32)0xc800 + ((u32)n * (u32)0x10))
138 #define XUSBPSU_DEPCMDPAR1(n) ((u32)0xc804 + ((u32)n * (u32)0x10))
139 #define XUSBPSU_DEPCMDPAR0(n) ((u32)0xc808 + ((u32)n * (u32)0x10))
140 #define XUSBPSU_DEPCMD(n) ((u32)0xc80c + ((u32)n * (u32)0x10))
143 #define XUSBPSU_OCFG 0x0000cc00U
144 #define XUSBPSU_OCTL 0x0000cc04U
145 #define XUSBPSU_OEVT 0xcc08U
146 #define XUSBPSU_OEVTEN 0xcc0CU
147 #define XUSBPSU_OSTS 0xcc10U
151 /* Global Configuration Register */
152 #define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
153 #define XUSBPSU_GCTL_U2RSTECN (1 << 16)
154 #define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
155 #define XUSBPSU_GCTL_CLK_BUS (0U)
156 #define XUSBPSU_GCTL_CLK_PIPE (1U)
157 #define XUSBPSU_GCTL_CLK_PIPEHALF (2U)
158 #define XUSBPSU_GCTL_CLK_MASK (3U)
160 #define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
161 #define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
162 #define XUSBPSU_GCTL_PRTCAP_HOST 1U
163 #define XUSBPSU_GCTL_PRTCAP_DEVICE 2U
164 #define XUSBPSU_GCTL_PRTCAP_OTG 3U
166 #define XUSBPSU_GCTL_CORESOFTRESET (0x00000001U << 11)
167 #define XUSBPSU_GCTL_SOFITPSYNC (0x00000001U << 10)
168 #define XUSBPSU_GCTL_SCALEDOWN(n) ((u32)(n) << 4)
169 #define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
170 #define XUSBPSU_GCTL_DISSCRAMBLE (0x00000001U << 3)
171 #define XUSBPSU_GCTL_U2EXIT_LFPS (0x00000001U << 2)
172 #define XUSBPSU_GCTL_GBLHIBERNATIONEN (0x00000001U << 1)
173 #define XUSBPSU_GCTL_DSBLCLKGTNG (0x00000001U << 0)
175 /* Global Status Register Device Interrupt Mask */
176 #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
178 /* Global USB2 PHY Configuration Register */
179 #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31)
180 #define XUSBPSU_GUSB2PHYCFG_SUSPHY (0x00000001U << 6)
182 /* Global USB3 PIPE Control Register */
183 #define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (0x00000001U << 31)
184 #define XUSBPSU_GUSB3PIPECTL_SUSPHY (0x00000001U << 17)
186 /* Global TX Fifo Size Register */
187 #define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((u32)(n) & (u32)0xffffU)
188 #define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((u32)(n) & 0xffff0000U)
190 /* Global Event Size Registers */
191 #define XUSBPSU_GEVNTSIZ_INTMASK ((u32)0x00000001U << 31U)
192 #define XUSBPSU_GEVNTSIZ_SIZE(n) ((u32)(n) & (u32)0xffffU)
194 /* Global HWPARAMS1 Register */
195 #define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((u32)(n) & ((u32)3 << 24)) >> 24)
196 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0U
197 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1U
198 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2U
199 #define XUSBPSU_GHWPARAMS1_PWROPT(n) ((u32)(n) << 24)
200 #define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
202 /* Global HWPARAMS4 Register */
203 #define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
204 #define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15U
206 /* Device Configuration Register */
207 #define XUSBPSU_DCFG_DEVADDR(addr) ((u32)(addr) << 3)
208 #define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
210 #define XUSBPSU_DCFG_SPEED_MASK 7U
211 #define XUSBPSU_DCFG_SUPERSPEED 4U
212 #define XUSBPSU_DCFG_HIGHSPEED 0U
213 #define XUSBPSU_DCFG_FULLSPEED2 1U
214 #define XUSBPSU_DCFG_LOWSPEED 2U
215 #define XUSBPSU_DCFG_FULLSPEED1 3U
217 #define XUSBPSU_DCFG_LPM_CAP (0x00000001U << 22U)
219 /* Device Control Register */
220 #define XUSBPSU_DCTL_RUN_STOP (0x00000001U << 31U)
221 #define XUSBPSU_DCTL_CSFTRST ((u32)0x00000001U << 30U)
222 #define XUSBPSU_DCTL_LSFTRST (0x00000001U << 29U)
224 #define XUSBPSU_DCTL_HIRD_THRES_MASK (0x0000001fU << 24U)
225 #define XUSBPSU_DCTL_HIRD_THRES(n) ((u32)(n) << 24)
227 #define XUSBPSU_DCTL_APPL1RES (0x00000001U << 23)
229 /* These apply for core versions 1.87a and earlier */
230 #define XUSBPSU_DCTL_TRGTULST_MASK (0x0000000fU << 17)
231 #define XUSBPSU_DCTL_TRGTULST(n) ((u32)(n) << 17)
232 #define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
233 #define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
234 #define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
235 #define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
236 #define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
238 /* These apply for core versions 1.94a and later */
239 #define XUSBPSU_DCTL_KEEP_CONNECT (0x00000001U << 19)
240 #define XUSBPSU_DCTL_L1_HIBER_EN (0x00000001U << 18)
241 #define XUSBPSU_DCTL_CRS (0x00000001U << 17)
242 #define XUSBPSU_DCTL_CSS (0x00000001U << 16)
244 #define XUSBPSU_DCTL_INITU2ENA (0x00000001U << 12)
245 #define XUSBPSU_DCTL_ACCEPTU2ENA (0x00000001U << 11)
246 #define XUSBPSU_DCTL_INITU1ENA (0x00000001U << 10)
247 #define XUSBPSU_DCTL_ACCEPTU1ENA (0x00000001U << 9)
248 #define XUSBPSU_DCTL_TSTCTRL_MASK (0x0000000fU << 1)
250 #define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0000000fU << 5)
251 #define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
253 #define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
254 #define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
255 #define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
256 #define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
257 #define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
258 #define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
259 #define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
261 /* Device Event Enable Register */
262 #define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN ((u32)0x00000001 << 12)
263 #define XUSBPSU_DEVTEN_EVNTOVERFLOWEN ((u32)0x00000001 << 11)
264 #define XUSBPSU_DEVTEN_CMDCMPLTEN ((u32)0x00000001 << 10)
265 #define XUSBPSU_DEVTEN_ERRTICERREN ((u32)0x00000001 << 9)
266 #define XUSBPSU_DEVTEN_SOFEN ((u32)0x00000001 << 7)
267 #define XUSBPSU_DEVTEN_EOPFEN ((u32)0x00000001 << 6)
268 #define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN ((u32)0x00000001 << 5)
269 #define XUSBPSU_DEVTEN_WKUPEVTEN ((u32)0x00000001 << 4)
270 #define XUSBPSU_DEVTEN_ULSTCNGEN ((u32)0x00000001 << 3)
271 #define XUSBPSU_DEVTEN_CONNECTDONEEN ((u32)0x00000001 << 2)
272 #define XUSBPSU_DEVTEN_USBRSTEN ((u32)0x00000001 << 1)
273 #define XUSBPSU_DEVTEN_DISCONNEVTEN ((u32)0x00000001 << 0)
275 /* Device Status Register */
276 #define XUSBPSU_DSTS_DCNRD (0x00000001U << 29)
278 /* This applies for core versions 1.87a and earlier */
279 #define XUSBPSU_DSTS_PWRUPREQ (0x00000001U << 24)
281 /* These apply for core versions 1.94a and later */
282 #define XUSBPSU_DSTS_RSS (0x00000001U << 25)
283 #define XUSBPSU_DSTS_SSS (0x00000001U << 24)
285 #define XUSBPSU_DSTS_COREIDLE (0x00000001U << 23)
286 #define XUSBPSU_DSTS_DEVCTRLHLT (0x00000001U << 22)
288 #define XUSBPSU_DSTS_USBLNKST_MASK (0x0000000fU << 18)
289 #define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
291 #define XUSBPSU_DSTS_RXFIFOEMPTY (0x00000001U << 17)
293 #define XUSBPSU_DSTS_SOFFN_MASK (0x00003fffU << 3)
294 #define XUSBPSU_DSTS_SOFFN(n) (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
296 #define XUSBPSU_DSTS_CONNECTSPD (0x00000007U << 0)
298 #define XUSBPSU_DSTS_SUPERSPEED (4U << 0)
299 #define XUSBPSU_DSTS_HIGHSPEED (0U << 0)
300 #define XUSBPSU_DSTS_FULLSPEED2 (1U << 0)
301 #define XUSBPSU_DSTS_LOWSPEED (2U << 0)
302 #define XUSBPSU_DSTS_FULLSPEED1 (3U << 0)
304 /*Portpmsc 3.0 bit field*/
305 #define XUSBPSU_PORTMSC_30_FLA_MASK (1U << 16)
306 #define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK (0xffU << 8)
307 #define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT (8U)
308 #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0)
309 #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U)
314 /**************************** Type Definitions *******************************/
316 /***************** Macros (Inline Functions) Definitions *********************/
318 /*****************************************************************************/
321 * Read a register of the USBPS8 device. This macro provides register
322 * access to all registers using the register offsets defined above.
324 * @param InstancePtr is a pointer to the XUsbPsu instance.
325 * @param Offset is the offset of the register to read.
327 * @return The contents of the register.
329 * @note C-style Signature:
330 * u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
332 ******************************************************************************/
333 #define XUsbPsu_ReadReg(InstancePtr, Offset) \
334 Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
336 /*****************************************************************************/
339 * Write a register of the USBPS8 device. This macro provides
340 * register access to all registers using the register offsets defined above.
342 * @param InstancePtr is a pointer to the XUsbPsu instance.
343 * @param RegOffset is the offset of the register to write.
344 * @param Data is the value to write to the register.
348 * @note C-style Signature:
349 * void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
350 * u32 Offset,u32 Data)
352 ******************************************************************************/
353 #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
354 Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
356 /************************** Function Prototypes ******************************/
362 #endif /* End of protection macro. */