git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_0/src/xzdma_g.c

   1
   2 /*******************************************************************
   3 *
   4 * CAUTION: This file is automatically generated by HSI.
   5 * Version:
   6 * DO NOT EDIT.
   7 *
   8 * Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
   9 *Permission is hereby granted, free of charge, to any person obtaining a copy
  10 *of this software and associated documentation files (the Software), to deal
  11 *in the Software without restriction, including without limitation the rights
  12 *to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 *copies of the Software, and to permit persons to whom the Software is
  14 *furnished to do so, subject to the following conditions:
  15 *
  16 *The above copyright notice and this permission notice shall be included in
  17 *all copies or substantial portions of the Software.
  18 *
  19 * Use of the Software is limited solely to applications:
  20 *(a) running on a Xilinx device, or
  21 *(b) that interact with a Xilinx device through a bus or interconnect.
  22 *
  23 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25 *FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  26 *XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  27 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
  28 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  29 *
  30 *Except as contained in this notice, the name of the Xilinx shall not be used
  31 *in advertising or otherwise to promote the sale, use or other dealings in
  32 *this Software without prior written authorization from Xilinx.
  33 *
  34
  35 *
  36 * Description: Driver configuration
  37 *
  38 *******************************************************************/
  39
  40 #include "xparameters.h"
  41 #include "xzdma.h"
  42
  43 /*
  44 * The configuration table for devices
  45 */
  46
  47 XZDma_Config XZDma_ConfigTable[] =
  48 {
  49         {
  50                 XPAR_PSU_ADMA_0_DEVICE_ID,
  51                 XPAR_PSU_ADMA_0_BASEADDR,
  52                 XPAR_PSU_ADMA_0_DMA_MODE
  53         },
  54         {
  55                 XPAR_PSU_ADMA_1_DEVICE_ID,
  56                 XPAR_PSU_ADMA_1_BASEADDR,
  57                 XPAR_PSU_ADMA_1_DMA_MODE
  58         },
  59         {
  60                 XPAR_PSU_ADMA_2_DEVICE_ID,
  61                 XPAR_PSU_ADMA_2_BASEADDR,
  62                 XPAR_PSU_ADMA_2_DMA_MODE
  63         },
  64         {
  65                 XPAR_PSU_ADMA_3_DEVICE_ID,
  66                 XPAR_PSU_ADMA_3_BASEADDR,
  67                 XPAR_PSU_ADMA_3_DMA_MODE
  68         },
  69         {
  70                 XPAR_PSU_ADMA_4_DEVICE_ID,
  71                 XPAR_PSU_ADMA_4_BASEADDR,
  72                 XPAR_PSU_ADMA_4_DMA_MODE
  73         },
  74         {
  75                 XPAR_PSU_ADMA_5_DEVICE_ID,
  76                 XPAR_PSU_ADMA_5_BASEADDR,
  77                 XPAR_PSU_ADMA_5_DMA_MODE
  78         },
  79         {
  80                 XPAR_PSU_ADMA_6_DEVICE_ID,
  81                 XPAR_PSU_ADMA_6_BASEADDR,
  82                 XPAR_PSU_ADMA_6_DMA_MODE
  83         },
  84         {
  85                 XPAR_PSU_ADMA_7_DEVICE_ID,
  86                 XPAR_PSU_ADMA_7_BASEADDR,
  87                 XPAR_PSU_ADMA_7_DMA_MODE
  88         },
  89         {
  90                 XPAR_PSU_GDMA_0_DEVICE_ID,
  91                 XPAR_PSU_GDMA_0_BASEADDR,
  92                 XPAR_PSU_GDMA_0_DMA_MODE
  93         },
  94         {
  95                 XPAR_PSU_GDMA_1_DEVICE_ID,
  96                 XPAR_PSU_GDMA_1_BASEADDR,
  97                 XPAR_PSU_GDMA_1_DMA_MODE
  98         },
  99         {
 100                 XPAR_PSU_GDMA_2_DEVICE_ID,
 101                 XPAR_PSU_GDMA_2_BASEADDR,
 102                 XPAR_PSU_GDMA_2_DMA_MODE
 103         },
 104         {
 105                 XPAR_PSU_GDMA_3_DEVICE_ID,
 106                 XPAR_PSU_GDMA_3_BASEADDR,
 107                 XPAR_PSU_GDMA_3_DMA_MODE
 108         },
 109         {
 110                 XPAR_PSU_GDMA_4_DEVICE_ID,
 111                 XPAR_PSU_GDMA_4_BASEADDR,
 112                 XPAR_PSU_GDMA_4_DMA_MODE
 113         },
 114         {
 115                 XPAR_PSU_GDMA_5_DEVICE_ID,
 116                 XPAR_PSU_GDMA_5_BASEADDR,
 117                 XPAR_PSU_GDMA_5_DMA_MODE
 118         },
 119         {
 120                 XPAR_PSU_GDMA_6_DEVICE_ID,
 121                 XPAR_PSU_GDMA_6_BASEADDR,
 122                 XPAR_PSU_GDMA_6_DMA_MODE
 123         },
 124         {
 125                 XPAR_PSU_GDMA_7_DEVICE_ID,
 126                 XPAR_PSU_GDMA_7_BASEADDR,
 127                 XPAR_PSU_GDMA_7_DMA_MODE
 128         }
 129 };
 130
 131