1 /******************************************************************************
3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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31 ******************************************************************************/
32 /****************************************************************************/
37 * This file is automatically generated
39 *****************************************************************************/
44 #define DPLL_CFG_LOCK_DLY 63
45 #define DPLL_CFG_LOCK_CNT 625
46 #define DPLL_CFG_LFHF 3
48 #define DPLL_CFG_RES 2
50 static int mask_pollOnValue(u32 add, u32 mask, u32 value);
52 static int mask_poll(u32 add, u32 mask);
54 static void mask_delay(u32 delay);
56 static u32 mask_read(u32 add, u32 mask);
58 static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly,
59 int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
62 void PSU_Mask_Write(unsigned long offset, unsigned long mask,
65 unsigned long RegVal = 0x0;
67 RegVal = Xil_In32(offset);
69 RegVal |= (val & mask);
70 Xil_Out32(offset, RegVal);
73 void prog_reg(unsigned long addr, unsigned long mask,
74 unsigned long shift, unsigned long value) {
77 rdata = Xil_In32(addr);
78 rdata = rdata & (~mask);
79 rdata = rdata | (value << shift);
80 Xil_Out32(addr, rdata);
83 unsigned long psu_pll_init_data(void)
89 * Register : RPLL_CFG @ 0XFF5E0034
91 * PLL loop filter resistor control
92 * PSU_CRL_APB_RPLL_CFG_RES 0xc
94 * PLL charge pump control
95 * PSU_CRL_APB_RPLL_CFG_CP 0x3
97 * PLL loop filter high frequency capacitor control
98 * PSU_CRL_APB_RPLL_CFG_LFHF 0x3
100 * Lock circuit counter setting
101 * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339
103 * Lock circuit configuration settings for lock windowsize
104 * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
106 * Helper data. Values are to be looked up in a table from Data Sheet
107 * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU)
109 PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU);
110 /*##################################################################### */
116 * Register : RPLL_CTRL @ 0XFF5E0030
118 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
119 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
120 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
121 * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
123 * The integer portion of the feedback divider to the PLL
124 * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d
126 * This turns on the divide by 2 that is inside of the PLL. This does not c
127 * hange the VCO frequency, just the output frequency
128 * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
131 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U)
133 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U);
134 /*##################################################################### */
140 * Register : RPLL_CTRL @ 0XFF5E0030
142 * Bypasses the PLL clock. The usable clock will be determined from the POS
143 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
144 * clock and 4 cycles of the new clock. This is not usually an issue, but d
145 * esigners must be aware.)
146 * PSU_CRL_APB_RPLL_CTRL_BYPASS 1
149 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U)
151 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
152 /*##################################################################### */
158 * Register : RPLL_CTRL @ 0XFF5E0030
160 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
162 * PSU_CRL_APB_RPLL_CTRL_RESET 1
165 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U)
167 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
168 /*##################################################################### */
174 * Register : RPLL_CTRL @ 0XFF5E0030
176 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
178 * PSU_CRL_APB_RPLL_CTRL_RESET 0
181 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U)
183 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
184 /*##################################################################### */
190 * Register : PLL_STATUS @ 0XFF5E0040
193 * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
194 * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U)
196 mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U);
198 /*##################################################################### */
204 * Register : RPLL_CTRL @ 0XFF5E0030
206 * Bypasses the PLL clock. The usable clock will be determined from the POS
207 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
208 * clock and 4 cycles of the new clock. This is not usually an issue, but d
209 * esigners must be aware.)
210 * PSU_CRL_APB_RPLL_CTRL_BYPASS 0
213 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U)
215 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
216 /*##################################################################### */
219 * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
221 * Divisor value for this clock.
222 * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
224 * Control for a clock that will be generated in the LPD, but used in the F
225 * PD as a clock source for the peripheral clock muxes.
226 * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
228 PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
229 0x00003F00U, 0x00000200U);
230 /*##################################################################### */
239 * Register : IOPLL_CFG @ 0XFF5E0024
241 * PLL loop filter resistor control
242 * PSU_CRL_APB_IOPLL_CFG_RES 0x2
244 * PLL charge pump control
245 * PSU_CRL_APB_IOPLL_CFG_CP 0x4
247 * PLL loop filter high frequency capacitor control
248 * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
250 * Lock circuit counter setting
251 * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258
253 * Lock circuit configuration settings for lock windowsize
254 * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
256 * Helper data. Values are to be looked up in a table from Data Sheet
257 * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U)
259 PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
260 /*##################################################################### */
266 * Register : IOPLL_CTRL @ 0XFF5E0020
268 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
269 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
270 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
271 * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
273 * The integer portion of the feedback divider to the PLL
274 * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a
276 * This turns on the divide by 2 that is inside of the PLL. This does not c
277 * hange the VCO frequency, just the output frequency
278 * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1
281 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U)
283 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
284 /*##################################################################### */
290 * Register : IOPLL_CTRL @ 0XFF5E0020
292 * Bypasses the PLL clock. The usable clock will be determined from the POS
293 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
294 * clock and 4 cycles of the new clock. This is not usually an issue, but d
295 * esigners must be aware.)
296 * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
299 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U)
301 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
302 /*##################################################################### */
308 * Register : IOPLL_CTRL @ 0XFF5E0020
310 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
312 * PSU_CRL_APB_IOPLL_CTRL_RESET 1
315 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U)
317 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
318 /*##################################################################### */
324 * Register : IOPLL_CTRL @ 0XFF5E0020
326 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
328 * PSU_CRL_APB_IOPLL_CTRL_RESET 0
331 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U)
333 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
334 /*##################################################################### */
340 * Register : PLL_STATUS @ 0XFF5E0040
343 * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
344 * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U)
346 mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U);
348 /*##################################################################### */
354 * Register : IOPLL_CTRL @ 0XFF5E0020
356 * Bypasses the PLL clock. The usable clock will be determined from the POS
357 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
358 * clock and 4 cycles of the new clock. This is not usually an issue, but d
359 * esigners must be aware.)
360 * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
363 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U)
365 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
366 /*##################################################################### */
369 * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044
371 * Divisor value for this clock.
372 * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
374 * Control for a clock that will be generated in the LPD, but used in the F
375 * PD as a clock source for the peripheral clock muxes.
376 * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U)
378 PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET,
379 0x00003F00U, 0x00000300U);
380 /*##################################################################### */
389 * Register : APLL_CFG @ 0XFD1A0024
391 * PLL loop filter resistor control
392 * PSU_CRF_APB_APLL_CFG_RES 0x2
394 * PLL charge pump control
395 * PSU_CRF_APB_APLL_CFG_CP 0x3
397 * PLL loop filter high frequency capacitor control
398 * PSU_CRF_APB_APLL_CFG_LFHF 0x3
400 * Lock circuit counter setting
401 * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
403 * Lock circuit configuration settings for lock windowsize
404 * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
406 * Helper data. Values are to be looked up in a table from Data Sheet
407 * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
409 PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
410 /*##################################################################### */
416 * Register : APLL_CTRL @ 0XFD1A0020
418 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
419 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
420 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
421 * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
423 * The integer portion of the feedback divider to the PLL
424 * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48
426 * This turns on the divide by 2 that is inside of the PLL. This does not c
427 * hange the VCO frequency, just the output frequency
428 * PSU_CRF_APB_APLL_CTRL_DIV2 0x1
431 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U)
433 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U);
434 /*##################################################################### */
440 * Register : APLL_CTRL @ 0XFD1A0020
442 * Bypasses the PLL clock. The usable clock will be determined from the POS
443 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
444 * clock and 4 cycles of the new clock. This is not usually an issue, but d
445 * esigners must be aware.)
446 * PSU_CRF_APB_APLL_CTRL_BYPASS 1
449 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U)
451 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
452 /*##################################################################### */
458 * Register : APLL_CTRL @ 0XFD1A0020
460 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
462 * PSU_CRF_APB_APLL_CTRL_RESET 1
465 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U)
467 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
468 /*##################################################################### */
474 * Register : APLL_CTRL @ 0XFD1A0020
476 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
478 * PSU_CRF_APB_APLL_CTRL_RESET 0
481 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U)
483 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
484 /*##################################################################### */
490 * Register : PLL_STATUS @ 0XFD1A0044
493 * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
494 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U)
496 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U);
498 /*##################################################################### */
504 * Register : APLL_CTRL @ 0XFD1A0020
506 * Bypasses the PLL clock. The usable clock will be determined from the POS
507 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
508 * clock and 4 cycles of the new clock. This is not usually an issue, but d
509 * esigners must be aware.)
510 * PSU_CRF_APB_APLL_CTRL_BYPASS 0
513 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U)
515 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
516 /*##################################################################### */
519 * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048
521 * Divisor value for this clock.
522 * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
524 * Control for a clock that will be generated in the FPD, but used in the L
525 * PD as a clock source for the peripheral clock muxes.
526 * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U)
528 PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET,
529 0x00003F00U, 0x00000300U);
530 /*##################################################################### */
539 * Register : DPLL_CFG @ 0XFD1A0030
541 * PLL loop filter resistor control
542 * PSU_CRF_APB_DPLL_CFG_RES 0x2
544 * PLL charge pump control
545 * PSU_CRF_APB_DPLL_CFG_CP 0x3
547 * PLL loop filter high frequency capacitor control
548 * PSU_CRF_APB_DPLL_CFG_LFHF 0x3
550 * Lock circuit counter setting
551 * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
553 * Lock circuit configuration settings for lock windowsize
554 * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
556 * Helper data. Values are to be looked up in a table from Data Sheet
557 * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
559 PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
560 /*##################################################################### */
566 * Register : DPLL_CTRL @ 0XFD1A002C
568 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
569 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
570 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
571 * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
573 * The integer portion of the feedback divider to the PLL
574 * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
576 * This turns on the divide by 2 that is inside of the PLL. This does not c
577 * hange the VCO frequency, just the output frequency
578 * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
581 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U)
583 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U);
584 /*##################################################################### */
590 * Register : DPLL_CTRL @ 0XFD1A002C
592 * Bypasses the PLL clock. The usable clock will be determined from the POS
593 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
594 * clock and 4 cycles of the new clock. This is not usually an issue, but d
595 * esigners must be aware.)
596 * PSU_CRF_APB_DPLL_CTRL_BYPASS 1
599 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U)
601 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
602 /*##################################################################### */
608 * Register : DPLL_CTRL @ 0XFD1A002C
610 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
612 * PSU_CRF_APB_DPLL_CTRL_RESET 1
615 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U)
617 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
618 /*##################################################################### */
624 * Register : DPLL_CTRL @ 0XFD1A002C
626 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
628 * PSU_CRF_APB_DPLL_CTRL_RESET 0
631 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U)
633 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
634 /*##################################################################### */
640 * Register : PLL_STATUS @ 0XFD1A0044
643 * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
644 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U)
646 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U);
648 /*##################################################################### */
654 * Register : DPLL_CTRL @ 0XFD1A002C
656 * Bypasses the PLL clock. The usable clock will be determined from the POS
657 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
658 * clock and 4 cycles of the new clock. This is not usually an issue, but d
659 * esigners must be aware.)
660 * PSU_CRF_APB_DPLL_CTRL_BYPASS 0
663 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U)
665 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
666 /*##################################################################### */
669 * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C
671 * Divisor value for this clock.
672 * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2
674 * Control for a clock that will be generated in the FPD, but used in the L
675 * PD as a clock source for the peripheral clock muxes.
676 * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U)
678 PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET,
679 0x00003F00U, 0x00000200U);
680 /*##################################################################### */
689 * Register : VPLL_CFG @ 0XFD1A003C
691 * PLL loop filter resistor control
692 * PSU_CRF_APB_VPLL_CFG_RES 0x2
694 * PLL charge pump control
695 * PSU_CRF_APB_VPLL_CFG_CP 0x4
697 * PLL loop filter high frequency capacitor control
698 * PSU_CRF_APB_VPLL_CFG_LFHF 0x3
700 * Lock circuit counter setting
701 * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258
703 * Lock circuit configuration settings for lock windowsize
704 * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
706 * Helper data. Values are to be looked up in a table from Data Sheet
707 * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U)
709 PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
710 /*##################################################################### */
716 * Register : VPLL_CTRL @ 0XFD1A0038
718 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
719 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
720 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
721 * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
723 * The integer portion of the feedback divider to the PLL
724 * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a
726 * This turns on the divide by 2 that is inside of the PLL. This does not c
727 * hange the VCO frequency, just the output frequency
728 * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
731 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U)
733 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
734 /*##################################################################### */
740 * Register : VPLL_CTRL @ 0XFD1A0038
742 * Bypasses the PLL clock. The usable clock will be determined from the POS
743 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
744 * clock and 4 cycles of the new clock. This is not usually an issue, but d
745 * esigners must be aware.)
746 * PSU_CRF_APB_VPLL_CTRL_BYPASS 1
749 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U)
751 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
752 /*##################################################################### */
758 * Register : VPLL_CTRL @ 0XFD1A0038
760 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
762 * PSU_CRF_APB_VPLL_CTRL_RESET 1
765 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U)
767 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
768 /*##################################################################### */
774 * Register : VPLL_CTRL @ 0XFD1A0038
776 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
778 * PSU_CRF_APB_VPLL_CTRL_RESET 0
781 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U)
783 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
784 /*##################################################################### */
790 * Register : PLL_STATUS @ 0XFD1A0044
793 * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
794 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U)
796 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U);
798 /*##################################################################### */
804 * Register : VPLL_CTRL @ 0XFD1A0038
806 * Bypasses the PLL clock. The usable clock will be determined from the POS
807 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
808 * clock and 4 cycles of the new clock. This is not usually an issue, but d
809 * esigners must be aware.)
810 * PSU_CRF_APB_VPLL_CTRL_BYPASS 0
813 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U)
815 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
816 /*##################################################################### */
819 * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050
821 * Divisor value for this clock.
822 * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
824 * Control for a clock that will be generated in the FPD, but used in the L
825 * PD as a clock source for the peripheral clock muxes.
826 * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U)
828 PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET,
829 0x00003F00U, 0x00000300U);
830 /*##################################################################### */
838 unsigned long psu_clock_init_data(void)
841 * CLOCK CONTROL SLCR REGISTER
844 * Register : GEM3_REF_CTRL @ 0XFF5E005C
846 * Clock active for the RX channel
847 * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1
849 * Clock active signal. Switch to 0 to disable the clock
850 * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1
853 * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
856 * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
858 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
859 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
860 * usually an issue, but designers must be aware.)
861 * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
863 * This register controls this reference clock
864 * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
866 PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET,
867 0x063F3F07U, 0x06010C00U);
868 /*##################################################################### */
871 * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
874 * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
876 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
877 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
878 * usually an issue, but designers must be aware.)
879 * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0
882 * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
884 * Clock active signal. Switch to 0 to disable the clock
885 * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
887 * This register controls this reference clock
888 * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U)
890 PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET,
891 0x013F3F07U, 0x01010600U);
892 /*##################################################################### */
895 * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
897 * Clock active signal. Switch to 0 to disable the clock
898 * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
901 * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
904 * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
906 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
907 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
908 * usually an issue, but designers must be aware.)
909 * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
911 * This register controls this reference clock
912 * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U)
914 PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET,
915 0x023F3F07U, 0x02010600U);
916 /*##################################################################### */
919 * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
921 * Clock active signal. Switch to 0 to disable the clock
922 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
925 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3
928 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19
930 * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
931 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
932 * usually an issue, but designers must be aware.)
933 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
935 * This register controls this reference clock
936 * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U)
938 PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET,
939 0x023F3F07U, 0x02031900U);
940 /*##################################################################### */
943 * Register : QSPI_REF_CTRL @ 0XFF5E0068
945 * Clock active signal. Switch to 0 to disable the clock
946 * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1
949 * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
952 * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
954 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
955 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
956 * usually an issue, but designers must be aware.)
957 * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
959 * This register controls this reference clock
960 * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
962 PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
963 0x013F3F07U, 0x01010C00U);
964 /*##################################################################### */
967 * Register : SDIO1_REF_CTRL @ 0XFF5E0070
969 * Clock active signal. Switch to 0 to disable the clock
970 * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
973 * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
976 * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
978 * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
979 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
980 * usually an issue, but designers must be aware.)
981 * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
983 * This register controls this reference clock
984 * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U)
986 PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET,
987 0x013F3F07U, 0x01010800U);
988 /*##################################################################### */
991 * Register : SDIO_CLK_CTRL @ 0XFF18030C
993 * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
995 * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
997 * SoC Debug Clock Control
998 * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U)
1000 PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET,
1001 0x00020000U, 0x00000000U);
1002 /*##################################################################### */
1005 * Register : UART0_REF_CTRL @ 0XFF5E0074
1007 * Clock active signal. Switch to 0 to disable the clock
1008 * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
1011 * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
1014 * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
1016 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1017 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1018 * usually an issue, but designers must be aware.)
1019 * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
1021 * This register controls this reference clock
1022 * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
1024 PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET,
1025 0x013F3F07U, 0x01010F00U);
1026 /*##################################################################### */
1029 * Register : UART1_REF_CTRL @ 0XFF5E0078
1031 * Clock active signal. Switch to 0 to disable the clock
1032 * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
1035 * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
1038 * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
1040 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1041 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1042 * usually an issue, but designers must be aware.)
1043 * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
1045 * This register controls this reference clock
1046 * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
1048 PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET,
1049 0x013F3F07U, 0x01010F00U);
1050 /*##################################################################### */
1053 * Register : I2C0_REF_CTRL @ 0XFF5E0120
1055 * Clock active signal. Switch to 0 to disable the clock
1056 * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1
1059 * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
1062 * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
1064 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1065 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1066 * usually an issue, but designers must be aware.)
1067 * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
1069 * This register controls this reference clock
1070 * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
1072 PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET,
1073 0x013F3F07U, 0x01010F00U);
1074 /*##################################################################### */
1077 * Register : I2C1_REF_CTRL @ 0XFF5E0124
1079 * Clock active signal. Switch to 0 to disable the clock
1080 * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
1083 * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
1086 * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
1088 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1089 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1090 * usually an issue, but designers must be aware.)
1091 * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
1093 * This register controls this reference clock
1094 * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
1096 PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET,
1097 0x013F3F07U, 0x01010F00U);
1098 /*##################################################################### */
1101 * Register : CAN1_REF_CTRL @ 0XFF5E0088
1103 * Clock active signal. Switch to 0 to disable the clock
1104 * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
1107 * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
1110 * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
1112 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1113 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1114 * usually an issue, but designers must be aware.)
1115 * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
1117 * This register controls this reference clock
1118 * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
1120 PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET,
1121 0x013F3F07U, 0x01010F00U);
1122 /*##################################################################### */
1125 * Register : CPU_R5_CTRL @ 0XFF5E0090
1127 * Turing this off will shut down the OCM, some parts of the APM, and preve
1128 * nt transactions going from the FPD to the LPD and could lead to system h
1130 * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
1133 * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
1135 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1136 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1137 * usually an issue, but designers must be aware.)
1138 * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
1140 * This register controls this reference clock
1141 * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U)
1143 PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U);
1144 /*##################################################################### */
1147 * Register : IOU_SWITCH_CTRL @ 0XFF5E009C
1149 * Clock active signal. Switch to 0 to disable the clock
1150 * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
1153 * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
1155 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1156 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1157 * usually an issue, but designers must be aware.)
1158 * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
1160 * This register controls this reference clock
1161 * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U)
1163 PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET,
1164 0x01003F07U, 0x01000602U);
1165 /*##################################################################### */
1168 * Register : PCAP_CTRL @ 0XFF5E00A4
1170 * Clock active signal. Switch to 0 to disable the clock
1171 * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
1174 * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
1176 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1177 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1178 * usually an issue, but designers must be aware.)
1179 * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
1181 * This register controls this reference clock
1182 * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U)
1184 PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U);
1185 /*##################################################################### */
1188 * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8
1190 * Clock active signal. Switch to 0 to disable the clock
1191 * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
1194 * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
1196 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1197 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1198 * usually an issue, but designers must be aware.)
1199 * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
1201 * This register controls this reference clock
1202 * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U)
1204 PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET,
1205 0x01003F07U, 0x01000302U);
1206 /*##################################################################### */
1209 * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC
1211 * Clock active signal. Switch to 0 to disable the clock
1212 * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
1215 * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
1217 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1218 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1219 * usually an issue, but designers must be aware.)
1220 * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
1222 * This register controls this reference clock
1223 * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
1225 PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET,
1226 0x01003F07U, 0x01000F02U);
1227 /*##################################################################### */
1230 * Register : DBG_LPD_CTRL @ 0XFF5E00B0
1232 * Clock active signal. Switch to 0 to disable the clock
1233 * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
1236 * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
1238 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1239 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1240 * usually an issue, but designers must be aware.)
1241 * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
1243 * This register controls this reference clock
1244 * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U)
1246 PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET,
1247 0x01003F07U, 0x01000602U);
1248 /*##################################################################### */
1251 * Register : ADMA_REF_CTRL @ 0XFF5E00B8
1253 * Clock active signal. Switch to 0 to disable the clock
1254 * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
1257 * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
1259 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1260 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1261 * usually an issue, but designers must be aware.)
1262 * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
1264 * This register controls this reference clock
1265 * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U)
1267 PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET,
1268 0x01003F07U, 0x01000302U);
1269 /*##################################################################### */
1272 * Register : PL0_REF_CTRL @ 0XFF5E00C0
1274 * Clock active signal. Switch to 0 to disable the clock
1275 * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
1278 * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
1281 * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
1283 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1284 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1285 * usually an issue, but designers must be aware.)
1286 * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
1288 * This register controls this reference clock
1289 * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
1291 PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET,
1292 0x013F3F07U, 0x01010F00U);
1293 /*##################################################################### */
1296 * Register : AMS_REF_CTRL @ 0XFF5E0108
1299 * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
1302 * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e
1304 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1305 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1306 * usually an issue, but designers must be aware.)
1307 * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
1309 * Clock active signal. Switch to 0 to disable the clock
1310 * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
1312 * This register controls this reference clock
1313 * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U)
1315 PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET,
1316 0x013F3F07U, 0x01011E02U);
1317 /*##################################################################### */
1320 * Register : DLL_REF_CTRL @ 0XFF5E0104
1322 * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
1323 * of the old clock and 4 cycles of the new clock. This is not usually an
1324 * issue, but designers must be aware.)
1325 * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
1327 * This register controls this reference clock
1328 * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U)
1330 PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET,
1331 0x00000007U, 0x00000000U);
1332 /*##################################################################### */
1335 * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
1338 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
1340 * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
1341 * only be toggled after 4 cycles of the old clock and 4 cycles of the new
1342 * clock. This is not usually an issue, but designers must be aware.)
1343 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
1345 * Clock active signal. Switch to 0 to disable the clock
1346 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
1348 * This register controls this reference clock
1349 * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U)
1351 PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET,
1352 0x01003F07U, 0x01000F00U);
1353 /*##################################################################### */
1356 * Register : SATA_REF_CTRL @ 0XFD1A00A0
1358 * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
1359 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1360 * is not usually an issue, but designers must be aware.)
1361 * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0
1363 * Clock active signal. Switch to 0 to disable the clock
1364 * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1
1367 * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2
1369 * This register controls this reference clock
1370 * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U)
1372 PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET,
1373 0x01003F07U, 0x01000200U);
1374 /*##################################################################### */
1377 * Register : PCIE_REF_CTRL @ 0XFD1A00B4
1379 * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
1380 * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
1381 * k. This is not usually an issue, but designers must be aware.)
1382 * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
1384 * Clock active signal. Switch to 0 to disable the clock
1385 * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
1388 * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
1390 * This register controls this reference clock
1391 * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U)
1393 PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET,
1394 0x01003F07U, 0x01000200U);
1395 /*##################################################################### */
1398 * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070
1401 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
1404 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5
1406 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1407 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1408 * les of the new clock. This is not usually an issue, but designers must b
1410 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0
1412 * Clock active signal. Switch to 0 to disable the clock
1413 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
1415 * This register controls this reference clock
1416 * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U)
1418 PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET,
1419 0x013F3F07U, 0x01010500U);
1420 /*##################################################################### */
1423 * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074
1426 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
1429 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf
1431 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1432 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1433 * les of the new clock. This is not usually an issue, but designers must b
1435 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3
1437 * Clock active signal. Switch to 0 to disable the clock
1438 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1
1440 * This register controls this reference clock
1441 * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U)
1443 PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET,
1444 0x013F3F07U, 0x01010F03U);
1445 /*##################################################################### */
1448 * Register : DP_STC_REF_CTRL @ 0XFD1A007C
1451 * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1
1454 * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe
1456 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
1457 * led after 4 cycles of the old clock and 4 cycles of the new clock. This
1458 * is not usually an issue, but designers must be aware.)
1459 * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3
1461 * Clock active signal. Switch to 0 to disable the clock
1462 * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1
1464 * This register controls this reference clock
1465 * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U)
1467 PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET,
1468 0x013F3F07U, 0x01010E03U);
1469 /*##################################################################### */
1472 * Register : ACPU_CTRL @ 0XFD1A0060
1475 * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1
1477 * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
1478 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1479 * usually an issue, but designers must be aware.)
1480 * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0
1482 * Clock active signal. Switch to 0 to disable the clock. For the half spee
1484 * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1
1486 * Clock active signal. Switch to 0 to disable the clock. For the full spee
1487 * d ACPUX Clock. This will shut off the high speed clock to the entire APU
1488 * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1
1490 * This register controls this reference clock
1491 * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U)
1493 PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U);
1494 /*##################################################################### */
1497 * Register : DBG_FPD_CTRL @ 0XFD1A0068
1500 * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2
1502 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1503 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1504 * is not usually an issue, but designers must be aware.)
1505 * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0
1507 * Clock active signal. Switch to 0 to disable the clock
1508 * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1
1510 * This register controls this reference clock
1511 * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U)
1513 PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET,
1514 0x01003F07U, 0x01000200U);
1515 /*##################################################################### */
1518 * Register : DDR_CTRL @ 0XFD1A0080
1521 * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2
1523 * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
1524 * of the old clock and 4 cycles of the new clock. This is not usually an i
1525 * ssue, but designers must be aware.)
1526 * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0
1528 * This register controls this reference clock
1529 * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U)
1531 PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U);
1532 /*##################################################################### */
1535 * Register : GPU_REF_CTRL @ 0XFD1A0084
1538 * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1
1540 * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
1541 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1542 * is not usually an issue, but designers must be aware.)
1543 * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0
1545 * Clock active signal. Switch to 0 to disable the clock, which will stop c
1546 * lock for GPU (and both Pixel Processors).
1547 * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1
1549 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1550 * k only to this Pixel Processor
1551 * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1
1553 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1554 * k only to this Pixel Processor
1555 * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1
1557 * This register controls this reference clock
1558 * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U)
1560 PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET,
1561 0x07003F07U, 0x07000100U);
1562 /*##################################################################### */
1565 * Register : GDMA_REF_CTRL @ 0XFD1A00B8
1568 * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2
1570 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1571 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1572 * usually an issue, but designers must be aware.)
1573 * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0
1575 * Clock active signal. Switch to 0 to disable the clock
1576 * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1
1578 * This register controls this reference clock
1579 * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U)
1581 PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET,
1582 0x01003F07U, 0x01000200U);
1583 /*##################################################################### */
1586 * Register : DPDMA_REF_CTRL @ 0XFD1A00BC
1589 * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2
1591 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1592 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1593 * usually an issue, but designers must be aware.)
1594 * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0
1596 * Clock active signal. Switch to 0 to disable the clock
1597 * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1
1599 * This register controls this reference clock
1600 * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U)
1602 PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET,
1603 0x01003F07U, 0x01000200U);
1604 /*##################################################################### */
1607 * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0
1610 * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2
1612 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1613 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1614 * usually an issue, but designers must be aware.)
1615 * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3
1617 * Clock active signal. Switch to 0 to disable the clock
1618 * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1
1620 * This register controls this reference clock
1621 * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U)
1623 PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET,
1624 0x01003F07U, 0x01000203U);
1625 /*##################################################################### */
1628 * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4
1631 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5
1633 * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
1634 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1635 * is not usually an issue, but designers must be aware.)
1636 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2
1638 * Clock active signal. Switch to 0 to disable the clock
1639 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1
1641 * This register controls this reference clock
1642 * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U)
1644 PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET,
1645 0x01003F07U, 0x01000502U);
1646 /*##################################################################### */
1649 * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
1652 * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2
1654 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1655 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1656 * is not usually an issue, but designers must be aware.)
1657 * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0
1659 * This register controls this reference clock
1660 * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U)
1662 PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET,
1663 0x00003F07U, 0x00000200U);
1664 /*##################################################################### */
1667 * Register : IOU_TTC_APB_CLK @ 0XFF180380
1669 * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
1670 * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
1671 * clock for the APB interface of TTC0
1672 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0
1674 * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
1675 * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
1676 * clock for the APB interface of TTC1
1677 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0
1679 * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
1680 * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
1681 * clock for the APB interface of TTC2
1682 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0
1684 * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
1685 * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
1686 * clock for the APB interface of TTC3
1687 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0
1689 * TTC APB clock select
1690 * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U)
1692 PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET,
1693 0x000000FFU, 0x00000000U);
1694 /*##################################################################### */
1697 * Register : WDT_CLK_SEL @ 0XFD610100
1699 * System watchdog timer clock source selection: 0: Internal APB clock 1: E
1700 * xternal (PL clock via EMIO or Pinout clock via MIO)
1701 * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0
1703 * SWDT clock source select
1704 * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U)
1706 PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET,
1707 0x00000001U, 0x00000000U);
1708 /*##################################################################### */
1711 * Register : WDT_CLK_SEL @ 0XFF180300
1713 * System watchdog timer clock source selection: 0: internal clock APB cloc
1714 * k 1: external clock from PL via EMIO, or from pinout via MIO
1715 * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0
1717 * SWDT clock source select
1718 * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U)
1720 PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET,
1721 0x00000001U, 0x00000000U);
1722 /*##################################################################### */
1725 * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050
1727 * System watchdog timer clock source selection: 0: internal clock APB cloc
1728 * k 1: external clock pss_ref_clk
1729 * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0
1731 * SWDT clock source select
1732 * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U)
1734 PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET,
1735 0x00000001U, 0x00000000U);
1736 /*##################################################################### */
1741 unsigned long psu_ddr_init_data(void)
1744 * DDR INITIALIZATION
1747 * DDR CONTROLLER RESET
1750 * Register : RST_DDR_SS @ 0XFD1A0108
1752 * DDR block level reset inside of the DDR Sub System
1753 * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1
1755 * DDR sub system block level reset
1756 * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U)
1758 PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U);
1759 /*##################################################################### */
1762 * Register : MSTR @ 0XFD070000
1764 * Indicates the configuration of the device used in the system. - 00 - x4
1765 * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
1766 * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1
1768 * Choose which registers are used. - 0 - Original registers - 1 - Shadow r
1770 * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0
1772 * Only present for multi-rank configurations. Each bit represents one rank
1773 * . For two-rank configurations, only bits[25:24] are present. - 1 - popul
1774 * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
1775 * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
1776 * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
1777 * k - 0011 - Two ranks - 1111 - Four ranks
1778 * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1
1780 * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
1781 * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
1782 * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
1783 * values are reserved. This controls the burst size used to access the SDR
1784 * AM. This must match the burst length mode register setting in the SDRAM.
1785 * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
1786 * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
1787 * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1788 * PSU_DDRC_MSTR_BURST_RDWR 0x4
1790 * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
1791 * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
1792 * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
1793 * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
1794 * s bit must be set to '0'.
1795 * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0
1797 * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
1798 * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
1799 * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
1800 * only supported when the SDRAM bus width is a multiple of 16, and quarter
1801 * bus width mode is only supported when the SDRAM bus width is a multiple
1802 * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
1803 * th refers to DQ bus width (excluding any ECC width).
1804 * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0
1806 * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
1807 * RAM in normal mode (1N). This register can be changed, only when the Con
1808 * troller is in self-refresh mode. This signal must be set the same value
1809 * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
1810 * parameter MEMC_CMD_RTN2IDLE is set
1811 * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0
1813 * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
1814 * g, all command signals (except chip select) are held for 2 clocks on the
1815 * SDRAM bus. Chip select is asserted on the second cycle of the command N
1816 * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
1817 * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
1818 * s set Note: 2T timing is not supported in DDR4 geardown mode.
1819 * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0
1821 * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
1822 * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
1823 * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
1824 * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
1825 * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
1826 * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
1827 * , and this bit must be set to '0'
1828 * PSU_DDRC_MSTR_BURSTCHOP 0x0
1830 * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
1831 * evice in use Present only in designs configured to support LPDDR4.
1832 * PSU_DDRC_MSTR_LPDDR4 0x0
1834 * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
1835 * in use Present only in designs configured to support DDR4.
1836 * PSU_DDRC_MSTR_DDR4 0x1
1838 * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
1839 * evice in use Present only in designs configured to support LPDDR3.
1840 * PSU_DDRC_MSTR_LPDDR3 0x0
1842 * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
1843 * evice in use Present only in designs configured to support LPDDR2.
1844 * PSU_DDRC_MSTR_LPDDR2 0x0
1846 * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
1847 * vice in use Only present in designs that support DDR3.
1848 * PSU_DDRC_MSTR_DDR3 0x0
1851 * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U)
1853 PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U);
1854 /*##################################################################### */
1857 * Register : MRCTRL0 @ 0XFD070010
1859 * Setting this register bit to 1 triggers a mode register read or write op
1860 * eration. When the MR operation is complete, the uMCTL2 automatically cle
1861 * ars this bit. The other register fields of this register must be written
1862 * in a separate APB transaction, before setting this mr_wr bit. It is rec
1863 * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
1865 * PSU_DDRC_MRCTRL0_MR_WR 0x0
1867 * Address of the mode register that is to be written to. - 0000 - MR0 - 00
1868 * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
1869 * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
1870 * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
1871 * o used for writing to control words of RDIMMs. In that case, it correspo
1872 * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
1873 * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
1874 * s the bit[2:0] must be set to an appropriate value which is considered b
1875 * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
1877 * PSU_DDRC_MRCTRL0_MR_ADDR 0x0
1879 * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
1880 * d to access all ranks, so all bits should be set to 1. However, for mult
1881 * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
1882 * ary to access ranks individually. Examples (assume uMCTL2 is configured
1883 * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
1884 * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
1886 * PSU_DDRC_MRCTRL0_MR_RANK 0x3
1888 * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
1889 * efore automatic SDRAM initialization routine or not. For DDR4, this bit
1890 * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
1891 * ialization. For LPDDR4, this bit can be used to program additional mode
1892 * registers before automatic SDRAM initialization if necessary. Note: This
1893 * must be cleared to 0 after completing Software operation. Otherwise, SD
1894 * RAM initialization routine will not re-start. - 0 - Software interventio
1895 * n is not allowed - 1 - Software intervention is allowed
1896 * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0
1898 * Indicates whether the mode register operation is MRS in PDA mode or not
1899 * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
1900 * PSU_DDRC_MRCTRL0_PDA_EN 0x0
1902 * Indicates whether the mode register operation is MRS or WR/RD for MPR (o
1903 * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
1904 * PSU_DDRC_MRCTRL0_MPR_EN 0x0
1906 * Indicates whether the mode register operation is read or write. Only use
1907 * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
1908 * PSU_DDRC_MRCTRL0_MR_TYPE 0x0
1910 * Mode Register Read/Write Control Register 0. Note: Do not enable more th
1911 * an one of the following fields simultaneously: - sw_init_int - pda_en -
1913 * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U)
1915 PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U);
1916 /*##################################################################### */
1919 * Register : DERATEEN @ 0XFD070020
1921 * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
1922 * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
1923 * esigns configured to support LPDDR4. The required number of cycles for d
1924 * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
1925 * eriod, and rounding up the next integer.
1926 * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2
1928 * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
1929 * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
1930 * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
1931 * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0
1933 * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
1934 * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
1935 * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
1936 * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
1937 * 75 ns is less than a core_ddrc_core_clk period or not.
1938 * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0
1940 * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
1941 * g parameter derating is enabled using MR4 read value. Present only in de
1942 * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
1943 * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
1944 * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0
1946 * Temperature Derate Enable Register
1947 * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U)
1949 PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U);
1950 /*##################################################################### */
1953 * Register : DERATEINT @ 0XFD070024
1955 * Interval between two MR4 reads, used to derate the timing parameters. Pr
1956 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
1957 * egister must not be set to zero
1958 * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000
1960 * Temperature Derate Interval Register
1961 * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
1963 PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U);
1964 /*##################################################################### */
1967 * Register : PWRCTL @ 0XFD070030
1969 * Self refresh state is an intermediate state to enter to Self refresh pow
1970 * er down state or exit Self refresh power down state for LPDDR4. This reg
1971 * ister controls transition from the Self refresh state. - 1 - Prohibit tr
1972 * ansition from Self refresh state - 0 - Allow transition from Self refres
1974 * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0
1976 * A value of 1 to this register causes system to move to Self Refresh stat
1977 * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
1978 * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
1979 * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
1980 * PSU_DDRC_PWRCTL_SELFREF_SW 0x0
1982 * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
1983 * when the transaction store is empty. This register must be reset to '0'
1984 * to bring uMCTL2 out of maximum power saving mode. Present only in desig
1985 * ns configured to support DDR4. For non-DDR4, this register should not be
1986 * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
1987 * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
1988 * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
1989 * PSU_DDRC_PWRCTL_MPSM_EN 0x0
1991 * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
1992 * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
1993 * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
1994 * be asserted in Self Refresh. In DDR4, can be asserted in following: - i
1995 * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
1996 * n be asserted in following: - in Self Refresh - in Power Down - in Deep
1997 * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
1998 * rted in following: - in Self Refresh Power Down - in Power Down - during
1999 * Normal operation (Clock Stop)
2000 * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0
2002 * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
2003 * transaction store is empty. This register must be reset to '0' to bring
2004 * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
2005 * initialization on deep power-down exit. Present only in designs configu
2006 * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
2007 * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
2008 * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0
2010 * If true then the uMCTL2 goes into power-down after a programmable number
2011 * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
2012 * x32). This register bit may be re-programmed during the course of normal
2014 * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0
2016 * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
2017 * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
2018 * selfref_to_x32)'. This register bit may be re-programmed during the cour
2019 * se of normal operation.
2020 * PSU_DDRC_PWRCTL_SELFREF_EN 0x0
2022 * Low Power Control Register
2023 * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U)
2025 PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U);
2026 /*##################################################################### */
2029 * Register : PWRTMG @ 0XFD070034
2031 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
2032 * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
2033 * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2034 * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40
2036 * Minimum deep power-down time. For mDDR, value from the JEDEC specificati
2037 * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
2038 * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
2039 * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
2040 * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
2042 * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84
2044 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
2045 * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
2046 * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
2047 * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10
2049 * Low Power Timing Register
2050 * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U)
2052 PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U);
2053 /*##################################################################### */
2056 * Register : RFSHCTL0 @ 0XFD070050
2058 * Threshold value in number of clock cycles before the critical refresh or
2059 * page timer expires. A critical refresh is to be issued before this thre
2060 * shold is reached. It is recommended that this not be changed from the de
2061 * fault value, currently shown as 0x2. It must always be less than interna
2062 * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
2063 * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
2064 * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
2065 * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
2067 * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2
2069 * If the refresh timer (tRFCnom, also known as tREFI) has expired at least
2070 * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
2071 * a speculative refresh may be performed. A speculative refresh is a refr
2072 * esh performed at a time when refresh would be useful, but before it is a
2073 * bsolutely required. When the SDRAM bus is idle for a period of time dete
2074 * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
2075 * at least once since the last refresh, then a speculative refresh is per
2076 * formed. Speculative refreshes continues successively until there are no
2077 * refreshes pending or until new reads or writes are issued to the uMCTL2.
2078 * FOR PERFORMANCE ONLY.
2079 * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10
2081 * The programmed value + 1 is the number of refresh timeouts that is allow
2082 * ed to accumulate before traffic is blocked and the refreshes are forced
2083 * to execute. Closing pages to perform a refresh is a one-time penalty tha
2084 * t must be paid for each group of refreshes. Therefore, performing refres
2085 * hes in a burst reduces the per-refresh penalty of these page closings. H
2086 * igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
2087 * lower numbers decreases the worst-case latency associated with refreshes
2088 * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
2089 * For information on burst refresh feature refer to section 3.9 of DDR2 J
2090 * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
2091 * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
2092 * I cycles using the burst refresh feature. In DDR4 mode, according to Fin
2093 * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
2094 * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
2095 * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
2096 * ure that tRFCmax is not violated due to a PHY-initiated update occurring
2097 * shortly before a refresh burst was due. In this situation, the refresh
2098 * burst will be delayed until the PHY-initiated update is complete.
2099 * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0
2101 * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
2102 * traffic to flow to other banks. Per bank refresh is not supported by all
2103 * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
2104 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
2105 * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0
2107 * Refresh Control Register 0
2108 * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U)
2110 PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U);
2111 /*##################################################################### */
2114 * Register : RFSHCTL1 @ 0XFD070054
2116 * Refresh timer start for rank 1 (only present in multi-rank configuration
2117 * s). This is useful in staggering the refreshes to multiple ranks to help
2118 * traffic to proceed. This is explained in Refresh Controls section of ar
2119 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2120 * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0
2122 * Refresh timer start for rank 0 (only present in multi-rank configuration
2123 * s). This is useful in staggering the refreshes to multiple ranks to help
2124 * traffic to proceed. This is explained in Refresh Controls section of ar
2125 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2126 * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0
2128 * Refresh Control Register 1
2129 * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U)
2131 PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U);
2132 /*##################################################################### */
2135 * Register : RFSHCTL3 @ 0XFD070060
2137 * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
2138 * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
2139 * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
2140 * te: The on-the-fly modes is not supported in this version of the uMCTL2.
2141 * Note: This must be set up while the Controller is in reset or while the
2142 * Controller is in self-refresh mode. Changing this during normal operati
2143 * on is not allowed. Making this a dynamic register will be supported in f
2144 * uture version of the uMCTL2.
2145 * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0
2147 * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
2148 * the refresh register(s) have been updated. The value is automatically up
2149 * dated when exiting reset, so it does not need to be toggled initially.
2150 * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0
2152 * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
2153 * h is disabled, the SoC core must generate refreshes using the registers
2154 * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
2155 * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
2156 * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
2157 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
2158 * isable auto-refresh is not supported, and this bit must be set to '0'. T
2159 * his register field is changeable on the fly.
2160 * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1
2162 * Refresh Control Register 3
2163 * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U)
2165 PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U);
2166 /*##################################################################### */
2169 * Register : RFSHTMG @ 0XFD070064
2171 * tREFI: Average time interval between refreshes per rank (Specification:
2172 * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
2173 * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
2174 * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
2175 * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
2176 * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
2177 * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
2178 * ue is different depending on the refresh mode. The user should program t
2179 * he appropriate value from the spec based on the value programmed in the
2180 * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
2181 * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
2182 * an 0x1. Unit: Multiples of 32 clocks.
2183 * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81
2185 * Used only when LPDDR3 memory type is connected. Should only be changed w
2186 * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
2187 * equired by some LPDDR3 devices which comply with earlier versions of the
2188 * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
2189 * - tREFBW parameter used
2190 * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1
2192 * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
2193 * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
2194 * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
2195 * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
2196 * all-bank refreshes, the tRFCmin value in the above equations is equal to
2197 * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
2198 * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
2199 * equations is different depending on the refresh mode (fixed 1X,2X,4X) an
2200 * d the device density. The user should program the appropriate value from
2201 * the spec based on the 'refresh_mode' and the device density that is use
2203 * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b
2205 * Refresh Timing Register
2206 * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU)
2208 PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU);
2209 /*##################################################################### */
2212 * Register : ECCCFG0 @ 0XFD070070
2214 * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
2216 * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1
2218 * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
2219 * er 1 beat - all other settings are reserved for future use
2220 * PSU_DDRC_ECCCFG0_ECC_MODE 0x0
2222 * ECC Configuration Register 0
2223 * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U)
2225 PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U);
2226 /*##################################################################### */
2229 * Register : ECCCFG1 @ 0XFD070074
2231 * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
2232 * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
2234 * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0
2236 * Enable ECC data poisoning - introduces ECC errors on writes to address s
2237 * pecified by the ECCPOISONADDR0/1 registers
2238 * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0
2240 * ECC Configuration Register 1
2241 * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U)
2243 PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U);
2244 /*##################################################################### */
2247 * Register : CRCPARCTL1 @ 0XFD0700C4
2249 * The maximum number of DFI PHY clock cycles allowed from the assertion of
2250 * the dfi_rddata_en signal to the assertion of each of the corresponding
2251 * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
2252 * parameter tphy_rdlat. Refer to PHY specification for correct value. This
2253 * value it only used for detecting read data timeout when DDR4 retry is e
2254 * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
2255 * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
2256 * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
2257 * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
2258 * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
2259 * rdlat < 'd114 Unit: DFI Clocks
2260 * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10
2262 * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
2263 * re has an option to read the mode registers in the DRAM before the hardw
2264 * are begins the retry process - 1: Wait for software to read/write the mo
2265 * de registers before hardware begins the retry. After software is done wi
2266 * th its operations, it will clear the alert interrupt register bit - 0: H
2267 * ardware can begin the retry right away after the dfi_alert_n pulse goes
2268 * away. The value on this register is valid only when retry is enabled (PA
2269 * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
2270 * he software doesn't clear the interrupt register after handling the pari
2271 * ty/CRC error, then the hardware will not begin the retry process and the
2272 * system will hang. In the case of Parity/CRC error, there are two possib
2273 * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
2274 * t parity' mode register bit is NOT set: the commands sent during retry a
2275 * nd normal operation are executed without parity checking. The value in t
2276 * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
2277 * parity' mode register bit is SET: Parity checking is done for commands s
2278 * ent during retry and normal operation. If multiple errors occur before M
2279 * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
2281 * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1
2283 * - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
2284 * 0: Disable command retry mechanism when C/A Parity or CRC features are
2285 * enabled. Note that retry functionality is not supported if burst chop is
2286 * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
2287 * SHCTL3.dis_auto_refresh = 1)
2288 * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0
2290 * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
2291 * t includes DM signal Present only in designs configured to support DDR4.
2292 * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0
2294 * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
2295 * n of CRC The setting of this register should match the CRC mode register
2296 * setting in the DRAM.
2297 * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0
2299 * C/A Parity enable register - 1: Enable generation of C/A parity and dete
2300 * ction of C/A parity error - 0: Disable generation of C/A parity and disa
2301 * ble detection of C/A parity error If RCD's parity error detection or SDR
2302 * AM's parity detection is enabled, this register should be 1.
2303 * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0
2305 * CRC Parity Control Register1
2306 * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U)
2308 PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U);
2309 /*##################################################################### */
2312 * Register : CRCPARCTL2 @ 0XFD0700C8
2314 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
2315 * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
2316 * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
2317 * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
2318 * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
2319 * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40
2321 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
2322 * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
2323 * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
2324 * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
2325 * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
2326 * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5
2328 * Indicates the maximum duration in number of DRAM clock cycles for which
2329 * a command should be held in the Command Retry FIFO before it is popped o
2330 * ut. Every location in the Command Retry FIFO has an associated down coun
2331 * ting timer that will use this register as the start value. The down coun
2332 * ting starts when a command is loaded into the FIFO. The timer counts dow
2333 * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
2334 * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
2335 * or occurs before the counter reaches zero. The counter is reset to 0, af
2336 * ter all the commands in the FIFO are retried. Recommended(minimum) value
2337 * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
2338 * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
2339 * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
2340 * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
2341 * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
2342 * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
2343 * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
2344 * ) should be considered. Note 3: Use the worst case(longer) value for PHY
2345 * Latencies/Board delay Note 4: The Recommended values are minimum value
2346 * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
2347 * value can be set to this register is defined below: - MEMC_BURST_LENGTH
2348 * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
2349 * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
2350 * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
2351 * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
2352 * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
2353 * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
2354 * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
2355 * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
2356 * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
2357 * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
2358 * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
2359 * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
2361 * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f
2363 * CRC Parity Control Register2
2364 * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
2366 PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU);
2367 /*##################################################################### */
2370 * Register : INIT0 @ 0XFD0700D0
2372 * If lower bit is enabled the SDRAM initialization routine is skipped. The
2373 * upper bit decides what state the controller starts up in when reset is
2374 * removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
2375 * SDRAM Intialization routine is skipped after power-up. Controller starts
2376 * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
2377 * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
2378 * ation routine is run after power-up. Note: The only 2'b00 is supported f
2379 * or LPDDR4 in this version of the uMCTL2.
2380 * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0
2382 * Cycles to wait after driving CKE high to start the SDRAM initialization
2383 * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
2384 * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
2385 * R3 typically requires this to be programmed for a delay of 200 us. LPDDR
2386 * 4 typically requires this to be programmed for a delay of 2 us. For conf
2387 * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
2388 * ded by 2, and round it up to next integer value.
2389 * PSU_DDRC_INIT0_POST_CKE_X1024 0x2
2391 * Cycles to wait after reset before driving CKE high to start the SDRAM in
2392 * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
2393 * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
2394 * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
2395 * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
2396 * 2, and round it up to next integer value.
2397 * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106
2399 * SDRAM Initialization Register 0
2400 * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
2402 PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U);
2403 /*##################################################################### */
2406 * Register : INIT1 @ 0XFD0700D4
2408 * Number of cycles to assert SDRAM reset signal during init sequence. This
2409 * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
2410 * r use with a DDR PHY, this should be set to a minimum of 1
2411 * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2
2413 * Cycles to wait after completing the SDRAM initialization sequence before
2414 * starting the dynamic scheduler. Unit: Counts of a global timer that pul
2415 * ses every 32 clock cycles. There is no known specific requirement for th
2416 * is; it may be set to zero.
2417 * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0
2419 * Wait period before driving the OCD complete command to SDRAM. Unit: Coun
2420 * ts of a global timer that pulses every 32 clock cycles. There is no know
2421 * n specific requirement for this; it may be set to zero.
2422 * PSU_DDRC_INIT1_PRE_OCD_X32 0x0
2424 * SDRAM Initialization Register 1
2425 * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
2427 PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U);
2428 /*##################################################################### */
2431 * Register : INIT2 @ 0XFD0700D8
2433 * Idle time after the reset command, tINIT4. Present only in designs confi
2434 * gured to support LPDDR2. Unit: 32 clock cycles.
2435 * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23
2437 * Time to wait after the first CKE high, tINIT2. Present only in designs c
2438 * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
2439 * ypically requires 5 x tCK delay.
2440 * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5
2442 * SDRAM Initialization Register 2
2443 * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
2445 PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U);
2446 /*##################################################################### */
2449 * Register : INIT3 @ 0XFD0700DC
2451 * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
2452 * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
2453 * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
2454 * DDR3/LPDDR4 - Value to write to MR1 register
2455 * PSU_DDRC_INIT3_MR 0x730
2457 * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
2458 * ng in this register is ignored. The uMCTL2 sets those bits appropriately
2459 * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
2460 * ation mode training is enabled, this bit is set appropriately by the uMC
2461 * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
2462 * LPDDR3/LPDDR4 - Value to write to MR2 register
2463 * PSU_DDRC_INIT3_EMR 0x301
2465 * SDRAM Initialization Register 3
2466 * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U)
2468 PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U);
2469 /*##################################################################### */
2472 * Register : INIT4 @ 0XFD0700E0
2474 * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
2475 * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
2477 * PSU_DDRC_INIT4_EMR2 0x20
2479 * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
2480 * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
2482 * PSU_DDRC_INIT4_EMR3 0x200
2484 * SDRAM Initialization Register 4
2485 * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
2487 PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U);
2488 /*##################################################################### */
2491 * Register : INIT5 @ 0XFD0700E4
2493 * ZQ initial calibration, tZQINIT. Present only in designs configured to s
2494 * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
2495 * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
2497 * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21
2499 * Maximum duration of the auto initialization, tINIT5. Present only in des
2500 * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
2502 * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4
2504 * SDRAM Initialization Register 5
2505 * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
2507 PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U);
2508 /*##################################################################### */
2511 * Register : INIT6 @ 0XFD0700E8
2513 * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
2515 * PSU_DDRC_INIT6_MR4 0x0
2517 * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
2519 * PSU_DDRC_INIT6_MR5 0x6c0
2521 * SDRAM Initialization Register 6
2522 * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
2524 PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U);
2525 /*##################################################################### */
2528 * Register : INIT7 @ 0XFD0700EC
2530 * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
2532 * PSU_DDRC_INIT7_MR6 0x819
2534 * SDRAM Initialization Register 7
2535 * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
2537 PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U);
2538 /*##################################################################### */
2541 * Register : DIMMCTL @ 0XFD0700F0
2543 * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
2544 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
2545 * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
2546 * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
2547 * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0
2549 * Enable for BG1 bit of MRS command. BG1 bit of the mode register address
2550 * is specified as RFU (Reserved for Future Use) and must be programmed to
2551 * 0 during MRS. In case where DRAMs which do not have BG1 are attached and
2552 * both the CA parity and the Output Inversion are enabled, this must be s
2553 * et to 0, so that the calculation of CA parity will not include BG1 bit.
2554 * Note: This has no effect on the address of any other memory accesses, or
2555 * of software-driven mode register accesses. If address mirroring is enab
2556 * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
2557 * abled - 0 - Disabled
2558 * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1
2560 * Enable for A17 bit of MRS command. A17 bit of the mode register address
2561 * is specified as RFU (Reserved for Future Use) and must be programmed to
2562 * 0 during MRS. In case where DRAMs which do not have A17 are attached and
2563 * the Output Inversion are enabled, this must be set to 0, so that the ca
2564 * lculation of CA parity will not include A17 bit. Note: This has no effec
2565 * t on the address of any other memory accesses, or of software-driven mod
2566 * e register accesses. - 1 - Enabled - 0 - Disabled
2567 * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0
2569 * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
2570 * M implements the Output Inversion feature by default, which means that t
2571 * he following address, bank address and bank group bits of B-side DRAMs a
2572 * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
2573 * sures that, for mode register accesses generated by the uMCTL2 during th
2574 * e automatic initialization routine and enabling of a particular DDR4 fea
2575 * ture, separate A-side and B-side mode register accesses are generated. F
2576 * or B-side mode register accesses, these bits are inverted within the uMC
2577 * TL2 to compensate for this RDIMM inversion. Note: This has no effect on
2578 * the address of any other memory accesses, or of software-driven mode reg
2579 * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
2580 * Do not implement output inversion for B-side DRAMs.
2581 * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0
2583 * Address Mirroring Enable (for multi-rank UDIMM implementations and multi
2584 * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
2585 * address mirroring for odd ranks, which means that the following address
2586 * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
2587 * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
2588 * his bit ensures that, for mode register accesses during the automatic in
2589 * itialization routine, these bits are swapped within the uMCTL2 to compen
2590 * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
2591 * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
2592 * e automatic MRS access to enable/disable of a particular DDR4 feature. N
2593 * ote: This has no effect on the address of any other memory accesses, or
2594 * of software-driven mode register accesses. This is not supported for mDD
2595 * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
2596 * output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2597 * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
2598 * ks, implement address mirroring for MRS commands to during initializatio
2599 * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
2600 * lements address mirroring) - 0 - Do not implement address mirroring
2601 * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0
2603 * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
2604 * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
2605 * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
2606 * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
2607 * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
2608 * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
2609 * nds to even and odd ranks seperately - 0 - Do not stagger accesses
2610 * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0
2612 * DIMM Control Register
2613 * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U)
2615 PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U);
2616 /*##################################################################### */
2619 * Register : RANKCTL @ 0XFD0700F4
2621 * Only present for multi-rank configurations. Indicates the number of cloc
2622 * ks of gap in data responses when performing consecutive writes to differ
2623 * ent ranks. This is used to switch the delays in the PHY to match the ran
2624 * k requirements. This value should consider both PHY requirement and ODT
2625 * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
2626 * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
2627 * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
2628 * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
2629 * reased by 1. - ODT requirement: The value programmed in this register ta
2630 * kes care of the ODT switch off timing requirement when switching ranks d
2631 * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
2632 * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
2633 * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
2634 * RATIO=2, program this to the larger value divided by two and round it up
2635 * to the next integer.
2636 * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6
2638 * Only present for multi-rank configurations. Indicates the number of cloc
2639 * ks of gap in data responses when performing consecutive reads to differe
2640 * nt ranks. This is used to switch the delays in the PHY to match the rank
2641 * requirements. This value should consider both PHY requirement and ODT r
2642 * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
2643 * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
2644 * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
2645 * ), should be increased by 1. - ODT requirement: The value programmed in
2646 * this register takes care of the ODT switch off timing requirement when s
2647 * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
2648 * program this to the larger of PHY requirement or ODT requirement. For co
2649 * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
2650 * vided by two and round it up to the next integer.
2651 * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6
2653 * Only present for multi-rank configurations. Background: Reads to the sam
2654 * e rank can be performed back-to-back. Reads to different ranks require a
2655 * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
2656 * to avoid possible data bus contention as well as to give PHY enough tim
2657 * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
2658 * access on a cycle-by-cycle basis; therefore after a read is scheduled,
2659 * there are few clock cycles (determined by the value on RANKCTL.diff_rank
2660 * _rd_gap register) in which only reads from the same rank are eligible to
2661 * be scheduled. This prevents reads from other ranks from having fair acc
2662 * ess to the data bus. This parameter represents the maximum number of rea
2663 * ds that can be scheduled consecutively to the same rank. After this numb
2664 * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
2665 * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
2666 * her numbers increase bandwidth utilization, lower numbers increase fairn
2667 * ess. This feature can be DISABLED by setting this register to 0. When se
2668 * t to 0, the Controller will stay on the same rank as long as commands ar
2669 * e available for it. Minimum programmable value is 0 (feature disabled) a
2670 * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
2671 * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf
2673 * Rank Control Register
2674 * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
2676 PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU);
2677 /*##################################################################### */
2680 * Register : DRAMTMG0 @ 0XFD070100
2682 * Minimum time between write and precharge to same bank. Unit: Clocks Spec
2683 * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
2684 * @400MHz and less for lower frequencies where: - WL = write latency - BL
2685 * = burst length. This must match the value programmed in the BL bit of t
2686 * he mode register to the SDRAM. BST (burst terminate) is not supported at
2687 * present. - tWR = Write recovery time. This comes directly from the SDRA
2688 * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
2689 * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
2690 * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
2691 * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
2692 * p to the next integer value.
2693 * PSU_DDRC_DRAMTMG0_WR2PRE 0x11
2695 * tFAW Valid only when 8 or more banks(or banks x bank groups) are present
2696 * . In 8-bank design, at most 4 banks must be activated in a rolling windo
2697 * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
2698 * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
2699 * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
2701 * PSU_DDRC_DRAMTMG0_T_FAW 0x10
2703 * tRAS(max): Maximum time between activate and precharge to same bank. Thi
2704 * s is the maximum time that a page can be kept open Minimum value of this
2705 * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
2706 * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
2708 * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24
2710 * tRAS(min): Minimum time between activate and precharge to the same bank.
2711 * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
2712 * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
2713 * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
2714 * e next integer value. Unit: Clocks
2715 * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
2717 * SDRAM Timing Register 0
2718 * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U)
2720 PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U);
2721 /*##################################################################### */
2724 * Register : DRAMTMG1 @ 0XFD070104
2726 * tXP: Minimum time after power-down exit to any operation. For DDR3, this
2727 * should be programmed to tXPDLL if slow powerdown exit is selected in MR
2728 * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
2729 * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
2730 * up to the next integer value. Units: Clocks
2731 * PSU_DDRC_DRAMTMG1_T_XP 0x4
2733 * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
2734 * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
2735 * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
2736 * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
2737 * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
2738 * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
2739 * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
2740 * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
2741 * ve value by 2 and round it up to the next integer value. Unit: Clocks.
2742 * PSU_DDRC_DRAMTMG1_RD2PRE 0x4
2744 * tRC: Minimum time between activates to same bank. For configurations wit
2745 * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
2746 * r value. Unit: Clocks.
2747 * PSU_DDRC_DRAMTMG1_T_RC 0x1a
2749 * SDRAM Timing Register 1
2750 * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU)
2752 PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU);
2753 /*##################################################################### */
2756 * Register : DRAMTMG2 @ 0XFD070108
2758 * Set to WL Time from write command to write data on SDRAM interface. This
2759 * must be set to WL. For mDDR, it should normally be set to 1. Note that,
2760 * depending on the PHY, if using RDIMM, it may be necessary to use a valu
2761 * e of WL + 1 to compensate for the extra cycle of latency through the RDI
2762 * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
2763 * d using the above equation by 2, and round it up to next integer. This r
2764 * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
2765 * is set), as the DFI read and write latencies defined in DFITMG0 and DFI
2766 * TMG1 are sufficient for those protocols Unit: clocks
2767 * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7
2769 * Set to RL Time from read command to read data on SDRAM interface. This m
2770 * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
2771 * t be necessary to use a value of RL + 1 to compensate for the extra cycl
2772 * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
2773 * , divide the value calculated using the above equation by 2, and round i
2774 * t up to next integer. This register field is not required for DDR2 and D
2775 * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
2776 * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
2778 * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8
2780 * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
2781 * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
2782 * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
2783 * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
2784 * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
2785 * command. Include time for bus turnaround and all per-bank, per-rank, an
2786 * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
2787 * urst length. This must match the value programmed in the BL bit of the m
2788 * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
2789 * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
2790 * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
2791 * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
2792 * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
2793 * culated using the above equation by 2, and round it up to next integer.
2794 * PSU_DDRC_DRAMTMG2_RD2WR 0x6
2796 * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
2797 * m time from write command to read command for same bank group. In others
2798 * , minimum time from write command to read command. Includes time for bus
2799 * turnaround, recovery times, and all per-bank, per-rank, and global cons
2800 * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
2801 * tency - BL = burst length. This must match the value programmed in the B
2802 * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
2803 * d command delay for same bank group. This comes directly from the SDRAM
2804 * specification. - tWTR = internal write to read command delay. This comes
2805 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
2806 * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
2807 * e the value calculated using the above equation by 2, and round it up to
2809 * PSU_DDRC_DRAMTMG2_WR2RD 0xd
2811 * SDRAM Timing Register 2
2812 * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU)
2814 PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU);
2815 /*##################################################################### */
2818 * Register : DRAMTMG3 @ 0XFD07010C
2820 * Time to wait after a mode register write or read (MRW or MRR). Present o
2821 * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
2822 * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
2823 * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
2824 * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
2825 * , this register is used for the time from a MRW/MRR to a MRW/MRR.
2826 * PSU_DDRC_DRAMTMG3_T_MRW 0x5
2828 * tMRD: Cycles to wait after a mode register write or read. Depending on t
2829 * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
2830 * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
2831 * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
2832 * program this to (tMRD/2) and round it up to the next integer value. If
2833 * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
2834 * PSU_DDRC_DRAMTMG3_T_MRD 0x4
2836 * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
2837 * mand and following non-load mode command. If C/A parity for DDR4 is used
2838 * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
2839 * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
2840 * using RDIMM, depending on the PHY, it may be necessary to use a value of
2841 * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
2842 * pplied to mode register writes by the RDIMM chip.
2843 * PSU_DDRC_DRAMTMG3_T_MOD 0xc
2845 * SDRAM Timing Register 3
2846 * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
2848 PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU);
2849 /*##################################################################### */
2852 * Register : DRAMTMG4 @ 0XFD070110
2854 * tRCD - tAL: Minimum time from activate to read or write command to same
2855 * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
2856 * - tAL)/2) and round it up to the next integer value. Minimum value allow
2857 * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
2858 * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2859 * PSU_DDRC_DRAMTMG4_T_RCD 0x8
2861 * DDR4: tCCD_L: This is the minimum time between two reads or two writes f
2862 * or same bank group. Others: tCCD: This is the minimum time between two r
2863 * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
2864 * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
2866 * PSU_DDRC_DRAMTMG4_T_CCD 0x3
2868 * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
2869 * or same bank group. Others: tRRD: Minimum time between activates from ba
2870 * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
2871 * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
2873 * PSU_DDRC_DRAMTMG4_T_RRD 0x3
2875 * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
2876 * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
2877 * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
2878 * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
2879 * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2880 * PSU_DDRC_DRAMTMG4_T_RP 0x9
2882 * SDRAM Timing Register 4
2883 * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
2885 PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U);
2886 /*##################################################################### */
2889 * Register : DRAMTMG5 @ 0XFD070114
2891 * This is the time before Self Refresh Exit that CK is maintained as a val
2892 * id clock before issuing SRX. Specifies the clock stable time before SRX.
2893 * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
2894 * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
2895 * FREQ_RATIO=2, program this to recommended value divided by two and round
2896 * it up to next integer.
2897 * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6
2899 * This is the time after Self Refresh Down Entry that CK is maintained as
2900 * a valid clock. Specifies the clock disable delay after SRE. Recommended
2901 * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
2902 * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
2903 * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
2904 * o and round it up to next integer.
2905 * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6
2907 * Minimum CKE low width for Self refresh or Self refresh power down entry
2908 * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
2909 * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
2910 * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
2911 * _RATIO=2, program this to recommended value divided by two and round it
2912 * up to next integer.
2913 * PSU_DDRC_DRAMTMG5_T_CKESR 0x4
2915 * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
2916 * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
2917 * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
2918 * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
2919 * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
2920 * round it up to the next integer value. Unit: Clocks.
2921 * PSU_DDRC_DRAMTMG5_T_CKE 0x3
2923 * SDRAM Timing Register 5
2924 * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
2926 PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U);
2927 /*##################################################################### */
2930 * Register : DRAMTMG6 @ 0XFD070118
2932 * This is the time after Deep Power Down Entry that CK is maintained as a
2933 * valid clock. Specifies the clock disable delay after DPDE. Recommended s
2934 * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
2935 * FREQ_RATIO=2, program this to recommended value divided by two and round
2936 * it up to next integer. This is only present for designs supporting mDDR
2937 * or LPDDR2/LPDDR3 devices.
2938 * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1
2940 * This is the time before Deep Power Down Exit that CK is maintained as a
2941 * valid clock before issuing DPDX. Specifies the clock stable time before
2942 * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
2943 * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
2944 * ed by two and round it up to next integer. This is only present for desi
2945 * gns supporting mDDR or LPDDR2 devices.
2946 * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1
2948 * This is the time before Clock Stop Exit that CK is maintained as a valid
2949 * clock before issuing Clock Stop Exit. Specifies the clock stable time b
2950 * efore next command after Clock Stop Exit. Recommended settings: - mDDR:
2951 * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
2952 * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
2953 * two and round it up to next integer. This is only present for designs su
2954 * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2955 * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4
2957 * SDRAM Timing Register 6
2958 * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U)
2960 PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U);
2961 /*##################################################################### */
2964 * Register : DRAMTMG7 @ 0XFD07011C
2966 * This is the time after Power Down Entry that CK is maintained as a valid
2967 * clock. Specifies the clock disable delay after PDE. Recommended setting
2968 * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
2969 * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
2970 * wo and round it up to next integer. This is only present for designs sup
2971 * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2972 * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
2974 * This is the time before Power Down Exit that CK is maintained as a valid
2975 * clock before issuing PDX. Specifies the clock stable time before PDX. R
2976 * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
2977 * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
2978 * divided by two and round it up to next integer. This is only present for
2979 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2980 * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
2982 * SDRAM Timing Register 7
2983 * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U)
2985 PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U);
2986 /*##################################################################### */
2989 * Register : DRAMTMG8 @ 0XFD070120
2991 * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
2992 * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
2993 * to the above value divided by 2 and round up to next integer value. Unit
2994 * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
2995 * mands. Note: Ensure this is less than or equal to t_xs_x32.
2996 * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3
2998 * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
2999 * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
3000 * is to the above value divided by 2 and round up to next integer value. U
3001 * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
3003 * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3
3005 * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
3006 * urations with MEMC_FREQ_RATIO=2, program this to the above value divided
3007 * by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
3008 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
3009 * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd
3011 * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
3012 * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
3013 * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
3014 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
3015 * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6
3017 * SDRAM Timing Register 8
3018 * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U)
3020 PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U);
3021 /*##################################################################### */
3024 * Register : DRAMTMG9 @ 0XFD070124
3026 * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
3027 * nly with MEMC_FREQ_RATIO=2
3028 * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0
3030 * tCCD_S: This is the minimum time between two reads or two writes for dif
3031 * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
3032 * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
3033 * , program this to (tCCD_S/2) and round it up to the next integer value.
3034 * Present only in designs configured to support DDR4. Unit: clocks.
3035 * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2
3037 * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
3038 * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
3039 * is to (tRRD_S/2) and round it up to the next integer value. Present only
3040 * in designs configured to support DDR4. Unit: Clocks.
3041 * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2
3043 * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
3044 * for different bank group. Includes time for bus turnaround, recovery ti
3045 * mes, and all per-bank, per-rank, and global constraints. Present only in
3046 * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
3047 * ite latency - PL = Parity latency - BL = burst length. This must match t
3048 * he value programmed in the BL bit of the mode register to the SDRAM - tW
3049 * TR_S = internal write to read command delay for different bank group. Th
3050 * is comes directly from the SDRAM specification. For configurations with
3051 * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
3052 * by 2, and round it up to next integer.
3053 * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb
3055 * SDRAM Timing Register 9
3056 * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU)
3058 PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU);
3059 /*##################################################################### */
3062 * Register : DRAMTMG11 @ 0XFD07012C
3064 * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
3065 * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
3066 * ) and round it up to the next integer value. Present only in designs con
3067 * figured to support DDR4. Unit: Multiples of 32 clocks.
3068 * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70
3070 * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
3071 * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
3072 * )+1. Present only in designs configured to support DDR4. Unit: clocks.
3073 * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7
3075 * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
3076 * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
3077 * eger value. Present only in designs configured to support DDR4. Unit: Cl
3079 * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1
3081 * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
3082 * n designs configured to support DDR4. Unit: Clocks. For configurations w
3083 * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
3084 * ion by 2, and round it up to next integer.
3085 * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe
3087 * SDRAM Timing Register 11
3088 * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU)
3090 PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU);
3091 /*##################################################################### */
3094 * Register : DRAMTMG12 @ 0XFD070130
3096 * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
3097 * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
3098 * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
3100 * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2
3102 * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
3103 * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
3104 * p to next integer value.
3105 * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6
3107 * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
3108 * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
3109 * and round it up to next integer value.
3110 * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8
3112 * SDRAM Timing Register 12
3113 * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U)
3115 PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U);
3116 /*##################################################################### */
3119 * Register : ZQCTL0 @ 0XFD070180
3121 * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
3122 * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
3123 * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
3124 * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
3125 * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3126 * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1
3128 * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
3129 * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
3130 * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
3131 * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
3132 * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
3133 * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3134 * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0
3136 * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
3137 * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
3138 * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
3139 * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
3140 * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
3142 * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0
3144 * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
3145 * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
3146 * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
3147 * mode. This is only present for designs supporting DDR4 devices.
3148 * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0
3150 * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
3151 * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
3152 * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
3153 * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
3154 * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
3155 * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
3156 * o the next integer value. Unit: Clock cycles. This is only present for d
3157 * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3158 * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100
3160 * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
3161 * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
3162 * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
3163 * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
3164 * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
3165 * DDR3/LPDDR4 devices.
3166 * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40
3168 * ZQ Control Register 0
3169 * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U)
3171 PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U);
3172 /*##################################################################### */
3175 * Register : ZQCTL1 @ 0XFD070184
3177 * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
3178 * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
3179 * RATIO=2, program this to tZQReset/2 and round it up to the next integer
3180 * value. Unit: Clock cycles. This is only present for designs supporting L
3181 * PDDR2/LPDDR3/LPDDR4 devices.
3182 * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20
3184 * Average interval to wait between automatically issuing ZQCS (ZQ calibrat
3185 * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
3186 * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
3187 * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
3189 * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc
3191 * ZQ Control Register 1
3192 * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU)
3194 PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU);
3195 /*##################################################################### */
3198 * Register : DFITMG0 @ 0XFD070190
3200 * Specifies the number of DFI clock cycles after an assertion or de-assert
3201 * ion of the DFI control signals that the control signals at the PHY-DRAM
3202 * interface reflect the assertion or de-assertion. If the DFI clock and th
3203 * e memory clock are not phase-aligned, this timing parameter should be ro
3204 * unded up to the next integer value. Note that if using RDIMM, it is nece
3205 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
3206 * erms of DFI clock.
3207 * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4
3209 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
3210 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
3211 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
3212 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
3214 * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1
3216 * Time from the assertion of a read command on the DFI interface to the as
3217 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
3218 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
3219 * depending on the PHY, if using RDIMM, it may be necessary to use the val
3220 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
3221 * the extra cycle of latency through the RDIMM. Unit: Clocks
3222 * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb
3224 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
3225 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
3226 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
3227 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
3228 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
3229 * n for correct value.
3230 * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1
3232 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
3233 * ted to when the associated write data is driven on the dfi_wrdata signal
3234 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
3235 * specification for correct value. Note, max supported value is 8. Unit:
3237 * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2
3239 * Write latency Number of clocks from the write command to write data enab
3240 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
3241 * lat. Refer to PHY specification for correct value.Note that, depending o
3242 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
3243 * in the calculation of tphy_wrlat. This is to compensate for the extra c
3244 * ycle of latency through the RDIMM.
3245 * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb
3247 * DFI Timing Register 0
3248 * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
3250 PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU);
3251 /*##################################################################### */
3254 * Register : DFITMG1 @ 0XFD070194
3256 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
3257 * asserted and when the associated command is driven. This field is used
3258 * for CAL mode, should be set to '0' or the value which matches the CAL mo
3259 * de register setting in the DRAM. If the PHY can add the latency for CAL
3260 * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
3261 * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0
3263 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
3264 * asserted and when the associated dfi_parity_in signal is driven.
3265 * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0
3267 * Specifies the number of DFI clocks between when the dfi_wrdata_en signal
3268 * is asserted and when the corresponding write data transfer is completed
3269 * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
3270 * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
3271 * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
3272 * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
3273 * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
3274 * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
3275 * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
3276 * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3
3278 * Specifies the number of DFI clock cycles from the assertion of the dfi_d
3279 * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
3280 * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
3281 * and the memory clock are not phase aligned, this timing parameter should
3282 * be rounded up to the next integer value.
3283 * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3
3285 * Specifies the number of DFI clock cycles from the de-assertion of the df
3286 * i_dram_clk_disable signal on the DFI until the first valid rising edge o
3287 * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
3288 * DFI clock and the memory clock are not phase aligned, this timing param
3289 * eter should be rounded up to the next integer value.
3290 * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4
3292 * DFI Timing Register 1
3293 * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U)
3295 PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U);
3296 /*##################################################################### */
3299 * Register : DFILPCFG0 @ 0XFD070198
3301 * Setting for DFI's tlp_resp time. Same value is used for both Power Down,
3302 * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
3303 * pecification onwards, recommends using a fixed value of 7 always.
3304 * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7
3306 * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
3307 * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
3308 * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
3309 * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
3310 * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
3311 * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
3312 * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
3314 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0
3316 * Enables DFI Low Power interface handshaking during Deep Power Down Entry
3317 * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
3318 * porting mDDR or LPDDR2/LPDDR3 devices.
3319 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0
3321 * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
3322 * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
3323 * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
3324 * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
3325 * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
3326 * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3327 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0
3329 * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
3330 * it. - 0 - Disabled - 1 - Enabled
3331 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1
3333 * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
3334 * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
3335 * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
3336 * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
3337 * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
3338 * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3339 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
3341 * Enables DFI Low Power interface handshaking during Power Down Entry/Exit
3342 * . - 0 - Disabled - 1 - Enabled
3343 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
3345 * DFI Low Power Configuration Register 0
3346 * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
3348 PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U);
3349 /*##################################################################### */
3352 * Register : DFILPCFG1 @ 0XFD07019C
3354 * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
3355 * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
3356 * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
3357 * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
3358 * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
3359 * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
3360 * ted This is only present for designs supporting DDR4 devices.
3361 * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2
3363 * Enables DFI Low Power interface handshaking during Maximum Power Saving
3364 * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
3365 * esigns supporting DDR4 devices.
3366 * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1
3368 * DFI Low Power Configuration Register 1
3369 * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U)
3371 PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U);
3372 /*##################################################################### */
3375 * Register : DFIUPD0 @ 0XFD0701A0
3377 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
3378 * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
3379 * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
3380 * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0
3382 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
3383 * following a self-refresh exit. The core must issue the dfi_ctrlupd_req
3384 * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
3385 * rlupd_req after exiting self-refresh.
3386 * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0
3388 * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
3389 * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
3391 * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40
3393 * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
3394 * gnal must be asserted. The uMCTL2 expects the PHY to respond within this
3395 * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
3396 * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
3397 * variable is 0x3. Unit: Clocks
3398 * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3
3400 * DFI Update Register 0
3401 * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U)
3403 PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U);
3404 /*##################################################################### */
3407 * Register : DFIUPD1 @ 0XFD0701A4
3409 * This is the minimum amount of time between uMCTL2 initiated DFI update r
3410 * equests (which is executed whenever the uMCTL2 is idle). Set this number
3411 * higher to reduce the frequency of update requests, which can have a sma
3412 * ll impact on the latency of the first read request when the uMCTL2 is id
3413 * le. Unit: 1024 clocks
3414 * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41
3416 * This is the maximum amount of time between uMCTL2 initiated DFI update r
3417 * equests. This timer resets with each update request; when the timer expi
3418 * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
3419 * _ackx is received. PHY can use this idle time to recalibrate the delay l
3420 * ines to the DLLs. The DFI controller update is also used to reset PHY FI
3421 * FO pointers in case of data capture errors. Updates are required to main
3422 * tain calibration over PVT, but frequent updates may impact performance.
3423 * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
3424 * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
3426 * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1
3428 * DFI Update Register 1
3429 * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U)
3431 PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U);
3432 /*##################################################################### */
3435 * Register : DFIMISC @ 0XFD0701B0
3437 * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
3438 * s are active low - 1: Signals are active high
3439 * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0
3441 * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
3442 * - 1 - PHY implements DBI functionality. Present only in designs configu
3443 * red to support DDR4 and LPDDR4.
3444 * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0
3446 * PHY initialization complete enable signal. When asserted the dfi_init_co
3447 * mplete signal can be used to trigger SDRAM initialisation
3448 * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0
3450 * DFI Miscellaneous Control Register
3451 * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U)
3453 PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U);
3454 /*##################################################################### */
3457 * Register : DFITMG2 @ 0XFD0701B4
3459 * >Number of clocks between when a read command is sent on the DFI control
3460 * interface and when the associated dfi_rddata_cs signal is asserted. Thi
3461 * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
3462 * cification for correct value.
3463 * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9
3465 * Number of clocks between when a write command is sent on the DFI control
3466 * interface and when the associated dfi_wrdata_cs signal is asserted. Thi
3467 * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
3468 * cification for correct value.
3469 * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6
3471 * DFI Timing Register 2
3472 * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U)
3474 PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U);
3475 /*##################################################################### */
3478 * Register : DBICTL @ 0XFD0701C0
3480 * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
3481 * BI is enabled. This signal must be set the same value as DRAM's mode reg
3482 * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
3483 * e set to 0. - LPDDR4: MR3[6]
3484 * PSU_DDRC_DBICTL_RD_DBI_EN 0x0
3486 * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
3487 * e DBI is enabled. This signal must be set the same value as DRAM's mode
3488 * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
3489 * t be set to 0. - LPDDR4: MR3[7]
3490 * PSU_DDRC_DBICTL_WR_DBI_EN 0x0
3492 * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
3493 * s signal must be set the same logical value as DRAM's mode register. - D
3494 * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
3495 * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
3496 * [5] which is opposite polarity from this signal
3497 * PSU_DDRC_DBICTL_DM_EN 0x1
3499 * DM/DBI Control Register
3500 * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U)
3502 PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U);
3503 /*##################################################################### */
3506 * Register : ADDRMAP0 @ 0XFD070200
3508 * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
3509 * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
3510 * by adding the internal base to the value of this field. If set to 31, r
3511 * ank address bit 0 is set to 0.
3512 * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f
3514 * Address Map Register 0
3515 * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU)
3517 PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU);
3518 /*##################################################################### */
3521 * Register : ADDRMAP1 @ 0XFD070204
3523 * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
3524 * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
3525 * by adding the internal base to the value of this field. If set to 31, ba
3526 * nk address bit 2 is set to 0.
3527 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f
3529 * Selects the HIF address bits used as bank address bit 1. Valid Range: 0
3530 * to 30 Internal Base: 3 The selected HIF address bit for each of the bank
3531 * address bits is determined by adding the internal base to the value of
3533 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa
3535 * Selects the HIF address bits used as bank address bit 0. Valid Range: 0
3536 * to 30 Internal Base: 2 The selected HIF address bit for each of the bank
3537 * address bits is determined by adding the internal base to the value of
3539 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa
3541 * Address Map Register 1
3542 * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
3544 PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU);
3545 /*##################################################################### */
3548 * Register : ADDRMAP2 @ 0XFD070208
3550 * - Full bus width mode: Selects the HIF address bit used as column addres
3551 * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
3552 * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
3553 * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
3554 * : 5 The selected HIF address bit is determined by adding the internal ba
3555 * se to the value of this field. If set to 15, this column address bit is
3557 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
3559 * - Full bus width mode: Selects the HIF address bit used as column addres
3560 * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
3561 * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
3562 * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
3563 * 4 The selected HIF address bit is determined by adding the internal bas
3564 * e to the value of this field. If set to 15, this column address bit is s
3566 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
3568 * - Full bus width mode: Selects the HIF address bit used as column addres
3569 * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
3570 * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
3571 * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
3572 * elected HIF address bit is determined by adding the internal base to the
3573 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
3574 * 6, it is required to program this to 0, hence register does not exist in
3576 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
3578 * - Full bus width mode: Selects the HIF address bit used as column addres
3579 * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
3580 * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
3581 * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
3582 * elected HIF address bit is determined by adding the internal base to the
3583 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
3584 * or 16, it is required to program this to 0.
3585 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
3587 * Address Map Register 2
3588 * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
3590 PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U);
3591 /*##################################################################### */
3594 * Register : ADDRMAP3 @ 0XFD07020C
3596 * - Full bus width mode: Selects the HIF address bit used as column addres
3597 * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
3598 * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
3599 * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
3600 * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
3601 * HIF address bit is determined by adding the internal base to the value o
3602 * f this field. If set to 15, this column address bit is set to 0. Note: P
3603 * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
3604 * r indicating auto-precharge, and hence no source address bit can be mapp
3605 * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
3606 * for auto-precharge in the CA bus and hence column bit 10 is used.
3607 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0
3609 * - Full bus width mode: Selects the HIF address bit used as column addres
3610 * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
3611 * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
3612 * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
3613 * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
3614 * d by adding the internal base to the value of this field. If set to 15,
3615 * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
3616 * cation, column address bit 10 is reserved for indicating auto-precharge,
3617 * and hence no source address bit can be mapped to column address bit 10.
3618 * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
3619 * bus and hence column bit 10 is used.
3620 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0
3622 * - Full bus width mode: Selects the HIF address bit used as column addres
3623 * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
3624 * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
3625 * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
3626 * 7 The selected HIF address bit is determined by adding the internal bas
3627 * e to the value of this field. If set to 15, this column address bit is s
3629 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0
3631 * - Full bus width mode: Selects the HIF address bit used as column addres
3632 * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
3633 * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
3634 * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
3635 * 6 The selected HIF address bit is determined by adding the internal bas
3636 * e to the value of this field. If set to 15, this column address bit is s
3638 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0
3640 * Address Map Register 3
3641 * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
3643 PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U);
3644 /*##################################################################### */
3647 * Register : ADDRMAP4 @ 0XFD070210
3649 * - Full bus width mode: Selects the HIF address bit used as column addres
3650 * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
3651 * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
3652 * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
3653 * and 15 Internal Base: 11 The selected HIF address bit is determined by
3654 * adding the internal base to the value of this field. If set to 15, this
3655 * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
3656 * n, column address bit 10 is reserved for indicating auto-precharge, and
3657 * hence no source address bit can be mapped to column address bit 10. In L
3658 * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
3659 * and hence column bit 10 is used.
3660 * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf
3662 * - Full bus width mode: Selects the HIF address bit used as column addres
3663 * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
3664 * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
3665 * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
3666 * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
3667 * address bit is determined by adding the internal base to the value of t
3668 * his field. If set to 15, this column address bit is set to 0. Note: Per
3669 * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
3670 * ndicating auto-precharge, and hence no source address bit can be mapped
3671 * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
3672 * auto-precharge in the CA bus and hence column bit 10 is used.
3673 * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf
3675 * Address Map Register 4
3676 * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU)
3678 PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU);
3679 /*##################################################################### */
3682 * Register : ADDRMAP5 @ 0XFD070214
3684 * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
3685 * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
3686 * d by adding the internal base to the value of this field. If set to 15,
3687 * row address bit 11 is set to 0.
3688 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8
3690 * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
3691 * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
3692 * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
3693 * w address bit 10) The selected HIF address bit for each of the row addre
3694 * ss bits is determined by adding the internal base to the value of this f
3695 * ield. When value 15 is used the values of row address bits 2 to 10 are d
3696 * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
3697 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf
3699 * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
3700 * o 11 Internal Base: 7 The selected HIF address bit for each of the row a
3701 * ddress bits is determined by adding the internal base to the value of th
3703 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8
3705 * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
3706 * o 11 Internal Base: 6 The selected HIF address bit for each of the row a
3707 * ddress bits is determined by adding the internal base to the value of th
3709 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8
3711 * Address Map Register 5
3712 * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
3714 PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U);
3715 /*##################################################################### */
3718 * Register : ADDRMAP6 @ 0XFD070218
3720 * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
3721 * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
3722 * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
3723 * All addresses are valid Present only in designs configured to support L
3725 * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0
3727 * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
3728 * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
3729 * d by adding the internal base to the value of this field. If set to 15,
3730 * row address bit 15 is set to 0.
3731 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf
3733 * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
3734 * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
3735 * d by adding the internal base to the value of this field. If set to 15,
3736 * row address bit 14 is set to 0.
3737 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8
3739 * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
3740 * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
3741 * d by adding the internal base to the value of this field. If set to 15,
3742 * row address bit 13 is set to 0.
3743 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8
3745 * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
3746 * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
3747 * d by adding the internal base to the value of this field. If set to 15,
3748 * row address bit 12 is set to 0.
3749 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8
3751 * Address Map Register 6
3752 * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
3754 PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U);
3755 /*##################################################################### */
3758 * Register : ADDRMAP7 @ 0XFD07021C
3760 * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
3761 * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
3762 * d by adding the internal base to the value of this field. If set to 15,
3763 * row address bit 17 is set to 0.
3764 * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf
3766 * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
3767 * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
3768 * d by adding the internal base to the value of this field. If set to 15,
3769 * row address bit 16 is set to 0.
3770 * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf
3772 * Address Map Register 7
3773 * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
3775 PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU);
3776 /*##################################################################### */
3779 * Register : ADDRMAP8 @ 0XFD070220
3781 * Selects the HIF address bits used as bank group address bit 1. Valid Ran
3782 * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
3783 * ch of the bank group address bits is determined by adding the internal b
3784 * ase to the value of this field. If set to 31, bank group address bit 1 i
3786 * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8
3788 * Selects the HIF address bits used as bank group address bit 0. Valid Ran
3789 * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
3790 * e bank group address bits is determined by adding the internal base to t
3791 * he value of this field.
3792 * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8
3794 * Address Map Register 8
3795 * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U)
3797 PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U);
3798 /*##################################################################### */
3801 * Register : ADDRMAP9 @ 0XFD070224
3803 * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
3804 * o 11 Internal Base: 11 The selected HIF address bit for each of the row
3805 * address bits is determined by adding the internal base to the value of t
3806 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3807 * _10 is set to value 15.
3808 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8
3810 * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
3811 * o 11 Internal Base: 10 The selected HIF address bit for each of the row
3812 * address bits is determined by adding the internal base to the value of t
3813 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3814 * _10 is set to value 15.
3815 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8
3817 * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
3818 * o 11 Internal Base: 9 The selected HIF address bit for each of the row a
3819 * ddress bits is determined by adding the internal base to the value of th
3820 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3821 * 10 is set to value 15.
3822 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8
3824 * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
3825 * o 11 Internal Base: 8 The selected HIF address bit for each of the row a
3826 * ddress bits is determined by adding the internal base to the value of th
3827 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3828 * 10 is set to value 15.
3829 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8
3831 * Address Map Register 9
3832 * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
3834 PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U);
3835 /*##################################################################### */
3838 * Register : ADDRMAP10 @ 0XFD070228
3840 * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
3841 * o 11 Internal Base: 15 The selected HIF address bit for each of the row
3842 * address bits is determined by adding the internal base to the value of t
3843 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3844 * _10 is set to value 15.
3845 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8
3847 * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
3848 * o 11 Internal Base: 14 The selected HIF address bit for each of the row
3849 * address bits is determined by adding the internal base to the value of t
3850 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3851 * _10 is set to value 15.
3852 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8
3854 * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
3855 * o 11 Internal Base: 13 The selected HIF address bit for each of the row
3856 * address bits is determined by adding the internal base to the value of t
3857 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3858 * _10 is set to value 15.
3859 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8
3861 * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
3862 * o 11 Internal Base: 12 The selected HIF address bit for each of the row
3863 * address bits is determined by adding the internal base to the value of t
3864 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3865 * _10 is set to value 15.
3866 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8
3868 * Address Map Register 10
3869 * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
3871 PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U);
3872 /*##################################################################### */
3875 * Register : ADDRMAP11 @ 0XFD07022C
3877 * Selects the HIF address bits used as row address bit 10. Valid Range: 0
3878 * to 11 Internal Base: 16 The selected HIF address bit for each of the row
3879 * address bits is determined by adding the internal base to the value of
3880 * this field. This register field is used only when ADDRMAP5.addrmap_row_b
3881 * 2_10 is set to value 15.
3882 * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8
3884 * Address Map Register 11
3885 * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U)
3887 PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U);
3888 /*##################################################################### */
3891 * Register : ODTCFG @ 0XFD070240
3893 * Cycles to hold ODT for a write command. The minimum supported value is 2
3894 * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
3895 * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
3896 * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
3897 * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
3898 * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
3899 * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6
3901 * The delay, in clock cycles, from issuing a write command to setting ODT
3902 * values associated with that command. ODT setting must remain constant fo
3903 * r the entire time that DQS is driven by the uMCTL2. Recommended values:
3904 * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
3905 * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
3906 * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
3907 * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
3908 * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0
3910 * Cycles to hold ODT for a read command. The minimum supported value is 2.
3911 * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
3912 * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
3913 * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
3914 * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
3915 * RU(tODTon(max)/tCK)
3916 * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6
3918 * The delay, in clock cycles, from issuing a read command to setting ODT v
3919 * alues associated with that command. ODT setting must remain constant for
3920 * the entire time that DQS is driven by the uMCTL2. Recommended values: D
3921 * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
3922 * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
3923 * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
3924 * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
3925 * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
3926 * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
3927 * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
3928 * U(tODTon(max)/tCK)
3929 * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0
3931 * ODT Configuration Register
3932 * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
3934 PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U);
3935 /*##################################################################### */
3938 * Register : ODTMAP @ 0XFD070244
3940 * Indicates which remote ODTs must be turned on during a read from rank 1.
3941 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3942 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3943 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
3944 * 1 to enable its ODT. Present only in configurations that have 2 or more
3946 * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0
3948 * Indicates which remote ODTs must be turned on during a write to rank 1.
3949 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3950 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3951 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3952 * to enable its ODT. Present only in configurations that have 2 or more r
3954 * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0
3956 * Indicates which remote ODTs must be turned on during a read from rank 0.
3957 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3958 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3959 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
3960 * 1 to enable its ODT.
3961 * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0
3963 * Indicates which remote ODTs must be turned on during a write to rank 0.
3964 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3965 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3966 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3967 * to enable its ODT.
3968 * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1
3970 * ODT/Rank Map Register
3971 * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U)
3973 PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U);
3974 /*##################################################################### */
3977 * Register : SCHED @ 0XFD070250
3979 * When the preferred transaction store is empty for these many clock cycle
3980 * s, switch to the alternate transaction store if it is non-empty. The rea
3981 * d transaction store (both high and low priority) is the default preferre
3982 * d transaction store and the write transaction store is the alternative s
3983 * tore. When prefer write over read is set this is reversed. 0x0 is a lega
3984 * l value for this register. When set to 0x0, the transaction store switch
3985 * ing will happen immediately when the switching conditions become true. F
3986 * OR PERFORMANCE ONLY
3987 * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1
3990 * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0
3992 * Number of entries in the low priority transaction store is this value +
3993 * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
3994 * ries available for the high priority transaction store. Setting this to
3995 * maximum value allocates all entries to low priority transaction store. S
3996 * etting this to 0 allocates 1 entry to low priority transaction store and
3997 * the rest to high priority transaction store. Note: In ECC configuration
3998 * s, the numbers of write and low priority read credits issued is one less
3999 * than in the non-ECC case. One entry each is reserved in the write and l
4000 * ow-priority read CAMs for storing the RMW requests arising out of single
4001 * bit error correction RMW operation.
4002 * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20
4004 * If true, bank is kept open only while there are page hit transactions av
4005 * ailable in the CAM to that bank. The last read or write command in the C
4006 * AM with a bank and page hit will be executed with auto-precharge if SCHE
4007 * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
4008 * e_timer is set to 0, explicit precharge (and not auto-precharge) may be
4009 * issued in some cases where there is a mode switch between Write and Read
4010 * or between LPR and HPR. The Read and Write commands that are executed a
4011 * s part of the ECC scrub requests are also executed without auto-precharg
4012 * e. If false, the bank remains open until there is a need to close it (to
4013 * open a different page, or for page timeout or refresh timeout) - also k
4014 * nown as open page policy. The open page policy can be overridden by sett
4015 * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
4016 * The pageclose feature provids a midway between Open and Close page polic
4017 * ies. FOR PERFORMANCE ONLY.
4018 * PSU_DDRC_SCHED_PAGECLOSE 0x0
4020 * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
4021 * PSU_DDRC_SCHED_PREFER_WRITE 0x0
4023 * Active low signal. When asserted ('0'), all incoming transactions are fo
4024 * rced to low priority. This implies that all High Priority Read (HPR) and
4025 * Variable Priority Read commands (VPR) will be treated as Low Priority R
4026 * ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
4027 * commands will be treated as Normal Priority Write (NPW) commands. Forci
4028 * ng the incoming transactions to low priority implicitly turns off Bypass
4029 * path for read commands. FOR PERFORMANCE ONLY.
4030 * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1
4032 * Scheduler Control Register
4033 * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U)
4035 PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U);
4036 /*##################################################################### */
4039 * Register : PERFLPR1 @ 0XFD070264
4041 * Number of transactions that are serviced once the LPR queue goes critica
4042 * l is the smaller of: - (a) This number - (b) Number of transactions avai
4043 * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
4044 * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8
4046 * Number of clocks that the LPR queue can be starved before it goes critic
4047 * al. The minimum valid functional value for this register is 0x1. Program
4048 * ming it to 0x0 will disable the starvation functionality; during normal
4049 * operation, this function should not be disabled as it will cause excessi
4050 * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4051 * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40
4053 * Low Priority Read CAM Register 1
4054 * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U)
4056 PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U);
4057 /*##################################################################### */
4060 * Register : PERFWR1 @ 0XFD07026C
4062 * Number of transactions that are serviced once the WR queue goes critical
4063 * is the smaller of: - (a) This number - (b) Number of transactions avail
4064 * able. Unit: Transaction. FOR PERFORMANCE ONLY.
4065 * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8
4067 * Number of clocks that the WR queue can be starved before it goes critica
4068 * l. The minimum valid functional value for this register is 0x1. Programm
4069 * ing it to 0x0 will disable the starvation functionality; during normal o
4070 * peration, this function should not be disabled as it will cause excessiv
4071 * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4072 * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40
4074 * Write CAM Register 1
4075 * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U)
4077 PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U);
4078 /*##################################################################### */
4081 * Register : DQMAP0 @ 0XFD070280
4083 * DQ nibble map for DQ bits [12-15] Present only in designs configured to
4085 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0
4087 * DQ nibble map for DQ bits [8-11] Present only in designs configured to s
4089 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0
4091 * DQ nibble map for DQ bits [4-7] Present only in designs configured to su
4093 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0
4095 * DQ nibble map for DQ bits [0-3] Present only in designs configured to su
4097 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0
4100 * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U)
4102 PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4103 /*##################################################################### */
4106 * Register : DQMAP1 @ 0XFD070284
4108 * DQ nibble map for DQ bits [28-31] Present only in designs configured to
4110 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0
4112 * DQ nibble map for DQ bits [24-27] Present only in designs configured to
4114 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0
4116 * DQ nibble map for DQ bits [20-23] Present only in designs configured to
4118 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0
4120 * DQ nibble map for DQ bits [16-19] Present only in designs configured to
4122 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0
4125 * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U)
4127 PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4128 /*##################################################################### */
4131 * Register : DQMAP2 @ 0XFD070288
4133 * DQ nibble map for DQ bits [44-47] Present only in designs configured to
4135 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0
4137 * DQ nibble map for DQ bits [40-43] Present only in designs configured to
4139 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0
4141 * DQ nibble map for DQ bits [36-39] Present only in designs configured to
4143 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0
4145 * DQ nibble map for DQ bits [32-35] Present only in designs configured to
4147 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0
4150 * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U)
4152 PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4153 /*##################################################################### */
4156 * Register : DQMAP3 @ 0XFD07028C
4158 * DQ nibble map for DQ bits [60-63] Present only in designs configured to
4160 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0
4162 * DQ nibble map for DQ bits [56-59] Present only in designs configured to
4164 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0
4166 * DQ nibble map for DQ bits [52-55] Present only in designs configured to
4168 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0
4170 * DQ nibble map for DQ bits [48-51] Present only in designs configured to
4172 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0
4175 * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U)
4177 PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4178 /*##################################################################### */
4181 * Register : DQMAP4 @ 0XFD070290
4183 * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
4184 * igured to support DDR4.
4185 * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0
4187 * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
4188 * igured to support DDR4.
4189 * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0
4192 * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U)
4194 PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U);
4195 /*##################################################################### */
4198 * Register : DQMAP5 @ 0XFD070294
4200 * All even ranks have the same DQ mapping controled by DQMAP0-4 register a
4201 * s rank 0. This register provides DQ swap function for all odd ranks to s
4202 * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
4203 * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
4204 * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
4205 * configured to support DDR4.
4206 * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1
4209 * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U)
4211 PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U);
4212 /*##################################################################### */
4215 * Register : DBG0 @ 0XFD070300
4217 * When this is set to '0', auto-precharge is disabled for the flushed comm
4218 * and in a collision case. Collision cases are write followed by read to s
4219 * ame address, read followed by write to same address, or write followed b
4220 * y write to same address with DBG0.dis_wc bit = 1 (where same address com
4221 * parisons exclude the two address bits representing critical word). FOR D
4223 * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0
4225 * When 1, disable write combine. FOR DEBUG ONLY
4226 * PSU_DDRC_DBG0_DIS_WC 0x0
4229 * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U)
4231 PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U);
4232 /*##################################################################### */
4235 * Register : DBGCMD @ 0XFD07030C
4237 * Setting this register bit to 1 allows refresh and ZQCS commands to be tr
4238 * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
4239 * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
4240 * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
4241 * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
4242 * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
4243 * function, and are ignored by the uMCTL2 logic. This register is static,
4244 * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
4246 * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0
4248 * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
4249 * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
4250 * is automatically cleared. This operation must only be performed when DF
4251 * IUPD0.dis_auto_ctrlupd=1.
4252 * PSU_DDRC_DBGCMD_CTRLUPD 0x0
4254 * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
4255 * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
4256 * s request is stored in the uMCTL2, the bit is automatically cleared. Thi
4257 * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
4258 * mended NOT to set this register bit if in Init operating mode. This regi
4259 * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
4260 * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
4262 * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0
4264 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
4265 * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
4266 * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
4267 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
4268 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
4269 * t or Deep power-down operating modes or Maximum Power Saving Mode.
4270 * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0
4272 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
4273 * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
4274 * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
4275 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
4276 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
4277 * t or Deep power-down operating modes or Maximum Power Saving Mode.
4278 * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0
4280 * Command Debug Register
4281 * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U)
4283 PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U);
4284 /*##################################################################### */
4287 * Register : SWCTL @ 0XFD070320
4289 * Enable quasi-dynamic register programming outside reset. Program registe
4290 * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
4291 * programming is done.
4292 * PSU_DDRC_SWCTL_SW_DONE 0x0
4294 * Software register programming control enable
4295 * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U)
4297 PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U);
4298 /*##################################################################### */
4301 * Register : PCCFG @ 0XFD070400
4303 * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
4304 * s every AXI burst into multiple HIF commands, using the memory burst len
4305 * gth as a unit. If set to 1, then XPI will use half of the memory burst l
4306 * ength as a unit. This applies to both reads and writes. When MSTR.data_b
4307 * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
4308 * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
4309 * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
4310 * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
4311 * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
4312 * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
4313 * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
4314 * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
4315 * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
4316 * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
4318 * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0
4320 * Page match four limit. If set to 1, limits the number of consecutive sam
4321 * e page DDRC transactions that can be granted by the Port Arbiter to four
4322 * when Page Match feature is enabled. If set to 0, there is no limit impo
4323 * sed on number of consecutive same page DDRC transactions.
4324 * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0
4326 * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
4327 * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
4328 * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
4329 * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
4330 * t DDRC are driven to 1b'0.
4331 * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1
4333 * Port Common Configuration Register
4334 * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U)
4336 PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U);
4337 /*##################################################################### */
4340 * Register : PCFGR_0 @ 0XFD070404
4342 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4343 * ng port is granted, the port is continued to be granted if the following
4344 * immediate commands are to the same memory page (same bank and same row)
4345 * . See also related PCCFG.pagematch_limit register.
4346 * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0
4348 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4349 * bled and arurgent is asserted by the master, that port becomes the highe
4350 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4351 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4352 * urgent signal can be asserted anytime and as long as required which is i
4353 * ndependent of address handshaking (it is not associated with any particu
4355 * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1
4357 * If set to 1, enables aging function for the read channel of the port.
4358 * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0
4360 * Determines the initial load value of read aging counters. These counters
4361 * will be parallel loaded after reset, or after each grant to the corresp
4362 * onding port. The aging counters down-count every clock cycle where the p
4363 * ort is requesting but not granted. The higher significant 5-bits of the
4364 * read aging counter sets the priority of the read channel of a given port
4365 * . Port's priority will increase as the higher significant 5-bits of the
4366 * counter starts to decrease. When the aging counter becomes 0, the corres
4367 * ponding port channel will have the highest priority level (timeout condi
4368 * tion - Priority0). For multi-port configurations, the aging counters can
4369 * not be used to set port priorities when external dynamic priority inputs
4370 * (arqos) are enabled (timeout is still applicable). For single port conf
4371 * igurations, the aging counters are only used when they timeout (become 0
4372 * ) to force read-write direction switching. In this case, external dynami
4373 * c priority input, arqos (for reads only) can still be used to set the DD
4374 * RC read priority (2 priority levels: low priority read - LPR, high prior
4375 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4376 * s register field are tied internally to 2'b00.
4377 * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf
4379 * Port n Configuration Read Register
4380 * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU)
4382 PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU);
4383 /*##################################################################### */
4386 * Register : PCFGW_0 @ 0XFD070408
4388 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4389 * ng port is granted, the port is continued to be granted if the following
4390 * immediate commands are to the same memory page (same bank and same row)
4391 * . See also related PCCFG.pagematch_limit register.
4392 * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0
4394 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4395 * bled and awurgent is asserted by the master, that port becomes the highe
4396 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4397 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4398 * serted anytime and as long as required which is independent of address h
4399 * andshaking (it is not associated with any particular command).
4400 * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1
4402 * If set to 1, enables aging function for the write channel of the port.
4403 * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0
4405 * Determines the initial load value of write aging counters. These counter
4406 * s will be parallel loaded after reset, or after each grant to the corres
4407 * ponding port. The aging counters down-count every clock cycle where the
4408 * port is requesting but not granted. The higher significant 5-bits of the
4409 * write aging counter sets the initial priority of the write channel of a
4410 * given port. Port's priority will increase as the higher significant 5-b
4411 * its of the counter starts to decrease. When the aging counter becomes 0,
4412 * the corresponding port channel will have the highest priority level. Fo
4413 * r multi-port configurations, the aging counters cannot be used to set po
4414 * rt priorities when external dynamic priority inputs (awqos) are enabled
4415 * (timeout is still applicable). For single port configurations, the aging
4416 * counters are only used when they timeout (become 0) to force read-write
4417 * direction switching. Note: The two LSBs of this register field are tied
4418 * internally to 2'b00.
4419 * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf
4421 * Port n Configuration Write Register
4422 * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU)
4424 PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU);
4425 /*##################################################################### */
4428 * Register : PCTRL_0 @ 0XFD070490
4431 * PSU_DDRC_PCTRL_0_PORT_EN 0x1
4433 * Port n Control Register
4434 * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U)
4436 PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U);
4437 /*##################################################################### */
4440 * Register : PCFGQOS0_0 @ 0XFD070494
4442 * This bitfield indicates the traffic class of region 1. Valid values are:
4443 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4444 * maps to the blue address queue. In this case, valid values are 0: LPR a
4445 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4446 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4448 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2
4450 * This bitfield indicates the traffic class of region 0. Valid values are:
4451 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4452 * maps to the blue address queue. In this case, valid values are: 0: LPR
4453 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4454 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4456 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0
4458 * Separation level1 indicating the end of region0 mapping; start of region
4459 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4460 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4461 * lues are used directly as port priorities, where the higher the value co
4462 * rresponds to higher port priority. All of the map_level* registers must
4463 * be set to distinct values.
4464 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb
4466 * Port n Read QoS Configuration Register 0
4467 * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU)
4469 PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU);
4470 /*##################################################################### */
4473 * Register : PCFGQOS1_0 @ 0XFD070498
4475 * Specifies the timeout value for transactions mapped to the red address q
4477 * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0
4479 * Specifies the timeout value for transactions mapped to the blue address
4481 * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0
4483 * Port n Read QoS Configuration Register 1
4484 * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U)
4486 PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U);
4487 /*##################################################################### */
4490 * Register : PCFGR_1 @ 0XFD0704B4
4492 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4493 * ng port is granted, the port is continued to be granted if the following
4494 * immediate commands are to the same memory page (same bank and same row)
4495 * . See also related PCCFG.pagematch_limit register.
4496 * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0
4498 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4499 * bled and arurgent is asserted by the master, that port becomes the highe
4500 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4501 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4502 * urgent signal can be asserted anytime and as long as required which is i
4503 * ndependent of address handshaking (it is not associated with any particu
4505 * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1
4507 * If set to 1, enables aging function for the read channel of the port.
4508 * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0
4510 * Determines the initial load value of read aging counters. These counters
4511 * will be parallel loaded after reset, or after each grant to the corresp
4512 * onding port. The aging counters down-count every clock cycle where the p
4513 * ort is requesting but not granted. The higher significant 5-bits of the
4514 * read aging counter sets the priority of the read channel of a given port
4515 * . Port's priority will increase as the higher significant 5-bits of the
4516 * counter starts to decrease. When the aging counter becomes 0, the corres
4517 * ponding port channel will have the highest priority level (timeout condi
4518 * tion - Priority0). For multi-port configurations, the aging counters can
4519 * not be used to set port priorities when external dynamic priority inputs
4520 * (arqos) are enabled (timeout is still applicable). For single port conf
4521 * igurations, the aging counters are only used when they timeout (become 0
4522 * ) to force read-write direction switching. In this case, external dynami
4523 * c priority input, arqos (for reads only) can still be used to set the DD
4524 * RC read priority (2 priority levels: low priority read - LPR, high prior
4525 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4526 * s register field are tied internally to 2'b00.
4527 * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf
4529 * Port n Configuration Read Register
4530 * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU)
4532 PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU);
4533 /*##################################################################### */
4536 * Register : PCFGW_1 @ 0XFD0704B8
4538 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4539 * ng port is granted, the port is continued to be granted if the following
4540 * immediate commands are to the same memory page (same bank and same row)
4541 * . See also related PCCFG.pagematch_limit register.
4542 * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0
4544 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4545 * bled and awurgent is asserted by the master, that port becomes the highe
4546 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4547 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4548 * serted anytime and as long as required which is independent of address h
4549 * andshaking (it is not associated with any particular command).
4550 * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1
4552 * If set to 1, enables aging function for the write channel of the port.
4553 * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0
4555 * Determines the initial load value of write aging counters. These counter
4556 * s will be parallel loaded after reset, or after each grant to the corres
4557 * ponding port. The aging counters down-count every clock cycle where the
4558 * port is requesting but not granted. The higher significant 5-bits of the
4559 * write aging counter sets the initial priority of the write channel of a
4560 * given port. Port's priority will increase as the higher significant 5-b
4561 * its of the counter starts to decrease. When the aging counter becomes 0,
4562 * the corresponding port channel will have the highest priority level. Fo
4563 * r multi-port configurations, the aging counters cannot be used to set po
4564 * rt priorities when external dynamic priority inputs (awqos) are enabled
4565 * (timeout is still applicable). For single port configurations, the aging
4566 * counters are only used when they timeout (become 0) to force read-write
4567 * direction switching. Note: The two LSBs of this register field are tied
4568 * internally to 2'b00.
4569 * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf
4571 * Port n Configuration Write Register
4572 * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU)
4574 PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU);
4575 /*##################################################################### */
4578 * Register : PCTRL_1 @ 0XFD070540
4581 * PSU_DDRC_PCTRL_1_PORT_EN 0x1
4583 * Port n Control Register
4584 * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U)
4586 PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U);
4587 /*##################################################################### */
4590 * Register : PCFGQOS0_1 @ 0XFD070544
4592 * This bitfield indicates the traffic class of region2. For dual address q
4593 * ueue configurations, region2 maps to the red address queue. Valid values
4594 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
4595 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
4596 * ased to LPR traffic.
4597 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2
4599 * This bitfield indicates the traffic class of region 1. Valid values are:
4600 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4601 * maps to the blue address queue. In this case, valid values are 0: LPR a
4602 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4603 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4605 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0
4607 * This bitfield indicates the traffic class of region 0. Valid values are:
4608 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4609 * maps to the blue address queue. In this case, valid values are: 0: LPR
4610 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4611 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4613 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0
4615 * Separation level2 indicating the end of region1 mapping; start of region
4616 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
4617 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
4618 * that for PA, arqos values are used directly as port priorities, where t
4619 * he higher the value corresponds to higher port priority. All of the map_
4620 * level* registers must be set to distinct values.
4621 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb
4623 * Separation level1 indicating the end of region0 mapping; start of region
4624 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4625 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4626 * lues are used directly as port priorities, where the higher the value co
4627 * rresponds to higher port priority. All of the map_level* registers must
4628 * be set to distinct values.
4629 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3
4631 * Port n Read QoS Configuration Register 0
4632 * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U)
4634 PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U);
4635 /*##################################################################### */
4638 * Register : PCFGQOS1_1 @ 0XFD070548
4640 * Specifies the timeout value for transactions mapped to the red address q
4642 * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0
4644 * Specifies the timeout value for transactions mapped to the blue address
4646 * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0
4648 * Port n Read QoS Configuration Register 1
4649 * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U)
4651 PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U);
4652 /*##################################################################### */
4655 * Register : PCFGR_2 @ 0XFD070564
4657 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4658 * ng port is granted, the port is continued to be granted if the following
4659 * immediate commands are to the same memory page (same bank and same row)
4660 * . See also related PCCFG.pagematch_limit register.
4661 * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0
4663 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4664 * bled and arurgent is asserted by the master, that port becomes the highe
4665 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4666 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4667 * urgent signal can be asserted anytime and as long as required which is i
4668 * ndependent of address handshaking (it is not associated with any particu
4670 * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1
4672 * If set to 1, enables aging function for the read channel of the port.
4673 * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0
4675 * Determines the initial load value of read aging counters. These counters
4676 * will be parallel loaded after reset, or after each grant to the corresp
4677 * onding port. The aging counters down-count every clock cycle where the p
4678 * ort is requesting but not granted. The higher significant 5-bits of the
4679 * read aging counter sets the priority of the read channel of a given port
4680 * . Port's priority will increase as the higher significant 5-bits of the
4681 * counter starts to decrease. When the aging counter becomes 0, the corres
4682 * ponding port channel will have the highest priority level (timeout condi
4683 * tion - Priority0). For multi-port configurations, the aging counters can
4684 * not be used to set port priorities when external dynamic priority inputs
4685 * (arqos) are enabled (timeout is still applicable). For single port conf
4686 * igurations, the aging counters are only used when they timeout (become 0
4687 * ) to force read-write direction switching. In this case, external dynami
4688 * c priority input, arqos (for reads only) can still be used to set the DD
4689 * RC read priority (2 priority levels: low priority read - LPR, high prior
4690 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4691 * s register field are tied internally to 2'b00.
4692 * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf
4694 * Port n Configuration Read Register
4695 * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU)
4697 PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU);
4698 /*##################################################################### */
4701 * Register : PCFGW_2 @ 0XFD070568
4703 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4704 * ng port is granted, the port is continued to be granted if the following
4705 * immediate commands are to the same memory page (same bank and same row)
4706 * . See also related PCCFG.pagematch_limit register.
4707 * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0
4709 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4710 * bled and awurgent is asserted by the master, that port becomes the highe
4711 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4712 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4713 * serted anytime and as long as required which is independent of address h
4714 * andshaking (it is not associated with any particular command).
4715 * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1
4717 * If set to 1, enables aging function for the write channel of the port.
4718 * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0
4720 * Determines the initial load value of write aging counters. These counter
4721 * s will be parallel loaded after reset, or after each grant to the corres
4722 * ponding port. The aging counters down-count every clock cycle where the
4723 * port is requesting but not granted. The higher significant 5-bits of the
4724 * write aging counter sets the initial priority of the write channel of a
4725 * given port. Port's priority will increase as the higher significant 5-b
4726 * its of the counter starts to decrease. When the aging counter becomes 0,
4727 * the corresponding port channel will have the highest priority level. Fo
4728 * r multi-port configurations, the aging counters cannot be used to set po
4729 * rt priorities when external dynamic priority inputs (awqos) are enabled
4730 * (timeout is still applicable). For single port configurations, the aging
4731 * counters are only used when they timeout (become 0) to force read-write
4732 * direction switching. Note: The two LSBs of this register field are tied
4733 * internally to 2'b00.
4734 * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf
4736 * Port n Configuration Write Register
4737 * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU)
4739 PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU);
4740 /*##################################################################### */
4743 * Register : PCTRL_2 @ 0XFD0705F0
4746 * PSU_DDRC_PCTRL_2_PORT_EN 0x1
4748 * Port n Control Register
4749 * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U)
4751 PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U);
4752 /*##################################################################### */
4755 * Register : PCFGQOS0_2 @ 0XFD0705F4
4757 * This bitfield indicates the traffic class of region2. For dual address q
4758 * ueue configurations, region2 maps to the red address queue. Valid values
4759 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
4760 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
4761 * ased to LPR traffic.
4762 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2
4764 * This bitfield indicates the traffic class of region 1. Valid values are:
4765 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4766 * maps to the blue address queue. In this case, valid values are 0: LPR a
4767 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4768 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4770 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0
4772 * This bitfield indicates the traffic class of region 0. Valid values are:
4773 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4774 * maps to the blue address queue. In this case, valid values are: 0: LPR
4775 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4776 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4778 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0
4780 * Separation level2 indicating the end of region1 mapping; start of region
4781 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
4782 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
4783 * that for PA, arqos values are used directly as port priorities, where t
4784 * he higher the value corresponds to higher port priority. All of the map_
4785 * level* registers must be set to distinct values.
4786 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb
4788 * Separation level1 indicating the end of region0 mapping; start of region
4789 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4790 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4791 * lues are used directly as port priorities, where the higher the value co
4792 * rresponds to higher port priority. All of the map_level* registers must
4793 * be set to distinct values.
4794 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3
4796 * Port n Read QoS Configuration Register 0
4797 * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U)
4799 PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U);
4800 /*##################################################################### */
4803 * Register : PCFGQOS1_2 @ 0XFD0705F8
4805 * Specifies the timeout value for transactions mapped to the red address q
4807 * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0
4809 * Specifies the timeout value for transactions mapped to the blue address
4811 * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0
4813 * Port n Read QoS Configuration Register 1
4814 * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U)
4816 PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U);
4817 /*##################################################################### */
4820 * Register : PCFGR_3 @ 0XFD070614
4822 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4823 * ng port is granted, the port is continued to be granted if the following
4824 * immediate commands are to the same memory page (same bank and same row)
4825 * . See also related PCCFG.pagematch_limit register.
4826 * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0
4828 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4829 * bled and arurgent is asserted by the master, that port becomes the highe
4830 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4831 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4832 * urgent signal can be asserted anytime and as long as required which is i
4833 * ndependent of address handshaking (it is not associated with any particu
4835 * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1
4837 * If set to 1, enables aging function for the read channel of the port.
4838 * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0
4840 * Determines the initial load value of read aging counters. These counters
4841 * will be parallel loaded after reset, or after each grant to the corresp
4842 * onding port. The aging counters down-count every clock cycle where the p
4843 * ort is requesting but not granted. The higher significant 5-bits of the
4844 * read aging counter sets the priority of the read channel of a given port
4845 * . Port's priority will increase as the higher significant 5-bits of the
4846 * counter starts to decrease. When the aging counter becomes 0, the corres
4847 * ponding port channel will have the highest priority level (timeout condi
4848 * tion - Priority0). For multi-port configurations, the aging counters can
4849 * not be used to set port priorities when external dynamic priority inputs
4850 * (arqos) are enabled (timeout is still applicable). For single port conf
4851 * igurations, the aging counters are only used when they timeout (become 0
4852 * ) to force read-write direction switching. In this case, external dynami
4853 * c priority input, arqos (for reads only) can still be used to set the DD
4854 * RC read priority (2 priority levels: low priority read - LPR, high prior
4855 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4856 * s register field are tied internally to 2'b00.
4857 * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf
4859 * Port n Configuration Read Register
4860 * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU)
4862 PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU);
4863 /*##################################################################### */
4866 * Register : PCFGW_3 @ 0XFD070618
4868 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4869 * ng port is granted, the port is continued to be granted if the following
4870 * immediate commands are to the same memory page (same bank and same row)
4871 * . See also related PCCFG.pagematch_limit register.
4872 * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0
4874 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4875 * bled and awurgent is asserted by the master, that port becomes the highe
4876 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4877 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4878 * serted anytime and as long as required which is independent of address h
4879 * andshaking (it is not associated with any particular command).
4880 * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1
4882 * If set to 1, enables aging function for the write channel of the port.
4883 * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0
4885 * Determines the initial load value of write aging counters. These counter
4886 * s will be parallel loaded after reset, or after each grant to the corres
4887 * ponding port. The aging counters down-count every clock cycle where the
4888 * port is requesting but not granted. The higher significant 5-bits of the
4889 * write aging counter sets the initial priority of the write channel of a
4890 * given port. Port's priority will increase as the higher significant 5-b
4891 * its of the counter starts to decrease. When the aging counter becomes 0,
4892 * the corresponding port channel will have the highest priority level. Fo
4893 * r multi-port configurations, the aging counters cannot be used to set po
4894 * rt priorities when external dynamic priority inputs (awqos) are enabled
4895 * (timeout is still applicable). For single port configurations, the aging
4896 * counters are only used when they timeout (become 0) to force read-write
4897 * direction switching. Note: The two LSBs of this register field are tied
4898 * internally to 2'b00.
4899 * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf
4901 * Port n Configuration Write Register
4902 * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU)
4904 PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU);
4905 /*##################################################################### */
4908 * Register : PCTRL_3 @ 0XFD0706A0
4911 * PSU_DDRC_PCTRL_3_PORT_EN 0x1
4913 * Port n Control Register
4914 * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U)
4916 PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U);
4917 /*##################################################################### */
4920 * Register : PCFGQOS0_3 @ 0XFD0706A4
4922 * This bitfield indicates the traffic class of region 1. Valid values are:
4923 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4924 * maps to the blue address queue. In this case, valid values are 0: LPR a
4925 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4926 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4928 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1
4930 * This bitfield indicates the traffic class of region 0. Valid values are:
4931 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4932 * maps to the blue address queue. In this case, valid values are: 0: LPR
4933 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4934 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4936 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0
4938 * Separation level1 indicating the end of region0 mapping; start of region
4939 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4940 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4941 * lues are used directly as port priorities, where the higher the value co
4942 * rresponds to higher port priority. All of the map_level* registers must
4943 * be set to distinct values.
4944 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3
4946 * Port n Read QoS Configuration Register 0
4947 * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U)
4949 PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U);
4950 /*##################################################################### */
4953 * Register : PCFGQOS1_3 @ 0XFD0706A8
4955 * Specifies the timeout value for transactions mapped to the red address q
4957 * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0
4959 * Specifies the timeout value for transactions mapped to the blue address
4961 * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f
4963 * Port n Read QoS Configuration Register 1
4964 * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)
4966 PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU);
4967 /*##################################################################### */
4970 * Register : PCFGWQOS0_3 @ 0XFD0706AC
4972 * This bitfield indicates the traffic class of region 1. Valid values are:
4973 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4974 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
4976 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1
4978 * This bitfield indicates the traffic class of region 0. Valid values are:
4979 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4980 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
4982 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0
4984 * Separation level indicating the end of region0 mapping; start of region0
4985 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
4986 * . Note that for PA, awqos values are used directly as port priorities, w
4987 * here the higher the value corresponds to higher port priority.
4988 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3
4990 * Port n Write QoS Configuration Register 0
4991 * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U)
4993 PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U);
4994 /*##################################################################### */
4997 * Register : PCFGWQOS1_3 @ 0XFD0706B0
4999 * Specifies the timeout value for write transactions.
5000 * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f
5002 * Port n Write QoS Configuration Register 1
5003 * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU)
5005 PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU);
5006 /*##################################################################### */
5009 * Register : PCFGR_4 @ 0XFD0706C4
5011 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5012 * ng port is granted, the port is continued to be granted if the following
5013 * immediate commands are to the same memory page (same bank and same row)
5014 * . See also related PCCFG.pagematch_limit register.
5015 * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0
5017 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
5018 * bled and arurgent is asserted by the master, that port becomes the highe
5019 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
5020 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
5021 * urgent signal can be asserted anytime and as long as required which is i
5022 * ndependent of address handshaking (it is not associated with any particu
5024 * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1
5026 * If set to 1, enables aging function for the read channel of the port.
5027 * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0
5029 * Determines the initial load value of read aging counters. These counters
5030 * will be parallel loaded after reset, or after each grant to the corresp
5031 * onding port. The aging counters down-count every clock cycle where the p
5032 * ort is requesting but not granted. The higher significant 5-bits of the
5033 * read aging counter sets the priority of the read channel of a given port
5034 * . Port's priority will increase as the higher significant 5-bits of the
5035 * counter starts to decrease. When the aging counter becomes 0, the corres
5036 * ponding port channel will have the highest priority level (timeout condi
5037 * tion - Priority0). For multi-port configurations, the aging counters can
5038 * not be used to set port priorities when external dynamic priority inputs
5039 * (arqos) are enabled (timeout is still applicable). For single port conf
5040 * igurations, the aging counters are only used when they timeout (become 0
5041 * ) to force read-write direction switching. In this case, external dynami
5042 * c priority input, arqos (for reads only) can still be used to set the DD
5043 * RC read priority (2 priority levels: low priority read - LPR, high prior
5044 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
5045 * s register field are tied internally to 2'b00.
5046 * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf
5048 * Port n Configuration Read Register
5049 * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU)
5051 PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU);
5052 /*##################################################################### */
5055 * Register : PCFGW_4 @ 0XFD0706C8
5057 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5058 * ng port is granted, the port is continued to be granted if the following
5059 * immediate commands are to the same memory page (same bank and same row)
5060 * . See also related PCCFG.pagematch_limit register.
5061 * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0
5063 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
5064 * bled and awurgent is asserted by the master, that port becomes the highe
5065 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
5066 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
5067 * serted anytime and as long as required which is independent of address h
5068 * andshaking (it is not associated with any particular command).
5069 * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1
5071 * If set to 1, enables aging function for the write channel of the port.
5072 * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0
5074 * Determines the initial load value of write aging counters. These counter
5075 * s will be parallel loaded after reset, or after each grant to the corres
5076 * ponding port. The aging counters down-count every clock cycle where the
5077 * port is requesting but not granted. The higher significant 5-bits of the
5078 * write aging counter sets the initial priority of the write channel of a
5079 * given port. Port's priority will increase as the higher significant 5-b
5080 * its of the counter starts to decrease. When the aging counter becomes 0,
5081 * the corresponding port channel will have the highest priority level. Fo
5082 * r multi-port configurations, the aging counters cannot be used to set po
5083 * rt priorities when external dynamic priority inputs (awqos) are enabled
5084 * (timeout is still applicable). For single port configurations, the aging
5085 * counters are only used when they timeout (become 0) to force read-write
5086 * direction switching. Note: The two LSBs of this register field are tied
5087 * internally to 2'b00.
5088 * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf
5090 * Port n Configuration Write Register
5091 * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU)
5093 PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU);
5094 /*##################################################################### */
5097 * Register : PCTRL_4 @ 0XFD070750
5100 * PSU_DDRC_PCTRL_4_PORT_EN 0x1
5102 * Port n Control Register
5103 * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U)
5105 PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U);
5106 /*##################################################################### */
5109 * Register : PCFGQOS0_4 @ 0XFD070754
5111 * This bitfield indicates the traffic class of region 1. Valid values are:
5112 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
5113 * maps to the blue address queue. In this case, valid values are 0: LPR a
5114 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
5115 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
5117 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1
5119 * This bitfield indicates the traffic class of region 0. Valid values are:
5120 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
5121 * maps to the blue address queue. In this case, valid values are: 0: LPR
5122 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
5123 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
5125 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0
5127 * Separation level1 indicating the end of region0 mapping; start of region
5128 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
5129 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
5130 * lues are used directly as port priorities, where the higher the value co
5131 * rresponds to higher port priority. All of the map_level* registers must
5132 * be set to distinct values.
5133 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3
5135 * Port n Read QoS Configuration Register 0
5136 * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U)
5138 PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U);
5139 /*##################################################################### */
5142 * Register : PCFGQOS1_4 @ 0XFD070758
5144 * Specifies the timeout value for transactions mapped to the red address q
5146 * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0
5148 * Specifies the timeout value for transactions mapped to the blue address
5150 * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f
5152 * Port n Read QoS Configuration Register 1
5153 * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU)
5155 PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU);
5156 /*##################################################################### */
5159 * Register : PCFGWQOS0_4 @ 0XFD07075C
5161 * This bitfield indicates the traffic class of region 1. Valid values are:
5162 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5163 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
5165 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1
5167 * This bitfield indicates the traffic class of region 0. Valid values are:
5168 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5169 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
5171 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0
5173 * Separation level indicating the end of region0 mapping; start of region0
5174 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
5175 * . Note that for PA, awqos values are used directly as port priorities, w
5176 * here the higher the value corresponds to higher port priority.
5177 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3
5179 * Port n Write QoS Configuration Register 0
5180 * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U)
5182 PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U);
5183 /*##################################################################### */
5186 * Register : PCFGWQOS1_4 @ 0XFD070760
5188 * Specifies the timeout value for write transactions.
5189 * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f
5191 * Port n Write QoS Configuration Register 1
5192 * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU)
5194 PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU);
5195 /*##################################################################### */
5198 * Register : PCFGR_5 @ 0XFD070774
5200 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5201 * ng port is granted, the port is continued to be granted if the following
5202 * immediate commands are to the same memory page (same bank and same row)
5203 * . See also related PCCFG.pagematch_limit register.
5204 * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0
5206 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
5207 * bled and arurgent is asserted by the master, that port becomes the highe
5208 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
5209 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
5210 * urgent signal can be asserted anytime and as long as required which is i
5211 * ndependent of address handshaking (it is not associated with any particu
5213 * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1
5215 * If set to 1, enables aging function for the read channel of the port.
5216 * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0
5218 * Determines the initial load value of read aging counters. These counters
5219 * will be parallel loaded after reset, or after each grant to the corresp
5220 * onding port. The aging counters down-count every clock cycle where the p
5221 * ort is requesting but not granted. The higher significant 5-bits of the
5222 * read aging counter sets the priority of the read channel of a given port
5223 * . Port's priority will increase as the higher significant 5-bits of the
5224 * counter starts to decrease. When the aging counter becomes 0, the corres
5225 * ponding port channel will have the highest priority level (timeout condi
5226 * tion - Priority0). For multi-port configurations, the aging counters can
5227 * not be used to set port priorities when external dynamic priority inputs
5228 * (arqos) are enabled (timeout is still applicable). For single port conf
5229 * igurations, the aging counters are only used when they timeout (become 0
5230 * ) to force read-write direction switching. In this case, external dynami
5231 * c priority input, arqos (for reads only) can still be used to set the DD
5232 * RC read priority (2 priority levels: low priority read - LPR, high prior
5233 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
5234 * s register field are tied internally to 2'b00.
5235 * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf
5237 * Port n Configuration Read Register
5238 * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU)
5240 PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU);
5241 /*##################################################################### */
5244 * Register : PCFGW_5 @ 0XFD070778
5246 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5247 * ng port is granted, the port is continued to be granted if the following
5248 * immediate commands are to the same memory page (same bank and same row)
5249 * . See also related PCCFG.pagematch_limit register.
5250 * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0
5252 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
5253 * bled and awurgent is asserted by the master, that port becomes the highe
5254 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
5255 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
5256 * serted anytime and as long as required which is independent of address h
5257 * andshaking (it is not associated with any particular command).
5258 * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1
5260 * If set to 1, enables aging function for the write channel of the port.
5261 * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0
5263 * Determines the initial load value of write aging counters. These counter
5264 * s will be parallel loaded after reset, or after each grant to the corres
5265 * ponding port. The aging counters down-count every clock cycle where the
5266 * port is requesting but not granted. The higher significant 5-bits of the
5267 * write aging counter sets the initial priority of the write channel of a
5268 * given port. Port's priority will increase as the higher significant 5-b
5269 * its of the counter starts to decrease. When the aging counter becomes 0,
5270 * the corresponding port channel will have the highest priority level. Fo
5271 * r multi-port configurations, the aging counters cannot be used to set po
5272 * rt priorities when external dynamic priority inputs (awqos) are enabled
5273 * (timeout is still applicable). For single port configurations, the aging
5274 * counters are only used when they timeout (become 0) to force read-write
5275 * direction switching. Note: The two LSBs of this register field are tied
5276 * internally to 2'b00.
5277 * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf
5279 * Port n Configuration Write Register
5280 * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU)
5282 PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU);
5283 /*##################################################################### */
5286 * Register : PCTRL_5 @ 0XFD070800
5289 * PSU_DDRC_PCTRL_5_PORT_EN 0x1
5291 * Port n Control Register
5292 * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U)
5294 PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U);
5295 /*##################################################################### */
5298 * Register : PCFGQOS0_5 @ 0XFD070804
5300 * This bitfield indicates the traffic class of region 1. Valid values are:
5301 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
5302 * maps to the blue address queue. In this case, valid values are 0: LPR a
5303 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
5304 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
5306 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1
5308 * This bitfield indicates the traffic class of region 0. Valid values are:
5309 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
5310 * maps to the blue address queue. In this case, valid values are: 0: LPR
5311 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
5312 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
5314 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0
5316 * Separation level1 indicating the end of region0 mapping; start of region
5317 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
5318 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
5319 * lues are used directly as port priorities, where the higher the value co
5320 * rresponds to higher port priority. All of the map_level* registers must
5321 * be set to distinct values.
5322 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3
5324 * Port n Read QoS Configuration Register 0
5325 * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U)
5327 PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U);
5328 /*##################################################################### */
5331 * Register : PCFGQOS1_5 @ 0XFD070808
5333 * Specifies the timeout value for transactions mapped to the red address q
5335 * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0
5337 * Specifies the timeout value for transactions mapped to the blue address
5339 * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f
5341 * Port n Read QoS Configuration Register 1
5342 * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU)
5344 PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU);
5345 /*##################################################################### */
5348 * Register : PCFGWQOS0_5 @ 0XFD07080C
5350 * This bitfield indicates the traffic class of region 1. Valid values are:
5351 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5352 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
5354 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1
5356 * This bitfield indicates the traffic class of region 0. Valid values are:
5357 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5358 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
5360 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0
5362 * Separation level indicating the end of region0 mapping; start of region0
5363 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
5364 * . Note that for PA, awqos values are used directly as port priorities, w
5365 * here the higher the value corresponds to higher port priority.
5366 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3
5368 * Port n Write QoS Configuration Register 0
5369 * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U)
5371 PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U);
5372 /*##################################################################### */
5375 * Register : PCFGWQOS1_5 @ 0XFD070810
5377 * Specifies the timeout value for write transactions.
5378 * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f
5380 * Port n Write QoS Configuration Register 1
5381 * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU)
5383 PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU);
5384 /*##################################################################### */
5387 * Register : SARBASE0 @ 0XFD070F04
5389 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
5390 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
5391 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5392 * PSU_DDRC_SARBASE0_BASE_ADDR 0x0
5394 * SAR Base Address Register n
5395 * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U)
5397 PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U);
5398 /*##################################################################### */
5401 * Register : SARSIZE0 @ 0XFD070F08
5403 * Number of blocks for address region n. This register determines the tota
5404 * l size of the region in multiples of minimum block size as specified by
5405 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
5406 * as number of blocks = nblocks + 1. For example, if register is programme
5407 * d to 0, region will have 1 block.
5408 * PSU_DDRC_SARSIZE0_NBLOCKS 0x0
5410 * SAR Size Register n
5411 * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U)
5413 PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U);
5414 /*##################################################################### */
5417 * Register : SARBASE1 @ 0XFD070F0C
5419 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
5420 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
5421 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5422 * PSU_DDRC_SARBASE1_BASE_ADDR 0x10
5424 * SAR Base Address Register n
5425 * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U)
5427 PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U);
5428 /*##################################################################### */
5431 * Register : SARSIZE1 @ 0XFD070F10
5433 * Number of blocks for address region n. This register determines the tota
5434 * l size of the region in multiples of minimum block size as specified by
5435 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
5436 * as number of blocks = nblocks + 1. For example, if register is programme
5437 * d to 0, region will have 1 block.
5438 * PSU_DDRC_SARSIZE1_NBLOCKS 0xf
5440 * SAR Size Register n
5441 * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU)
5443 PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU);
5444 /*##################################################################### */
5447 * Register : DFITMG0_SHADOW @ 0XFD072190
5449 * Specifies the number of DFI clock cycles after an assertion or de-assert
5450 * ion of the DFI control signals that the control signals at the PHY-DRAM
5451 * interface reflect the assertion or de-assertion. If the DFI clock and th
5452 * e memory clock are not phase-aligned, this timing parameter should be ro
5453 * unded up to the next integer value. Note that if using RDIMM, it is nece
5454 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
5455 * erms of DFI clock.
5456 * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7
5458 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
5459 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
5460 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
5461 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
5463 * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1
5465 * Time from the assertion of a read command on the DFI interface to the as
5466 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
5467 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
5468 * depending on the PHY, if using RDIMM, it may be necessary to use the val
5469 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
5470 * the extra cycle of latency through the RDIMM. Unit: Clocks
5471 * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2
5473 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
5474 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
5475 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
5476 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
5477 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
5478 * n for correct value.
5479 * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1
5481 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
5482 * ted to when the associated write data is driven on the dfi_wrdata signal
5483 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
5484 * specification for correct value. Note, max supported value is 8. Unit:
5486 * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0
5488 * Write latency Number of clocks from the write command to write data enab
5489 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
5490 * lat. Refer to PHY specification for correct value.Note that, depending o
5491 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
5492 * in the calculation of tphy_wrlat. This is to compensate for the extra c
5493 * ycle of latency through the RDIMM.
5494 * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2
5496 * DFI Timing Shadow Register 0
5497 * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U)
5499 PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U);
5500 /*##################################################################### */
5503 * DDR CONTROLLER RESET
5506 * Register : RST_DDR_SS @ 0XFD1A0108
5508 * DDR block level reset inside of the DDR Sub System
5509 * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0
5511 * APM block level reset inside of the DDR Sub System
5512 * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0
5514 * DDR sub system block level reset
5515 * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U)
5517 PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U);
5518 /*##################################################################### */
5524 * Register : PGCR0 @ 0XFD080010
5527 * PSU_DDR_PHY_PGCR0_ADCP 0x0
5529 * Reserved. Returns zeroes on reads.
5530 * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0
5533 * PSU_DDR_PHY_PGCR0_PHYFRST 0x1
5535 * Oscillator Mode Address/Command Delay Line Select
5536 * PSU_DDR_PHY_PGCR0_OSCACDL 0x3
5538 * Reserved. Returns zeroes on reads.
5539 * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0
5541 * Digital Test Output Select
5542 * PSU_DDR_PHY_PGCR0_DTOSEL 0x0
5544 * Reserved. Returns zeroes on reads.
5545 * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0
5547 * Oscillator Mode Division
5548 * PSU_DDR_PHY_PGCR0_OSCDIV 0xf
5551 * PSU_DDR_PHY_PGCR0_OSCEN 0x0
5553 * Reserved. Returns zeroes on reads.
5554 * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0
5556 * PHY General Configuration Register 0
5557 * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)
5559 PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U);
5560 /*##################################################################### */
5563 * Register : PGCR2 @ 0XFD080018
5565 * Clear Training Status Registers
5566 * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0
5568 * Clear Impedance Calibration
5569 * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0
5571 * Clear Parity Error
5572 * PSU_DDR_PHY_PGCR2_CLRPERR 0x0
5574 * Initialization Complete Pin Configuration
5575 * PSU_DDR_PHY_PGCR2_ICPC 0x0
5577 * Data Training PUB Mode Exit Timer
5578 * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf
5580 * Initialization Bypass
5581 * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0
5584 * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
5587 * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010
5589 * PHY General Configuration Register 2
5590 * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U)
5592 PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U);
5593 /*##################################################################### */
5596 * Register : PGCR3 @ 0XFD08001C
5599 * PSU_DDR_PHY_PGCR3_CKNEN 0x55
5602 * PSU_DDR_PHY_PGCR3_CKEN 0xaa
5604 * Reserved. Return zeroes on reads.
5605 * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
5607 * Enable Clock Gating for AC [0] ctl_rd_clk
5608 * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
5610 * Enable Clock Gating for AC [0] ddr_clk
5611 * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
5613 * Enable Clock Gating for AC [0] ctl_clk
5614 * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
5616 * Reserved. Return zeroes on reads.
5617 * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
5619 * Controls DDL Bypass Modes
5620 * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
5622 * IO Loop-Back Select
5623 * PSU_DDR_PHY_PGCR3_IOLB 0x0
5625 * AC Receive FIFO Read Mode
5626 * PSU_DDR_PHY_PGCR3_RDMODE 0x0
5628 * Read FIFO Reset Disable
5629 * PSU_DDR_PHY_PGCR3_DISRST 0x0
5631 * Clock Level when Clock Gating
5632 * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
5634 * PHY General Configuration Register 3
5635 * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
5637 PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U);
5638 /*##################################################################### */
5641 * Register : PGCR5 @ 0XFD080024
5643 * Frequency B Ratio Term
5644 * PSU_DDR_PHY_PGCR5_FRQBT 0x1
5646 * Frequency A Ratio Term
5647 * PSU_DDR_PHY_PGCR5_FRQAT 0x1
5649 * DFI Disconnect Time Period
5650 * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0
5652 * Receiver bias core side control
5653 * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf
5655 * Reserved. Return zeroes on reads.
5656 * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0
5658 * Internal VREF generator REFSEL ragne select
5659 * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1
5661 * DDL Page Read Write select
5662 * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0
5664 * DDL Page Read Write select
5665 * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0
5667 * PHY General Configuration Register 5
5668 * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)
5670 PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U);
5671 /*##################################################################### */
5674 * Register : PTR0 @ 0XFD080040
5676 * PLL Power-Down Time
5677 * PSU_DDR_PHY_PTR0_TPLLPD 0x56
5679 * PLL Gear Shift Time
5680 * PSU_DDR_PHY_PTR0_TPLLGS 0x2155
5683 * PSU_DDR_PHY_PTR0_TPHYRST 0x10
5685 * PHY Timing Register 0
5686 * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U)
5688 PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U);
5689 /*##################################################################### */
5692 * Register : PTR1 @ 0XFD080044
5695 * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141
5697 * Reserved. Returns zeroes on reads.
5698 * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0
5701 * PSU_DDR_PHY_PTR1_TPLLRST 0xaff
5703 * PHY Timing Register 1
5704 * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU)
5706 PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU);
5707 /*##################################################################### */
5710 * Register : PLLCR0 @ 0XFD080068
5713 * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0
5716 * PSU_DDR_PHY_PLLCR0_PLLRST 0x0
5719 * PSU_DDR_PHY_PLLCR0_PLLPD 0x0
5721 * Reference Stop Mode
5722 * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0
5724 * PLL Frequency Select
5725 * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1
5728 * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0
5730 * Charge Pump Proportional Current Control
5731 * PSU_DDR_PHY_PLLCR0_CPPC 0x8
5733 * Charge Pump Integrating Current Control
5734 * PSU_DDR_PHY_PLLCR0_CPIC 0x0
5737 * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0
5739 * Reserved. Return zeroes on reads.
5740 * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0
5742 * Analog Test Enable
5743 * PSU_DDR_PHY_PLLCR0_ATOEN 0x0
5745 * Analog Test Control
5746 * PSU_DDR_PHY_PLLCR0_ATC 0x0
5748 * Digital Test Control
5749 * PSU_DDR_PHY_PLLCR0_DTC 0x0
5751 * PLL Control Register 0 (Type B PLL Only)
5752 * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U)
5754 PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U);
5755 /*##################################################################### */
5758 * Register : DSGCR @ 0XFD080090
5760 * Reserved. Return zeroes on reads.
5761 * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0
5763 * When RDBI enabled, this bit is used to select RDBI CL calculation, if it
5764 * is 1b1, calculation will use RDBICL, otherwise use default calculation.
5765 * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0
5767 * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
5769 * PSU_DDR_PHY_DSGCR_RDBICL 0x2
5771 * PHY Impedance Update Enable
5772 * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1
5774 * Reserved. Return zeroes on reads.
5775 * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0
5777 * SDRAM Reset Output Enable
5778 * PSU_DDR_PHY_DSGCR_RSTOE 0x1
5780 * Single Data Rate Mode
5781 * PSU_DDR_PHY_DSGCR_SDRMODE 0x0
5783 * Reserved. Return zeroes on reads.
5784 * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0
5786 * ATO Analog Test Enable
5787 * PSU_DDR_PHY_DSGCR_ATOAE 0x0
5790 * PSU_DDR_PHY_DSGCR_DTOOE 0x0
5793 * PSU_DDR_PHY_DSGCR_DTOIOM 0x0
5795 * DTO Power Down Receiver
5796 * PSU_DDR_PHY_DSGCR_DTOPDR 0x1
5798 * Reserved. Return zeroes on reads
5799 * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0
5801 * DTO On-Die Termination
5802 * PSU_DDR_PHY_DSGCR_DTOODT 0x0
5804 * PHY Update Acknowledge Delay
5805 * PSU_DDR_PHY_DSGCR_PUAD 0x5
5807 * Controller Update Acknowledge Enable
5808 * PSU_DDR_PHY_DSGCR_CUAEN 0x1
5810 * Reserved. Return zeroes on reads
5811 * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0
5813 * Controller Impedance Update Enable
5814 * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0
5816 * Reserved. Return zeroes on reads
5817 * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0
5819 * PHY Update Request Enable
5820 * PSU_DDR_PHY_DSGCR_PUREN 0x1
5822 * DDR System General Configuration Register
5823 * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U)
5825 PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U);
5826 /*##################################################################### */
5829 * Register : GPR0 @ 0XFD0800C0
5831 * General Purpose Register 0
5832 * PSU_DDR_PHY_GPR0_GPR0 0xd3
5834 * General Purpose Register 0
5835 * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U)
5837 PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U);
5838 /*##################################################################### */
5841 * Register : DCR @ 0XFD080100
5843 * DDR4 Gear Down Timing.
5844 * PSU_DDR_PHY_DCR_GEARDN 0x0
5846 * Un-used Bank Group
5847 * PSU_DDR_PHY_DCR_UBG 0x0
5849 * Un-buffered DIMM Address Mirroring
5850 * PSU_DDR_PHY_DCR_UDIMM 0x0
5853 * PSU_DDR_PHY_DCR_DDR2T 0x0
5855 * No Simultaneous Rank Access
5856 * PSU_DDR_PHY_DCR_NOSRA 0x1
5858 * Reserved. Return zeroes on reads.
5859 * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0
5862 * PSU_DDR_PHY_DCR_BYTEMASK 0x1
5865 * PSU_DDR_PHY_DCR_DDRTYPE 0x0
5867 * Multi-Purpose Register (MPR) DQ (DDR3 Only)
5868 * PSU_DDR_PHY_DCR_MPRDQ 0x0
5870 * Primary DQ (DDR3 Only)
5871 * PSU_DDR_PHY_DCR_PDQ 0x0
5874 * PSU_DDR_PHY_DCR_DDR8BNK 0x1
5877 * PSU_DDR_PHY_DCR_DDRMD 0x4
5879 * DRAM Configuration Register
5880 * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)
5882 PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU);
5883 /*##################################################################### */
5886 * Register : DTPR0 @ 0XFD080110
5888 * Reserved. Return zeroes on reads.
5889 * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0
5891 * Activate to activate command delay (different banks)
5892 * PSU_DDR_PHY_DTPR0_TRRD 0x6
5894 * Reserved. Return zeroes on reads.
5895 * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0
5897 * Activate to precharge command delay
5898 * PSU_DDR_PHY_DTPR0_TRAS 0x24
5900 * Reserved. Return zeroes on reads.
5901 * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
5903 * Precharge command period
5904 * PSU_DDR_PHY_DTPR0_TRP 0xf
5906 * Reserved. Return zeroes on reads.
5907 * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
5909 * Internal read to precharge command delay
5910 * PSU_DDR_PHY_DTPR0_TRTP 0x8
5912 * DRAM Timing Parameters Register 0
5913 * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U)
5915 PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U);
5916 /*##################################################################### */
5919 * Register : DTPR1 @ 0XFD080114
5921 * Reserved. Return zeroes on reads.
5922 * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0
5924 * Minimum delay from when write leveling mode is programmed to the first D
5925 * QS/DQS# rising edge.
5926 * PSU_DDR_PHY_DTPR1_TWLMRD 0x28
5928 * Reserved. Return zeroes on reads.
5929 * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0
5931 * 4-bank activate period
5932 * PSU_DDR_PHY_DTPR1_TFAW 0x20
5934 * Reserved. Return zeroes on reads.
5935 * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0
5937 * Load mode update delay (DDR4 and DDR3 only)
5938 * PSU_DDR_PHY_DTPR1_TMOD 0x0
5940 * Reserved. Return zeroes on reads.
5941 * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0
5943 * Load mode cycle time
5944 * PSU_DDR_PHY_DTPR1_TMRD 0x8
5946 * DRAM Timing Parameters Register 1
5947 * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U)
5949 PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U);
5950 /*##################################################################### */
5953 * Register : DTPR2 @ 0XFD080118
5955 * Reserved. Return zeroes on reads.
5956 * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0
5958 * Read to Write command delay. Valid values are
5959 * PSU_DDR_PHY_DTPR2_TRTW 0x0
5961 * Reserved. Return zeroes on reads.
5962 * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0
5964 * Read to ODT delay (DDR3 only)
5965 * PSU_DDR_PHY_DTPR2_TRTODT 0x0
5967 * Reserved. Return zeroes on reads.
5968 * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0
5970 * CKE minimum pulse width
5971 * PSU_DDR_PHY_DTPR2_TCKE 0x7
5973 * Reserved. Return zeroes on reads.
5974 * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0
5976 * Self refresh exit delay
5977 * PSU_DDR_PHY_DTPR2_TXS 0x300
5979 * DRAM Timing Parameters Register 2
5980 * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U)
5982 PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U);
5983 /*##################################################################### */
5986 * Register : DTPR3 @ 0XFD08011C
5988 * ODT turn-off delay extension
5989 * PSU_DDR_PHY_DTPR3_TOFDX 0x4
5991 * Read to read and write to write command delay
5992 * PSU_DDR_PHY_DTPR3_TCCD 0x0
5995 * PSU_DDR_PHY_DTPR3_TDLLK 0x300
5997 * Reserved. Return zeroes on reads.
5998 * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0
6000 * Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
6001 * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8
6003 * Reserved. Return zeroes on reads.
6004 * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
6006 * DQS output access time from CK/CK# (LPDDR2/3 only)
6007 * PSU_DDR_PHY_DTPR3_TDQSCK 0x0
6009 * DRAM Timing Parameters Register 3
6010 * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
6012 PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U);
6013 /*##################################################################### */
6016 * Register : DTPR4 @ 0XFD080120
6018 * Reserved. Return zeroes on reads.
6019 * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0
6021 * ODT turn-on/turn-off delays (DDR2 only)
6022 * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0
6024 * Reserved. Return zeroes on reads.
6025 * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0
6027 * Refresh-to-Refresh
6028 * PSU_DDR_PHY_DTPR4_TRFC 0x116
6030 * Reserved. Return zeroes on reads.
6031 * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0
6033 * Write leveling output delay
6034 * PSU_DDR_PHY_DTPR4_TWLO 0x2b
6036 * Reserved. Return zeroes on reads.
6037 * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0
6039 * Power down exit delay
6040 * PSU_DDR_PHY_DTPR4_TXP 0x7
6042 * DRAM Timing Parameters Register 4
6043 * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U)
6045 PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U);
6046 /*##################################################################### */
6049 * Register : DTPR5 @ 0XFD080124
6051 * Reserved. Return zeroes on reads.
6052 * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0
6054 * Activate to activate command delay (same bank)
6055 * PSU_DDR_PHY_DTPR5_TRC 0x33
6057 * Reserved. Return zeroes on reads.
6058 * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0
6060 * Activate to read or write delay
6061 * PSU_DDR_PHY_DTPR5_TRCD 0xf
6063 * Reserved. Return zeroes on reads.
6064 * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0
6066 * Internal write to read command delay
6067 * PSU_DDR_PHY_DTPR5_TWTR 0x8
6069 * DRAM Timing Parameters Register 5
6070 * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U)
6072 PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U);
6073 /*##################################################################### */
6076 * Register : DTPR6 @ 0XFD080128
6078 * PUB Write Latency Enable
6079 * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0
6081 * PUB Read Latency Enable
6082 * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0
6084 * Reserved. Return zeroes on reads.
6085 * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0
6088 * PSU_DDR_PHY_DTPR6_PUBWL 0xe
6090 * Reserved. Return zeroes on reads.
6091 * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0
6094 * PSU_DDR_PHY_DTPR6_PUBRL 0xf
6096 * DRAM Timing Parameters Register 6
6097 * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)
6099 PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU);
6100 /*##################################################################### */
6103 * Register : RDIMMGCR0 @ 0XFD080140
6105 * Reserved. Return zeroes on reads.
6106 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0
6108 * RDMIMM Quad CS Enable
6109 * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0
6111 * Reserved. Return zeroes on reads.
6112 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0
6114 * RDIMM Outputs I/O Mode
6115 * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1
6117 * Reserved. Return zeroes on reads.
6118 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0
6120 * ERROUT# Output Enable
6121 * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0
6124 * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1
6126 * ERROUT# Power Down Receiver
6127 * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0
6129 * Reserved. Return zeroes on reads.
6130 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0
6132 * ERROUT# On-Die Termination
6133 * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0
6136 * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0
6139 * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0
6141 * Reserved. Return zeroes on reads.
6142 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0
6144 * Reserved. Return zeroes on reads.
6145 * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0
6147 * Rank Mirror Enable.
6148 * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2
6150 * Reserved. Return zeroes on reads.
6151 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0
6153 * Stop on Parity Error
6154 * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0
6156 * Parity Error No Registering
6157 * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0
6160 * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0
6162 * RDIMM General Configuration Register 0
6163 * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U)
6165 PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U);
6166 /*##################################################################### */
6169 * Register : RDIMMGCR1 @ 0XFD080144
6171 * Reserved. Return zeroes on reads.
6172 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0
6174 * Address [17] B-side Inversion Disable
6175 * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0
6177 * Reserved. Return zeroes on reads.
6178 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0
6180 * Command word to command word programming delay
6181 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0
6183 * Reserved. Return zeroes on reads.
6184 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0
6186 * Command word to command word programming delay
6187 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0
6189 * Reserved. Return zeroes on reads.
6190 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0
6192 * Command word to command word programming delay
6193 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0
6195 * Reserved. Return zeroes on reads.
6196 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0
6198 * Stabilization time
6199 * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80
6201 * RDIMM General Configuration Register 1
6202 * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)
6204 PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U);
6205 /*##################################################################### */
6208 * Register : RDIMMCR0 @ 0XFD080150
6210 * DDR4/DDR3 Control Word 7
6211 * PSU_DDR_PHY_RDIMMCR0_RC7 0x0
6213 * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
6214 * PSU_DDR_PHY_RDIMMCR0_RC6 0x0
6216 * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
6217 * PSU_DDR_PHY_RDIMMCR0_RC5 0x0
6219 * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
6220 * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
6222 * PSU_DDR_PHY_RDIMMCR0_RC4 0x0
6224 * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
6225 * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
6227 * PSU_DDR_PHY_RDIMMCR0_RC3 0x0
6229 * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
6230 * (Timing Control Word)
6231 * PSU_DDR_PHY_RDIMMCR0_RC2 0x0
6233 * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
6234 * PSU_DDR_PHY_RDIMMCR0_RC1 0x0
6236 * DDR4/DDR3 Control Word 0 (Global Features Control Word)
6237 * PSU_DDR_PHY_RDIMMCR0_RC0 0x0
6239 * RDIMM Control Register 0
6240 * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
6242 PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6243 /*##################################################################### */
6246 * Register : RDIMMCR1 @ 0XFD080154
6249 * PSU_DDR_PHY_RDIMMCR1_RC15 0x0
6251 * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
6252 * PSU_DDR_PHY_RDIMMCR1_RC14 0x0
6254 * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
6255 * PSU_DDR_PHY_RDIMMCR1_RC13 0x0
6257 * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
6258 * PSU_DDR_PHY_RDIMMCR1_RC12 0x0
6260 * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
6261 * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
6262 * PSU_DDR_PHY_RDIMMCR1_RC11 0x0
6264 * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
6265 * PSU_DDR_PHY_RDIMMCR1_RC10 0x2
6267 * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
6268 * PSU_DDR_PHY_RDIMMCR1_RC9 0x0
6270 * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
6271 * trol Word 8 (Additional Input Bus Termination Setting Control Word)
6272 * PSU_DDR_PHY_RDIMMCR1_RC8 0x0
6274 * RDIMM Control Register 1
6275 * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U)
6277 PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U);
6278 /*##################################################################### */
6281 * Register : MR0 @ 0XFD080180
6283 * Reserved. Return zeroes on reads.
6284 * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6
6286 * CA Terminating Rank
6287 * PSU_DDR_PHY_MR0_CATR 0x0
6289 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
6290 * be programmed to 0x0.
6291 * PSU_DDR_PHY_MR0_RSVD_6_5 0x1
6293 * Built-in Self-Test for RZQ
6294 * PSU_DDR_PHY_MR0_RZQI 0x2
6296 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
6297 * be programmed to 0x0.
6298 * PSU_DDR_PHY_MR0_RSVD_2_0 0x0
6300 * LPDDR4 Mode Register 0
6301 * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U)
6303 PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U);
6304 /*##################################################################### */
6307 * Register : MR1 @ 0XFD080184
6309 * Reserved. Return zeroes on reads.
6310 * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3
6312 * Read Postamble Length
6313 * PSU_DDR_PHY_MR1_RDPST 0x0
6315 * Write-recovery for auto-precharge command
6316 * PSU_DDR_PHY_MR1_NWR 0x0
6318 * Read Preamble Length
6319 * PSU_DDR_PHY_MR1_RDPRE 0x0
6321 * Write Preamble Length
6322 * PSU_DDR_PHY_MR1_WRPRE 0x0
6325 * PSU_DDR_PHY_MR1_BL 0x1
6327 * LPDDR4 Mode Register 1
6328 * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U)
6330 PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U);
6331 /*##################################################################### */
6334 * Register : MR2 @ 0XFD080188
6336 * Reserved. Return zeroes on reads.
6337 * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0
6340 * PSU_DDR_PHY_MR2_WRL 0x0
6343 * PSU_DDR_PHY_MR2_WLS 0x0
6346 * PSU_DDR_PHY_MR2_WL 0x4
6349 * PSU_DDR_PHY_MR2_RL 0x0
6351 * LPDDR4 Mode Register 2
6352 * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U)
6354 PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U);
6355 /*##################################################################### */
6358 * Register : MR3 @ 0XFD08018C
6360 * Reserved. Return zeroes on reads.
6361 * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2
6364 * PSU_DDR_PHY_MR3_DBIWR 0x0
6367 * PSU_DDR_PHY_MR3_DBIRD 0x0
6369 * Pull-down Drive Strength
6370 * PSU_DDR_PHY_MR3_PDDS 0x0
6372 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6374 * PSU_DDR_PHY_MR3_RSVD 0x0
6376 * Write Postamble Length
6377 * PSU_DDR_PHY_MR3_WRPST 0x0
6379 * Pull-up Calibration Point
6380 * PSU_DDR_PHY_MR3_PUCAL 0x0
6382 * LPDDR4 Mode Register 3
6383 * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)
6385 PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U);
6386 /*##################################################################### */
6389 * Register : MR4 @ 0XFD080190
6391 * Reserved. Return zeroes on reads.
6392 * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0
6394 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6396 * PSU_DDR_PHY_MR4_RSVD_15_13 0x0
6399 * PSU_DDR_PHY_MR4_WRP 0x0
6402 * PSU_DDR_PHY_MR4_RDP 0x0
6404 * Read Preamble Training Mode
6405 * PSU_DDR_PHY_MR4_RPTM 0x0
6407 * Self Refresh Abort
6408 * PSU_DDR_PHY_MR4_SRA 0x0
6410 * CS to Command Latency Mode
6411 * PSU_DDR_PHY_MR4_CS2CMDL 0x0
6413 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6415 * PSU_DDR_PHY_MR4_RSVD1 0x0
6417 * Internal VREF Monitor
6418 * PSU_DDR_PHY_MR4_IVM 0x0
6420 * Temperature Controlled Refresh Mode
6421 * PSU_DDR_PHY_MR4_TCRM 0x0
6423 * Temperature Controlled Refresh Range
6424 * PSU_DDR_PHY_MR4_TCRR 0x0
6426 * Maximum Power Down Mode
6427 * PSU_DDR_PHY_MR4_MPDM 0x0
6429 * This is a JEDEC reserved bit and is recommended by JEDEC to be programme
6431 * PSU_DDR_PHY_MR4_RSVD_0 0x0
6433 * DDR4 Mode Register 4
6434 * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U)
6436 PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6437 /*##################################################################### */
6440 * Register : MR5 @ 0XFD080194
6442 * Reserved. Return zeroes on reads.
6443 * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0
6445 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6447 * PSU_DDR_PHY_MR5_RSVD 0x0
6450 * PSU_DDR_PHY_MR5_RDBI 0x0
6453 * PSU_DDR_PHY_MR5_WDBI 0x0
6456 * PSU_DDR_PHY_MR5_DM 0x1
6458 * CA Parity Persistent Error
6459 * PSU_DDR_PHY_MR5_CAPPE 0x1
6462 * PSU_DDR_PHY_MR5_RTTPARK 0x3
6464 * ODT Input Buffer during Power Down mode
6465 * PSU_DDR_PHY_MR5_ODTIBPD 0x0
6467 * C/A Parity Error Status
6468 * PSU_DDR_PHY_MR5_CAPES 0x0
6471 * PSU_DDR_PHY_MR5_CRCEC 0x0
6473 * C/A Parity Latency Mode
6474 * PSU_DDR_PHY_MR5_CAPM 0x0
6476 * DDR4 Mode Register 5
6477 * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)
6479 PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U);
6480 /*##################################################################### */
6483 * Register : MR6 @ 0XFD080198
6485 * Reserved. Return zeroes on reads.
6486 * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0
6488 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6490 * PSU_DDR_PHY_MR6_RSVD_15_13 0x0
6492 * CAS_n to CAS_n command delay for same bank group (tCCD_L)
6493 * PSU_DDR_PHY_MR6_TCCDL 0x2
6495 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6497 * PSU_DDR_PHY_MR6_RSVD_9_8 0x0
6499 * VrefDQ Training Enable
6500 * PSU_DDR_PHY_MR6_VDDQTEN 0x0
6502 * VrefDQ Training Range
6503 * PSU_DDR_PHY_MR6_VDQTRG 0x0
6505 * VrefDQ Training Values
6506 * PSU_DDR_PHY_MR6_VDQTVAL 0x19
6508 * DDR4 Mode Register 6
6509 * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U)
6511 PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U);
6512 /*##################################################################### */
6515 * Register : MR11 @ 0XFD0801AC
6517 * Reserved. Return zeroes on reads.
6518 * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0
6520 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6522 * PSU_DDR_PHY_MR11_RSVD 0x0
6524 * Power Down Control
6525 * PSU_DDR_PHY_MR11_PDCTL 0x0
6527 * DQ Bus Receiver On-Die-Termination
6528 * PSU_DDR_PHY_MR11_DQODT 0x0
6530 * LPDDR4 Mode Register 11
6531 * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)
6533 PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6534 /*##################################################################### */
6537 * Register : MR12 @ 0XFD0801B0
6539 * Reserved. Return zeroes on reads.
6540 * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0
6542 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6544 * PSU_DDR_PHY_MR12_RSVD 0x0
6546 * VREF_CA Range Select.
6547 * PSU_DDR_PHY_MR12_VR_CA 0x1
6549 * Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
6550 * PSU_DDR_PHY_MR12_VREF_CA 0xd
6552 * LPDDR4 Mode Register 12
6553 * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)
6555 PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU);
6556 /*##################################################################### */
6559 * Register : MR13 @ 0XFD0801B4
6561 * Reserved. Return zeroes on reads.
6562 * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0
6564 * Frequency Set Point Operation Mode
6565 * PSU_DDR_PHY_MR13_FSPOP 0x0
6567 * Frequency Set Point Write Enable
6568 * PSU_DDR_PHY_MR13_FSPWR 0x0
6571 * PSU_DDR_PHY_MR13_DMD 0x0
6573 * Refresh Rate Option
6574 * PSU_DDR_PHY_MR13_RRO 0x0
6576 * VREF Current Generator
6577 * PSU_DDR_PHY_MR13_VRCG 0x1
6580 * PSU_DDR_PHY_MR13_VRO 0x0
6582 * Read Preamble Training Mode
6583 * PSU_DDR_PHY_MR13_RPT 0x0
6585 * Command Bus Training
6586 * PSU_DDR_PHY_MR13_CBT 0x0
6588 * LPDDR4 Mode Register 13
6589 * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)
6591 PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U);
6592 /*##################################################################### */
6595 * Register : MR14 @ 0XFD0801B8
6597 * Reserved. Return zeroes on reads.
6598 * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0
6600 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6602 * PSU_DDR_PHY_MR14_RSVD 0x0
6604 * VREFDQ Range Selects.
6605 * PSU_DDR_PHY_MR14_VR_DQ 0x1
6607 * Reserved. Return zeroes on reads.
6608 * PSU_DDR_PHY_MR14_VREF_DQ 0xd
6610 * LPDDR4 Mode Register 14
6611 * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)
6613 PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU);
6614 /*##################################################################### */
6617 * Register : MR22 @ 0XFD0801D8
6619 * Reserved. Return zeroes on reads.
6620 * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0
6622 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6624 * PSU_DDR_PHY_MR22_RSVD 0x0
6626 * CA ODT termination disable.
6627 * PSU_DDR_PHY_MR22_ODTD_CA 0x0
6630 * PSU_DDR_PHY_MR22_ODTE_CS 0x0
6633 * PSU_DDR_PHY_MR22_ODTE_CK 0x0
6635 * Controller ODT value for VOH calibration.
6636 * PSU_DDR_PHY_MR22_CODT 0x0
6638 * LPDDR4 Mode Register 22
6639 * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)
6641 PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6642 /*##################################################################### */
6645 * Register : DTCR0 @ 0XFD080200
6647 * Refresh During Training
6648 * PSU_DDR_PHY_DTCR0_RFSHDT 0x8
6650 * Reserved. Return zeroes on reads.
6651 * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
6653 * Data Training Debug Rank Select
6654 * PSU_DDR_PHY_DTCR0_DTDRS 0x0
6656 * Data Training with Early/Extended Gate
6657 * PSU_DDR_PHY_DTCR0_DTEXG 0x0
6659 * Data Training Extended Write DQS
6660 * PSU_DDR_PHY_DTCR0_DTEXD 0x0
6662 * Data Training Debug Step
6663 * PSU_DDR_PHY_DTCR0_DTDSTP 0x0
6665 * Data Training Debug Enable
6666 * PSU_DDR_PHY_DTCR0_DTDEN 0x0
6668 * Data Training Debug Byte Select
6669 * PSU_DDR_PHY_DTCR0_DTDBS 0x0
6671 * Data Training read DBI deskewing configuration
6672 * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
6674 * Reserved. Return zeroes on reads.
6675 * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
6677 * Data Training Write Bit Deskew Data Mask
6678 * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1
6680 * Refreshes Issued During Entry to Training
6681 * PSU_DDR_PHY_DTCR0_RFSHEN 0x1
6683 * Data Training Compare Data
6684 * PSU_DDR_PHY_DTCR0_DTCMPD 0x1
6686 * Data Training Using MPR
6687 * PSU_DDR_PHY_DTCR0_DTMPR 0x1
6689 * Reserved. Return zeroes on reads.
6690 * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0
6692 * Data Training Repeat Number
6693 * PSU_DDR_PHY_DTCR0_DTRPTN 0x7
6695 * Data Training Configuration Register 0
6696 * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
6698 PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U);
6699 /*##################################################################### */
6702 * Register : DTCR1 @ 0XFD080204
6705 * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0
6708 * PSU_DDR_PHY_DTCR1_RANKEN 0x1
6710 * Reserved. Return zeroes on reads.
6711 * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0
6713 * Data Training Rank
6714 * PSU_DDR_PHY_DTCR1_DTRANK 0x0
6716 * Reserved. Return zeroes on reads.
6717 * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0
6719 * Read Leveling Gate Sampling Difference
6720 * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2
6722 * Reserved. Return zeroes on reads.
6723 * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0
6725 * Read Leveling Gate Shift
6726 * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3
6728 * Reserved. Return zeroes on reads.
6729 * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0
6731 * Read Preamble Training enable
6732 * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1
6734 * Read Leveling Enable
6735 * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1
6737 * Basic Gate Training Enable
6738 * PSU_DDR_PHY_DTCR1_BSTEN 0x0
6740 * Data Training Configuration Register 1
6741 * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U)
6743 PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U);
6744 /*##################################################################### */
6747 * Register : CATR0 @ 0XFD080240
6749 * Reserved. Return zeroes on reads.
6750 * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0
6752 * Minimum time (in terms of number of dram clocks) between two consectuve
6753 * CA calibration command
6754 * PSU_DDR_PHY_CATR0_CACD 0x14
6756 * Reserved. Return zeroes on reads.
6757 * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0
6759 * Minimum time (in terms of number of dram clocks) PUB should wait before
6760 * sampling the CA response after Calibration command has been sent to the
6762 * PSU_DDR_PHY_CATR0_CAADR 0x10
6764 * CA_1 Response Byte Lane 1
6765 * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5
6767 * CA_1 Response Byte Lane 0
6768 * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4
6770 * CA Training Register 0
6771 * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U)
6773 PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U);
6774 /*##################################################################### */
6777 * Register : DQSDR0 @ 0XFD080250
6779 * Number of delay taps by which the DQS gate LCDL will be updated when DQS
6781 * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0
6783 * Drift Impedance Update
6784 * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0
6787 * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0
6789 * Reserved. Return zeroes on reads.
6790 * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0
6792 * Drift Read Spacing
6793 * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0
6795 * Drift Back-to-Back Reads
6796 * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8
6799 * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8
6801 * Reserved. Return zeroes on reads.
6802 * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0
6805 * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0
6807 * DQS Drift Update Mode
6808 * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0
6810 * DQS Drift Detection Mode
6811 * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0
6813 * DQS Drift Detection Enable
6814 * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0
6816 * DQS Drift Register 0
6817 * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U)
6819 PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U);
6820 /*##################################################################### */
6823 * Register : BISTLSR @ 0XFD080414
6825 * LFSR seed for pseudo-random BIST patterns
6826 * PSU_DDR_PHY_BISTLSR_SEED 0x12341000
6828 * BIST LFSR Seed Register
6829 * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
6831 PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U);
6832 /*##################################################################### */
6835 * Register : RIOCR5 @ 0XFD0804F4
6837 * Reserved. Return zeroes on reads.
6838 * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0
6840 * Reserved. Return zeros on reads.
6841 * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0
6843 * SDRAM On-die Termination Output Enable (OE) Mode Selection.
6844 * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5
6846 * Rank I/O Configuration Register 5
6847 * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)
6849 PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U);
6850 /*##################################################################### */
6853 * Register : ACIOCR0 @ 0XFD080500
6855 * Address/Command Slew Rate (D3F I/O Only)
6856 * PSU_DDR_PHY_ACIOCR0_ACSR 0x0
6858 * SDRAM Reset I/O Mode
6859 * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1
6861 * SDRAM Reset Power Down Receiver
6862 * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1
6864 * Reserved. Return zeroes on reads.
6865 * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0
6867 * SDRAM Reset On-Die Termination
6868 * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0
6870 * Reserved. Return zeroes on reads.
6871 * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0
6873 * CK Duty Cycle Correction
6874 * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0
6876 * AC Power Down Receiver Mode
6877 * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2
6879 * AC On-die Termination Mode
6880 * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2
6882 * Reserved. Return zeroes on reads.
6883 * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0
6885 * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
6886 * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0
6888 * AC I/O Configuration Register 0
6889 * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U)
6891 PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U);
6892 /*##################################################################### */
6895 * Register : ACIOCR2 @ 0XFD080508
6897 * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
6899 * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0
6901 * Clock gating for Output Enable D slices [0]
6902 * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0
6904 * Clock gating for Power Down Receiver D slices [0]
6905 * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0
6907 * Clock gating for Termination Enable D slices [0]
6908 * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0
6910 * Clock gating for CK# D slices [1:0]
6911 * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2
6913 * Clock gating for CK D slices [1:0]
6914 * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2
6916 * Clock gating for AC D slices [23:0]
6917 * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0
6919 * AC I/O Configuration Register 2
6920 * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)
6922 PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U);
6923 /*##################################################################### */
6926 * Register : ACIOCR3 @ 0XFD08050C
6928 * SDRAM Parity Output Enable (OE) Mode Selection
6929 * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0
6931 * SDRAM Bank Group Output Enable (OE) Mode Selection
6932 * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0
6934 * SDRAM Bank Address Output Enable (OE) Mode Selection
6935 * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0
6937 * SDRAM A[17] Output Enable (OE) Mode Selection
6938 * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0
6940 * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
6941 * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0
6943 * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
6944 * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0
6946 * Reserved. Return zeroes on reads.
6947 * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0
6949 * Reserved. Return zeros on reads.
6950 * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0
6952 * SDRAM CK Output Enable (OE) Mode Selection.
6953 * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9
6955 * AC I/O Configuration Register 3
6956 * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)
6958 PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U);
6959 /*##################################################################### */
6962 * Register : ACIOCR4 @ 0XFD080510
6964 * Clock gating for AC LB slices and loopback read valid slices
6965 * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0
6967 * Clock gating for Output Enable D slices [1]
6968 * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0
6970 * Clock gating for Power Down Receiver D slices [1]
6971 * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0
6973 * Clock gating for Termination Enable D slices [1]
6974 * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0
6976 * Clock gating for CK# D slices [3:2]
6977 * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2
6979 * Clock gating for CK D slices [3:2]
6980 * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2
6982 * Clock gating for AC D slices [47:24]
6983 * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0
6985 * AC I/O Configuration Register 4
6986 * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)
6988 PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U);
6989 /*##################################################################### */
6992 * Register : IOVCR0 @ 0XFD080520
6994 * Reserved. Return zeroes on reads.
6995 * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0
6997 * Address/command lane VREF Pad Enable
6998 * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0
7000 * Address/command lane Internal VREF Enable
7001 * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0
7003 * Address/command lane Single-End VREF Enable
7004 * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1
7006 * Address/command lane Internal VREF Enable
7007 * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1
7009 * External VREF generato REFSEL range select
7010 * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0
7012 * Address/command lane External VREF Select
7013 * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0
7015 * Single ended VREF generator REFSEL range select
7016 * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1
7018 * Address/command lane Single-End VREF Select
7019 * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30
7021 * Internal VREF generator REFSEL ragne select
7022 * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1
7024 * REFSEL Control for internal AC IOs
7025 * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e
7027 * IO VREF Control Register 0
7028 * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU)
7030 PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU);
7031 /*##################################################################### */
7034 * Register : VTCR0 @ 0XFD080528
7036 * Number of ctl_clk required to meet (> 150ns) timing requirements during
7037 * DRAM DQ VREF training
7038 * PSU_DDR_PHY_VTCR0_TVREF 0x7
7040 * DRM DQ VREF training Enable
7041 * PSU_DDR_PHY_VTCR0_DVEN 0x1
7043 * Per Device Addressability Enable
7044 * PSU_DDR_PHY_VTCR0_PDAEN 0x1
7046 * Reserved. Returns zeroes on reads.
7047 * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0
7050 * PSU_DDR_PHY_VTCR0_VWCR 0x4
7052 * DRAM DQ VREF step size used during DRAM VREF training
7053 * PSU_DDR_PHY_VTCR0_DVSS 0x0
7055 * Maximum VREF limit value used during DRAM VREF training
7056 * PSU_DDR_PHY_VTCR0_DVMAX 0x32
7058 * Minimum VREF limit value used during DRAM VREF training
7059 * PSU_DDR_PHY_VTCR0_DVMIN 0x0
7061 * Initial DRAM DQ VREF value used during DRAM VREF training
7062 * PSU_DDR_PHY_VTCR0_DVINIT 0x19
7064 * VREF Training Control Register 0
7065 * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)
7067 PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U);
7068 /*##################################################################### */
7071 * Register : VTCR1 @ 0XFD08052C
7073 * Host VREF step size used during VREF training. The register value of N i
7074 * ndicates step size of (N+1)
7075 * PSU_DDR_PHY_VTCR1_HVSS 0x0
7077 * Reserved. Returns zeroes on reads.
7078 * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0
7080 * Maximum VREF limit value used during DRAM VREF training.
7081 * PSU_DDR_PHY_VTCR1_HVMAX 0x7f
7083 * Reserved. Returns zeroes on reads.
7084 * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0
7086 * Minimum VREF limit value used during DRAM VREF training.
7087 * PSU_DDR_PHY_VTCR1_HVMIN 0x0
7089 * Reserved. Returns zeroes on reads.
7090 * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0
7092 * Static Host Vref Rank Value
7093 * PSU_DDR_PHY_VTCR1_SHRNK 0x0
7095 * Static Host Vref Rank Enable
7096 * PSU_DDR_PHY_VTCR1_SHREN 0x1
7098 * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
7099 * ements during Host IO VREF training
7100 * PSU_DDR_PHY_VTCR1_TVREFIO 0x7
7102 * Eye LCDL Offset value for VREF training
7103 * PSU_DDR_PHY_VTCR1_EOFF 0x0
7105 * Number of LCDL Eye points for which VREF training is repeated
7106 * PSU_DDR_PHY_VTCR1_ENUM 0x0
7108 * HOST (IO) internal VREF training Enable
7109 * PSU_DDR_PHY_VTCR1_HVEN 0x1
7111 * Host IO Type Control
7112 * PSU_DDR_PHY_VTCR1_HVIO 0x1
7114 * VREF Training Control Register 1
7115 * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
7117 PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U);
7118 /*##################################################################### */
7121 * Register : ACBDLR1 @ 0XFD080544
7123 * Reserved. Return zeroes on reads.
7124 * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
7126 * Delay select for the BDL on Parity.
7127 * PSU_DDR_PHY_ACBDLR1_PARBD 0x0
7129 * Reserved. Return zeroes on reads.
7130 * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
7132 * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
7134 * PSU_DDR_PHY_ACBDLR1_A16BD 0x0
7136 * Reserved. Return zeroes on reads.
7137 * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
7139 * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
7140 * s pin is connected to CAS.
7141 * PSU_DDR_PHY_ACBDLR1_A17BD 0x0
7143 * Reserved. Return zeroes on reads.
7144 * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
7146 * Delay select for the BDL on ACTN.
7147 * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
7149 * AC Bit Delay Line Register 1
7150 * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
7152 PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7153 /*##################################################################### */
7156 * Register : ACBDLR2 @ 0XFD080548
7158 * Reserved. Return zeroes on reads.
7159 * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
7161 * Delay select for the BDL on BG[1].
7162 * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
7164 * Reserved. Return zeroes on reads.
7165 * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
7167 * Delay select for the BDL on BG[0].
7168 * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
7170 * Reser.ved Return zeroes on reads.
7171 * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
7173 * Delay select for the BDL on BA[1].
7174 * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
7176 * Reserved. Return zeroes on reads.
7177 * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
7179 * Delay select for the BDL on BA[0].
7180 * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
7182 * AC Bit Delay Line Register 2
7183 * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
7185 PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7186 /*##################################################################### */
7189 * Register : ACBDLR6 @ 0XFD080558
7191 * Reserved. Return zeroes on reads.
7192 * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
7194 * Delay select for the BDL on Address A[3].
7195 * PSU_DDR_PHY_ACBDLR6_A03BD 0x0
7197 * Reserved. Return zeroes on reads.
7198 * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
7200 * Delay select for the BDL on Address A[2].
7201 * PSU_DDR_PHY_ACBDLR6_A02BD 0x0
7203 * Reserved. Return zeroes on reads.
7204 * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
7206 * Delay select for the BDL on Address A[1].
7207 * PSU_DDR_PHY_ACBDLR6_A01BD 0x0
7209 * Reserved. Return zeroes on reads.
7210 * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
7212 * Delay select for the BDL on Address A[0].
7213 * PSU_DDR_PHY_ACBDLR6_A00BD 0x0
7215 * AC Bit Delay Line Register 6
7216 * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
7218 PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7219 /*##################################################################### */
7222 * Register : ACBDLR7 @ 0XFD08055C
7224 * Reserved. Return zeroes on reads.
7225 * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
7227 * Delay select for the BDL on Address A[7].
7228 * PSU_DDR_PHY_ACBDLR7_A07BD 0x0
7230 * Reserved. Return zeroes on reads.
7231 * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
7233 * Delay select for the BDL on Address A[6].
7234 * PSU_DDR_PHY_ACBDLR7_A06BD 0x0
7236 * Reserved. Return zeroes on reads.
7237 * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0
7239 * Delay select for the BDL on Address A[5].
7240 * PSU_DDR_PHY_ACBDLR7_A05BD 0x0
7242 * Reserved. Return zeroes on reads.
7243 * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0
7245 * Delay select for the BDL on Address A[4].
7246 * PSU_DDR_PHY_ACBDLR7_A04BD 0x0
7248 * AC Bit Delay Line Register 7
7249 * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)
7251 PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7252 /*##################################################################### */
7255 * Register : ACBDLR8 @ 0XFD080560
7257 * Reserved. Return zeroes on reads.
7258 * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0
7260 * Delay select for the BDL on Address A[11].
7261 * PSU_DDR_PHY_ACBDLR8_A11BD 0x0
7263 * Reserved. Return zeroes on reads.
7264 * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0
7266 * Delay select for the BDL on Address A[10].
7267 * PSU_DDR_PHY_ACBDLR8_A10BD 0x0
7269 * Reserved. Return zeroes on reads.
7270 * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0
7272 * Delay select for the BDL on Address A[9].
7273 * PSU_DDR_PHY_ACBDLR8_A09BD 0x0
7275 * Reserved. Return zeroes on reads.
7276 * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0
7278 * Delay select for the BDL on Address A[8].
7279 * PSU_DDR_PHY_ACBDLR8_A08BD 0x0
7281 * AC Bit Delay Line Register 8
7282 * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U)
7284 PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7285 /*##################################################################### */
7288 * Register : ACBDLR9 @ 0XFD080564
7290 * Reserved. Return zeroes on reads.
7291 * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
7293 * Delay select for the BDL on Address A[15].
7294 * PSU_DDR_PHY_ACBDLR9_A15BD 0x0
7296 * Reserved. Return zeroes on reads.
7297 * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
7299 * Delay select for the BDL on Address A[14].
7300 * PSU_DDR_PHY_ACBDLR9_A14BD 0x0
7302 * Reserved. Return zeroes on reads.
7303 * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
7305 * Delay select for the BDL on Address A[13].
7306 * PSU_DDR_PHY_ACBDLR9_A13BD 0x0
7308 * Reserved. Return zeroes on reads.
7309 * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
7311 * Delay select for the BDL on Address A[12].
7312 * PSU_DDR_PHY_ACBDLR9_A12BD 0x0
7314 * AC Bit Delay Line Register 9
7315 * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
7317 PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7318 /*##################################################################### */
7321 * Register : ZQCR @ 0XFD080680
7323 * Reserved. Return zeroes on reads.
7324 * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
7327 * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0
7329 * Programmable Wait for Frequency B
7330 * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11
7332 * Programmable Wait for Frequency A
7333 * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15
7335 * ZQ VREF Pad Enable
7336 * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0
7338 * ZQ Internal VREF Enable
7339 * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1
7341 * Choice of termination mode
7342 * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1
7344 * Force ZCAL VT update
7345 * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0
7348 * PSU_DDR_PHY_ZQCR_IODLMT 0x2
7350 * Averaging algorithm enable, if set, enables averaging algorithm
7351 * PSU_DDR_PHY_ZQCR_AVGEN 0x1
7353 * Maximum number of averaging rounds to be used by averaging algorithm
7354 * PSU_DDR_PHY_ZQCR_AVGMAX 0x2
7356 * ZQ Calibration Type
7357 * PSU_DDR_PHY_ZQCR_ZCALT 0x0
7360 * PSU_DDR_PHY_ZQCR_ZQPD 0x0
7362 * ZQ Impedance Control Register
7363 * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U)
7365 PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U);
7366 /*##################################################################### */
7369 * Register : ZQ0PR0 @ 0XFD080684
7371 * Pull-down drive strength ZCTRL over-ride enable
7372 * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0
7374 * Pull-up drive strength ZCTRL over-ride enable
7375 * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0
7377 * Pull-down termination ZCTRL over-ride enable
7378 * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0
7380 * Pull-up termination ZCTRL over-ride enable
7381 * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0
7383 * Calibration segment bypass
7384 * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0
7386 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
7387 * is driven by the PUB
7388 * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0
7390 * Termination adjustment
7391 * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0
7393 * Pulldown drive strength adjustment
7394 * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0
7396 * Pullup drive strength adjustment
7397 * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0
7399 * DRAM Impedance Divide Ratio
7400 * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7
7402 * HOST Impedance Divide Ratio
7403 * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9
7405 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
7406 * ve strength calibration)
7407 * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd
7409 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
7410 * strength calibration)
7411 * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd
7413 * ZQ n Impedance Control Program Register 0
7414 * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU)
7416 PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU);
7417 /*##################################################################### */
7420 * Register : ZQ0OR0 @ 0XFD080694
7422 * Reserved. Return zeros on reads.
7423 * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0
7425 * Override value for the pull-up output impedance
7426 * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1
7428 * Reserved. Return zeros on reads.
7429 * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0
7431 * Override value for the pull-down output impedance
7432 * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210
7434 * ZQ n Impedance Control Override Data Register 0
7435 * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)
7437 PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U);
7438 /*##################################################################### */
7441 * Register : ZQ0OR1 @ 0XFD080698
7443 * Reserved. Return zeros on reads.
7444 * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0
7446 * Override value for the pull-up termination
7447 * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1
7449 * Reserved. Return zeros on reads.
7450 * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0
7452 * Override value for the pull-down termination
7453 * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0
7455 * ZQ n Impedance Control Override Data Register 1
7456 * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)
7458 PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U);
7459 /*##################################################################### */
7462 * Register : ZQ1PR0 @ 0XFD0806A4
7464 * Pull-down drive strength ZCTRL over-ride enable
7465 * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0
7467 * Pull-up drive strength ZCTRL over-ride enable
7468 * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0
7470 * Pull-down termination ZCTRL over-ride enable
7471 * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0
7473 * Pull-up termination ZCTRL over-ride enable
7474 * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0
7476 * Calibration segment bypass
7477 * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0
7479 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
7480 * is driven by the PUB
7481 * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0
7483 * Termination adjustment
7484 * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0
7486 * Pulldown drive strength adjustment
7487 * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1
7489 * Pullup drive strength adjustment
7490 * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0
7492 * DRAM Impedance Divide Ratio
7493 * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7
7495 * HOST Impedance Divide Ratio
7496 * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb
7498 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
7499 * ve strength calibration)
7500 * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd
7502 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
7503 * strength calibration)
7504 * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb
7506 * ZQ n Impedance Control Program Register 0
7507 * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)
7509 PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU);
7510 /*##################################################################### */
7513 * Register : DX0GCR0 @ 0XFD080700
7515 * Calibration Bypass
7516 * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0
7518 * Master Delay Line Enable
7519 * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1
7521 * Configurable ODT(TE) Phase Shift
7522 * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0
7524 * DQS Duty Cycle Correction
7525 * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0
7527 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7528 * input for the respective bypte lane of the PHY
7529 * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8
7531 * Reserved. Return zeroes on reads.
7532 * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0
7534 * DQSNSE Power Down Receiver
7535 * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0
7537 * DQSSE Power Down Receiver
7538 * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0
7540 * RTT On Additive Latency
7541 * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0
7544 * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3
7546 * Configurable PDR Phase Shift
7547 * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0
7550 * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0
7552 * DQSG Power Down Receiver
7553 * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0
7555 * Reserved. Return zeroes on reads.
7556 * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0
7558 * DQSG On-Die Termination
7559 * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0
7561 * DQSG Output Enable
7562 * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1
7564 * Reserved. Return zeroes on reads.
7565 * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0
7567 * DATX8 n General Configuration Register 0
7568 * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U)
7570 PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7571 /*##################################################################### */
7574 * Register : DX0GCR4 @ 0XFD080710
7576 * Byte lane VREF IOM (Used only by D4MU IOs)
7577 * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0
7579 * Byte Lane VREF Pad Enable
7580 * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0
7582 * Byte Lane Internal VREF Enable
7583 * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3
7585 * Byte Lane Single-End VREF Enable
7586 * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1
7588 * Reserved. Returns zeros on reads.
7589 * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0
7591 * External VREF generator REFSEL range select
7592 * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0
7594 * Byte Lane External VREF Select
7595 * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0
7597 * Single ended VREF generator REFSEL range select
7598 * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1
7600 * Byte Lane Single-End VREF Select
7601 * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30
7603 * Reserved. Returns zeros on reads.
7604 * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0
7606 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7607 * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf
7609 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7610 * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0
7612 * DATX8 n General Configuration Register 4
7613 * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)
7615 PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7616 /*##################################################################### */
7619 * Register : DX0GCR5 @ 0XFD080714
7621 * Reserved. Returns zeros on reads.
7622 * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0
7624 * Byte Lane internal VREF Select for Rank 3
7625 * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9
7627 * Reserved. Returns zeros on reads.
7628 * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0
7630 * Byte Lane internal VREF Select for Rank 2
7631 * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9
7633 * Reserved. Returns zeros on reads.
7634 * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
7636 * Byte Lane internal VREF Select for Rank 1
7637 * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
7639 * Reserved. Returns zeros on reads.
7640 * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
7642 * Byte Lane internal VREF Select for Rank 0
7643 * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
7645 * DATX8 n General Configuration Register 5
7646 * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U)
7648 PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
7649 /*##################################################################### */
7652 * Register : DX0GCR6 @ 0XFD080718
7654 * Reserved. Returns zeros on reads.
7655 * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0
7657 * DRAM DQ VREF Select for Rank3
7658 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9
7660 * Reserved. Returns zeros on reads.
7661 * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0
7663 * DRAM DQ VREF Select for Rank2
7664 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9
7666 * Reserved. Returns zeros on reads.
7667 * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0
7669 * DRAM DQ VREF Select for Rank1
7670 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b
7672 * Reserved. Returns zeros on reads.
7673 * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0
7675 * DRAM DQ VREF Select for Rank0
7676 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b
7678 * DATX8 n General Configuration Register 6
7679 * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)
7681 PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
7682 /*##################################################################### */
7685 * Register : DX1GCR0 @ 0XFD080800
7687 * Calibration Bypass
7688 * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0
7690 * Master Delay Line Enable
7691 * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1
7693 * Configurable ODT(TE) Phase Shift
7694 * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0
7696 * DQS Duty Cycle Correction
7697 * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0
7699 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7700 * input for the respective bypte lane of the PHY
7701 * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8
7703 * Reserved. Return zeroes on reads.
7704 * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0
7706 * DQSNSE Power Down Receiver
7707 * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0
7709 * DQSSE Power Down Receiver
7710 * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0
7712 * RTT On Additive Latency
7713 * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0
7716 * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3
7718 * Configurable PDR Phase Shift
7719 * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0
7722 * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0
7724 * DQSG Power Down Receiver
7725 * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0
7727 * Reserved. Return zeroes on reads.
7728 * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0
7730 * DQSG On-Die Termination
7731 * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0
7733 * DQSG Output Enable
7734 * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1
7736 * Reserved. Return zeroes on reads.
7737 * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0
7739 * DATX8 n General Configuration Register 0
7740 * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U)
7742 PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7743 /*##################################################################### */
7746 * Register : DX1GCR4 @ 0XFD080810
7748 * Byte lane VREF IOM (Used only by D4MU IOs)
7749 * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0
7751 * Byte Lane VREF Pad Enable
7752 * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0
7754 * Byte Lane Internal VREF Enable
7755 * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3
7757 * Byte Lane Single-End VREF Enable
7758 * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1
7760 * Reserved. Returns zeros on reads.
7761 * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0
7763 * External VREF generator REFSEL range select
7764 * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0
7766 * Byte Lane External VREF Select
7767 * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0
7769 * Single ended VREF generator REFSEL range select
7770 * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1
7772 * Byte Lane Single-End VREF Select
7773 * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30
7775 * Reserved. Returns zeros on reads.
7776 * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0
7778 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7779 * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf
7781 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7782 * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0
7784 * DATX8 n General Configuration Register 4
7785 * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)
7787 PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7788 /*##################################################################### */
7791 * Register : DX1GCR5 @ 0XFD080814
7793 * Reserved. Returns zeros on reads.
7794 * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0
7796 * Byte Lane internal VREF Select for Rank 3
7797 * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9
7799 * Reserved. Returns zeros on reads.
7800 * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0
7802 * Byte Lane internal VREF Select for Rank 2
7803 * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9
7805 * Reserved. Returns zeros on reads.
7806 * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
7808 * Byte Lane internal VREF Select for Rank 1
7809 * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
7811 * Reserved. Returns zeros on reads.
7812 * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
7814 * Byte Lane internal VREF Select for Rank 0
7815 * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
7817 * DATX8 n General Configuration Register 5
7818 * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U)
7820 PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
7821 /*##################################################################### */
7824 * Register : DX1GCR6 @ 0XFD080818
7826 * Reserved. Returns zeros on reads.
7827 * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0
7829 * DRAM DQ VREF Select for Rank3
7830 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9
7832 * Reserved. Returns zeros on reads.
7833 * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0
7835 * DRAM DQ VREF Select for Rank2
7836 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9
7838 * Reserved. Returns zeros on reads.
7839 * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0
7841 * DRAM DQ VREF Select for Rank1
7842 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b
7844 * Reserved. Returns zeros on reads.
7845 * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0
7847 * DRAM DQ VREF Select for Rank0
7848 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b
7850 * DATX8 n General Configuration Register 6
7851 * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)
7853 PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
7854 /*##################################################################### */
7857 * Register : DX2GCR0 @ 0XFD080900
7859 * Calibration Bypass
7860 * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0
7862 * Master Delay Line Enable
7863 * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1
7865 * Configurable ODT(TE) Phase Shift
7866 * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0
7868 * DQS Duty Cycle Correction
7869 * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0
7871 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7872 * input for the respective bypte lane of the PHY
7873 * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8
7875 * Reserved. Return zeroes on reads.
7876 * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0
7878 * DQSNSE Power Down Receiver
7879 * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0
7881 * DQSSE Power Down Receiver
7882 * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0
7884 * RTT On Additive Latency
7885 * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0
7888 * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3
7890 * Configurable PDR Phase Shift
7891 * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0
7894 * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0
7896 * DQSG Power Down Receiver
7897 * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0
7899 * Reserved. Return zeroes on reads.
7900 * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0
7902 * DQSG On-Die Termination
7903 * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0
7905 * DQSG Output Enable
7906 * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1
7908 * Reserved. Return zeroes on reads.
7909 * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0
7911 * DATX8 n General Configuration Register 0
7912 * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U)
7914 PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7915 /*##################################################################### */
7918 * Register : DX2GCR1 @ 0XFD080904
7920 * Enables the PDR mode for DQ[7:0]
7921 * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0
7923 * Reserved. Returns zeroes on reads.
7924 * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0
7926 * Select the delayed or non-delayed read data strobe #
7927 * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1
7929 * Select the delayed or non-delayed read data strobe
7930 * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1
7932 * Enables Read Data Strobe in a byte lane
7933 * PSU_DDR_PHY_DX2GCR1_OEEN 0x1
7935 * Enables PDR in a byte lane
7936 * PSU_DDR_PHY_DX2GCR1_PDREN 0x1
7938 * Enables ODT/TE in a byte lane
7939 * PSU_DDR_PHY_DX2GCR1_TEEN 0x1
7941 * Enables Write Data strobe in a byte lane
7942 * PSU_DDR_PHY_DX2GCR1_DSEN 0x1
7944 * Enables DM pin in a byte lane
7945 * PSU_DDR_PHY_DX2GCR1_DMEN 0x1
7947 * Enables DQ corresponding to each bit in a byte
7948 * PSU_DDR_PHY_DX2GCR1_DQEN 0xff
7950 * DATX8 n General Configuration Register 1
7951 * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)
7953 PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
7954 /*##################################################################### */
7957 * Register : DX2GCR4 @ 0XFD080910
7959 * Byte lane VREF IOM (Used only by D4MU IOs)
7960 * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0
7962 * Byte Lane VREF Pad Enable
7963 * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0
7965 * Byte Lane Internal VREF Enable
7966 * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3
7968 * Byte Lane Single-End VREF Enable
7969 * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1
7971 * Reserved. Returns zeros on reads.
7972 * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0
7974 * External VREF generator REFSEL range select
7975 * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0
7977 * Byte Lane External VREF Select
7978 * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0
7980 * Single ended VREF generator REFSEL range select
7981 * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1
7983 * Byte Lane Single-End VREF Select
7984 * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30
7986 * Reserved. Returns zeros on reads.
7987 * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0
7989 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7990 * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf
7992 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7993 * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0
7995 * DATX8 n General Configuration Register 4
7996 * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)
7998 PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7999 /*##################################################################### */
8002 * Register : DX2GCR5 @ 0XFD080914
8004 * Reserved. Returns zeros on reads.
8005 * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0
8007 * Byte Lane internal VREF Select for Rank 3
8008 * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9
8010 * Reserved. Returns zeros on reads.
8011 * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0
8013 * Byte Lane internal VREF Select for Rank 2
8014 * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9
8016 * Reserved. Returns zeros on reads.
8017 * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
8019 * Byte Lane internal VREF Select for Rank 1
8020 * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
8022 * Reserved. Returns zeros on reads.
8023 * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
8025 * Byte Lane internal VREF Select for Rank 0
8026 * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
8028 * DATX8 n General Configuration Register 5
8029 * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U)
8031 PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8032 /*##################################################################### */
8035 * Register : DX2GCR6 @ 0XFD080918
8037 * Reserved. Returns zeros on reads.
8038 * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0
8040 * DRAM DQ VREF Select for Rank3
8041 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9
8043 * Reserved. Returns zeros on reads.
8044 * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0
8046 * DRAM DQ VREF Select for Rank2
8047 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9
8049 * Reserved. Returns zeros on reads.
8050 * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0
8052 * DRAM DQ VREF Select for Rank1
8053 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b
8055 * Reserved. Returns zeros on reads.
8056 * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0
8058 * DRAM DQ VREF Select for Rank0
8059 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b
8061 * DATX8 n General Configuration Register 6
8062 * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)
8064 PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8065 /*##################################################################### */
8068 * Register : DX3GCR0 @ 0XFD080A00
8070 * Calibration Bypass
8071 * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0
8073 * Master Delay Line Enable
8074 * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1
8076 * Configurable ODT(TE) Phase Shift
8077 * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0
8079 * DQS Duty Cycle Correction
8080 * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0
8082 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8083 * input for the respective bypte lane of the PHY
8084 * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8
8086 * Reserved. Return zeroes on reads.
8087 * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0
8089 * DQSNSE Power Down Receiver
8090 * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0
8092 * DQSSE Power Down Receiver
8093 * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0
8095 * RTT On Additive Latency
8096 * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0
8099 * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3
8101 * Configurable PDR Phase Shift
8102 * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0
8105 * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0
8107 * DQSG Power Down Receiver
8108 * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0
8110 * Reserved. Return zeroes on reads.
8111 * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0
8113 * DQSG On-Die Termination
8114 * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0
8116 * DQSG Output Enable
8117 * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1
8119 * Reserved. Return zeroes on reads.
8120 * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0
8122 * DATX8 n General Configuration Register 0
8123 * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)
8125 PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8126 /*##################################################################### */
8129 * Register : DX3GCR1 @ 0XFD080A04
8131 * Enables the PDR mode for DQ[7:0]
8132 * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0
8134 * Reserved. Returns zeroes on reads.
8135 * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0
8137 * Select the delayed or non-delayed read data strobe #
8138 * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1
8140 * Select the delayed or non-delayed read data strobe
8141 * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1
8143 * Enables Read Data Strobe in a byte lane
8144 * PSU_DDR_PHY_DX3GCR1_OEEN 0x1
8146 * Enables PDR in a byte lane
8147 * PSU_DDR_PHY_DX3GCR1_PDREN 0x1
8149 * Enables ODT/TE in a byte lane
8150 * PSU_DDR_PHY_DX3GCR1_TEEN 0x1
8152 * Enables Write Data strobe in a byte lane
8153 * PSU_DDR_PHY_DX3GCR1_DSEN 0x1
8155 * Enables DM pin in a byte lane
8156 * PSU_DDR_PHY_DX3GCR1_DMEN 0x1
8158 * Enables DQ corresponding to each bit in a byte
8159 * PSU_DDR_PHY_DX3GCR1_DQEN 0xff
8161 * DATX8 n General Configuration Register 1
8162 * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)
8164 PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8165 /*##################################################################### */
8168 * Register : DX3GCR4 @ 0XFD080A10
8170 * Byte lane VREF IOM (Used only by D4MU IOs)
8171 * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0
8173 * Byte Lane VREF Pad Enable
8174 * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0
8176 * Byte Lane Internal VREF Enable
8177 * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3
8179 * Byte Lane Single-End VREF Enable
8180 * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1
8182 * Reserved. Returns zeros on reads.
8183 * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0
8185 * External VREF generator REFSEL range select
8186 * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0
8188 * Byte Lane External VREF Select
8189 * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0
8191 * Single ended VREF generator REFSEL range select
8192 * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1
8194 * Byte Lane Single-End VREF Select
8195 * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30
8197 * Reserved. Returns zeros on reads.
8198 * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0
8200 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8201 * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf
8203 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8204 * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0
8206 * DATX8 n General Configuration Register 4
8207 * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)
8209 PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8210 /*##################################################################### */
8213 * Register : DX3GCR5 @ 0XFD080A14
8215 * Reserved. Returns zeros on reads.
8216 * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0
8218 * Byte Lane internal VREF Select for Rank 3
8219 * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9
8221 * Reserved. Returns zeros on reads.
8222 * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0
8224 * Byte Lane internal VREF Select for Rank 2
8225 * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9
8227 * Reserved. Returns zeros on reads.
8228 * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
8230 * Byte Lane internal VREF Select for Rank 1
8231 * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
8233 * Reserved. Returns zeros on reads.
8234 * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
8236 * Byte Lane internal VREF Select for Rank 0
8237 * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
8239 * DATX8 n General Configuration Register 5
8240 * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)
8242 PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8243 /*##################################################################### */
8246 * Register : DX3GCR6 @ 0XFD080A18
8248 * Reserved. Returns zeros on reads.
8249 * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0
8251 * DRAM DQ VREF Select for Rank3
8252 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9
8254 * Reserved. Returns zeros on reads.
8255 * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0
8257 * DRAM DQ VREF Select for Rank2
8258 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9
8260 * Reserved. Returns zeros on reads.
8261 * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0
8263 * DRAM DQ VREF Select for Rank1
8264 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b
8266 * Reserved. Returns zeros on reads.
8267 * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0
8269 * DRAM DQ VREF Select for Rank0
8270 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b
8272 * DATX8 n General Configuration Register 6
8273 * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)
8275 PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8276 /*##################################################################### */
8279 * Register : DX4GCR0 @ 0XFD080B00
8281 * Calibration Bypass
8282 * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0
8284 * Master Delay Line Enable
8285 * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1
8287 * Configurable ODT(TE) Phase Shift
8288 * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0
8290 * DQS Duty Cycle Correction
8291 * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0
8293 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8294 * input for the respective bypte lane of the PHY
8295 * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8
8297 * Reserved. Return zeroes on reads.
8298 * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0
8300 * DQSNSE Power Down Receiver
8301 * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0
8303 * DQSSE Power Down Receiver
8304 * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0
8306 * RTT On Additive Latency
8307 * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0
8310 * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3
8312 * Configurable PDR Phase Shift
8313 * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0
8316 * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0
8318 * DQSG Power Down Receiver
8319 * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0
8321 * Reserved. Return zeroes on reads.
8322 * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0
8324 * DQSG On-Die Termination
8325 * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0
8327 * DQSG Output Enable
8328 * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1
8330 * Reserved. Return zeroes on reads.
8331 * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0
8333 * DATX8 n General Configuration Register 0
8334 * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)
8336 PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8337 /*##################################################################### */
8340 * Register : DX4GCR1 @ 0XFD080B04
8342 * Enables the PDR mode for DQ[7:0]
8343 * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0
8345 * Reserved. Returns zeroes on reads.
8346 * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0
8348 * Select the delayed or non-delayed read data strobe #
8349 * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1
8351 * Select the delayed or non-delayed read data strobe
8352 * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1
8354 * Enables Read Data Strobe in a byte lane
8355 * PSU_DDR_PHY_DX4GCR1_OEEN 0x1
8357 * Enables PDR in a byte lane
8358 * PSU_DDR_PHY_DX4GCR1_PDREN 0x1
8360 * Enables ODT/TE in a byte lane
8361 * PSU_DDR_PHY_DX4GCR1_TEEN 0x1
8363 * Enables Write Data strobe in a byte lane
8364 * PSU_DDR_PHY_DX4GCR1_DSEN 0x1
8366 * Enables DM pin in a byte lane
8367 * PSU_DDR_PHY_DX4GCR1_DMEN 0x1
8369 * Enables DQ corresponding to each bit in a byte
8370 * PSU_DDR_PHY_DX4GCR1_DQEN 0xff
8372 * DATX8 n General Configuration Register 1
8373 * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)
8375 PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8376 /*##################################################################### */
8379 * Register : DX4GCR4 @ 0XFD080B10
8381 * Byte lane VREF IOM (Used only by D4MU IOs)
8382 * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0
8384 * Byte Lane VREF Pad Enable
8385 * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0
8387 * Byte Lane Internal VREF Enable
8388 * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3
8390 * Byte Lane Single-End VREF Enable
8391 * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1
8393 * Reserved. Returns zeros on reads.
8394 * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0
8396 * External VREF generator REFSEL range select
8397 * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0
8399 * Byte Lane External VREF Select
8400 * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0
8402 * Single ended VREF generator REFSEL range select
8403 * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1
8405 * Byte Lane Single-End VREF Select
8406 * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30
8408 * Reserved. Returns zeros on reads.
8409 * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0
8411 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8412 * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf
8414 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8415 * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0
8417 * DATX8 n General Configuration Register 4
8418 * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)
8420 PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8421 /*##################################################################### */
8424 * Register : DX4GCR5 @ 0XFD080B14
8426 * Reserved. Returns zeros on reads.
8427 * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0
8429 * Byte Lane internal VREF Select for Rank 3
8430 * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9
8432 * Reserved. Returns zeros on reads.
8433 * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0
8435 * Byte Lane internal VREF Select for Rank 2
8436 * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9
8438 * Reserved. Returns zeros on reads.
8439 * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
8441 * Byte Lane internal VREF Select for Rank 1
8442 * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
8444 * Reserved. Returns zeros on reads.
8445 * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
8447 * Byte Lane internal VREF Select for Rank 0
8448 * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
8450 * DATX8 n General Configuration Register 5
8451 * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)
8453 PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8454 /*##################################################################### */
8457 * Register : DX4GCR6 @ 0XFD080B18
8459 * Reserved. Returns zeros on reads.
8460 * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0
8462 * DRAM DQ VREF Select for Rank3
8463 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9
8465 * Reserved. Returns zeros on reads.
8466 * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0
8468 * DRAM DQ VREF Select for Rank2
8469 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9
8471 * Reserved. Returns zeros on reads.
8472 * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0
8474 * DRAM DQ VREF Select for Rank1
8475 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b
8477 * Reserved. Returns zeros on reads.
8478 * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0
8480 * DRAM DQ VREF Select for Rank0
8481 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b
8483 * DATX8 n General Configuration Register 6
8484 * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)
8486 PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8487 /*##################################################################### */
8490 * Register : DX5GCR0 @ 0XFD080C00
8492 * Calibration Bypass
8493 * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0
8495 * Master Delay Line Enable
8496 * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1
8498 * Configurable ODT(TE) Phase Shift
8499 * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0
8501 * DQS Duty Cycle Correction
8502 * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0
8504 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8505 * input for the respective bypte lane of the PHY
8506 * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8
8508 * Reserved. Return zeroes on reads.
8509 * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0
8511 * DQSNSE Power Down Receiver
8512 * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0
8514 * DQSSE Power Down Receiver
8515 * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0
8517 * RTT On Additive Latency
8518 * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0
8521 * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3
8523 * Configurable PDR Phase Shift
8524 * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0
8527 * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0
8529 * DQSG Power Down Receiver
8530 * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0
8532 * Reserved. Return zeroes on reads.
8533 * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0
8535 * DQSG On-Die Termination
8536 * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0
8538 * DQSG Output Enable
8539 * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1
8541 * Reserved. Return zeroes on reads.
8542 * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0
8544 * DATX8 n General Configuration Register 0
8545 * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)
8547 PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8548 /*##################################################################### */
8551 * Register : DX5GCR1 @ 0XFD080C04
8553 * Enables the PDR mode for DQ[7:0]
8554 * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0
8556 * Reserved. Returns zeroes on reads.
8557 * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0
8559 * Select the delayed or non-delayed read data strobe #
8560 * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1
8562 * Select the delayed or non-delayed read data strobe
8563 * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1
8565 * Enables Read Data Strobe in a byte lane
8566 * PSU_DDR_PHY_DX5GCR1_OEEN 0x1
8568 * Enables PDR in a byte lane
8569 * PSU_DDR_PHY_DX5GCR1_PDREN 0x1
8571 * Enables ODT/TE in a byte lane
8572 * PSU_DDR_PHY_DX5GCR1_TEEN 0x1
8574 * Enables Write Data strobe in a byte lane
8575 * PSU_DDR_PHY_DX5GCR1_DSEN 0x1
8577 * Enables DM pin in a byte lane
8578 * PSU_DDR_PHY_DX5GCR1_DMEN 0x1
8580 * Enables DQ corresponding to each bit in a byte
8581 * PSU_DDR_PHY_DX5GCR1_DQEN 0xff
8583 * DATX8 n General Configuration Register 1
8584 * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)
8586 PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8587 /*##################################################################### */
8590 * Register : DX5GCR4 @ 0XFD080C10
8592 * Byte lane VREF IOM (Used only by D4MU IOs)
8593 * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0
8595 * Byte Lane VREF Pad Enable
8596 * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0
8598 * Byte Lane Internal VREF Enable
8599 * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3
8601 * Byte Lane Single-End VREF Enable
8602 * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1
8604 * Reserved. Returns zeros on reads.
8605 * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0
8607 * External VREF generator REFSEL range select
8608 * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0
8610 * Byte Lane External VREF Select
8611 * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0
8613 * Single ended VREF generator REFSEL range select
8614 * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1
8616 * Byte Lane Single-End VREF Select
8617 * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30
8619 * Reserved. Returns zeros on reads.
8620 * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0
8622 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8623 * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf
8625 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8626 * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0
8628 * DATX8 n General Configuration Register 4
8629 * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)
8631 PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8632 /*##################################################################### */
8635 * Register : DX5GCR5 @ 0XFD080C14
8637 * Reserved. Returns zeros on reads.
8638 * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0
8640 * Byte Lane internal VREF Select for Rank 3
8641 * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9
8643 * Reserved. Returns zeros on reads.
8644 * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0
8646 * Byte Lane internal VREF Select for Rank 2
8647 * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9
8649 * Reserved. Returns zeros on reads.
8650 * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
8652 * Byte Lane internal VREF Select for Rank 1
8653 * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
8655 * Reserved. Returns zeros on reads.
8656 * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
8658 * Byte Lane internal VREF Select for Rank 0
8659 * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
8661 * DATX8 n General Configuration Register 5
8662 * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)
8664 PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8665 /*##################################################################### */
8668 * Register : DX5GCR6 @ 0XFD080C18
8670 * Reserved. Returns zeros on reads.
8671 * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0
8673 * DRAM DQ VREF Select for Rank3
8674 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9
8676 * Reserved. Returns zeros on reads.
8677 * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0
8679 * DRAM DQ VREF Select for Rank2
8680 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9
8682 * Reserved. Returns zeros on reads.
8683 * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0
8685 * DRAM DQ VREF Select for Rank1
8686 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b
8688 * Reserved. Returns zeros on reads.
8689 * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0
8691 * DRAM DQ VREF Select for Rank0
8692 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b
8694 * DATX8 n General Configuration Register 6
8695 * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)
8697 PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8698 /*##################################################################### */
8701 * Register : DX6GCR0 @ 0XFD080D00
8703 * Calibration Bypass
8704 * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0
8706 * Master Delay Line Enable
8707 * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1
8709 * Configurable ODT(TE) Phase Shift
8710 * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0
8712 * DQS Duty Cycle Correction
8713 * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0
8715 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8716 * input for the respective bypte lane of the PHY
8717 * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8
8719 * Reserved. Return zeroes on reads.
8720 * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0
8722 * DQSNSE Power Down Receiver
8723 * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0
8725 * DQSSE Power Down Receiver
8726 * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0
8728 * RTT On Additive Latency
8729 * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0
8732 * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3
8734 * Configurable PDR Phase Shift
8735 * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0
8738 * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0
8740 * DQSG Power Down Receiver
8741 * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0
8743 * Reserved. Return zeroes on reads.
8744 * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0
8746 * DQSG On-Die Termination
8747 * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0
8749 * DQSG Output Enable
8750 * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1
8752 * Reserved. Return zeroes on reads.
8753 * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0
8755 * DATX8 n General Configuration Register 0
8756 * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)
8758 PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8759 /*##################################################################### */
8762 * Register : DX6GCR1 @ 0XFD080D04
8764 * Enables the PDR mode for DQ[7:0]
8765 * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0
8767 * Reserved. Returns zeroes on reads.
8768 * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0
8770 * Select the delayed or non-delayed read data strobe #
8771 * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1
8773 * Select the delayed or non-delayed read data strobe
8774 * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1
8776 * Enables Read Data Strobe in a byte lane
8777 * PSU_DDR_PHY_DX6GCR1_OEEN 0x1
8779 * Enables PDR in a byte lane
8780 * PSU_DDR_PHY_DX6GCR1_PDREN 0x1
8782 * Enables ODT/TE in a byte lane
8783 * PSU_DDR_PHY_DX6GCR1_TEEN 0x1
8785 * Enables Write Data strobe in a byte lane
8786 * PSU_DDR_PHY_DX6GCR1_DSEN 0x1
8788 * Enables DM pin in a byte lane
8789 * PSU_DDR_PHY_DX6GCR1_DMEN 0x1
8791 * Enables DQ corresponding to each bit in a byte
8792 * PSU_DDR_PHY_DX6GCR1_DQEN 0xff
8794 * DATX8 n General Configuration Register 1
8795 * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)
8797 PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8798 /*##################################################################### */
8801 * Register : DX6GCR4 @ 0XFD080D10
8803 * Byte lane VREF IOM (Used only by D4MU IOs)
8804 * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0
8806 * Byte Lane VREF Pad Enable
8807 * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0
8809 * Byte Lane Internal VREF Enable
8810 * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3
8812 * Byte Lane Single-End VREF Enable
8813 * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1
8815 * Reserved. Returns zeros on reads.
8816 * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0
8818 * External VREF generator REFSEL range select
8819 * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0
8821 * Byte Lane External VREF Select
8822 * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0
8824 * Single ended VREF generator REFSEL range select
8825 * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1
8827 * Byte Lane Single-End VREF Select
8828 * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30
8830 * Reserved. Returns zeros on reads.
8831 * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0
8833 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8834 * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf
8836 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8837 * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0
8839 * DATX8 n General Configuration Register 4
8840 * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)
8842 PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8843 /*##################################################################### */
8846 * Register : DX6GCR5 @ 0XFD080D14
8848 * Reserved. Returns zeros on reads.
8849 * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0
8851 * Byte Lane internal VREF Select for Rank 3
8852 * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9
8854 * Reserved. Returns zeros on reads.
8855 * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0
8857 * Byte Lane internal VREF Select for Rank 2
8858 * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9
8860 * Reserved. Returns zeros on reads.
8861 * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
8863 * Byte Lane internal VREF Select for Rank 1
8864 * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
8866 * Reserved. Returns zeros on reads.
8867 * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
8869 * Byte Lane internal VREF Select for Rank 0
8870 * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
8872 * DATX8 n General Configuration Register 5
8873 * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)
8875 PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8876 /*##################################################################### */
8879 * Register : DX6GCR6 @ 0XFD080D18
8881 * Reserved. Returns zeros on reads.
8882 * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0
8884 * DRAM DQ VREF Select for Rank3
8885 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9
8887 * Reserved. Returns zeros on reads.
8888 * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0
8890 * DRAM DQ VREF Select for Rank2
8891 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9
8893 * Reserved. Returns zeros on reads.
8894 * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0
8896 * DRAM DQ VREF Select for Rank1
8897 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b
8899 * Reserved. Returns zeros on reads.
8900 * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0
8902 * DRAM DQ VREF Select for Rank0
8903 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b
8905 * DATX8 n General Configuration Register 6
8906 * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)
8908 PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8909 /*##################################################################### */
8912 * Register : DX7GCR0 @ 0XFD080E00
8914 * Calibration Bypass
8915 * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0
8917 * Master Delay Line Enable
8918 * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1
8920 * Configurable ODT(TE) Phase Shift
8921 * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0
8923 * DQS Duty Cycle Correction
8924 * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0
8926 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8927 * input for the respective bypte lane of the PHY
8928 * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8
8930 * Reserved. Return zeroes on reads.
8931 * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0
8933 * DQSNSE Power Down Receiver
8934 * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0
8936 * DQSSE Power Down Receiver
8937 * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0
8939 * RTT On Additive Latency
8940 * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0
8943 * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3
8945 * Configurable PDR Phase Shift
8946 * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0
8949 * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0
8951 * DQSG Power Down Receiver
8952 * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0
8954 * Reserved. Return zeroes on reads.
8955 * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0
8957 * DQSG On-Die Termination
8958 * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0
8960 * DQSG Output Enable
8961 * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1
8963 * Reserved. Return zeroes on reads.
8964 * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0
8966 * DATX8 n General Configuration Register 0
8967 * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)
8969 PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8970 /*##################################################################### */
8973 * Register : DX7GCR1 @ 0XFD080E04
8975 * Enables the PDR mode for DQ[7:0]
8976 * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0
8978 * Reserved. Returns zeroes on reads.
8979 * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0
8981 * Select the delayed or non-delayed read data strobe #
8982 * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1
8984 * Select the delayed or non-delayed read data strobe
8985 * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1
8987 * Enables Read Data Strobe in a byte lane
8988 * PSU_DDR_PHY_DX7GCR1_OEEN 0x1
8990 * Enables PDR in a byte lane
8991 * PSU_DDR_PHY_DX7GCR1_PDREN 0x1
8993 * Enables ODT/TE in a byte lane
8994 * PSU_DDR_PHY_DX7GCR1_TEEN 0x1
8996 * Enables Write Data strobe in a byte lane
8997 * PSU_DDR_PHY_DX7GCR1_DSEN 0x1
8999 * Enables DM pin in a byte lane
9000 * PSU_DDR_PHY_DX7GCR1_DMEN 0x1
9002 * Enables DQ corresponding to each bit in a byte
9003 * PSU_DDR_PHY_DX7GCR1_DQEN 0xff
9005 * DATX8 n General Configuration Register 1
9006 * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)
9008 PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
9009 /*##################################################################### */
9012 * Register : DX7GCR4 @ 0XFD080E10
9014 * Byte lane VREF IOM (Used only by D4MU IOs)
9015 * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0
9017 * Byte Lane VREF Pad Enable
9018 * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0
9020 * Byte Lane Internal VREF Enable
9021 * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3
9023 * Byte Lane Single-End VREF Enable
9024 * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1
9026 * Reserved. Returns zeros on reads.
9027 * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0
9029 * External VREF generator REFSEL range select
9030 * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0
9032 * Byte Lane External VREF Select
9033 * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0
9035 * Single ended VREF generator REFSEL range select
9036 * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1
9038 * Byte Lane Single-End VREF Select
9039 * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30
9041 * Reserved. Returns zeros on reads.
9042 * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0
9044 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9045 * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf
9047 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9048 * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0
9050 * DATX8 n General Configuration Register 4
9051 * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)
9053 PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
9054 /*##################################################################### */
9057 * Register : DX7GCR5 @ 0XFD080E14
9059 * Reserved. Returns zeros on reads.
9060 * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0
9062 * Byte Lane internal VREF Select for Rank 3
9063 * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9
9065 * Reserved. Returns zeros on reads.
9066 * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0
9068 * Byte Lane internal VREF Select for Rank 2
9069 * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9
9071 * Reserved. Returns zeros on reads.
9072 * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
9074 * Byte Lane internal VREF Select for Rank 1
9075 * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
9077 * Reserved. Returns zeros on reads.
9078 * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
9080 * Byte Lane internal VREF Select for Rank 0
9081 * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
9083 * DATX8 n General Configuration Register 5
9084 * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)
9086 PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
9087 /*##################################################################### */
9090 * Register : DX7GCR6 @ 0XFD080E18
9092 * Reserved. Returns zeros on reads.
9093 * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0
9095 * DRAM DQ VREF Select for Rank3
9096 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9
9098 * Reserved. Returns zeros on reads.
9099 * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0
9101 * DRAM DQ VREF Select for Rank2
9102 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9
9104 * Reserved. Returns zeros on reads.
9105 * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0
9107 * DRAM DQ VREF Select for Rank1
9108 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b
9110 * Reserved. Returns zeros on reads.
9111 * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0
9113 * DRAM DQ VREF Select for Rank0
9114 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b
9116 * DATX8 n General Configuration Register 6
9117 * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)
9119 PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
9120 /*##################################################################### */
9123 * Register : DX8GCR0 @ 0XFD080F00
9125 * Calibration Bypass
9126 * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0
9128 * Master Delay Line Enable
9129 * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1
9131 * Configurable ODT(TE) Phase Shift
9132 * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0
9134 * DQS Duty Cycle Correction
9135 * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0
9137 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
9138 * input for the respective bypte lane of the PHY
9139 * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8
9141 * Reserved. Return zeroes on reads.
9142 * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0
9144 * DQSNSE Power Down Receiver
9145 * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0
9147 * DQSSE Power Down Receiver
9148 * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0
9150 * RTT On Additive Latency
9151 * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0
9154 * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3
9156 * Configurable PDR Phase Shift
9157 * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0
9160 * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0
9162 * DQSG Power Down Receiver
9163 * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1
9165 * Reserved. Return zeroes on reads.
9166 * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0
9168 * DQSG On-Die Termination
9169 * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0
9171 * DQSG Output Enable
9172 * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1
9174 * Reserved. Return zeroes on reads.
9175 * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0
9177 * DATX8 n General Configuration Register 0
9178 * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)
9180 PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U);
9181 /*##################################################################### */
9184 * Register : DX8GCR1 @ 0XFD080F04
9186 * Enables the PDR mode for DQ[7:0]
9187 * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0
9189 * Reserved. Returns zeroes on reads.
9190 * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0
9192 * Select the delayed or non-delayed read data strobe #
9193 * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1
9195 * Select the delayed or non-delayed read data strobe
9196 * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1
9198 * Enables Read Data Strobe in a byte lane
9199 * PSU_DDR_PHY_DX8GCR1_OEEN 0x1
9201 * Enables PDR in a byte lane
9202 * PSU_DDR_PHY_DX8GCR1_PDREN 0x1
9204 * Enables ODT/TE in a byte lane
9205 * PSU_DDR_PHY_DX8GCR1_TEEN 0x1
9207 * Enables Write Data strobe in a byte lane
9208 * PSU_DDR_PHY_DX8GCR1_DSEN 0x1
9210 * Enables DM pin in a byte lane
9211 * PSU_DDR_PHY_DX8GCR1_DMEN 0x1
9213 * Enables DQ corresponding to each bit in a byte
9214 * PSU_DDR_PHY_DX8GCR1_DQEN 0x0
9216 * DATX8 n General Configuration Register 1
9217 * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)
9219 PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U);
9220 /*##################################################################### */
9223 * Register : DX8GCR4 @ 0XFD080F10
9225 * Byte lane VREF IOM (Used only by D4MU IOs)
9226 * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0
9228 * Byte Lane VREF Pad Enable
9229 * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0
9231 * Byte Lane Internal VREF Enable
9232 * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3
9234 * Byte Lane Single-End VREF Enable
9235 * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1
9237 * Reserved. Returns zeros on reads.
9238 * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0
9240 * External VREF generator REFSEL range select
9241 * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0
9243 * Byte Lane External VREF Select
9244 * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0
9246 * Single ended VREF generator REFSEL range select
9247 * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1
9249 * Byte Lane Single-End VREF Select
9250 * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30
9252 * Reserved. Returns zeros on reads.
9253 * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0
9255 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9256 * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf
9258 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9259 * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0
9261 * DATX8 n General Configuration Register 4
9262 * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)
9264 PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
9265 /*##################################################################### */
9268 * Register : DX8GCR5 @ 0XFD080F14
9270 * Reserved. Returns zeros on reads.
9271 * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0
9273 * Byte Lane internal VREF Select for Rank 3
9274 * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9
9276 * Reserved. Returns zeros on reads.
9277 * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0
9279 * Byte Lane internal VREF Select for Rank 2
9280 * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9
9282 * Reserved. Returns zeros on reads.
9283 * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
9285 * Byte Lane internal VREF Select for Rank 1
9286 * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
9288 * Reserved. Returns zeros on reads.
9289 * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
9291 * Byte Lane internal VREF Select for Rank 0
9292 * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
9294 * DATX8 n General Configuration Register 5
9295 * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)
9297 PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
9298 /*##################################################################### */
9301 * Register : DX8GCR6 @ 0XFD080F18
9303 * Reserved. Returns zeros on reads.
9304 * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0
9306 * DRAM DQ VREF Select for Rank3
9307 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9
9309 * Reserved. Returns zeros on reads.
9310 * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0
9312 * DRAM DQ VREF Select for Rank2
9313 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9
9315 * Reserved. Returns zeros on reads.
9316 * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0
9318 * DRAM DQ VREF Select for Rank1
9319 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b
9321 * Reserved. Returns zeros on reads.
9322 * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0
9324 * DRAM DQ VREF Select for Rank0
9325 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b
9327 * DATX8 n General Configuration Register 6
9328 * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)
9330 PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
9331 /*##################################################################### */
9334 * Register : DX8SL0OSC @ 0XFD081400
9336 * Reserved. Return zeroes on reads.
9337 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
9339 * Enable Clock Gating for DX ddr_clk
9340 * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
9342 * Enable Clock Gating for DX ctl_rd_clk
9343 * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
9345 * Enable Clock Gating for DX ctl_clk
9346 * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
9348 * Selects the level to which clocks will be stalled when clock gating is e
9350 * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
9353 * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
9355 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9356 * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
9358 * Loopback DQS Gating
9359 * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
9361 * Loopback DQS Shift
9362 * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
9364 * PHY High-Speed Reset
9365 * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
9368 * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
9370 * Delay Line Test Start
9371 * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
9373 * Delay Line Test Mode
9374 * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
9376 * Reserved. Caution, do not write to this register field.
9377 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
9379 * Oscillator Mode Write-Data Delay Line Select
9380 * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
9382 * Reserved. Caution, do not write to this register field.
9383 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
9385 * Oscillator Mode Write-Leveling Delay Line Select
9386 * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
9388 * Oscillator Mode Division
9389 * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
9392 * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
9394 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9395 * opback, and Gated Clock Control Register
9396 * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
9398 PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9399 /*##################################################################### */
9402 * Register : DX8SL0PLLCR0 @ 0XFD081404
9405 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0
9408 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0
9411 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0
9413 * Reference Stop Mode
9414 * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0
9416 * PLL Frequency Select
9417 * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1
9420 * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0
9422 * Charge Pump Proportional Current Control
9423 * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8
9425 * Charge Pump Integrating Current Control
9426 * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0
9429 * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0
9431 * Reserved. Return zeroes on reads.
9432 * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0
9434 * Analog Test Enable (ATOEN)
9435 * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0
9437 * Analog Test Control
9438 * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0
9440 * Digital Test Control
9441 * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0
9443 * DAXT8 0-1 PLL Control Register 0
9444 * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U)
9446 PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET,
9447 0xFFFFFFFFU, 0x01100000U);
9448 /*##################################################################### */
9451 * Register : DX8SL0DQSCTL @ 0XFD08141C
9453 * Reserved. Return zeroes on reads.
9454 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0
9456 * Read Path Rise-to-Rise Mode
9457 * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1
9459 * Reserved. Return zeroes on reads.
9460 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0
9462 * Write Path Rise-to-Rise Mode
9463 * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1
9465 * DQS Gate Extension
9466 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0
9468 * Low Power PLL Power Down
9469 * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1
9471 * Low Power I/O Power Down
9472 * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1
9474 * Reserved. Return zeroes on reads.
9475 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0
9478 * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1
9480 * Unused DQ I/O Mode
9481 * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0
9483 * Reserved. Return zeroes on reads.
9484 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0
9487 * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
9490 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
9493 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
9495 * DATX8 0-1 DQS Control Register
9496 * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
9498 PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET,
9499 0xFFFFFFFFU, 0x01264300U);
9500 /*##################################################################### */
9503 * Register : DX8SL0DXCTL2 @ 0XFD08142C
9505 * Reserved. Return zeroes on reads.
9506 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0
9508 * Configurable Read Data Enable
9509 * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0
9511 * OX Extension during Post-amble
9512 * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
9514 * OE Extension during Pre-amble
9515 * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
9517 * Reserved. Return zeroes on reads.
9518 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
9520 * I/O Assisted Gate Select
9521 * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0
9523 * I/O Loopback Select
9524 * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0
9526 * Reserved. Return zeroes on reads.
9527 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0
9529 * Low Power Wakeup Threshold
9530 * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc
9532 * Read Data Bus Inversion Enable
9533 * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0
9535 * Write Data Bus Inversion Enable
9536 * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0
9538 * PUB Read FIFO Bypass
9539 * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0
9541 * DATX8 Receive FIFO Read Mode
9542 * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0
9544 * Disables the Read FIFO Reset
9545 * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0
9547 * Read DQS Gate I/O Loopback
9548 * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0
9550 * Reserved. Return zeroes on reads.
9551 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
9553 * DATX8 0-1 DX Control Register 2
9554 * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
9556 PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET,
9557 0xFFFFFFFFU, 0x00041800U);
9558 /*##################################################################### */
9561 * Register : DX8SL0IOCR @ 0XFD081430
9563 * Reserved. Return zeroes on reads.
9564 * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0
9566 * PVREF_DAC REFSEL range select
9567 * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7
9569 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
9570 * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0
9573 * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2
9575 * DX IO Transmitter Mode
9576 * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0
9578 * DX IO Receiver Mode
9579 * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0
9581 * DATX8 0-1 I/O Configuration Register
9582 * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U)
9584 PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
9585 /*##################################################################### */
9588 * Register : DX8SL1OSC @ 0XFD081440
9590 * Reserved. Return zeroes on reads.
9591 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
9593 * Enable Clock Gating for DX ddr_clk
9594 * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
9596 * Enable Clock Gating for DX ctl_rd_clk
9597 * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
9599 * Enable Clock Gating for DX ctl_clk
9600 * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
9602 * Selects the level to which clocks will be stalled when clock gating is e
9604 * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
9607 * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
9609 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9610 * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
9612 * Loopback DQS Gating
9613 * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
9615 * Loopback DQS Shift
9616 * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
9618 * PHY High-Speed Reset
9619 * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
9622 * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
9624 * Delay Line Test Start
9625 * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
9627 * Delay Line Test Mode
9628 * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
9630 * Reserved. Caution, do not write to this register field.
9631 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
9633 * Oscillator Mode Write-Data Delay Line Select
9634 * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
9636 * Reserved. Caution, do not write to this register field.
9637 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
9639 * Oscillator Mode Write-Leveling Delay Line Select
9640 * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
9642 * Oscillator Mode Division
9643 * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
9646 * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
9648 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9649 * opback, and Gated Clock Control Register
9650 * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
9652 PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9653 /*##################################################################### */
9656 * Register : DX8SL1PLLCR0 @ 0XFD081444
9659 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0
9662 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0
9665 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0
9667 * Reference Stop Mode
9668 * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0
9670 * PLL Frequency Select
9671 * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1
9674 * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0
9676 * Charge Pump Proportional Current Control
9677 * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8
9679 * Charge Pump Integrating Current Control
9680 * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0
9683 * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0
9685 * Reserved. Return zeroes on reads.
9686 * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0
9688 * Analog Test Enable (ATOEN)
9689 * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0
9691 * Analog Test Control
9692 * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0
9694 * Digital Test Control
9695 * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0
9697 * DAXT8 0-1 PLL Control Register 0
9698 * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U)
9700 PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET,
9701 0xFFFFFFFFU, 0x01100000U);
9702 /*##################################################################### */
9705 * Register : DX8SL1DQSCTL @ 0XFD08145C
9707 * Reserved. Return zeroes on reads.
9708 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0
9710 * Read Path Rise-to-Rise Mode
9711 * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1
9713 * Reserved. Return zeroes on reads.
9714 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0
9716 * Write Path Rise-to-Rise Mode
9717 * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1
9719 * DQS Gate Extension
9720 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0
9722 * Low Power PLL Power Down
9723 * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1
9725 * Low Power I/O Power Down
9726 * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1
9728 * Reserved. Return zeroes on reads.
9729 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0
9732 * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1
9734 * Unused DQ I/O Mode
9735 * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0
9737 * Reserved. Return zeroes on reads.
9738 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0
9741 * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
9744 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
9747 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
9749 * DATX8 0-1 DQS Control Register
9750 * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
9752 PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET,
9753 0xFFFFFFFFU, 0x01264300U);
9754 /*##################################################################### */
9757 * Register : DX8SL1DXCTL2 @ 0XFD08146C
9759 * Reserved. Return zeroes on reads.
9760 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0
9762 * Configurable Read Data Enable
9763 * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0
9765 * OX Extension during Post-amble
9766 * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
9768 * OE Extension during Pre-amble
9769 * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
9771 * Reserved. Return zeroes on reads.
9772 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
9774 * I/O Assisted Gate Select
9775 * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0
9777 * I/O Loopback Select
9778 * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0
9780 * Reserved. Return zeroes on reads.
9781 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0
9783 * Low Power Wakeup Threshold
9784 * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc
9786 * Read Data Bus Inversion Enable
9787 * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0
9789 * Write Data Bus Inversion Enable
9790 * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0
9792 * PUB Read FIFO Bypass
9793 * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0
9795 * DATX8 Receive FIFO Read Mode
9796 * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0
9798 * Disables the Read FIFO Reset
9799 * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0
9801 * Read DQS Gate I/O Loopback
9802 * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0
9804 * Reserved. Return zeroes on reads.
9805 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
9807 * DATX8 0-1 DX Control Register 2
9808 * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
9810 PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET,
9811 0xFFFFFFFFU, 0x00041800U);
9812 /*##################################################################### */
9815 * Register : DX8SL1IOCR @ 0XFD081470
9817 * Reserved. Return zeroes on reads.
9818 * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0
9820 * PVREF_DAC REFSEL range select
9821 * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7
9823 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
9824 * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0
9827 * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2
9829 * DX IO Transmitter Mode
9830 * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0
9832 * DX IO Receiver Mode
9833 * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0
9835 * DATX8 0-1 I/O Configuration Register
9836 * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U)
9838 PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
9839 /*##################################################################### */
9842 * Register : DX8SL2OSC @ 0XFD081480
9844 * Reserved. Return zeroes on reads.
9845 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
9847 * Enable Clock Gating for DX ddr_clk
9848 * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
9850 * Enable Clock Gating for DX ctl_rd_clk
9851 * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
9853 * Enable Clock Gating for DX ctl_clk
9854 * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
9856 * Selects the level to which clocks will be stalled when clock gating is e
9858 * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
9861 * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
9863 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9864 * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
9866 * Loopback DQS Gating
9867 * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
9869 * Loopback DQS Shift
9870 * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
9872 * PHY High-Speed Reset
9873 * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
9876 * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
9878 * Delay Line Test Start
9879 * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
9881 * Delay Line Test Mode
9882 * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
9884 * Reserved. Caution, do not write to this register field.
9885 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
9887 * Oscillator Mode Write-Data Delay Line Select
9888 * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
9890 * Reserved. Caution, do not write to this register field.
9891 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
9893 * Oscillator Mode Write-Leveling Delay Line Select
9894 * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
9896 * Oscillator Mode Division
9897 * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
9900 * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
9902 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9903 * opback, and Gated Clock Control Register
9904 * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
9906 PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9907 /*##################################################################### */
9910 * Register : DX8SL2PLLCR0 @ 0XFD081484
9913 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0
9916 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0
9919 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0
9921 * Reference Stop Mode
9922 * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0
9924 * PLL Frequency Select
9925 * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1
9928 * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0
9930 * Charge Pump Proportional Current Control
9931 * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8
9933 * Charge Pump Integrating Current Control
9934 * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0
9937 * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0
9939 * Reserved. Return zeroes on reads.
9940 * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0
9942 * Analog Test Enable (ATOEN)
9943 * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0
9945 * Analog Test Control
9946 * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0
9948 * Digital Test Control
9949 * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0
9951 * DAXT8 0-1 PLL Control Register 0
9952 * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U)
9954 PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET,
9955 0xFFFFFFFFU, 0x01100000U);
9956 /*##################################################################### */
9959 * Register : DX8SL2DQSCTL @ 0XFD08149C
9961 * Reserved. Return zeroes on reads.
9962 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
9964 * Read Path Rise-to-Rise Mode
9965 * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
9967 * Reserved. Return zeroes on reads.
9968 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
9970 * Write Path Rise-to-Rise Mode
9971 * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1
9973 * DQS Gate Extension
9974 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0
9976 * Low Power PLL Power Down
9977 * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1
9979 * Low Power I/O Power Down
9980 * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1
9982 * Reserved. Return zeroes on reads.
9983 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0
9986 * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1
9988 * Unused DQ I/O Mode
9989 * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0
9991 * Reserved. Return zeroes on reads.
9992 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0
9995 * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
9998 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
10001 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
10003 * DATX8 0-1 DQS Control Register
10004 * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
10006 PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET,
10007 0xFFFFFFFFU, 0x01264300U);
10008 /*##################################################################### */
10011 * Register : DX8SL2DXCTL2 @ 0XFD0814AC
10013 * Reserved. Return zeroes on reads.
10014 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0
10016 * Configurable Read Data Enable
10017 * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0
10019 * OX Extension during Post-amble
10020 * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
10022 * OE Extension during Pre-amble
10023 * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
10025 * Reserved. Return zeroes on reads.
10026 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
10028 * I/O Assisted Gate Select
10029 * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0
10031 * I/O Loopback Select
10032 * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0
10034 * Reserved. Return zeroes on reads.
10035 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0
10037 * Low Power Wakeup Threshold
10038 * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc
10040 * Read Data Bus Inversion Enable
10041 * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0
10043 * Write Data Bus Inversion Enable
10044 * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0
10046 * PUB Read FIFO Bypass
10047 * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0
10049 * DATX8 Receive FIFO Read Mode
10050 * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0
10052 * Disables the Read FIFO Reset
10053 * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0
10055 * Read DQS Gate I/O Loopback
10056 * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0
10058 * Reserved. Return zeroes on reads.
10059 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
10061 * DATX8 0-1 DX Control Register 2
10062 * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
10064 PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET,
10065 0xFFFFFFFFU, 0x00041800U);
10066 /*##################################################################### */
10069 * Register : DX8SL2IOCR @ 0XFD0814B0
10071 * Reserved. Return zeroes on reads.
10072 * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0
10074 * PVREF_DAC REFSEL range select
10075 * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7
10077 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10078 * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0
10081 * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2
10083 * DX IO Transmitter Mode
10084 * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0
10086 * DX IO Receiver Mode
10087 * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0
10089 * DATX8 0-1 I/O Configuration Register
10090 * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)
10092 PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10093 /*##################################################################### */
10096 * Register : DX8SL3OSC @ 0XFD0814C0
10098 * Reserved. Return zeroes on reads.
10099 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
10101 * Enable Clock Gating for DX ddr_clk
10102 * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
10104 * Enable Clock Gating for DX ctl_rd_clk
10105 * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
10107 * Enable Clock Gating for DX ctl_clk
10108 * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
10110 * Selects the level to which clocks will be stalled when clock gating is e
10112 * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
10115 * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
10117 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10118 * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
10120 * Loopback DQS Gating
10121 * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
10123 * Loopback DQS Shift
10124 * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
10126 * PHY High-Speed Reset
10127 * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
10130 * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
10132 * Delay Line Test Start
10133 * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
10135 * Delay Line Test Mode
10136 * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
10138 * Reserved. Caution, do not write to this register field.
10139 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
10141 * Oscillator Mode Write-Data Delay Line Select
10142 * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
10144 * Reserved. Caution, do not write to this register field.
10145 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
10147 * Oscillator Mode Write-Leveling Delay Line Select
10148 * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
10150 * Oscillator Mode Division
10151 * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
10153 * Oscillator Enable
10154 * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
10156 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
10157 * opback, and Gated Clock Control Register
10158 * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
10160 PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
10161 /*##################################################################### */
10164 * Register : DX8SL3PLLCR0 @ 0XFD0814C4
10167 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0
10170 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0
10173 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0
10175 * Reference Stop Mode
10176 * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0
10178 * PLL Frequency Select
10179 * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1
10182 * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0
10184 * Charge Pump Proportional Current Control
10185 * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8
10187 * Charge Pump Integrating Current Control
10188 * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0
10191 * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0
10193 * Reserved. Return zeroes on reads.
10194 * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0
10196 * Analog Test Enable (ATOEN)
10197 * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0
10199 * Analog Test Control
10200 * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0
10202 * Digital Test Control
10203 * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0
10205 * DAXT8 0-1 PLL Control Register 0
10206 * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U)
10208 PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET,
10209 0xFFFFFFFFU, 0x01100000U);
10210 /*##################################################################### */
10213 * Register : DX8SL3DQSCTL @ 0XFD0814DC
10215 * Reserved. Return zeroes on reads.
10216 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0
10218 * Read Path Rise-to-Rise Mode
10219 * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1
10221 * Reserved. Return zeroes on reads.
10222 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0
10224 * Write Path Rise-to-Rise Mode
10225 * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1
10227 * DQS Gate Extension
10228 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0
10230 * Low Power PLL Power Down
10231 * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1
10233 * Low Power I/O Power Down
10234 * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1
10236 * Reserved. Return zeroes on reads.
10237 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0
10239 * QS Counter Enable
10240 * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1
10242 * Unused DQ I/O Mode
10243 * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0
10245 * Reserved. Return zeroes on reads.
10246 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0
10249 * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
10252 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
10255 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
10257 * DATX8 0-1 DQS Control Register
10258 * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
10260 PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET,
10261 0xFFFFFFFFU, 0x01264300U);
10262 /*##################################################################### */
10265 * Register : DX8SL3DXCTL2 @ 0XFD0814EC
10267 * Reserved. Return zeroes on reads.
10268 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0
10270 * Configurable Read Data Enable
10271 * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0
10273 * OX Extension during Post-amble
10274 * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
10276 * OE Extension during Pre-amble
10277 * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
10279 * Reserved. Return zeroes on reads.
10280 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
10282 * I/O Assisted Gate Select
10283 * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0
10285 * I/O Loopback Select
10286 * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0
10288 * Reserved. Return zeroes on reads.
10289 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0
10291 * Low Power Wakeup Threshold
10292 * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc
10294 * Read Data Bus Inversion Enable
10295 * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0
10297 * Write Data Bus Inversion Enable
10298 * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0
10300 * PUB Read FIFO Bypass
10301 * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0
10303 * DATX8 Receive FIFO Read Mode
10304 * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0
10306 * Disables the Read FIFO Reset
10307 * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0
10309 * Read DQS Gate I/O Loopback
10310 * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0
10312 * Reserved. Return zeroes on reads.
10313 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
10315 * DATX8 0-1 DX Control Register 2
10316 * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
10318 PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET,
10319 0xFFFFFFFFU, 0x00041800U);
10320 /*##################################################################### */
10323 * Register : DX8SL3IOCR @ 0XFD0814F0
10325 * Reserved. Return zeroes on reads.
10326 * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0
10328 * PVREF_DAC REFSEL range select
10329 * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7
10331 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10332 * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0
10335 * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2
10337 * DX IO Transmitter Mode
10338 * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0
10340 * DX IO Receiver Mode
10341 * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0
10343 * DATX8 0-1 I/O Configuration Register
10344 * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)
10346 PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10347 /*##################################################################### */
10350 * Register : DX8SL4OSC @ 0XFD081500
10352 * Reserved. Return zeroes on reads.
10353 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
10355 * Enable Clock Gating for DX ddr_clk
10356 * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
10358 * Enable Clock Gating for DX ctl_rd_clk
10359 * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
10361 * Enable Clock Gating for DX ctl_clk
10362 * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
10364 * Selects the level to which clocks will be stalled when clock gating is e
10366 * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
10369 * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
10371 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10372 * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
10374 * Loopback DQS Gating
10375 * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
10377 * Loopback DQS Shift
10378 * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
10380 * PHY High-Speed Reset
10381 * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
10384 * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
10386 * Delay Line Test Start
10387 * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
10389 * Delay Line Test Mode
10390 * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
10392 * Reserved. Caution, do not write to this register field.
10393 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
10395 * Oscillator Mode Write-Data Delay Line Select
10396 * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
10398 * Reserved. Caution, do not write to this register field.
10399 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
10401 * Oscillator Mode Write-Leveling Delay Line Select
10402 * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
10404 * Oscillator Mode Division
10405 * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
10407 * Oscillator Enable
10408 * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
10410 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
10411 * opback, and Gated Clock Control Register
10412 * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
10414 PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
10415 /*##################################################################### */
10418 * Register : DX8SL4PLLCR0 @ 0XFD081504
10421 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0
10424 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0
10427 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0
10429 * Reference Stop Mode
10430 * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0
10432 * PLL Frequency Select
10433 * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1
10436 * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0
10438 * Charge Pump Proportional Current Control
10439 * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8
10441 * Charge Pump Integrating Current Control
10442 * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0
10445 * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0
10447 * Reserved. Return zeroes on reads.
10448 * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0
10450 * Analog Test Enable (ATOEN)
10451 * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0
10453 * Analog Test Control
10454 * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0
10456 * Digital Test Control
10457 * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0
10459 * DAXT8 0-1 PLL Control Register 0
10460 * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U)
10462 PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET,
10463 0xFFFFFFFFU, 0x01100000U);
10464 /*##################################################################### */
10467 * Register : DX8SL4DQSCTL @ 0XFD08151C
10469 * Reserved. Return zeroes on reads.
10470 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0
10472 * Read Path Rise-to-Rise Mode
10473 * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1
10475 * Reserved. Return zeroes on reads.
10476 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0
10478 * Write Path Rise-to-Rise Mode
10479 * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1
10481 * DQS Gate Extension
10482 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0
10484 * Low Power PLL Power Down
10485 * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1
10487 * Low Power I/O Power Down
10488 * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1
10490 * Reserved. Return zeroes on reads.
10491 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0
10493 * QS Counter Enable
10494 * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1
10496 * Unused DQ I/O Mode
10497 * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0
10499 * Reserved. Return zeroes on reads.
10500 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0
10503 * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
10506 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
10509 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
10511 * DATX8 0-1 DQS Control Register
10512 * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
10514 PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET,
10515 0xFFFFFFFFU, 0x01264300U);
10516 /*##################################################################### */
10519 * Register : DX8SL4DXCTL2 @ 0XFD08152C
10521 * Reserved. Return zeroes on reads.
10522 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0
10524 * Configurable Read Data Enable
10525 * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0
10527 * OX Extension during Post-amble
10528 * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
10530 * OE Extension during Pre-amble
10531 * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
10533 * Reserved. Return zeroes on reads.
10534 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
10536 * I/O Assisted Gate Select
10537 * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0
10539 * I/O Loopback Select
10540 * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0
10542 * Reserved. Return zeroes on reads.
10543 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0
10545 * Low Power Wakeup Threshold
10546 * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc
10548 * Read Data Bus Inversion Enable
10549 * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0
10551 * Write Data Bus Inversion Enable
10552 * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0
10554 * PUB Read FIFO Bypass
10555 * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0
10557 * DATX8 Receive FIFO Read Mode
10558 * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0
10560 * Disables the Read FIFO Reset
10561 * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0
10563 * Read DQS Gate I/O Loopback
10564 * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0
10566 * Reserved. Return zeroes on reads.
10567 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
10569 * DATX8 0-1 DX Control Register 2
10570 * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
10572 PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET,
10573 0xFFFFFFFFU, 0x00041800U);
10574 /*##################################################################### */
10577 * Register : DX8SL4IOCR @ 0XFD081530
10579 * Reserved. Return zeroes on reads.
10580 * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0
10582 * PVREF_DAC REFSEL range select
10583 * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7
10585 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10586 * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0
10589 * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2
10591 * DX IO Transmitter Mode
10592 * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0
10594 * DX IO Receiver Mode
10595 * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0
10597 * DATX8 0-1 I/O Configuration Register
10598 * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U)
10600 PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10601 /*##################################################################### */
10604 * Register : DX8SLbPLLCR0 @ 0XFD0817C4
10607 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0
10610 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0
10613 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0
10615 * Reference Stop Mode
10616 * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0
10618 * PLL Frequency Select
10619 * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1
10622 * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0
10624 * Charge Pump Proportional Current Control
10625 * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8
10627 * Charge Pump Integrating Current Control
10628 * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0
10631 * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0
10633 * Reserved. Return zeroes on reads.
10634 * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0
10636 * Analog Test Enable (ATOEN)
10637 * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0
10639 * Analog Test Control
10640 * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0
10642 * Digital Test Control
10643 * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0
10645 * DAXT8 0-8 PLL Control Register 0
10646 * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U)
10648 PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET,
10649 0xFFFFFFFFU, 0x01100000U);
10650 /*##################################################################### */
10653 * Register : DX8SLbDQSCTL @ 0XFD0817DC
10655 * Reserved. Return zeroes on reads.
10656 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0
10658 * Read Path Rise-to-Rise Mode
10659 * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1
10661 * Reserved. Return zeroes on reads.
10662 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0
10664 * Write Path Rise-to-Rise Mode
10665 * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1
10667 * DQS Gate Extension
10668 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0
10670 * Low Power PLL Power Down
10671 * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1
10673 * Low Power I/O Power Down
10674 * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1
10676 * Reserved. Return zeroes on reads.
10677 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0
10679 * QS Counter Enable
10680 * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1
10682 * Unused DQ I/O Mode
10683 * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0
10685 * Reserved. Return zeroes on reads.
10686 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0
10689 * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3
10692 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc
10695 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4
10697 * DATX8 0-8 DQS Control Register
10698 * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)
10700 PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET,
10701 0xFFFFFFFFU, 0x012643C4U);
10702 /*##################################################################### */
10707 unsigned long psu_ddr_qos_init_data(void)
10712 unsigned long psu_mio_init_data(void)
10718 * Register : MIO_PIN_0 @ 0XFF180000
10720 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
10722 * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1
10724 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10725 * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0
10727 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10728 * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
10729 * ]- (Test Scan Port) 3= Not Used
10730 * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0
10732 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g
10733 * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy
10734 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10735 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
10736 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
10737 * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out
10738 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
10739 * lk- (Trace Port Clock)
10740 * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0
10742 * Configures MIO Pin 0 peripheral interface mapping. S
10743 * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U)
10745 PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U);
10746 /*##################################################################### */
10749 * Register : MIO_PIN_1 @ 0XFF180004
10751 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
10752 * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
10753 * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1
10755 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10756 * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0
10758 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10759 * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
10760 * ]- (Test Scan Port) 3= Not Used
10761 * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0
10763 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g
10764 * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_
10765 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10766 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
10767 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou
10768 * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
10769 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
10771 * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0
10773 * Configures MIO Pin 1 peripheral interface mapping
10774 * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U)
10776 PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U);
10777 /*##################################################################### */
10780 * Register : MIO_PIN_2 @ 0XFF180008
10782 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
10783 * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
10784 * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1
10786 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10787 * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0
10789 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10790 * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
10791 * ]- (Test Scan Port) 3= Not Used
10792 * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0
10794 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g
10795 * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_
10796 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10797 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
10798 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I
10799 * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
10800 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
10801 * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0
10803 * Configures MIO Pin 2 peripheral interface mapping
10804 * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U)
10806 PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U);
10807 /*##################################################################### */
10810 * Register : MIO_PIN_3 @ 0XFF18000C
10812 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
10813 * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
10814 * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1
10816 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10817 * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0
10819 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10820 * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
10821 * ]- (Test Scan Port) 3= Not Used
10822 * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0
10824 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g
10825 * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy
10826 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10827 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
10828 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
10829 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out-
10830 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
10831 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
10832 * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0
10834 * Configures MIO Pin 3 peripheral interface mapping
10835 * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U)
10837 PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U);
10838 /*##################################################################### */
10841 * Register : MIO_PIN_4 @ 0XFF180010
10843 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
10844 * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
10845 * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1
10847 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10848 * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0
10850 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10851 * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
10852 * ]- (Test Scan Port) 3= Not Used
10853 * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0
10855 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g
10856 * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy
10857 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10858 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10859 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
10860 * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc
10861 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
10862 * utput, tracedq[2]- (Trace Port Databus)
10863 * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0
10865 * Configures MIO Pin 4 peripheral interface mapping
10866 * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U)
10868 PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U);
10869 /*##################################################################### */
10872 * Register : MIO_PIN_5 @ 0XFF180014
10874 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
10875 * (QSPI Slave Select)
10876 * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1
10878 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10879 * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0
10881 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10882 * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
10883 * ]- (Test Scan Port) 3= Not Used
10884 * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0
10886 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g
10887 * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_
10888 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10889 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
10890 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
10891 * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC
10892 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
10893 * trace, Output, tracedq[3]- (Trace Port Databus)
10894 * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0
10896 * Configures MIO Pin 5 peripheral interface mapping
10897 * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U)
10899 PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U);
10900 /*##################################################################### */
10903 * Register : MIO_PIN_6 @ 0XFF180018
10905 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l
10906 * pbk- (QSPI Clock to be fed-back)
10907 * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1
10909 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10910 * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0
10912 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10913 * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6
10914 * ]- (Test Scan Port) 3= Not Used
10915 * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0
10917 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g
10918 * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_
10919 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10920 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
10921 * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s
10922 * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT
10923 * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
10924 * Output, tracedq[4]- (Trace Port Databus)
10925 * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0
10927 * Configures MIO Pin 6 peripheral interface mapping
10928 * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U)
10930 PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U);
10931 /*##################################################################### */
10934 * Register : MIO_PIN_7 @ 0XFF18001C
10936 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_
10937 * upper- (QSPI Slave Select upper)
10938 * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1
10940 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10941 * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0
10943 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10944 * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7
10945 * ]- (Test Scan Port) 3= Not Used
10946 * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0
10948 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g
10949 * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy
10950 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10951 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
10952 * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma
10953 * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua
10954 * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t
10955 * racedq[5]- (Trace Port Databus)
10956 * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0
10958 * Configures MIO Pin 7 peripheral interface mapping
10959 * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U)
10961 PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U);
10962 /*##################################################################### */
10965 * Register : MIO_PIN_8 @ 0XFF180020
10967 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0
10968 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D
10970 * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1
10972 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10973 * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0
10975 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10976 * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8
10977 * ]- (Test Scan Port) 3= Not Used
10978 * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0
10980 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g
10981 * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy
10982 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10983 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10984 * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste
10985 * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_
10986 * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra
10988 * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0
10990 * Configures MIO Pin 8 peripheral interface mapping
10991 * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U)
10993 PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U);
10994 /*##################################################################### */
10997 * Register : MIO_PIN_9 @ 0XFF180024
10999 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1
11000 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D
11002 * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1
11004 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
11006 * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0
11008 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11009 * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9
11010 * ]- (Test Scan Port) 3= Not Used
11011 * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0
11013 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g
11014 * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_
11015 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
11016 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
11017 * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S
11018 * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3,
11019 * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA
11020 * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data
11022 * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0
11024 * Configures MIO Pin 9 peripheral interface mapping
11025 * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U)
11027 PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U);
11028 /*##################################################################### */
11031 * Register : MIO_PIN_10 @ 0XFF180028
11033 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2
11034 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D
11036 * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1
11038 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
11040 * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0
11042 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11043 * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[
11044 * 10]- (Test Scan Port) 3= Not Used
11045 * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0
11047 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0=
11048 * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph
11049 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11050 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11051 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
11052 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
11053 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
11054 * t, tracedq[8]- (Trace Port Databus)
11055 * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0
11057 * Configures MIO Pin 10 peripheral interface mapping
11058 * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U)
11060 PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U);
11061 /*##################################################################### */
11064 * Register : MIO_PIN_11 @ 0XFF18002C
11066 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3
11067 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D
11069 * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1
11071 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
11073 * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0
11075 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11076 * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[
11077 * 11]- (Test Scan Port) 3= Not Used
11078 * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0
11080 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0=
11081 * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p
11082 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11083 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11084 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
11085 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
11086 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
11087 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
11088 * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0
11090 * Configures MIO Pin 11 peripheral interface mapping
11091 * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U)
11093 PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U);
11094 /*##################################################################### */
11097 * Register : MIO_PIN_12 @ 0XFF180030
11099 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_
11100 * upper- (QSPI Upper Clock)
11101 * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1
11103 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
11104 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
11105 * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0
11107 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11108 * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[
11109 * 12]- (Test Scan Port) 3= Not Used
11110 * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0
11112 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0=
11113 * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p
11114 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11115 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT
11116 * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_
11117 * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O
11118 * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace
11119 * dq[10]- (Trace Port Databus)
11120 * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0
11122 * Configures MIO Pin 12 peripheral interface mapping
11123 * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U)
11125 PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U);
11126 /*##################################################################### */
11129 * Register : MIO_PIN_13 @ 0XFF180034
11131 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11132 * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0
11134 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA
11136 * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0
11138 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
11139 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t
11140 * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output,
11141 * test_scan_out[13]- (Test Scan Port) 3= Not Used
11142 * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0
11144 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0=
11145 * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph
11146 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11147 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA
11148 * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1,
11149 * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR
11150 * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data
11152 * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0
11154 * Configures MIO Pin 13 peripheral interface mapping
11155 * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U)
11157 PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U);
11158 /*##################################################################### */
11161 * Register : MIO_PIN_14 @ 0XFF180038
11163 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11164 * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0
11166 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND
11167 * Command Latch Enable)
11168 * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0
11170 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
11171 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t
11172 * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output,
11173 * test_scan_out[14]- (Test Scan Port) 3= Not Used
11174 * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0
11176 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0=
11177 * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph
11178 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11179 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT
11180 * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0,
11181 * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver
11182 * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
11183 * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2
11185 * Configures MIO Pin 14 peripheral interface mapping
11186 * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U)
11188 PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U);
11189 /*##################################################################### */
11192 * Register : MIO_PIN_15 @ 0XFF18003C
11194 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11195 * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0
11197 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND
11198 * Address Latch Enable)
11199 * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0
11201 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
11202 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t
11203 * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output,
11204 * test_scan_out[15]- (Test Scan Port) 3= Not Used
11205 * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0
11207 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0=
11208 * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p
11209 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11210 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT
11211 * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp
11212 * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou
11213 * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria
11214 * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
11215 * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2
11217 * Configures MIO Pin 15 peripheral interface mapping
11218 * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U)
11220 PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U);
11221 /*##################################################################### */
11224 * Register : MIO_PIN_16 @ 0XFF180040
11226 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11227 * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0
11229 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
11230 * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
11231 * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0
11233 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
11234 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t
11235 * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
11236 * test_scan_out[16]- (Test Scan Port) 3= Not Used
11237 * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0
11239 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0=
11240 * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p
11241 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11242 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11243 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
11244 * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
11245 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11246 * Output, tracedq[14]- (Trace Port Databus)
11247 * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2
11249 * Configures MIO Pin 16 peripheral interface mapping
11250 * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U)
11252 PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U);
11253 /*##################################################################### */
11256 * Register : MIO_PIN_17 @ 0XFF180044
11258 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11259 * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0
11261 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
11262 * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
11263 * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0
11265 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
11266 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t
11267 * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
11268 * test_scan_out[17]- (Test Scan Port) 3= Not Used
11269 * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0
11271 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0=
11272 * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph
11273 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11274 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11275 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
11276 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
11277 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
11278 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
11279 * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2
11281 * Configures MIO Pin 17 peripheral interface mapping
11282 * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U)
11284 PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U);
11285 /*##################################################################### */
11288 * Register : MIO_PIN_18 @ 0XFF180048
11290 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11291 * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0
11293 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
11294 * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
11295 * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0
11297 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
11298 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t
11299 * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output,
11300 * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11302 * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0
11304 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0=
11305 * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph
11306 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11307 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11308 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
11309 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
11310 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
11311 * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6
11313 * Configures MIO Pin 18 peripheral interface mapping
11314 * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U)
11316 PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U);
11317 /*##################################################################### */
11320 * Register : MIO_PIN_19 @ 0XFF18004C
11322 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11323 * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0
11325 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
11326 * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
11327 * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0
11329 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
11330 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t
11331 * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output,
11332 * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11334 * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0
11336 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0=
11337 * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p
11338 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11339 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11340 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
11341 * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
11342 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
11343 * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6
11345 * Configures MIO Pin 19 peripheral interface mapping
11346 * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U)
11348 PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U);
11349 /*##################################################################### */
11352 * Register : MIO_PIN_20 @ 0XFF180050
11354 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11355 * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0
11357 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
11358 * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
11359 * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0
11361 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
11362 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t
11363 * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output,
11364 * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11366 * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0
11368 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0=
11369 * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p
11370 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11371 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11372 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
11373 * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
11374 * 1_txd- (UART transmitter serial output) 7= Not Used
11375 * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6
11377 * Configures MIO Pin 20 peripheral interface mapping
11378 * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U)
11380 PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U);
11381 /*##################################################################### */
11384 * Register : MIO_PIN_21 @ 0XFF180054
11386 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11387 * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0
11389 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
11390 * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
11391 * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0
11393 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
11394 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes
11395 * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t
11396 * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
11398 * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0
11400 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0=
11401 * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph
11402 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11403 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11404 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
11405 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc
11406 * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
11407 * UART receiver serial input) 7= Not Used
11408 * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6
11410 * Configures MIO Pin 21 peripheral interface mapping
11411 * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U)
11413 PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U);
11414 /*##################################################################### */
11417 * Register : MIO_PIN_22 @ 0XFF180058
11419 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11420 * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0
11422 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN
11424 * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0
11426 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
11427 * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) =
11428 * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c
11429 * su_ext_tamper- (CSU Ext Tamper)
11430 * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0
11432 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0=
11433 * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph
11434 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11435 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11436 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
11437 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
11438 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
11440 * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0
11442 * Configures MIO Pin 22 peripheral interface mapping
11443 * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U)
11445 PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U);
11446 /*##################################################################### */
11449 * Register : MIO_PIN_23 @ 0XFF18005C
11451 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11452 * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0
11454 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (
11455 * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
11456 * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0
11458 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
11459 * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po
11460 * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp
11461 * ut, csu_ext_tamper- (CSU Ext Tamper)
11462 * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0
11464 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0=
11465 * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p
11466 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11467 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11468 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
11469 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
11470 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
11471 * tput) 7= Not Used
11472 * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0
11474 * Configures MIO Pin 23 peripheral interface mapping
11475 * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U)
11477 PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U);
11478 /*##################################################################### */
11481 * Register : MIO_PIN_24 @ 0XFF180060
11483 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11484 * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0
11486 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
11487 * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
11488 * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0
11490 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
11491 * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test
11492 * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
11493 * csu, Input, csu_ext_tamper- (CSU Ext Tamper)
11494 * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0
11496 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0=
11497 * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p
11498 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11499 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11500 * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T
11501 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
11503 * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1
11505 * Configures MIO Pin 24 peripheral interface mapping
11506 * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U)
11508 PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U);
11509 /*##################################################################### */
11512 * Register : MIO_PIN_25 @ 0XFF180064
11514 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11515 * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0
11517 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
11519 * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0
11521 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
11522 * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]-
11523 * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
11524 * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
11525 * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0
11527 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0=
11528 * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph
11529 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11530 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11531 * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou
11532 * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
11534 * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1
11536 * Configures MIO Pin 25 peripheral interface mapping
11537 * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U)
11539 PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U);
11540 /*##################################################################### */
11543 * Register : MIO_PIN_26 @ 0XFF180068
11545 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
11546 * clk- (TX RGMII clock)
11547 * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0
11549 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
11551 * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0
11553 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU
11554 * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca
11555 * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta
11556 * mper- (CSU Ext Tamper)
11557 * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
11559 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g
11560 * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_
11561 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11562 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
11563 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl
11564 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
11565 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
11566 * Trace Port Databus)
11567 * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
11569 * Configures MIO Pin 26 peripheral interface mapping
11570 * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U)
11572 PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U);
11573 /*##################################################################### */
11576 * Register : MIO_PIN_27 @ 0XFF18006C
11578 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11579 * [0]- (TX RGMII data)
11580 * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0
11582 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
11584 * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0
11586 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU
11587 * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca
11588 * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
11589 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11590 * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
11592 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g
11593 * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy
11594 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11595 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
11596 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
11597 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
11598 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
11600 * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
11602 * Configures MIO Pin 27 peripheral interface mapping
11603 * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U)
11605 PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U);
11606 /*##################################################################### */
11609 * Register : MIO_PIN_28 @ 0XFF180070
11611 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11612 * [1]- (TX RGMII data)
11613 * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0
11615 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
11617 * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0
11619 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU
11620 * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca
11621 * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
11622 * lug_detect- (Dp Aux Hot Plug)
11623 * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
11625 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g
11626 * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy
11627 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
11628 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
11629 * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
11630 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
11631 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
11632 * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
11634 * Configures MIO Pin 28 peripheral interface mapping
11635 * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U)
11637 PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U);
11638 /*##################################################################### */
11641 * Register : MIO_PIN_29 @ 0XFF180074
11643 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11644 * [2]- (TX RGMII data)
11645 * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0
11647 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11648 * PCIE Reset signal)
11649 * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0
11651 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU
11652 * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca
11653 * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
11654 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11655 * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
11657 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g
11658 * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_
11659 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
11660 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
11661 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output,
11662 * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
11663 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
11664 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
11665 * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
11667 * Configures MIO Pin 29 peripheral interface mapping
11668 * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U)
11670 PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U);
11671 /*##################################################################### */
11674 * Register : MIO_PIN_30 @ 0XFF180078
11676 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11677 * [3]- (TX RGMII data)
11678 * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0
11680 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11681 * PCIE Reset signal)
11682 * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0
11684 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU
11685 * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca
11686 * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
11687 * lug_detect- (Dp Aux Hot Plug)
11688 * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
11690 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g
11691 * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_
11692 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11693 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
11694 * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0
11695 * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock
11696 * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
11697 * tracedq[8]- (Trace Port Databus)
11698 * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
11700 * Configures MIO Pin 30 peripheral interface mapping
11701 * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U)
11703 PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U);
11704 /*##################################################################### */
11707 * Register : MIO_PIN_31 @ 0XFF18007C
11709 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
11710 * ctl- (TX RGMII control)
11711 * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0
11713 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11714 * PCIE Reset signal)
11715 * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0
11717 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU
11718 * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca
11719 * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta
11720 * mper- (CSU Ext Tamper)
11721 * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0
11723 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g
11724 * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy
11725 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11726 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
11727 * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
11728 * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT
11729 * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp
11730 * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
11731 * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0
11733 * Configures MIO Pin 31 peripheral interface mapping
11734 * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U)
11736 PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U);
11737 /*##################################################################### */
11740 * Register : MIO_PIN_32 @ 0XFF180080
11742 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
11743 * lk- (RX RGMII clock)
11744 * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0
11746 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
11747 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
11748 * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0
11750 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM
11751 * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc
11752 * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t
11753 * amper- (CSU Ext Tamper)
11754 * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1
11756 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g
11757 * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy
11758 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
11759 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
11760 * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
11761 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T
11762 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t
11763 * race, Output, tracedq[10]- (Trace Port Databus)
11764 * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0
11766 * Configures MIO Pin 32 peripheral interface mapping
11767 * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U)
11769 PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U);
11770 /*##################################################################### */
11773 * Register : MIO_PIN_33 @ 0XFF180084
11775 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11776 * 0]- (RX RGMII data)
11777 * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0
11779 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11780 * PCIE Reset signal)
11781 * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0
11783 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM
11784 * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc
11785 * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t
11786 * amper- (CSU Ext Tamper)
11787 * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1
11789 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g
11790 * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_
11791 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
11792 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
11793 * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas
11794 * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1
11795 * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq
11796 * [11]- (Trace Port Databus)
11797 * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0
11799 * Configures MIO Pin 33 peripheral interface mapping
11800 * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U)
11802 PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U);
11803 /*##################################################################### */
11806 * Register : MIO_PIN_34 @ 0XFF180088
11808 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11809 * 1]- (RX RGMII data)
11810 * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0
11812 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11813 * PCIE Reset signal)
11814 * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0
11816 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM
11817 * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc
11818 * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_
11819 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11820 * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1
11822 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g
11823 * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_
11824 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11825 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
11826 * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master
11827 * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx
11828 * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po
11830 * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0
11832 * Configures MIO Pin 34 peripheral interface mapping
11833 * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U)
11835 PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U);
11836 /*##################################################################### */
11839 * Register : MIO_PIN_35 @ 0XFF18008C
11841 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11842 * 2]- (RX RGMII data)
11843 * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0
11845 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11846 * PCIE Reset signal)
11847 * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0
11849 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM
11850 * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc
11851 * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_
11852 * plug_detect- (Dp Aux Hot Plug)
11853 * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1
11855 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g
11856 * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy
11857 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11858 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
11859 * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
11860 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2
11861 * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (
11862 * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po
11864 * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0
11866 * Configures MIO Pin 35 peripheral interface mapping
11867 * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U)
11869 PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U);
11870 /*##################################################################### */
11873 * Register : MIO_PIN_36 @ 0XFF180090
11875 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11876 * 3]- (RX RGMII data)
11877 * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0
11879 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11880 * PCIE Reset signal)
11881 * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0
11883 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM
11884 * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc
11885 * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_
11886 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11887 * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1
11889 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0=
11890 * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p
11891 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11892 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11893 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
11894 * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
11895 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11896 * Output, tracedq[14]- (Trace Port Databus)
11897 * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0
11899 * Configures MIO Pin 36 peripheral interface mapping
11900 * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U)
11902 PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U);
11903 /*##################################################################### */
11906 * Register : MIO_PIN_37 @ 0XFF180094
11908 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
11909 * tl- (RX RGMII control )
11910 * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0
11912 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11913 * PCIE Reset signal)
11914 * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0
11916 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM
11917 * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc
11918 * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_
11919 * plug_detect- (Dp Aux Hot Plug)
11920 * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1
11922 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0=
11923 * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph
11924 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11925 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11926 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
11927 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
11928 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
11929 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
11930 * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0
11932 * Configures MIO Pin 37 peripheral interface mapping
11933 * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U)
11935 PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U);
11936 /*##################################################################### */
11939 * Register : MIO_PIN_38 @ 0XFF180098
11941 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
11942 * clk- (TX RGMII clock)
11943 * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0
11945 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11946 * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0
11948 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
11949 * (SDSDIO clock) 2= Not Used 3= Not Used
11950 * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0
11952 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0=
11953 * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph
11954 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11955 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA
11956 * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s
11957 * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In
11958 * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
11959 * (Trace Port Clock)
11960 * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0
11962 * Configures MIO Pin 38 peripheral interface mapping
11963 * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U)
11965 PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U);
11966 /*##################################################################### */
11969 * Register : MIO_PIN_39 @ 0XFF18009C
11971 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
11972 * [0]- (TX RGMII data)
11973 * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0
11975 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11976 * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0
11978 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
11979 * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b
11980 * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
11981 * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2
11983 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0=
11984 * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p
11985 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11986 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT
11987 * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0,
11988 * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U
11989 * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
11991 * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0
11993 * Configures MIO Pin 39 peripheral interface mapping
11994 * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U)
11996 PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U);
11997 /*##################################################################### */
12000 * Register : MIO_PIN_40 @ 0XFF1800A0
12002 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
12003 * [1]- (TX RGMII data)
12004 * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0
12006 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12007 * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0
12009 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
12010 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1
12011 * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[
12012 * 5]- (8-bit Data bus) 3= Not Used
12013 * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2
12015 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0=
12016 * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p
12017 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12018 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ
12019 * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3
12020 * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi
12021 * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12022 * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0
12024 * Configures MIO Pin 40 peripheral interface mapping
12025 * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U)
12027 PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U);
12028 /*##################################################################### */
12031 * Register : MIO_PIN_41 @ 0XFF1800A4
12033 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
12034 * [2]- (TX RGMII data)
12035 * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0
12037 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12038 * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0
12040 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
12041 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s
12042 * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12043 * t[6]- (8-bit Data bus) 3= Not Used
12044 * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2
12046 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0=
12047 * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph
12048 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12049 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA
12050 * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu
12051 * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out
12052 * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp
12053 * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12054 * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0
12056 * Configures MIO Pin 41 peripheral interface mapping
12057 * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U)
12059 PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U);
12060 /*##################################################################### */
12063 * Register : MIO_PIN_42 @ 0XFF1800A8
12065 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
12066 * [3]- (TX RGMII data)
12067 * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0
12069 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12070 * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0
12072 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
12073 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s
12074 * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12075 * t[7]- (8-bit Data bus) 3= Not Used
12076 * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2
12078 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0=
12079 * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph
12080 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12081 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12082 * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp
12083 * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
12084 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
12085 * t, tracedq[2]- (Trace Port Databus)
12086 * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0
12088 * Configures MIO Pin 42 peripheral interface mapping
12089 * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U)
12091 PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U);
12092 /*##################################################################### */
12095 * Register : MIO_PIN_43 @ 0XFF1800AC
12097 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
12098 * ctl- (TX RGMII control)
12099 * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0
12101 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12102 * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0
12104 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
12105 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
12106 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
12107 * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0
12109 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0=
12110 * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p
12111 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12112 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12113 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal)
12114 * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
12115 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
12116 * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
12117 * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0
12119 * Configures MIO Pin 43 peripheral interface mapping
12120 * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U)
12122 PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U);
12123 /*##################################################################### */
12126 * Register : MIO_PIN_44 @ 0XFF1800B0
12128 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
12129 * lk- (RX RGMII clock)
12130 * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0
12132 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12133 * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0
12135 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
12136 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
12137 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
12138 * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2
12140 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0=
12141 * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p
12142 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12143 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12144 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4
12145 * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in-
12146 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
12148 * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0
12150 * Configures MIO Pin 44 peripheral interface mapping
12151 * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U)
12153 PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U);
12154 /*##################################################################### */
12157 * Register : MIO_PIN_45 @ 0XFF1800B4
12159 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12160 * 0]- (RX RGMII data)
12161 * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0
12163 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12164 * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0
12166 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
12167 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
12168 * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
12169 * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2
12171 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0=
12172 * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph
12173 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12174 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12175 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M
12176 * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
12177 * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
12178 * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0
12180 * Configures MIO Pin 45 peripheral interface mapping
12181 * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U)
12183 PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U);
12184 /*##################################################################### */
12187 * Register : MIO_PIN_46 @ 0XFF1800B8
12189 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12190 * 1]- (RX RGMII data)
12191 * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0
12193 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12194 * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0
12196 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
12197 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
12198 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12199 * t[0]- (8-bit Data bus) 3= Not Used
12200 * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2
12202 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0=
12203 * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph
12204 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12205 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12206 * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast
12207 * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
12208 * rxd- (UART receiver serial input) 7= Not Used
12209 * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0
12211 * Configures MIO Pin 46 peripheral interface mapping
12212 * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U)
12214 PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U);
12215 /*##################################################################### */
12218 * Register : MIO_PIN_47 @ 0XFF1800BC
12220 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12221 * 2]- (RX RGMII data)
12222 * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0
12224 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12225 * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0
12227 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
12228 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
12229 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12230 * t[1]- (8-bit Data bus) 3= Not Used
12231 * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2
12233 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0=
12234 * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p
12235 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12236 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12237 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste
12238 * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt
12239 * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
12240 * (UART transmitter serial output) 7= Not Used
12241 * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0
12243 * Configures MIO Pin 47 peripheral interface mapping
12244 * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U)
12246 PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U);
12247 /*##################################################################### */
12250 * Register : MIO_PIN_48 @ 0XFF1800C0
12252 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12253 * 3]- (RX RGMII data)
12254 * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0
12256 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12257 * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0
12259 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
12260 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
12261 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12262 * t[2]- (8-bit Data bus) 3= Not Used
12263 * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2
12265 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0=
12266 * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p
12267 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12268 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12269 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
12270 * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
12271 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
12273 * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0
12275 * Configures MIO Pin 48 peripheral interface mapping
12276 * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U)
12278 PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U);
12279 /*##################################################################### */
12282 * Register : MIO_PIN_49 @ 0XFF1800C4
12284 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
12285 * tl- (RX RGMII control )
12286 * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0
12288 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12289 * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0
12291 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
12292 * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
12293 * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
12294 * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2
12296 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0=
12297 * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph
12298 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12299 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12300 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
12301 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
12302 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12304 * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0
12306 * Configures MIO Pin 49 peripheral interface mapping
12307 * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U)
12309 PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U);
12310 /*##################################################################### */
12313 * Register : MIO_PIN_50 @ 0XFF1800C8
12315 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
12317 * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0
12319 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12320 * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0
12322 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
12323 * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
12324 * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
12325 * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2
12327 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0=
12328 * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph
12329 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12330 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12331 * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5=
12332 * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
12333 * iver serial input) 7= Not Used
12334 * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0
12336 * Configures MIO Pin 50 peripheral interface mapping
12337 * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U)
12339 PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U);
12340 /*##################################################################### */
12343 * Register : MIO_PIN_51 @ 0XFF1800CC
12345 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
12347 * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0
12349 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12350 * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0
12352 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
12353 * o1_clk_out- (SDSDIO clock) 3= Not Used
12354 * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2
12356 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0=
12357 * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p
12358 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12359 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12360 * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat
12361 * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa
12362 * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
12363 * serial output) 7= Not Used
12364 * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0
12366 * Configures MIO Pin 51 peripheral interface mapping
12367 * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U)
12369 PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U);
12370 /*##################################################################### */
12373 * Register : MIO_PIN_52 @ 0XFF1800D0
12375 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
12376 * clk- (TX RGMII clock)
12377 * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0
12379 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
12381 * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1
12383 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12385 * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0
12387 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
12388 * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
12389 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12390 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
12391 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
12392 * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
12393 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
12394 * lk- (Trace Port Clock)
12395 * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0
12397 * Configures MIO Pin 52 peripheral interface mapping
12398 * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U)
12400 PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U);
12401 /*##################################################################### */
12404 * Register : MIO_PIN_53 @ 0XFF1800D4
12406 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12407 * [0]- (TX RGMII data)
12408 * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0
12410 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
12411 * (Data bus direction control)
12412 * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1
12414 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12416 * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0
12418 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
12419 * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
12420 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12421 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
12422 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
12423 * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
12424 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
12426 * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0
12428 * Configures MIO Pin 53 peripheral interface mapping
12429 * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U)
12431 PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U);
12432 /*##################################################################### */
12435 * Register : MIO_PIN_54 @ 0XFF1800D8
12437 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12438 * [1]- (TX RGMII data)
12439 * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0
12441 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12442 * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
12444 * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1
12446 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12448 * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0
12450 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
12451 * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
12452 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
12453 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
12454 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
12455 * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
12456 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12457 * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0
12459 * Configures MIO Pin 54 peripheral interface mapping
12460 * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U)
12462 PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U);
12463 /*##################################################################### */
12466 * Register : MIO_PIN_55 @ 0XFF1800DC
12468 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12469 * [2]- (TX RGMII data)
12470 * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0
12472 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
12473 * (Data flow control signal from the PHY)
12474 * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1
12476 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12478 * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0
12480 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
12481 * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
12482 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
12483 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
12484 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
12485 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
12486 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
12487 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12488 * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0
12490 * Configures MIO Pin 55 peripheral interface mapping
12491 * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U)
12493 PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U);
12494 /*##################################################################### */
12497 * Register : MIO_PIN_56 @ 0XFF1800E0
12499 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12500 * [3]- (TX RGMII data)
12501 * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0
12503 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12504 * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
12506 * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1
12508 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12510 * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0
12512 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
12513 * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
12514 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12515 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
12516 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
12517 * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
12518 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
12519 * utput, tracedq[2]- (Trace Port Databus)
12520 * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0
12522 * Configures MIO Pin 56 peripheral interface mapping
12523 * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U)
12525 PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U);
12526 /*##################################################################### */
12529 * Register : MIO_PIN_57 @ 0XFF1800E4
12531 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
12532 * ctl- (TX RGMII control)
12533 * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0
12535 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12536 * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
12538 * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1
12540 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12542 * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0
12544 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
12545 * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
12546 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12547 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
12548 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
12549 * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
12550 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
12551 * trace, Output, tracedq[3]- (Trace Port Databus)
12552 * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0
12554 * Configures MIO Pin 57 peripheral interface mapping
12555 * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U)
12557 PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U);
12558 /*##################################################################### */
12561 * Register : MIO_PIN_58 @ 0XFF1800E8
12563 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
12564 * lk- (RX RGMII clock)
12565 * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0
12567 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
12568 * (Asserted to end or interrupt transfers)
12569 * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1
12571 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12573 * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0
12575 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
12576 * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
12577 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
12578 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
12579 * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
12580 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
12581 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
12582 * Trace Port Databus)
12583 * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0
12585 * Configures MIO Pin 58 peripheral interface mapping
12586 * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U)
12588 PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U);
12589 /*##################################################################### */
12592 * Register : MIO_PIN_59 @ 0XFF1800EC
12594 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12595 * 0]- (RX RGMII data)
12596 * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0
12598 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12599 * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
12601 * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1
12603 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12605 * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0
12607 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
12608 * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
12609 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
12610 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
12611 * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
12612 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
12613 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
12615 * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0
12617 * Configures MIO Pin 59 peripheral interface mapping
12618 * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U)
12620 PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U);
12621 /*##################################################################### */
12624 * Register : MIO_PIN_60 @ 0XFF1800F0
12626 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12627 * 1]- (RX RGMII data)
12628 * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0
12630 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12631 * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
12633 * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1
12635 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12637 * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0
12639 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
12640 * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
12641 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12642 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
12643 * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
12644 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
12645 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
12646 * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0
12648 * Configures MIO Pin 60 peripheral interface mapping
12649 * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U)
12651 PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U);
12652 /*##################################################################### */
12655 * Register : MIO_PIN_61 @ 0XFF1800F4
12657 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12658 * 2]- (RX RGMII data)
12659 * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0
12661 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12662 * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
12664 * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1
12666 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12668 * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0
12670 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
12671 * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
12672 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12673 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
12674 * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
12675 * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
12676 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
12677 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12678 * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0
12680 * Configures MIO Pin 61 peripheral interface mapping
12681 * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U)
12683 PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U);
12684 /*##################################################################### */
12687 * Register : MIO_PIN_62 @ 0XFF1800F8
12689 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12690 * 3]- (RX RGMII data)
12691 * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0
12693 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12694 * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
12696 * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1
12698 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12700 * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0
12702 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
12703 * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
12704 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12705 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12706 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
12707 * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
12708 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
12709 * t, tracedq[8]- (Trace Port Databus)
12710 * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0
12712 * Configures MIO Pin 62 peripheral interface mapping
12713 * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U)
12715 PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U);
12716 /*##################################################################### */
12719 * Register : MIO_PIN_63 @ 0XFF1800FC
12721 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
12722 * tl- (RX RGMII control )
12723 * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0
12725 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12726 * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
12728 * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1
12730 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12732 * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0
12734 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
12735 * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
12736 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12737 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12738 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
12739 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
12740 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
12741 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12742 * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0
12744 * Configures MIO Pin 63 peripheral interface mapping
12745 * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U)
12747 PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U);
12748 /*##################################################################### */
12751 * Register : MIO_PIN_64 @ 0XFF180100
12753 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
12754 * clk- (TX RGMII clock)
12755 * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1
12757 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
12759 * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0
12761 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
12762 * (SDSDIO clock) 2= Not Used 3= Not Used
12763 * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0
12765 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0=
12766 * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p
12767 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12768 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12769 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4
12770 * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in-
12771 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
12772 * trace, Output, tracedq[10]- (Trace Port Databus)
12773 * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0
12775 * Configures MIO Pin 64 peripheral interface mapping
12776 * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U)
12778 PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U);
12779 /*##################################################################### */
12782 * Register : MIO_PIN_65 @ 0XFF180104
12784 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12785 * [0]- (TX RGMII data)
12786 * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1
12788 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
12789 * (Data bus direction control)
12790 * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0
12792 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
12793 * card detect from connector) 2= Not Used 3= Not Used
12794 * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0
12796 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0=
12797 * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph
12798 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12799 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12800 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M
12801 * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u
12802 * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
12803 * dq[11]- (Trace Port Databus)
12804 * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0
12806 * Configures MIO Pin 65 peripheral interface mapping
12807 * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U)
12809 PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U);
12810 /*##################################################################### */
12813 * Register : MIO_PIN_66 @ 0XFF180108
12815 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12816 * [1]- (TX RGMII data)
12817 * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1
12819 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12820 * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
12822 * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0
12824 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
12825 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
12827 * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0
12829 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0=
12830 * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph
12831 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12832 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12833 * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast
12834 * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_
12835 * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
12837 * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0
12839 * Configures MIO Pin 66 peripheral interface mapping
12840 * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U)
12842 PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U);
12843 /*##################################################################### */
12846 * Register : MIO_PIN_67 @ 0XFF18010C
12848 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12849 * [2]- (TX RGMII data)
12850 * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1
12852 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
12853 * (Data flow control signal from the PHY)
12854 * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0
12856 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
12857 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
12858 * ot Used 3= Not Used
12859 * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0
12861 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0=
12862 * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p
12863 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12864 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12865 * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste
12866 * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt
12867 * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
12868 * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
12870 * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0
12872 * Configures MIO Pin 67 peripheral interface mapping
12873 * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U)
12875 PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U);
12876 /*##################################################################### */
12879 * Register : MIO_PIN_68 @ 0XFF180110
12881 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12882 * [3]- (TX RGMII data)
12883 * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1
12885 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12886 * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
12888 * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0
12890 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
12891 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
12892 * ot Used 3= Not Used
12893 * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0
12895 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0=
12896 * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p
12897 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12898 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12899 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
12900 * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
12901 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
12902 * Output, tracedq[14]- (Trace Port Databus)
12903 * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0
12905 * Configures MIO Pin 68 peripheral interface mapping
12906 * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U)
12908 PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U);
12909 /*##################################################################### */
12912 * Register : MIO_PIN_69 @ 0XFF180114
12914 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
12915 * ctl- (TX RGMII control)
12916 * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1
12918 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12919 * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
12921 * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0
12923 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
12924 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
12925 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
12926 * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0
12928 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0=
12929 * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph
12930 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12931 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12932 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
12933 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
12934 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12935 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
12936 * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0
12938 * Configures MIO Pin 69 peripheral interface mapping
12939 * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U)
12941 PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U);
12942 /*##################################################################### */
12945 * Register : MIO_PIN_70 @ 0XFF180118
12947 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
12948 * lk- (RX RGMII clock)
12949 * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1
12951 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
12952 * (Asserted to end or interrupt transfers)
12953 * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0
12955 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
12956 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
12957 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
12958 * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0
12960 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0=
12961 * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph
12962 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12963 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12964 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
12965 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
12966 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
12968 * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0
12970 * Configures MIO Pin 70 peripheral interface mapping
12971 * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U)
12973 PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U);
12974 /*##################################################################### */
12977 * Register : MIO_PIN_71 @ 0XFF18011C
12979 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
12980 * 0]- (RX RGMII data)
12981 * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1
12983 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12984 * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
12986 * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0
12988 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
12989 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
12990 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12991 * t[0]- (8-bit Data bus) 3= Not Used
12992 * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0
12994 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0=
12995 * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p
12996 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12997 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12998 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
12999 * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
13000 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
13001 * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0
13003 * Configures MIO Pin 71 peripheral interface mapping
13004 * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U)
13006 PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U);
13007 /*##################################################################### */
13010 * Register : MIO_PIN_72 @ 0XFF180120
13012 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
13013 * 1]- (RX RGMII data)
13014 * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1
13016 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13017 * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
13019 * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0
13021 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
13022 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
13023 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13024 * t[1]- (8-bit Data bus) 3= Not Used
13025 * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0
13027 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0=
13028 * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p
13029 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
13030 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
13031 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
13032 * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
13033 * al output) 7= Not Used
13034 * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0
13036 * Configures MIO Pin 72 peripheral interface mapping
13037 * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U)
13039 PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U);
13040 /*##################################################################### */
13043 * Register : MIO_PIN_73 @ 0XFF180124
13045 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
13046 * 2]- (RX RGMII data)
13047 * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1
13049 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13050 * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
13052 * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0
13054 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
13055 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
13056 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13057 * t[2]- (8-bit Data bus) 3= Not Used
13058 * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0
13060 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0=
13061 * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph
13062 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
13063 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
13064 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
13065 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
13066 * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13067 * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0
13069 * Configures MIO Pin 73 peripheral interface mapping
13070 * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U)
13072 PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U);
13073 /*##################################################################### */
13076 * Register : MIO_PIN_74 @ 0XFF180128
13078 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
13079 * 3]- (RX RGMII data)
13080 * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1
13082 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13083 * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
13085 * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0
13087 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
13088 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
13089 * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13090 * t[3]- (8-bit Data bus) 3= Not Used
13091 * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0
13093 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0=
13094 * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph
13095 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
13096 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
13097 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
13098 * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
13099 * UART receiver serial input) 7= Not Used
13100 * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0
13102 * Configures MIO Pin 74 peripheral interface mapping
13103 * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U)
13105 PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U);
13106 /*##################################################################### */
13109 * Register : MIO_PIN_75 @ 0XFF18012C
13111 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
13112 * tl- (RX RGMII control )
13113 * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1
13115 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13116 * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
13118 * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0
13120 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
13121 * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
13122 * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13123 * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0
13125 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0=
13126 * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p
13127 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
13128 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
13129 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
13130 * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
13131 * xd- (UART transmitter serial output) 7= Not Used
13132 * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0
13134 * Configures MIO Pin 75 peripheral interface mapping
13135 * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U)
13137 PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U);
13138 /*##################################################################### */
13141 * Register : MIO_PIN_76 @ 0XFF180130
13143 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
13144 * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0
13146 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13147 * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0
13149 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
13150 * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
13151 * clock) 3= Not Used
13152 * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0
13154 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0=
13155 * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p
13156 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
13157 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI
13158 * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
13159 * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
13160 * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6
13162 * Configures MIO Pin 76 peripheral interface mapping
13163 * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U)
13165 PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U);
13166 /*##################################################################### */
13169 * Register : MIO_PIN_77 @ 0XFF180134
13171 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
13172 * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0
13174 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13175 * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0
13177 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
13178 * 1_cd_n- (SD card detect from connector) 3= Not Used
13179 * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0
13181 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0=
13182 * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph
13183 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
13184 * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M
13185 * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input,
13186 * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5
13187 * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou
13188 * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
13189 * ut, gem3_mdio_out- (MDIO Data) 7= Not Used
13190 * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6
13192 * Configures MIO Pin 77 peripheral interface mapping
13193 * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U)
13195 PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U);
13196 /*##################################################################### */
13199 * Register : MIO_MST_TRI0 @ 0XFF180204
13201 * Master Tri-state Enable for pin 0, active high
13202 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0
13204 * Master Tri-state Enable for pin 1, active high
13205 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0
13207 * Master Tri-state Enable for pin 2, active high
13208 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0
13210 * Master Tri-state Enable for pin 3, active high
13211 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0
13213 * Master Tri-state Enable for pin 4, active high
13214 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0
13216 * Master Tri-state Enable for pin 5, active high
13217 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0
13219 * Master Tri-state Enable for pin 6, active high
13220 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0
13222 * Master Tri-state Enable for pin 7, active high
13223 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0
13225 * Master Tri-state Enable for pin 8, active high
13226 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0
13228 * Master Tri-state Enable for pin 9, active high
13229 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0
13231 * Master Tri-state Enable for pin 10, active high
13232 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0
13234 * Master Tri-state Enable for pin 11, active high
13235 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0
13237 * Master Tri-state Enable for pin 12, active high
13238 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0
13240 * Master Tri-state Enable for pin 13, active high
13241 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0
13243 * Master Tri-state Enable for pin 14, active high
13244 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0
13246 * Master Tri-state Enable for pin 15, active high
13247 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0
13249 * Master Tri-state Enable for pin 16, active high
13250 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0
13252 * Master Tri-state Enable for pin 17, active high
13253 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0
13255 * Master Tri-state Enable for pin 18, active high
13256 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1
13258 * Master Tri-state Enable for pin 19, active high
13259 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0
13261 * Master Tri-state Enable for pin 20, active high
13262 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0
13264 * Master Tri-state Enable for pin 21, active high
13265 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1
13267 * Master Tri-state Enable for pin 22, active high
13268 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0
13270 * Master Tri-state Enable for pin 23, active high
13271 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0
13273 * Master Tri-state Enable for pin 24, active high
13274 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0
13276 * Master Tri-state Enable for pin 25, active high
13277 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
13279 * Master Tri-state Enable for pin 26, active high
13280 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
13282 * Master Tri-state Enable for pin 27, active high
13283 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
13285 * Master Tri-state Enable for pin 28, active high
13286 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
13288 * Master Tri-state Enable for pin 29, active high
13289 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
13291 * Master Tri-state Enable for pin 30, active high
13292 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
13294 * Master Tri-state Enable for pin 31, active high
13295 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
13297 * MIO pin Tri-state Enables, 31:0
13298 * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
13300 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET,
13301 0xFFFFFFFFU, 0x52240000U);
13302 /*##################################################################### */
13305 * Register : MIO_MST_TRI1 @ 0XFF180208
13307 * Master Tri-state Enable for pin 32, active high
13308 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0
13310 * Master Tri-state Enable for pin 33, active high
13311 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0
13313 * Master Tri-state Enable for pin 34, active high
13314 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0
13316 * Master Tri-state Enable for pin 35, active high
13317 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0
13319 * Master Tri-state Enable for pin 36, active high
13320 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0
13322 * Master Tri-state Enable for pin 37, active high
13323 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0
13325 * Master Tri-state Enable for pin 38, active high
13326 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0
13328 * Master Tri-state Enable for pin 39, active high
13329 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0
13331 * Master Tri-state Enable for pin 40, active high
13332 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0
13334 * Master Tri-state Enable for pin 41, active high
13335 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0
13337 * Master Tri-state Enable for pin 42, active high
13338 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0
13340 * Master Tri-state Enable for pin 43, active high
13341 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0
13343 * Master Tri-state Enable for pin 44, active high
13344 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1
13346 * Master Tri-state Enable for pin 45, active high
13347 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1
13349 * Master Tri-state Enable for pin 46, active high
13350 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0
13352 * Master Tri-state Enable for pin 47, active high
13353 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0
13355 * Master Tri-state Enable for pin 48, active high
13356 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0
13358 * Master Tri-state Enable for pin 49, active high
13359 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0
13361 * Master Tri-state Enable for pin 50, active high
13362 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0
13364 * Master Tri-state Enable for pin 51, active high
13365 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0
13367 * Master Tri-state Enable for pin 52, active high
13368 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1
13370 * Master Tri-state Enable for pin 53, active high
13371 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1
13373 * Master Tri-state Enable for pin 54, active high
13374 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0
13376 * Master Tri-state Enable for pin 55, active high
13377 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1
13379 * Master Tri-state Enable for pin 56, active high
13380 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0
13382 * Master Tri-state Enable for pin 57, active high
13383 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
13385 * Master Tri-state Enable for pin 58, active high
13386 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0
13388 * Master Tri-state Enable for pin 59, active high
13389 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0
13391 * Master Tri-state Enable for pin 60, active high
13392 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0
13394 * Master Tri-state Enable for pin 61, active high
13395 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0
13397 * Master Tri-state Enable for pin 62, active high
13398 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0
13400 * Master Tri-state Enable for pin 63, active high
13401 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0
13403 * MIO pin Tri-state Enables, 63:32
13404 * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)
13406 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET,
13407 0xFFFFFFFFU, 0x00B03000U);
13408 /*##################################################################### */
13411 * Register : MIO_MST_TRI2 @ 0XFF18020C
13413 * Master Tri-state Enable for pin 64, active high
13414 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0
13416 * Master Tri-state Enable for pin 65, active high
13417 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0
13419 * Master Tri-state Enable for pin 66, active high
13420 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0
13422 * Master Tri-state Enable for pin 67, active high
13423 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0
13425 * Master Tri-state Enable for pin 68, active high
13426 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0
13428 * Master Tri-state Enable for pin 69, active high
13429 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0
13431 * Master Tri-state Enable for pin 70, active high
13432 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1
13434 * Master Tri-state Enable for pin 71, active high
13435 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1
13437 * Master Tri-state Enable for pin 72, active high
13438 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1
13440 * Master Tri-state Enable for pin 73, active high
13441 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1
13443 * Master Tri-state Enable for pin 74, active high
13444 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1
13446 * Master Tri-state Enable for pin 75, active high
13447 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1
13449 * Master Tri-state Enable for pin 76, active high
13450 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0
13452 * Master Tri-state Enable for pin 77, active high
13453 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0
13455 * MIO pin Tri-state Enables, 77:64
13456 * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U)
13458 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET,
13459 0x00003FFFU, 0x00000FC0U);
13460 /*##################################################################### */
13463 * Register : bank0_ctrl0 @ 0XFF180138
13465 * Each bit applies to a single IO. Bit 0 for MIO[0].
13466 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1
13468 * Each bit applies to a single IO. Bit 0 for MIO[0].
13469 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1
13471 * Each bit applies to a single IO. Bit 0 for MIO[0].
13472 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1
13474 * Each bit applies to a single IO. Bit 0 for MIO[0].
13475 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1
13477 * Each bit applies to a single IO. Bit 0 for MIO[0].
13478 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1
13480 * Each bit applies to a single IO. Bit 0 for MIO[0].
13481 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1
13483 * Each bit applies to a single IO. Bit 0 for MIO[0].
13484 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1
13486 * Each bit applies to a single IO. Bit 0 for MIO[0].
13487 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1
13489 * Each bit applies to a single IO. Bit 0 for MIO[0].
13490 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1
13492 * Each bit applies to a single IO. Bit 0 for MIO[0].
13493 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1
13495 * Each bit applies to a single IO. Bit 0 for MIO[0].
13496 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1
13498 * Each bit applies to a single IO. Bit 0 for MIO[0].
13499 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1
13501 * Each bit applies to a single IO. Bit 0 for MIO[0].
13502 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1
13504 * Each bit applies to a single IO. Bit 0 for MIO[0].
13505 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1
13507 * Each bit applies to a single IO. Bit 0 for MIO[0].
13508 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1
13510 * Each bit applies to a single IO. Bit 0 for MIO[0].
13511 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1
13513 * Each bit applies to a single IO. Bit 0 for MIO[0].
13514 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1
13516 * Each bit applies to a single IO. Bit 0 for MIO[0].
13517 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1
13519 * Each bit applies to a single IO. Bit 0 for MIO[0].
13520 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1
13522 * Each bit applies to a single IO. Bit 0 for MIO[0].
13523 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1
13525 * Each bit applies to a single IO. Bit 0 for MIO[0].
13526 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1
13528 * Each bit applies to a single IO. Bit 0 for MIO[0].
13529 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1
13531 * Each bit applies to a single IO. Bit 0 for MIO[0].
13532 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1
13534 * Each bit applies to a single IO. Bit 0 for MIO[0].
13535 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1
13537 * Each bit applies to a single IO. Bit 0 for MIO[0].
13538 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1
13540 * Each bit applies to a single IO. Bit 0 for MIO[0].
13541 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1
13543 * Drive0 control to MIO Bank 0 - control MIO[25:0]
13544 * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)
13546 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET,
13547 0x03FFFFFFU, 0x03FFFFFFU);
13548 /*##################################################################### */
13551 * Register : bank0_ctrl1 @ 0XFF18013C
13553 * Each bit applies to a single IO. Bit 0 for MIO[0].
13554 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1
13556 * Each bit applies to a single IO. Bit 0 for MIO[0].
13557 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1
13559 * Each bit applies to a single IO. Bit 0 for MIO[0].
13560 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1
13562 * Each bit applies to a single IO. Bit 0 for MIO[0].
13563 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1
13565 * Each bit applies to a single IO. Bit 0 for MIO[0].
13566 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1
13568 * Each bit applies to a single IO. Bit 0 for MIO[0].
13569 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1
13571 * Each bit applies to a single IO. Bit 0 for MIO[0].
13572 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1
13574 * Each bit applies to a single IO. Bit 0 for MIO[0].
13575 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1
13577 * Each bit applies to a single IO. Bit 0 for MIO[0].
13578 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1
13580 * Each bit applies to a single IO. Bit 0 for MIO[0].
13581 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1
13583 * Each bit applies to a single IO. Bit 0 for MIO[0].
13584 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1
13586 * Each bit applies to a single IO. Bit 0 for MIO[0].
13587 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1
13589 * Each bit applies to a single IO. Bit 0 for MIO[0].
13590 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1
13592 * Each bit applies to a single IO. Bit 0 for MIO[0].
13593 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1
13595 * Each bit applies to a single IO. Bit 0 for MIO[0].
13596 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1
13598 * Each bit applies to a single IO. Bit 0 for MIO[0].
13599 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1
13601 * Each bit applies to a single IO. Bit 0 for MIO[0].
13602 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1
13604 * Each bit applies to a single IO. Bit 0 for MIO[0].
13605 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1
13607 * Each bit applies to a single IO. Bit 0 for MIO[0].
13608 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1
13610 * Each bit applies to a single IO. Bit 0 for MIO[0].
13611 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1
13613 * Each bit applies to a single IO. Bit 0 for MIO[0].
13614 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1
13616 * Each bit applies to a single IO. Bit 0 for MIO[0].
13617 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1
13619 * Each bit applies to a single IO. Bit 0 for MIO[0].
13620 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1
13622 * Each bit applies to a single IO. Bit 0 for MIO[0].
13623 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1
13625 * Each bit applies to a single IO. Bit 0 for MIO[0].
13626 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1
13628 * Each bit applies to a single IO. Bit 0 for MIO[0].
13629 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1
13631 * Drive1 control to MIO Bank 0 - control MIO[25:0]
13632 * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)
13634 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET,
13635 0x03FFFFFFU, 0x03FFFFFFU);
13636 /*##################################################################### */
13639 * Register : bank0_ctrl3 @ 0XFF180140
13641 * Each bit applies to a single IO. Bit 0 for MIO[0].
13642 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0
13644 * Each bit applies to a single IO. Bit 0 for MIO[0].
13645 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0
13647 * Each bit applies to a single IO. Bit 0 for MIO[0].
13648 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0
13650 * Each bit applies to a single IO. Bit 0 for MIO[0].
13651 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0
13653 * Each bit applies to a single IO. Bit 0 for MIO[0].
13654 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0
13656 * Each bit applies to a single IO. Bit 0 for MIO[0].
13657 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0
13659 * Each bit applies to a single IO. Bit 0 for MIO[0].
13660 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0
13662 * Each bit applies to a single IO. Bit 0 for MIO[0].
13663 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0
13665 * Each bit applies to a single IO. Bit 0 for MIO[0].
13666 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0
13668 * Each bit applies to a single IO. Bit 0 for MIO[0].
13669 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0
13671 * Each bit applies to a single IO. Bit 0 for MIO[0].
13672 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0
13674 * Each bit applies to a single IO. Bit 0 for MIO[0].
13675 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0
13677 * Each bit applies to a single IO. Bit 0 for MIO[0].
13678 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0
13680 * Each bit applies to a single IO. Bit 0 for MIO[0].
13681 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0
13683 * Each bit applies to a single IO. Bit 0 for MIO[0].
13684 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0
13686 * Each bit applies to a single IO. Bit 0 for MIO[0].
13687 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0
13689 * Each bit applies to a single IO. Bit 0 for MIO[0].
13690 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0
13692 * Each bit applies to a single IO. Bit 0 for MIO[0].
13693 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0
13695 * Each bit applies to a single IO. Bit 0 for MIO[0].
13696 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0
13698 * Each bit applies to a single IO. Bit 0 for MIO[0].
13699 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0
13701 * Each bit applies to a single IO. Bit 0 for MIO[0].
13702 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0
13704 * Each bit applies to a single IO. Bit 0 for MIO[0].
13705 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0
13707 * Each bit applies to a single IO. Bit 0 for MIO[0].
13708 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0
13710 * Each bit applies to a single IO. Bit 0 for MIO[0].
13711 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0
13713 * Each bit applies to a single IO. Bit 0 for MIO[0].
13714 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0
13716 * Each bit applies to a single IO. Bit 0 for MIO[0].
13717 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0
13719 * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
13720 * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U)
13722 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET,
13723 0x03FFFFFFU, 0x00000000U);
13724 /*##################################################################### */
13727 * Register : bank0_ctrl4 @ 0XFF180144
13729 * Each bit applies to a single IO. Bit 0 for MIO[0].
13730 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
13732 * Each bit applies to a single IO. Bit 0 for MIO[0].
13733 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
13735 * Each bit applies to a single IO. Bit 0 for MIO[0].
13736 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
13738 * Each bit applies to a single IO. Bit 0 for MIO[0].
13739 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
13741 * Each bit applies to a single IO. Bit 0 for MIO[0].
13742 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
13744 * Each bit applies to a single IO. Bit 0 for MIO[0].
13745 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
13747 * Each bit applies to a single IO. Bit 0 for MIO[0].
13748 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
13750 * Each bit applies to a single IO. Bit 0 for MIO[0].
13751 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
13753 * Each bit applies to a single IO. Bit 0 for MIO[0].
13754 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
13756 * Each bit applies to a single IO. Bit 0 for MIO[0].
13757 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
13759 * Each bit applies to a single IO. Bit 0 for MIO[0].
13760 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
13762 * Each bit applies to a single IO. Bit 0 for MIO[0].
13763 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
13765 * Each bit applies to a single IO. Bit 0 for MIO[0].
13766 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
13768 * Each bit applies to a single IO. Bit 0 for MIO[0].
13769 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
13771 * Each bit applies to a single IO. Bit 0 for MIO[0].
13772 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
13774 * Each bit applies to a single IO. Bit 0 for MIO[0].
13775 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
13777 * Each bit applies to a single IO. Bit 0 for MIO[0].
13778 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
13780 * Each bit applies to a single IO. Bit 0 for MIO[0].
13781 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
13783 * Each bit applies to a single IO. Bit 0 for MIO[0].
13784 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
13786 * Each bit applies to a single IO. Bit 0 for MIO[0].
13787 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
13789 * Each bit applies to a single IO. Bit 0 for MIO[0].
13790 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
13792 * Each bit applies to a single IO. Bit 0 for MIO[0].
13793 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
13795 * Each bit applies to a single IO. Bit 0 for MIO[0].
13796 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
13798 * Each bit applies to a single IO. Bit 0 for MIO[0].
13799 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
13801 * Each bit applies to a single IO. Bit 0 for MIO[0].
13802 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
13804 * Each bit applies to a single IO. Bit 0 for MIO[0].
13805 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
13807 * When mio_bank0_pull_enable is set, this selects pull up or pull down for
13808 * MIO Bank 0 - control MIO[25:0]
13809 * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)
13811 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET,
13812 0x03FFFFFFU, 0x03FFFFFFU);
13813 /*##################################################################### */
13816 * Register : bank0_ctrl5 @ 0XFF180148
13818 * Each bit applies to a single IO. Bit 0 for MIO[0].
13819 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1
13821 * Each bit applies to a single IO. Bit 0 for MIO[0].
13822 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1
13824 * Each bit applies to a single IO. Bit 0 for MIO[0].
13825 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1
13827 * Each bit applies to a single IO. Bit 0 for MIO[0].
13828 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1
13830 * Each bit applies to a single IO. Bit 0 for MIO[0].
13831 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1
13833 * Each bit applies to a single IO. Bit 0 for MIO[0].
13834 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1
13836 * Each bit applies to a single IO. Bit 0 for MIO[0].
13837 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1
13839 * Each bit applies to a single IO. Bit 0 for MIO[0].
13840 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1
13842 * Each bit applies to a single IO. Bit 0 for MIO[0].
13843 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1
13845 * Each bit applies to a single IO. Bit 0 for MIO[0].
13846 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1
13848 * Each bit applies to a single IO. Bit 0 for MIO[0].
13849 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1
13851 * Each bit applies to a single IO. Bit 0 for MIO[0].
13852 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1
13854 * Each bit applies to a single IO. Bit 0 for MIO[0].
13855 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1
13857 * Each bit applies to a single IO. Bit 0 for MIO[0].
13858 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1
13860 * Each bit applies to a single IO. Bit 0 for MIO[0].
13861 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1
13863 * Each bit applies to a single IO. Bit 0 for MIO[0].
13864 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1
13866 * Each bit applies to a single IO. Bit 0 for MIO[0].
13867 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1
13869 * Each bit applies to a single IO. Bit 0 for MIO[0].
13870 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1
13872 * Each bit applies to a single IO. Bit 0 for MIO[0].
13873 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1
13875 * Each bit applies to a single IO. Bit 0 for MIO[0].
13876 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1
13878 * Each bit applies to a single IO. Bit 0 for MIO[0].
13879 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1
13881 * Each bit applies to a single IO. Bit 0 for MIO[0].
13882 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1
13884 * Each bit applies to a single IO. Bit 0 for MIO[0].
13885 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1
13887 * Each bit applies to a single IO. Bit 0 for MIO[0].
13888 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1
13890 * Each bit applies to a single IO. Bit 0 for MIO[0].
13891 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1
13893 * Each bit applies to a single IO. Bit 0 for MIO[0].
13894 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1
13896 * When set, this enables mio_bank0_pullupdown to selects pull up or pull d
13897 * own for MIO Bank 0 - control MIO[25:0]
13898 * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)
13900 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET,
13901 0x03FFFFFFU, 0x03FFFFFFU);
13902 /*##################################################################### */
13905 * Register : bank0_ctrl6 @ 0XFF18014C
13907 * Each bit applies to a single IO. Bit 0 for MIO[0].
13908 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
13910 * Each bit applies to a single IO. Bit 0 for MIO[0].
13911 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
13913 * Each bit applies to a single IO. Bit 0 for MIO[0].
13914 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
13916 * Each bit applies to a single IO. Bit 0 for MIO[0].
13917 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
13919 * Each bit applies to a single IO. Bit 0 for MIO[0].
13920 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
13922 * Each bit applies to a single IO. Bit 0 for MIO[0].
13923 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
13925 * Each bit applies to a single IO. Bit 0 for MIO[0].
13926 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
13928 * Each bit applies to a single IO. Bit 0 for MIO[0].
13929 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
13931 * Each bit applies to a single IO. Bit 0 for MIO[0].
13932 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
13934 * Each bit applies to a single IO. Bit 0 for MIO[0].
13935 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
13937 * Each bit applies to a single IO. Bit 0 for MIO[0].
13938 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
13940 * Each bit applies to a single IO. Bit 0 for MIO[0].
13941 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
13943 * Each bit applies to a single IO. Bit 0 for MIO[0].
13944 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
13946 * Each bit applies to a single IO. Bit 0 for MIO[0].
13947 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
13949 * Each bit applies to a single IO. Bit 0 for MIO[0].
13950 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
13952 * Each bit applies to a single IO. Bit 0 for MIO[0].
13953 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
13955 * Each bit applies to a single IO. Bit 0 for MIO[0].
13956 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
13958 * Each bit applies to a single IO. Bit 0 for MIO[0].
13959 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
13961 * Each bit applies to a single IO. Bit 0 for MIO[0].
13962 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
13964 * Each bit applies to a single IO. Bit 0 for MIO[0].
13965 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
13967 * Each bit applies to a single IO. Bit 0 for MIO[0].
13968 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
13970 * Each bit applies to a single IO. Bit 0 for MIO[0].
13971 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
13973 * Each bit applies to a single IO. Bit 0 for MIO[0].
13974 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
13976 * Each bit applies to a single IO. Bit 0 for MIO[0].
13977 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
13979 * Each bit applies to a single IO. Bit 0 for MIO[0].
13980 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
13982 * Each bit applies to a single IO. Bit 0 for MIO[0].
13983 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
13985 * Slew rate control to MIO Bank 0 - control MIO[25:0]
13986 * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U)
13988 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET,
13989 0x03FFFFFFU, 0x00000000U);
13990 /*##################################################################### */
13993 * Register : bank1_ctrl0 @ 0XFF180154
13995 * Each bit applies to a single IO. Bit 0 for MIO[26].
13996 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1
13998 * Each bit applies to a single IO. Bit 0 for MIO[26].
13999 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1
14001 * Each bit applies to a single IO. Bit 0 for MIO[26].
14002 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1
14004 * Each bit applies to a single IO. Bit 0 for MIO[26].
14005 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1
14007 * Each bit applies to a single IO. Bit 0 for MIO[26].
14008 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1
14010 * Each bit applies to a single IO. Bit 0 for MIO[26].
14011 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1
14013 * Each bit applies to a single IO. Bit 0 for MIO[26].
14014 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1
14016 * Each bit applies to a single IO. Bit 0 for MIO[26].
14017 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1
14019 * Each bit applies to a single IO. Bit 0 for MIO[26].
14020 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1
14022 * Each bit applies to a single IO. Bit 0 for MIO[26].
14023 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1
14025 * Each bit applies to a single IO. Bit 0 for MIO[26].
14026 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1
14028 * Each bit applies to a single IO. Bit 0 for MIO[26].
14029 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1
14031 * Each bit applies to a single IO. Bit 0 for MIO[26].
14032 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1
14034 * Each bit applies to a single IO. Bit 0 for MIO[26].
14035 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1
14037 * Each bit applies to a single IO. Bit 0 for MIO[26].
14038 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1
14040 * Each bit applies to a single IO. Bit 0 for MIO[26].
14041 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1
14043 * Each bit applies to a single IO. Bit 0 for MIO[26].
14044 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1
14046 * Each bit applies to a single IO. Bit 0 for MIO[26].
14047 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1
14049 * Each bit applies to a single IO. Bit 0 for MIO[26].
14050 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1
14052 * Each bit applies to a single IO. Bit 0 for MIO[26].
14053 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1
14055 * Each bit applies to a single IO. Bit 0 for MIO[26].
14056 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1
14058 * Each bit applies to a single IO. Bit 0 for MIO[26].
14059 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1
14061 * Each bit applies to a single IO. Bit 0 for MIO[26].
14062 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1
14064 * Each bit applies to a single IO. Bit 0 for MIO[26].
14065 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1
14067 * Each bit applies to a single IO. Bit 0 for MIO[26].
14068 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1
14070 * Each bit applies to a single IO. Bit 0 for MIO[26].
14071 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1
14073 * Drive0 control to MIO Bank 1 - control MIO[51:26]
14074 * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)
14076 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET,
14077 0x03FFFFFFU, 0x03FFFFFFU);
14078 /*##################################################################### */
14081 * Register : bank1_ctrl1 @ 0XFF180158
14083 * Each bit applies to a single IO. Bit 0 for MIO[26].
14084 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1
14086 * Each bit applies to a single IO. Bit 0 for MIO[26].
14087 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1
14089 * Each bit applies to a single IO. Bit 0 for MIO[26].
14090 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1
14092 * Each bit applies to a single IO. Bit 0 for MIO[26].
14093 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1
14095 * Each bit applies to a single IO. Bit 0 for MIO[26].
14096 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1
14098 * Each bit applies to a single IO. Bit 0 for MIO[26].
14099 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1
14101 * Each bit applies to a single IO. Bit 0 for MIO[26].
14102 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1
14104 * Each bit applies to a single IO. Bit 0 for MIO[26].
14105 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1
14107 * Each bit applies to a single IO. Bit 0 for MIO[26].
14108 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1
14110 * Each bit applies to a single IO. Bit 0 for MIO[26].
14111 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1
14113 * Each bit applies to a single IO. Bit 0 for MIO[26].
14114 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1
14116 * Each bit applies to a single IO. Bit 0 for MIO[26].
14117 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1
14119 * Each bit applies to a single IO. Bit 0 for MIO[26].
14120 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1
14122 * Each bit applies to a single IO. Bit 0 for MIO[26].
14123 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1
14125 * Each bit applies to a single IO. Bit 0 for MIO[26].
14126 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1
14128 * Each bit applies to a single IO. Bit 0 for MIO[26].
14129 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1
14131 * Each bit applies to a single IO. Bit 0 for MIO[26].
14132 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1
14134 * Each bit applies to a single IO. Bit 0 for MIO[26].
14135 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1
14137 * Each bit applies to a single IO. Bit 0 for MIO[26].
14138 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1
14140 * Each bit applies to a single IO. Bit 0 for MIO[26].
14141 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1
14143 * Each bit applies to a single IO. Bit 0 for MIO[26].
14144 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1
14146 * Each bit applies to a single IO. Bit 0 for MIO[26].
14147 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1
14149 * Each bit applies to a single IO. Bit 0 for MIO[26].
14150 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1
14152 * Each bit applies to a single IO. Bit 0 for MIO[26].
14153 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1
14155 * Each bit applies to a single IO. Bit 0 for MIO[26].
14156 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1
14158 * Each bit applies to a single IO. Bit 0 for MIO[26].
14159 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1
14161 * Drive1 control to MIO Bank 1 - control MIO[51:26]
14162 * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)
14164 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET,
14165 0x03FFFFFFU, 0x03FFFFFFU);
14166 /*##################################################################### */
14169 * Register : bank1_ctrl3 @ 0XFF18015C
14171 * Each bit applies to a single IO. Bit 0 for MIO[26].
14172 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0
14174 * Each bit applies to a single IO. Bit 0 for MIO[26].
14175 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0
14177 * Each bit applies to a single IO. Bit 0 for MIO[26].
14178 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0
14180 * Each bit applies to a single IO. Bit 0 for MIO[26].
14181 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0
14183 * Each bit applies to a single IO. Bit 0 for MIO[26].
14184 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0
14186 * Each bit applies to a single IO. Bit 0 for MIO[26].
14187 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0
14189 * Each bit applies to a single IO. Bit 0 for MIO[26].
14190 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0
14192 * Each bit applies to a single IO. Bit 0 for MIO[26].
14193 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0
14195 * Each bit applies to a single IO. Bit 0 for MIO[26].
14196 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0
14198 * Each bit applies to a single IO. Bit 0 for MIO[26].
14199 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0
14201 * Each bit applies to a single IO. Bit 0 for MIO[26].
14202 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0
14204 * Each bit applies to a single IO. Bit 0 for MIO[26].
14205 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0
14207 * Each bit applies to a single IO. Bit 0 for MIO[26].
14208 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0
14210 * Each bit applies to a single IO. Bit 0 for MIO[26].
14211 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0
14213 * Each bit applies to a single IO. Bit 0 for MIO[26].
14214 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0
14216 * Each bit applies to a single IO. Bit 0 for MIO[26].
14217 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0
14219 * Each bit applies to a single IO. Bit 0 for MIO[26].
14220 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0
14222 * Each bit applies to a single IO. Bit 0 for MIO[26].
14223 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0
14225 * Each bit applies to a single IO. Bit 0 for MIO[26].
14226 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0
14228 * Each bit applies to a single IO. Bit 0 for MIO[26].
14229 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0
14231 * Each bit applies to a single IO. Bit 0 for MIO[26].
14232 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0
14234 * Each bit applies to a single IO. Bit 0 for MIO[26].
14235 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0
14237 * Each bit applies to a single IO. Bit 0 for MIO[26].
14238 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0
14240 * Each bit applies to a single IO. Bit 0 for MIO[26].
14241 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0
14243 * Each bit applies to a single IO. Bit 0 for MIO[26].
14244 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0
14246 * Each bit applies to a single IO. Bit 0 for MIO[26].
14247 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0
14249 * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
14250 * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U)
14252 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET,
14253 0x03FFFFFFU, 0x00000000U);
14254 /*##################################################################### */
14257 * Register : bank1_ctrl4 @ 0XFF180160
14259 * Each bit applies to a single IO. Bit 0 for MIO[26].
14260 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
14262 * Each bit applies to a single IO. Bit 0 for MIO[26].
14263 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
14265 * Each bit applies to a single IO. Bit 0 for MIO[26].
14266 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
14268 * Each bit applies to a single IO. Bit 0 for MIO[26].
14269 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
14271 * Each bit applies to a single IO. Bit 0 for MIO[26].
14272 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
14274 * Each bit applies to a single IO. Bit 0 for MIO[26].
14275 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
14277 * Each bit applies to a single IO. Bit 0 for MIO[26].
14278 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
14280 * Each bit applies to a single IO. Bit 0 for MIO[26].
14281 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
14283 * Each bit applies to a single IO. Bit 0 for MIO[26].
14284 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
14286 * Each bit applies to a single IO. Bit 0 for MIO[26].
14287 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
14289 * Each bit applies to a single IO. Bit 0 for MIO[26].
14290 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
14292 * Each bit applies to a single IO. Bit 0 for MIO[26].
14293 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
14295 * Each bit applies to a single IO. Bit 0 for MIO[26].
14296 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
14298 * Each bit applies to a single IO. Bit 0 for MIO[26].
14299 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
14301 * Each bit applies to a single IO. Bit 0 for MIO[26].
14302 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
14304 * Each bit applies to a single IO. Bit 0 for MIO[26].
14305 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
14307 * Each bit applies to a single IO. Bit 0 for MIO[26].
14308 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
14310 * Each bit applies to a single IO. Bit 0 for MIO[26].
14311 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
14313 * Each bit applies to a single IO. Bit 0 for MIO[26].
14314 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
14316 * Each bit applies to a single IO. Bit 0 for MIO[26].
14317 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
14319 * Each bit applies to a single IO. Bit 0 for MIO[26].
14320 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
14322 * Each bit applies to a single IO. Bit 0 for MIO[26].
14323 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
14325 * Each bit applies to a single IO. Bit 0 for MIO[26].
14326 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
14328 * Each bit applies to a single IO. Bit 0 for MIO[26].
14329 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
14331 * Each bit applies to a single IO. Bit 0 for MIO[26].
14332 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
14334 * Each bit applies to a single IO. Bit 0 for MIO[26].
14335 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
14337 * When mio_bank1_pull_enable is set, this selects pull up or pull down for
14338 * MIO Bank 1 - control MIO[51:26]
14339 * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)
14341 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET,
14342 0x03FFFFFFU, 0x03FFFFFFU);
14343 /*##################################################################### */
14346 * Register : bank1_ctrl5 @ 0XFF180164
14348 * Each bit applies to a single IO. Bit 0 for MIO[26].
14349 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1
14351 * Each bit applies to a single IO. Bit 0 for MIO[26].
14352 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1
14354 * Each bit applies to a single IO. Bit 0 for MIO[26].
14355 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1
14357 * Each bit applies to a single IO. Bit 0 for MIO[26].
14358 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1
14360 * Each bit applies to a single IO. Bit 0 for MIO[26].
14361 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1
14363 * Each bit applies to a single IO. Bit 0 for MIO[26].
14364 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1
14366 * Each bit applies to a single IO. Bit 0 for MIO[26].
14367 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1
14369 * Each bit applies to a single IO. Bit 0 for MIO[26].
14370 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1
14372 * Each bit applies to a single IO. Bit 0 for MIO[26].
14373 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1
14375 * Each bit applies to a single IO. Bit 0 for MIO[26].
14376 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1
14378 * Each bit applies to a single IO. Bit 0 for MIO[26].
14379 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1
14381 * Each bit applies to a single IO. Bit 0 for MIO[26].
14382 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1
14384 * Each bit applies to a single IO. Bit 0 for MIO[26].
14385 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1
14387 * Each bit applies to a single IO. Bit 0 for MIO[26].
14388 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1
14390 * Each bit applies to a single IO. Bit 0 for MIO[26].
14391 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1
14393 * Each bit applies to a single IO. Bit 0 for MIO[26].
14394 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1
14396 * Each bit applies to a single IO. Bit 0 for MIO[26].
14397 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1
14399 * Each bit applies to a single IO. Bit 0 for MIO[26].
14400 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1
14402 * Each bit applies to a single IO. Bit 0 for MIO[26].
14403 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1
14405 * Each bit applies to a single IO. Bit 0 for MIO[26].
14406 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1
14408 * Each bit applies to a single IO. Bit 0 for MIO[26].
14409 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1
14411 * Each bit applies to a single IO. Bit 0 for MIO[26].
14412 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1
14414 * Each bit applies to a single IO. Bit 0 for MIO[26].
14415 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1
14417 * Each bit applies to a single IO. Bit 0 for MIO[26].
14418 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1
14420 * Each bit applies to a single IO. Bit 0 for MIO[26].
14421 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1
14423 * Each bit applies to a single IO. Bit 0 for MIO[26].
14424 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1
14426 * When set, this enables mio_bank1_pullupdown to selects pull up or pull d
14427 * own for MIO Bank 1 - control MIO[51:26]
14428 * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)
14430 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET,
14431 0x03FFFFFFU, 0x03FFFFFFU);
14432 /*##################################################################### */
14435 * Register : bank1_ctrl6 @ 0XFF180168
14437 * Each bit applies to a single IO. Bit 0 for MIO[26].
14438 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
14440 * Each bit applies to a single IO. Bit 0 for MIO[26].
14441 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
14443 * Each bit applies to a single IO. Bit 0 for MIO[26].
14444 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
14446 * Each bit applies to a single IO. Bit 0 for MIO[26].
14447 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
14449 * Each bit applies to a single IO. Bit 0 for MIO[26].
14450 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
14452 * Each bit applies to a single IO. Bit 0 for MIO[26].
14453 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
14455 * Each bit applies to a single IO. Bit 0 for MIO[26].
14456 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
14458 * Each bit applies to a single IO. Bit 0 for MIO[26].
14459 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
14461 * Each bit applies to a single IO. Bit 0 for MIO[26].
14462 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
14464 * Each bit applies to a single IO. Bit 0 for MIO[26].
14465 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
14467 * Each bit applies to a single IO. Bit 0 for MIO[26].
14468 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
14470 * Each bit applies to a single IO. Bit 0 for MIO[26].
14471 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
14473 * Each bit applies to a single IO. Bit 0 for MIO[26].
14474 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
14476 * Each bit applies to a single IO. Bit 0 for MIO[26].
14477 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
14479 * Each bit applies to a single IO. Bit 0 for MIO[26].
14480 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
14482 * Each bit applies to a single IO. Bit 0 for MIO[26].
14483 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
14485 * Each bit applies to a single IO. Bit 0 for MIO[26].
14486 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
14488 * Each bit applies to a single IO. Bit 0 for MIO[26].
14489 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
14491 * Each bit applies to a single IO. Bit 0 for MIO[26].
14492 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
14494 * Each bit applies to a single IO. Bit 0 for MIO[26].
14495 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
14497 * Each bit applies to a single IO. Bit 0 for MIO[26].
14498 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
14500 * Each bit applies to a single IO. Bit 0 for MIO[26].
14501 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
14503 * Each bit applies to a single IO. Bit 0 for MIO[26].
14504 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
14506 * Each bit applies to a single IO. Bit 0 for MIO[26].
14507 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
14509 * Each bit applies to a single IO. Bit 0 for MIO[26].
14510 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
14512 * Each bit applies to a single IO. Bit 0 for MIO[26].
14513 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
14515 * Slew rate control to MIO Bank 1 - control MIO[51:26]
14516 * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U)
14518 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET,
14519 0x03FFFFFFU, 0x00000000U);
14520 /*##################################################################### */
14523 * Register : bank2_ctrl0 @ 0XFF180170
14525 * Each bit applies to a single IO. Bit 0 for MIO[52].
14526 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1
14528 * Each bit applies to a single IO. Bit 0 for MIO[52].
14529 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1
14531 * Each bit applies to a single IO. Bit 0 for MIO[52].
14532 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1
14534 * Each bit applies to a single IO. Bit 0 for MIO[52].
14535 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1
14537 * Each bit applies to a single IO. Bit 0 for MIO[52].
14538 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1
14540 * Each bit applies to a single IO. Bit 0 for MIO[52].
14541 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1
14543 * Each bit applies to a single IO. Bit 0 for MIO[52].
14544 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1
14546 * Each bit applies to a single IO. Bit 0 for MIO[52].
14547 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1
14549 * Each bit applies to a single IO. Bit 0 for MIO[52].
14550 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1
14552 * Each bit applies to a single IO. Bit 0 for MIO[52].
14553 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1
14555 * Each bit applies to a single IO. Bit 0 for MIO[52].
14556 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1
14558 * Each bit applies to a single IO. Bit 0 for MIO[52].
14559 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1
14561 * Each bit applies to a single IO. Bit 0 for MIO[52].
14562 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1
14564 * Each bit applies to a single IO. Bit 0 for MIO[52].
14565 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1
14567 * Each bit applies to a single IO. Bit 0 for MIO[52].
14568 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1
14570 * Each bit applies to a single IO. Bit 0 for MIO[52].
14571 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1
14573 * Each bit applies to a single IO. Bit 0 for MIO[52].
14574 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1
14576 * Each bit applies to a single IO. Bit 0 for MIO[52].
14577 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1
14579 * Each bit applies to a single IO. Bit 0 for MIO[52].
14580 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1
14582 * Each bit applies to a single IO. Bit 0 for MIO[52].
14583 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1
14585 * Each bit applies to a single IO. Bit 0 for MIO[52].
14586 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1
14588 * Each bit applies to a single IO. Bit 0 for MIO[52].
14589 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1
14591 * Each bit applies to a single IO. Bit 0 for MIO[52].
14592 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1
14594 * Each bit applies to a single IO. Bit 0 for MIO[52].
14595 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1
14597 * Each bit applies to a single IO. Bit 0 for MIO[52].
14598 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1
14600 * Each bit applies to a single IO. Bit 0 for MIO[52].
14601 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1
14603 * Drive0 control to MIO Bank 2 - control MIO[77:52]
14604 * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)
14606 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET,
14607 0x03FFFFFFU, 0x03FFFFFFU);
14608 /*##################################################################### */
14611 * Register : bank2_ctrl1 @ 0XFF180174
14613 * Each bit applies to a single IO. Bit 0 for MIO[52].
14614 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1
14616 * Each bit applies to a single IO. Bit 0 for MIO[52].
14617 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1
14619 * Each bit applies to a single IO. Bit 0 for MIO[52].
14620 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1
14622 * Each bit applies to a single IO. Bit 0 for MIO[52].
14623 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1
14625 * Each bit applies to a single IO. Bit 0 for MIO[52].
14626 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1
14628 * Each bit applies to a single IO. Bit 0 for MIO[52].
14629 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1
14631 * Each bit applies to a single IO. Bit 0 for MIO[52].
14632 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1
14634 * Each bit applies to a single IO. Bit 0 for MIO[52].
14635 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1
14637 * Each bit applies to a single IO. Bit 0 for MIO[52].
14638 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1
14640 * Each bit applies to a single IO. Bit 0 for MIO[52].
14641 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1
14643 * Each bit applies to a single IO. Bit 0 for MIO[52].
14644 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1
14646 * Each bit applies to a single IO. Bit 0 for MIO[52].
14647 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1
14649 * Each bit applies to a single IO. Bit 0 for MIO[52].
14650 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1
14652 * Each bit applies to a single IO. Bit 0 for MIO[52].
14653 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1
14655 * Each bit applies to a single IO. Bit 0 for MIO[52].
14656 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1
14658 * Each bit applies to a single IO. Bit 0 for MIO[52].
14659 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1
14661 * Each bit applies to a single IO. Bit 0 for MIO[52].
14662 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1
14664 * Each bit applies to a single IO. Bit 0 for MIO[52].
14665 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1
14667 * Each bit applies to a single IO. Bit 0 for MIO[52].
14668 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1
14670 * Each bit applies to a single IO. Bit 0 for MIO[52].
14671 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1
14673 * Each bit applies to a single IO. Bit 0 for MIO[52].
14674 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1
14676 * Each bit applies to a single IO. Bit 0 for MIO[52].
14677 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1
14679 * Each bit applies to a single IO. Bit 0 for MIO[52].
14680 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1
14682 * Each bit applies to a single IO. Bit 0 for MIO[52].
14683 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1
14685 * Each bit applies to a single IO. Bit 0 for MIO[52].
14686 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1
14688 * Each bit applies to a single IO. Bit 0 for MIO[52].
14689 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1
14691 * Drive1 control to MIO Bank 2 - control MIO[77:52]
14692 * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)
14694 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET,
14695 0x03FFFFFFU, 0x03FFFFFFU);
14696 /*##################################################################### */
14699 * Register : bank2_ctrl3 @ 0XFF180178
14701 * Each bit applies to a single IO. Bit 0 for MIO[52].
14702 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0
14704 * Each bit applies to a single IO. Bit 0 for MIO[52].
14705 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0
14707 * Each bit applies to a single IO. Bit 0 for MIO[52].
14708 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0
14710 * Each bit applies to a single IO. Bit 0 for MIO[52].
14711 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0
14713 * Each bit applies to a single IO. Bit 0 for MIO[52].
14714 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0
14716 * Each bit applies to a single IO. Bit 0 for MIO[52].
14717 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0
14719 * Each bit applies to a single IO. Bit 0 for MIO[52].
14720 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0
14722 * Each bit applies to a single IO. Bit 0 for MIO[52].
14723 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0
14725 * Each bit applies to a single IO. Bit 0 for MIO[52].
14726 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0
14728 * Each bit applies to a single IO. Bit 0 for MIO[52].
14729 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0
14731 * Each bit applies to a single IO. Bit 0 for MIO[52].
14732 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0
14734 * Each bit applies to a single IO. Bit 0 for MIO[52].
14735 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0
14737 * Each bit applies to a single IO. Bit 0 for MIO[52].
14738 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0
14740 * Each bit applies to a single IO. Bit 0 for MIO[52].
14741 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0
14743 * Each bit applies to a single IO. Bit 0 for MIO[52].
14744 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0
14746 * Each bit applies to a single IO. Bit 0 for MIO[52].
14747 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0
14749 * Each bit applies to a single IO. Bit 0 for MIO[52].
14750 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0
14752 * Each bit applies to a single IO. Bit 0 for MIO[52].
14753 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0
14755 * Each bit applies to a single IO. Bit 0 for MIO[52].
14756 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0
14758 * Each bit applies to a single IO. Bit 0 for MIO[52].
14759 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0
14761 * Each bit applies to a single IO. Bit 0 for MIO[52].
14762 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0
14764 * Each bit applies to a single IO. Bit 0 for MIO[52].
14765 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0
14767 * Each bit applies to a single IO. Bit 0 for MIO[52].
14768 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0
14770 * Each bit applies to a single IO. Bit 0 for MIO[52].
14771 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0
14773 * Each bit applies to a single IO. Bit 0 for MIO[52].
14774 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0
14776 * Each bit applies to a single IO. Bit 0 for MIO[52].
14777 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0
14779 * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
14780 * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U)
14782 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET,
14783 0x03FFFFFFU, 0x00000000U);
14784 /*##################################################################### */
14787 * Register : bank2_ctrl4 @ 0XFF18017C
14789 * Each bit applies to a single IO. Bit 0 for MIO[52].
14790 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
14792 * Each bit applies to a single IO. Bit 0 for MIO[52].
14793 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
14795 * Each bit applies to a single IO. Bit 0 for MIO[52].
14796 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
14798 * Each bit applies to a single IO. Bit 0 for MIO[52].
14799 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
14801 * Each bit applies to a single IO. Bit 0 for MIO[52].
14802 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
14804 * Each bit applies to a single IO. Bit 0 for MIO[52].
14805 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
14807 * Each bit applies to a single IO. Bit 0 for MIO[52].
14808 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
14810 * Each bit applies to a single IO. Bit 0 for MIO[52].
14811 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
14813 * Each bit applies to a single IO. Bit 0 for MIO[52].
14814 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
14816 * Each bit applies to a single IO. Bit 0 for MIO[52].
14817 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
14819 * Each bit applies to a single IO. Bit 0 for MIO[52].
14820 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
14822 * Each bit applies to a single IO. Bit 0 for MIO[52].
14823 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
14825 * Each bit applies to a single IO. Bit 0 for MIO[52].
14826 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
14828 * Each bit applies to a single IO. Bit 0 for MIO[52].
14829 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
14831 * Each bit applies to a single IO. Bit 0 for MIO[52].
14832 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
14834 * Each bit applies to a single IO. Bit 0 for MIO[52].
14835 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
14837 * Each bit applies to a single IO. Bit 0 for MIO[52].
14838 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
14840 * Each bit applies to a single IO. Bit 0 for MIO[52].
14841 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
14843 * Each bit applies to a single IO. Bit 0 for MIO[52].
14844 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
14846 * Each bit applies to a single IO. Bit 0 for MIO[52].
14847 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
14849 * Each bit applies to a single IO. Bit 0 for MIO[52].
14850 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
14852 * Each bit applies to a single IO. Bit 0 for MIO[52].
14853 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
14855 * Each bit applies to a single IO. Bit 0 for MIO[52].
14856 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
14858 * Each bit applies to a single IO. Bit 0 for MIO[52].
14859 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
14861 * Each bit applies to a single IO. Bit 0 for MIO[52].
14862 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
14864 * Each bit applies to a single IO. Bit 0 for MIO[52].
14865 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
14867 * When mio_bank2_pull_enable is set, this selects pull up or pull down for
14868 * MIO Bank 2 - control MIO[77:52]
14869 * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)
14871 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET,
14872 0x03FFFFFFU, 0x03FFFFFFU);
14873 /*##################################################################### */
14876 * Register : bank2_ctrl5 @ 0XFF180180
14878 * Each bit applies to a single IO. Bit 0 for MIO[52].
14879 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1
14881 * Each bit applies to a single IO. Bit 0 for MIO[52].
14882 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1
14884 * Each bit applies to a single IO. Bit 0 for MIO[52].
14885 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1
14887 * Each bit applies to a single IO. Bit 0 for MIO[52].
14888 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1
14890 * Each bit applies to a single IO. Bit 0 for MIO[52].
14891 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1
14893 * Each bit applies to a single IO. Bit 0 for MIO[52].
14894 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1
14896 * Each bit applies to a single IO. Bit 0 for MIO[52].
14897 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1
14899 * Each bit applies to a single IO. Bit 0 for MIO[52].
14900 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1
14902 * Each bit applies to a single IO. Bit 0 for MIO[52].
14903 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1
14905 * Each bit applies to a single IO. Bit 0 for MIO[52].
14906 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1
14908 * Each bit applies to a single IO. Bit 0 for MIO[52].
14909 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1
14911 * Each bit applies to a single IO. Bit 0 for MIO[52].
14912 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1
14914 * Each bit applies to a single IO. Bit 0 for MIO[52].
14915 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1
14917 * Each bit applies to a single IO. Bit 0 for MIO[52].
14918 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1
14920 * Each bit applies to a single IO. Bit 0 for MIO[52].
14921 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1
14923 * Each bit applies to a single IO. Bit 0 for MIO[52].
14924 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1
14926 * Each bit applies to a single IO. Bit 0 for MIO[52].
14927 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1
14929 * Each bit applies to a single IO. Bit 0 for MIO[52].
14930 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1
14932 * Each bit applies to a single IO. Bit 0 for MIO[52].
14933 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1
14935 * Each bit applies to a single IO. Bit 0 for MIO[52].
14936 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1
14938 * Each bit applies to a single IO. Bit 0 for MIO[52].
14939 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1
14941 * Each bit applies to a single IO. Bit 0 for MIO[52].
14942 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1
14944 * Each bit applies to a single IO. Bit 0 for MIO[52].
14945 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1
14947 * Each bit applies to a single IO. Bit 0 for MIO[52].
14948 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1
14950 * Each bit applies to a single IO. Bit 0 for MIO[52].
14951 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1
14953 * Each bit applies to a single IO. Bit 0 for MIO[52].
14954 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1
14956 * When set, this enables mio_bank2_pullupdown to selects pull up or pull d
14957 * own for MIO Bank 2 - control MIO[77:52]
14958 * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)
14960 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET,
14961 0x03FFFFFFU, 0x03FFFFFFU);
14962 /*##################################################################### */
14965 * Register : bank2_ctrl6 @ 0XFF180184
14967 * Each bit applies to a single IO. Bit 0 for MIO[52].
14968 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
14970 * Each bit applies to a single IO. Bit 0 for MIO[52].
14971 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
14973 * Each bit applies to a single IO. Bit 0 for MIO[52].
14974 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
14976 * Each bit applies to a single IO. Bit 0 for MIO[52].
14977 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
14979 * Each bit applies to a single IO. Bit 0 for MIO[52].
14980 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
14982 * Each bit applies to a single IO. Bit 0 for MIO[52].
14983 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
14985 * Each bit applies to a single IO. Bit 0 for MIO[52].
14986 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
14988 * Each bit applies to a single IO. Bit 0 for MIO[52].
14989 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
14991 * Each bit applies to a single IO. Bit 0 for MIO[52].
14992 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
14994 * Each bit applies to a single IO. Bit 0 for MIO[52].
14995 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
14997 * Each bit applies to a single IO. Bit 0 for MIO[52].
14998 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
15000 * Each bit applies to a single IO. Bit 0 for MIO[52].
15001 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
15003 * Each bit applies to a single IO. Bit 0 for MIO[52].
15004 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
15006 * Each bit applies to a single IO. Bit 0 for MIO[52].
15007 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
15009 * Each bit applies to a single IO. Bit 0 for MIO[52].
15010 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
15012 * Each bit applies to a single IO. Bit 0 for MIO[52].
15013 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
15015 * Each bit applies to a single IO. Bit 0 for MIO[52].
15016 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
15018 * Each bit applies to a single IO. Bit 0 for MIO[52].
15019 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
15021 * Each bit applies to a single IO. Bit 0 for MIO[52].
15022 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
15024 * Each bit applies to a single IO. Bit 0 for MIO[52].
15025 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
15027 * Each bit applies to a single IO. Bit 0 for MIO[52].
15028 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
15030 * Each bit applies to a single IO. Bit 0 for MIO[52].
15031 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
15033 * Each bit applies to a single IO. Bit 0 for MIO[52].
15034 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
15036 * Each bit applies to a single IO. Bit 0 for MIO[52].
15037 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
15039 * Each bit applies to a single IO. Bit 0 for MIO[52].
15040 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
15042 * Each bit applies to a single IO. Bit 0 for MIO[52].
15043 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
15045 * Slew rate control to MIO Bank 2 - control MIO[77:52]
15046 * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U)
15048 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET,
15049 0x03FFFFFFU, 0x00000000U);
15050 /*##################################################################### */
15056 * Register : MIO_LOOPBACK @ 0XFF180200
15058 * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1
15059 * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
15061 * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0
15063 * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
15064 * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
15065 * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0
15067 * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping.
15068 * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0
15069 * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
15071 * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0
15073 * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1
15074 * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
15075 * . The other SPI core will appear on the LS Slave Select.
15076 * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0
15078 * Loopback function within MIO
15079 * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U)
15081 PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET,
15082 0x0000000FU, 0x00000000U);
15083 /*##################################################################### */
15088 unsigned long psu_peripherals_init_data(void)
15097 * Register : RST_FPD_TOP @ 0XFD1A0100
15099 * PCIE config reset
15100 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0
15102 * PCIE control block level reset
15103 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0
15105 * PCIE bridge block level reset (AXI interface)
15106 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0
15108 * Display Port block level reset (includes DPDMA)
15109 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0
15112 * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0
15114 * GDMA block level reset
15115 * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0
15117 * Pixel Processor (submodule of GPU) block level reset
15118 * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0
15120 * Pixel Processor (submodule of GPU) block level reset
15121 * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0
15123 * GPU block level reset
15124 * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0
15126 * GT block level reset
15127 * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0
15129 * Sata block level reset
15130 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0
15132 * FPD Block level software controlled reset
15133 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U)
15135 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U);
15136 /*##################################################################### */
15145 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15147 * Block level reset
15148 * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
15150 * Block level reset
15151 * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0
15153 * Block level reset
15154 * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0
15156 * Software control register for the IOU block. Each bit will cause a singl
15157 * erperipheral or part of the peripheral to be reset.
15158 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U)
15160 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15161 0x001A0000U, 0x00000000U);
15162 /*##################################################################### */
15165 * Register : RST_LPD_TOP @ 0XFF5E023C
15167 * Reset entire full power domain.
15168 * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0
15171 * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0
15174 * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0
15176 * Real Time Clock reset
15177 * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0
15180 * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0
15183 * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0
15185 * reset entire RPU power island
15186 * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0
15189 * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0
15191 * Software control register for the LPD block.
15192 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U)
15194 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U);
15195 /*##################################################################### */
15201 * Register : RST_LPD_IOU0 @ 0XFF5E0230
15204 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0
15206 * Software controlled reset for the GEMs
15207 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
15209 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
15210 0x00000008U, 0x00000000U);
15211 /*##################################################################### */
15217 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15219 * Block level reset
15220 * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0
15222 * Software control register for the IOU block. Each bit will cause a singl
15223 * erperipheral or part of the peripheral to be reset.
15224 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U)
15226 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15227 0x00000001U, 0x00000000U);
15228 /*##################################################################### */
15234 * Register : IOU_TAPDLY_BYPASS @ 0XFF180390
15236 * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
15237 * ss the Tap delay on the Rx clock signal of LQSPI
15238 * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
15240 * IOU tap delay bypass for the LQSPI and NAND controllers
15241 * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U)
15243 PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET,
15244 0x00000004U, 0x00000004U);
15245 /*##################################################################### */
15254 * Register : RST_LPD_TOP @ 0XFF5E023C
15256 * USB 0 reset for control registers
15257 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0
15259 * USB 0 sleep circuit reset
15260 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0
15263 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0
15265 * Software control register for the LPD block.
15266 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U)
15268 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U);
15269 /*##################################################################### */
15272 * USB0 PIPE POWER PRESENT
15275 * Register : fpd_power_prsnt @ 0XFF9D0080
15277 * This bit is used to choose between PIPE power present and 1'b1
15278 * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
15281 * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U)
15283 PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET,
15284 0x00000001U, 0x00000001U);
15285 /*##################################################################### */
15288 * Register : fpd_pipe_clk @ 0XFF9D007C
15290 * This bit is used to choose between PIPE clock coming from SerDes and the
15292 * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
15295 * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U)
15297 PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U);
15298 /*##################################################################### */
15304 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15306 * Block level reset
15307 * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0
15309 * Software control register for the IOU block. Each bit will cause a singl
15310 * erperipheral or part of the peripheral to be reset.
15311 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U)
15313 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15314 0x00000040U, 0x00000000U);
15315 /*##################################################################### */
15318 * Register : CTRL_REG_SD @ 0XFF180310
15320 * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
15321 * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0
15323 * SD eMMC selection
15324 * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U)
15326 PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET,
15327 0x00008000U, 0x00000000U);
15328 /*##################################################################### */
15331 * Register : SD_CONFIG_REG2 @ 0XFF180320
15333 * Should be set based on the final product usage 00 - Removable SCard Slot
15334 * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
15335 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0
15337 * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
15338 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1
15340 * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
15341 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0
15343 * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
15344 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1
15346 * SD Config Register 2
15347 * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U)
15349 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET,
15350 0x33800000U, 0x02800000U);
15351 /*##################################################################### */
15357 * Register : SD_CONFIG_REG1 @ 0XFF18031C
15359 * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
15360 * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8
15362 * Configures the Number of Taps (Phases) of the rxclk_in that is supported
15364 * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28
15366 * SD Config Register 1
15367 * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U)
15369 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET,
15370 0x7FFE0000U, 0x64500000U);
15371 /*##################################################################### */
15374 * Register : SD_DLL_CTRL @ 0XFF180358
15377 * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1
15379 * SDIO status register
15380 * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U)
15382 PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET,
15383 0x00000008U, 0x00000008U);
15384 /*##################################################################### */
15390 * Register : SD_CONFIG_REG3 @ 0XFF180324
15392 * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S
15393 * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other
15394 * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
15395 * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
15396 * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
15398 * SD Config Register 3
15399 * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U)
15401 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET,
15402 0x03C00000U, 0x00000000U);
15403 /*##################################################################### */
15409 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15411 * Block level reset
15412 * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0
15414 * Software control register for the IOU block. Each bit will cause a singl
15415 * erperipheral or part of the peripheral to be reset.
15416 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U)
15418 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15419 0x00000100U, 0x00000000U);
15420 /*##################################################################### */
15426 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15428 * Block level reset
15429 * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0
15431 * Block level reset
15432 * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0
15434 * Software control register for the IOU block. Each bit will cause a singl
15435 * erperipheral or part of the peripheral to be reset.
15436 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U)
15438 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15439 0x00000600U, 0x00000000U);
15440 /*##################################################################### */
15446 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15448 * Block level reset
15449 * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0
15451 * Software control register for the IOU block. Each bit will cause a singl
15452 * erperipheral or part of the peripheral to be reset.
15453 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U)
15455 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15456 0x00008000U, 0x00000000U);
15457 /*##################################################################### */
15466 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15468 * Block level reset
15469 * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0
15471 * Block level reset
15472 * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0
15474 * Block level reset
15475 * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0
15477 * Block level reset
15478 * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0
15480 * Software control register for the IOU block. Each bit will cause a singl
15481 * erperipheral or part of the peripheral to be reset.
15482 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U)
15484 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15485 0x00007800U, 0x00000000U);
15486 /*##################################################################### */
15492 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15494 * Block level reset
15495 * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0
15497 * Block level reset
15498 * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0
15500 * Software control register for the IOU block. Each bit will cause a singl
15501 * erperipheral or part of the peripheral to be reset.
15502 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U)
15504 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15505 0x00000006U, 0x00000000U);
15506 /*##################################################################### */
15512 * Register : Baud_rate_divider_reg0 @ 0XFF000034
15514 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
15515 * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
15517 * Baud Rate Divider Register
15518 * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U)
15520 PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET,
15521 0x000000FFU, 0x00000005U);
15522 /*##################################################################### */
15525 * Register : Baud_rate_gen_reg0 @ 0XFF000018
15527 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
15528 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
15529 * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f
15531 * Baud Rate Generator Register.
15532 * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU)
15534 PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET,
15535 0x0000FFFFU, 0x0000008FU);
15536 /*##################################################################### */
15539 * Register : Control_reg0 @ 0XFF000000
15541 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
15542 * fter a minimum of one character length and transmit a high level during
15543 * 12 bit periods. It can be set regardless of the value of STTBRK.
15544 * PSU_UART0_CONTROL_REG0_STPBRK 0x0
15546 * Start transmitter break: 0: no affect 1: start to transmit a break after
15547 * the characters currently present in the FIFO and the transmit shift reg
15548 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
15549 * ter break) is not high.
15550 * PSU_UART0_CONTROL_REG0_STTBRK 0x0
15552 * Restart receiver timeout counter: 1: receiver timeout counter is restart
15553 * ed. This bit is self clearing once the restart has completed.
15554 * PSU_UART0_CONTROL_REG0_RSTTO 0x0
15556 * Transmit disable: 0: enable transmitter 1: disable transmitter
15557 * PSU_UART0_CONTROL_REG0_TXDIS 0x0
15559 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
15560 * the TXDIS field is set to 0.
15561 * PSU_UART0_CONTROL_REG0_TXEN 0x1
15563 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
15564 * PSU_UART0_CONTROL_REG0_RXDIS 0x0
15566 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
15567 * is enabled, provided the RXDIS field is set to zero.
15568 * PSU_UART0_CONTROL_REG0_RXEN 0x1
15570 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
15571 * set and all pending transmitter data is discarded This bit is self clear
15572 * ing once the reset has completed.
15573 * PSU_UART0_CONTROL_REG0_TXRES 0x1
15575 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
15576 * and all pending receiver data is discarded. This bit is self clearing o
15577 * nce the reset has completed.
15578 * PSU_UART0_CONTROL_REG0_RXRES 0x1
15580 * UART Control Register
15581 * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U)
15583 PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U);
15584 /*##################################################################### */
15587 * Register : mode_reg0 @ 0XFF000004
15589 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
15590 * automatic echo 10: local loopback 11: remote loopback
15591 * PSU_UART0_MODE_REG0_CHMODE 0x0
15593 * Number of stop bits: Defines the number of stop bits to detect on receiv
15594 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
15595 * op bits 11: reserved
15596 * PSU_UART0_MODE_REG0_NBSTOP 0x0
15598 * Parity type select: Defines the expected parity to check on receive and
15599 * the parity to generate on transmit. 000: even parity 001: odd parity 010
15600 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
15602 * PSU_UART0_MODE_REG0_PAR 0x4
15604 * Character length select: Defines the number of bits in each character. 1
15605 * 1: 6 bits 10: 7 bits 0x: 8 bits
15606 * PSU_UART0_MODE_REG0_CHRL 0x0
15608 * Clock source select: This field defines whether a pre-scalar of 8 is app
15609 * lied to the baud rate generator input clock. 0: clock source is uart_ref
15610 * _clk 1: clock source is uart_ref_clk/8
15611 * PSU_UART0_MODE_REG0_CLKS 0x0
15613 * UART Mode Register
15614 * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U)
15616 PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U);
15617 /*##################################################################### */
15620 * Register : Baud_rate_divider_reg0 @ 0XFF010034
15622 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
15623 * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
15625 * Baud Rate Divider Register
15626 * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U)
15628 PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET,
15629 0x000000FFU, 0x00000005U);
15630 /*##################################################################### */
15633 * Register : Baud_rate_gen_reg0 @ 0XFF010018
15635 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
15636 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
15637 * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f
15639 * Baud Rate Generator Register.
15640 * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU)
15642 PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET,
15643 0x0000FFFFU, 0x0000008FU);
15644 /*##################################################################### */
15647 * Register : Control_reg0 @ 0XFF010000
15649 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
15650 * fter a minimum of one character length and transmit a high level during
15651 * 12 bit periods. It can be set regardless of the value of STTBRK.
15652 * PSU_UART1_CONTROL_REG0_STPBRK 0x0
15654 * Start transmitter break: 0: no affect 1: start to transmit a break after
15655 * the characters currently present in the FIFO and the transmit shift reg
15656 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
15657 * ter break) is not high.
15658 * PSU_UART1_CONTROL_REG0_STTBRK 0x0
15660 * Restart receiver timeout counter: 1: receiver timeout counter is restart
15661 * ed. This bit is self clearing once the restart has completed.
15662 * PSU_UART1_CONTROL_REG0_RSTTO 0x0
15664 * Transmit disable: 0: enable transmitter 1: disable transmitter
15665 * PSU_UART1_CONTROL_REG0_TXDIS 0x0
15667 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
15668 * the TXDIS field is set to 0.
15669 * PSU_UART1_CONTROL_REG0_TXEN 0x1
15671 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
15672 * PSU_UART1_CONTROL_REG0_RXDIS 0x0
15674 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
15675 * is enabled, provided the RXDIS field is set to zero.
15676 * PSU_UART1_CONTROL_REG0_RXEN 0x1
15678 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
15679 * set and all pending transmitter data is discarded This bit is self clear
15680 * ing once the reset has completed.
15681 * PSU_UART1_CONTROL_REG0_TXRES 0x1
15683 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
15684 * and all pending receiver data is discarded. This bit is self clearing o
15685 * nce the reset has completed.
15686 * PSU_UART1_CONTROL_REG0_RXRES 0x1
15688 * UART Control Register
15689 * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U)
15691 PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U);
15692 /*##################################################################### */
15695 * Register : mode_reg0 @ 0XFF010004
15697 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
15698 * automatic echo 10: local loopback 11: remote loopback
15699 * PSU_UART1_MODE_REG0_CHMODE 0x0
15701 * Number of stop bits: Defines the number of stop bits to detect on receiv
15702 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
15703 * op bits 11: reserved
15704 * PSU_UART1_MODE_REG0_NBSTOP 0x0
15706 * Parity type select: Defines the expected parity to check on receive and
15707 * the parity to generate on transmit. 000: even parity 001: odd parity 010
15708 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
15710 * PSU_UART1_MODE_REG0_PAR 0x4
15712 * Character length select: Defines the number of bits in each character. 1
15713 * 1: 6 bits 10: 7 bits 0x: 8 bits
15714 * PSU_UART1_MODE_REG0_CHRL 0x0
15716 * Clock source select: This field defines whether a pre-scalar of 8 is app
15717 * lied to the baud rate generator input clock. 0: clock source is uart_ref
15718 * _clk 1: clock source is uart_ref_clk/8
15719 * PSU_UART1_MODE_REG0_CLKS 0x0
15721 * UART Mode Register
15722 * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U)
15724 PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U);
15725 /*##################################################################### */
15731 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15733 * Block level reset
15734 * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0
15736 * Software control register for the IOU block. Each bit will cause a singl
15737 * erperipheral or part of the peripheral to be reset.
15738 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U)
15740 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15741 0x00040000U, 0x00000000U);
15742 /*##################################################################### */
15748 * Register : slcr_adma @ 0XFF4B0024
15750 * TrustZone Classification for ADMA
15751 * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF
15753 * RPU TrustZone settings
15754 * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU)
15756 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET,
15757 0x000000FFU, 0x000000FFU);
15758 /*##################################################################### */
15764 * CSU TAMPER STATUS
15767 * Register : tamper_status @ 0XFFCA5000
15770 * PSU_CSU_TAMPER_STATUS_TAMPER_0 0
15773 * PSU_CSU_TAMPER_STATUS_TAMPER_1 0
15775 * JTAG toggle detect
15776 * PSU_CSU_TAMPER_STATUS_TAMPER_2 0
15779 * PSU_CSU_TAMPER_STATUS_TAMPER_3 0
15781 * AMS over temperature alarm for LPD
15782 * PSU_CSU_TAMPER_STATUS_TAMPER_4 0
15784 * AMS over temperature alarm for APU
15785 * PSU_CSU_TAMPER_STATUS_TAMPER_5 0
15787 * AMS voltage alarm for VCCPINT_FPD
15788 * PSU_CSU_TAMPER_STATUS_TAMPER_6 0
15790 * AMS voltage alarm for VCCPINT_LPD
15791 * PSU_CSU_TAMPER_STATUS_TAMPER_7 0
15793 * AMS voltage alarm for VCCPAUX
15794 * PSU_CSU_TAMPER_STATUS_TAMPER_8 0
15796 * AMS voltage alarm for DDRPHY
15797 * PSU_CSU_TAMPER_STATUS_TAMPER_9 0
15799 * AMS voltage alarm for PSIO bank 0/1/2
15800 * PSU_CSU_TAMPER_STATUS_TAMPER_10 0
15802 * AMS voltage alarm for PSIO bank 3 (dedicated pins)
15803 * PSU_CSU_TAMPER_STATUS_TAMPER_11 0
15805 * AMS voltaage alarm for GT
15806 * PSU_CSU_TAMPER_STATUS_TAMPER_12 0
15808 * Tamper Response Status
15809 * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U)
15811 PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U);
15812 /*##################################################################### */
15815 * CSU TAMPER RESPONSE
15821 * Register : ACE_CTRL @ 0XFD5C0060
15823 * Set ACE outgoing AWQOS value
15824 * PSU_APU_ACE_CTRL_AWQOS 0X0
15826 * Set ACE outgoing ARQOS value
15827 * PSU_APU_ACE_CTRL_ARQOS 0X0
15829 * ACE Control Register
15830 * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U)
15832 PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U);
15833 /*##################################################################### */
15836 * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
15839 * Register : CONTROL @ 0XFFA60040
15841 * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and
15842 * the only module that potentially draws current from the battery will be
15843 * BBRAM. The value read through this bit does not necessarily reflect whe
15844 * ther RTC is enabled or not. It is expected that RTC is enabled every tim
15845 * e it is being configured. If RTC is not used in the design, FSBL will di
15846 * sable it by writing a 0 to this bit.
15847 * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1
15849 * This register controls various functionalities within the RTC
15850 * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U)
15852 PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U);
15853 /*##################################################################### */
15856 * TIMESTAMP COUNTER
15859 * Register : base_frequency_ID_register @ 0XFF260020
15861 * Frequency in number of ticks per second. Valid range from 10 MHz to 100
15863 * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0
15865 * Program this register to match the clock frequency of the timestamp gene
15866 * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0
15867 * 2FAF080. This register is not accessible to the read-only programming in
15869 * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U)
15871 PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET,
15872 0xFFFFFFFFU, 0x05F5B9F0U);
15873 /*##################################################################### */
15876 * Register : counter_control_register @ 0XFF260000
15878 * Enable 0: The counter is disabled and not incrementing. 1: The counter i
15879 * s enabled and is incrementing.
15880 * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
15882 * Controls the counter increments. This register is not accessible to the
15883 * read-only programming interface.
15884 * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U)
15886 PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET,
15887 0x00000001U, 0x00000001U);
15888 /*##################################################################### */
15906 * Register : DIRM_1 @ 0XFF0A0244
15908 * Operation is the same as DIRM_0[DIRECTION_0]
15909 * PSU_GPIO_DIRM_1_DIRECTION_1 0x20
15911 * Direction mode (GPIO Bank1, MIO)
15912 * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U)
15914 PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U);
15915 /*##################################################################### */
15921 * OUTPUT ENABLE BANK 0
15924 * OUTPUT ENABLE BANK 1
15927 * Register : OEN_1 @ 0XFF0A0248
15929 * Operation is the same as OEN_0[OP_ENABLE_0]
15930 * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20
15932 * Output enable (GPIO Bank1, MIO)
15933 * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U)
15935 PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U);
15936 /*##################################################################### */
15939 * OUTPUT ENABLE BANK 2
15942 * MASK_DATA_0_LSW LOW BANK [15:0]
15945 * MASK_DATA_0_MSW LOW BANK [25:16]
15948 * MASK_DATA_1_LSW LOW BANK [41:26]
15951 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
15953 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
15954 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
15956 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
15957 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
15959 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
15960 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U)
15962 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
15963 0xFFFFFFFFU, 0xFFDF0020U);
15964 /*##################################################################### */
15967 * MASK_DATA_1_MSW HIGH BANK [51:42]
15970 * MASK_DATA_1_LSW HIGH BANK [67:52]
15973 * MASK_DATA_1_LSW HIGH BANK [77:68]
15980 /*##################################################################### */
15983 * MASK_DATA_0_LSW LOW BANK [15:0]
15986 * MASK_DATA_0_MSW LOW BANK [25:16]
15989 * MASK_DATA_1_LSW LOW BANK [41:26]
15992 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
15994 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
15995 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
15997 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
15998 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0
16000 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
16001 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U)
16003 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
16004 0xFFFFFFFFU, 0xFFDF0000U);
16005 /*##################################################################### */
16008 * MASK_DATA_1_MSW HIGH BANK [51:42]
16011 * MASK_DATA_1_LSW HIGH BANK [67:52]
16014 * MASK_DATA_1_LSW HIGH BANK [77:68]
16021 /*##################################################################### */
16026 unsigned long psu_post_config_data(void)
16034 unsigned long psu_peripherals_powerdwn_data(void)
16037 * POWER DOWN REQUEST INTERRUPT ENABLE
16040 * POWER DOWN TRIGGER
16045 unsigned long psu_lpd_xppu_data(void)
16051 * APERTURE PERMISIION LIST
16054 * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF
16057 * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF
16060 * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF
16063 * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF
16066 * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF
16069 * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF
16072 * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF
16075 * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF
16078 * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09
16082 * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09
16086 * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF
16089 * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
16092 * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
16095 * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
16098 * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
16101 * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
16104 * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
16107 * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
16110 * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
16113 * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
16116 * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
16119 * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
16122 * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
16125 * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
16128 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16131 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16134 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16137 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16140 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16143 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16146 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16149 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16152 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16155 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16158 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16161 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16164 * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF
16168 * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
16171 * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF
16175 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16179 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16183 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16187 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16191 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16195 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16199 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16203 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16207 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16211 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
16214 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16217 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16220 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
16223 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
16226 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
16229 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
16232 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
16235 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16238 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16241 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16244 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16247 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16250 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16253 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16256 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16259 * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F
16263 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16266 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16269 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16272 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16275 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16278 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16281 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16284 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16287 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16290 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16293 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16297 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16301 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16305 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16309 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16313 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16317 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16321 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16325 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16329 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16333 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16337 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16341 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16345 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16349 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16353 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16357 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16361 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16365 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16369 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16372 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16375 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16378 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16381 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16384 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16387 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16390 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16393 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16396 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16399 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16402 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16405 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16408 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16411 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16414 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16417 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16420 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16423 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16426 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16429 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16432 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16435 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16438 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16441 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16444 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16447 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16450 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16453 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16456 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16459 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16462 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16465 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16468 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16471 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16474 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16477 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16480 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16483 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16486 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16489 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16493 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16497 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16501 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16505 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16509 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16513 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16517 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16521 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16525 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16529 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16533 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16537 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16541 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16545 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16549 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16553 * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
16556 * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F
16560 * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
16563 * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
16566 * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
16569 * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C
16573 * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
16576 * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
16579 * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF
16583 * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
16586 * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
16589 * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F
16593 * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF
16597 * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F
16601 * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
16604 * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
16607 * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F
16611 * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
16614 * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
16617 * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
16620 * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
16623 * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
16626 * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
16629 * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
16632 * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
16635 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16639 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16643 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16647 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16651 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16655 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16659 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16663 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16667 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16671 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16675 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16679 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16683 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16687 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16691 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16695 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16699 * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
16702 * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
16705 * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
16708 * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
16711 * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
16714 * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
16717 * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F
16721 * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F
16725 * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
16728 * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
16731 * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
16734 * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
16737 * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
16740 * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
16743 * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
16746 * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
16749 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16752 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16755 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16758 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16761 * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F
16765 * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F
16769 * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
16772 * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
16775 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16779 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16783 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16787 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16791 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16794 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16797 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16800 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16803 * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
16806 * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS:
16810 * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
16813 * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS:
16817 * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR
16821 * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF
16825 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16829 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16833 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16837 * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF
16841 * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA
16845 * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF
16849 * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR
16853 * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF
16857 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16861 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16865 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16869 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16873 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16877 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16881 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16885 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16889 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16893 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16897 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16901 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16905 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16909 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16913 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16917 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16921 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16925 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16929 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16932 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16935 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16938 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16941 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16944 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16947 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16950 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16953 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16956 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16959 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16962 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16965 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16968 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16971 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16974 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16977 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16980 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16983 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16986 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16989 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16992 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16995 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16998 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17001 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17004 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17007 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17010 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17013 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17016 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17019 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17022 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17025 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17028 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17031 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17034 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17037 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17040 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17043 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17046 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17049 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17052 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17055 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17058 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17061 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17064 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17067 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17070 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17073 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17076 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17079 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17082 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17085 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17088 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17091 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17094 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17097 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17100 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17103 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17106 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17109 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17112 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17115 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17118 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17121 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17124 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17127 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17130 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17133 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17136 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17139 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17142 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17145 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17148 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17151 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17154 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17157 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17160 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17163 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17166 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17169 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17172 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17175 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17178 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17181 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17184 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17187 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17190 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17193 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17196 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17199 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17202 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17205 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17208 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17211 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17214 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17217 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17220 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17223 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17226 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17229 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17232 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17235 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17238 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17241 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17244 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17247 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17250 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17253 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17256 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17259 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17262 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17265 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17268 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17271 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17274 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17277 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17280 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17283 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17286 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17289 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17292 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17295 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17298 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17301 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17304 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17307 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17310 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17313 * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
17316 * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
17319 * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF
17323 * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF
17327 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17331 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17335 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17339 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17343 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17346 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17349 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17352 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17355 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17358 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17361 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17364 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17367 * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS
17376 unsigned long psu_ddr_xmpu0_data(void)
17384 unsigned long psu_ddr_xmpu1_data(void)
17392 unsigned long psu_ddr_xmpu2_data(void)
17400 unsigned long psu_ddr_xmpu3_data(void)
17408 unsigned long psu_ddr_xmpu4_data(void)
17416 unsigned long psu_ddr_xmpu5_data(void)
17424 unsigned long psu_ocm_xmpu_data(void)
17432 unsigned long psu_fpd_xmpu_data(void)
17440 unsigned long psu_protection_lock_data(void)
17443 * LOCKING PROTECTION MODULE
17449 * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
17455 * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17458 * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17461 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17464 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17467 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17470 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17473 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17476 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17481 unsigned long psu_apply_master_tz(void)
17490 * Register : slcr_dpdma @ 0XFD690040
17492 * TrustZone classification for DisplayPort DMA
17493 * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1
17495 * DPDMA TrustZone Settings
17496 * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U)
17498 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET,
17499 0x00000001U, 0x00000001U);
17500 /*##################################################################### */
17509 * Register : slcr_pcie @ 0XFD690030
17511 * TrustZone classification for DMA Channel 0
17512 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1
17514 * TrustZone classification for DMA Channel 1
17515 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1
17517 * TrustZone classification for DMA Channel 2
17518 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1
17520 * TrustZone classification for DMA Channel 3
17521 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1
17523 * TrustZone classification for Ingress Address Translation 0
17524 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1
17526 * TrustZone classification for Ingress Address Translation 1
17527 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1
17529 * TrustZone classification for Ingress Address Translation 2
17530 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1
17532 * TrustZone classification for Ingress Address Translation 3
17533 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1
17535 * TrustZone classification for Ingress Address Translation 4
17536 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1
17538 * TrustZone classification for Ingress Address Translation 5
17539 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1
17541 * TrustZone classification for Ingress Address Translation 6
17542 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1
17544 * TrustZone classification for Ingress Address Translation 7
17545 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1
17547 * TrustZone classification for Egress Address Translation 0
17548 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1
17550 * TrustZone classification for Egress Address Translation 1
17551 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1
17553 * TrustZone classification for Egress Address Translation 2
17554 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1
17556 * TrustZone classification for Egress Address Translation 3
17557 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1
17559 * TrustZone classification for Egress Address Translation 4
17560 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1
17562 * TrustZone classification for Egress Address Translation 5
17563 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1
17565 * TrustZone classification for Egress Address Translation 6
17566 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1
17568 * TrustZone classification for Egress Address Translation 7
17569 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1
17571 * TrustZone classification for DMA Registers
17572 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1
17574 * TrustZone classification for MSIx Table
17575 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1
17577 * TrustZone classification for MSIx PBA
17578 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1
17580 * TrustZone classification for ECAM
17581 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1
17583 * TrustZone classification for Bridge Common Registers
17584 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1
17586 * PCIe TrustZone settings. This register may only be modified during bootu
17587 * p (while PCIe block is disabled)
17588 * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU)
17590 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET,
17591 0x01FFFFFFU, 0x01FFFFFFU);
17592 /*##################################################################### */
17598 * Register : slcr_usb @ 0XFF4B0034
17600 * TrustZone Classification for USB3_0
17601 * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1
17603 * TrustZone Classification for USB3_1
17604 * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1
17606 * USB3 TrustZone settings
17607 * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U)
17609 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET,
17610 0x00000003U, 0x00000003U);
17611 /*##################################################################### */
17617 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17619 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17620 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17621 * ccess [2] = '1'' : Instruction access
17622 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2
17624 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17625 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17626 * ccess [2] = '1'' : Instruction access
17627 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2
17629 * AXI read protection type selection
17630 * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U)
17632 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17633 0x003F0000U, 0x00120000U);
17634 /*##################################################################### */
17637 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17639 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17640 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17641 * ccess [2] = '1'' : Instruction access
17642 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2
17644 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17645 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17646 * ccess [2] = '1'' : Instruction access
17647 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2
17649 * AXI write protection type selection
17650 * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U)
17652 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17653 0x003F0000U, 0x00120000U);
17654 /*##################################################################### */
17660 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17662 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17663 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17664 * ccess [2] = '1'' : Instruction access
17665 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2
17667 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17668 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17669 * ccess [2] = '1'' : Instruction access
17670 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2
17672 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17673 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17674 * ccess [2] = '1'' : Instruction access
17675 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2
17677 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17678 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17679 * ccess [2] = '1'' : Instruction access
17680 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2
17682 * AXI read protection type selection
17683 * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U)
17685 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17686 0x00000FFFU, 0x00000492U);
17687 /*##################################################################### */
17690 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17692 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17693 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17694 * ccess [2] = '1'' : Instruction access
17695 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2
17697 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17698 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17699 * ccess [2] = '1'' : Instruction access
17700 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2
17702 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17703 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17704 * ccess [2] = '1'' : Instruction access
17705 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2
17707 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17708 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17709 * ccess [2] = '1'' : Instruction access
17710 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2
17712 * AXI write protection type selection
17713 * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U)
17715 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17716 0x00000FFFU, 0x00000492U);
17717 /*##################################################################### */
17723 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17725 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17726 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17727 * ccess [2] = '1'' : Instruction access
17728 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2
17730 * AXI write protection type selection
17731 * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U)
17733 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17734 0x0E000000U, 0x04000000U);
17735 /*##################################################################### */
17741 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17743 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17744 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17745 * ccess [2] = '1'' : Instruction access
17746 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2
17748 * AXI read protection type selection
17749 * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U)
17751 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17752 0x01C00000U, 0x00800000U);
17753 /*##################################################################### */
17756 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17758 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17759 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17760 * ccess [2] = '1'' : Instruction access
17761 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2
17763 * AXI write protection type selection
17764 * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U)
17766 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17767 0x01C00000U, 0x00800000U);
17768 /*##################################################################### */
17774 * Register : slcr_adma @ 0XFF4B0024
17776 * TrustZone Classification for ADMA
17777 * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF
17779 * RPU TrustZone settings
17780 * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU)
17782 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET,
17783 0x000000FFU, 0x000000FFU);
17784 /*##################################################################### */
17787 * Register : slcr_gdma @ 0XFD690050
17789 * TrustZone Classification for GDMA
17790 * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF
17792 * GDMA Trustzone Settings
17793 * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU)
17795 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET,
17796 0x000000FFU, 0x000000FFU);
17797 /*##################################################################### */
17802 unsigned long psu_serdes_init_data(void)
17805 * SERDES INITIALIZATION
17808 * GT REFERENCE CLOCK SOURCE SELECTION
17811 * Register : PLL_REF_SEL0 @ 0XFD410000
17813 * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17814 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17815 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17816 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17818 * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
17820 * PLL0 Reference Selection Register
17821 * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU)
17823 PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU);
17824 /*##################################################################### */
17827 * Register : PLL_REF_SEL1 @ 0XFD410004
17829 * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17830 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17831 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17832 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17834 * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9
17836 * PLL1 Reference Selection Register
17837 * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U)
17839 PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U);
17840 /*##################################################################### */
17843 * Register : PLL_REF_SEL2 @ 0XFD410008
17845 * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17846 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17847 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17848 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17850 * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
17852 * PLL2 Reference Selection Register
17853 * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U)
17855 PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U);
17856 /*##################################################################### */
17859 * Register : PLL_REF_SEL3 @ 0XFD41000C
17861 * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17862 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17863 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17864 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17866 * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF
17868 * PLL3 Reference Selection Register
17869 * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU)
17871 PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU);
17872 /*##################################################################### */
17875 * GT REFERENCE CLOCK FREQUENCY SELECTION
17878 * Register : L0_L0_REF_CLK_SEL @ 0XFD402860
17880 * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
17881 * ut. Set to 0 to select lane0 ref clock mux output.
17882 * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1
17884 * Lane0 Ref Clock Selection Register
17885 * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U)
17887 PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET,
17888 0x00000080U, 0x00000080U);
17889 /*##################################################################### */
17892 * Register : L0_L1_REF_CLK_SEL @ 0XFD402864
17894 * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
17895 * ut. Set to 0 to select lane1 ref clock mux output.
17896 * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
17898 * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
17899 * cer output from ref clock network
17900 * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
17902 * Lane1 Ref Clock Selection Register
17903 * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U)
17905 PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET,
17906 0x00000088U, 0x00000008U);
17907 /*##################################################################### */
17910 * Register : L0_L2_REF_CLK_SEL @ 0XFD402868
17912 * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
17913 * ut. Set to 0 to select lane2 ref clock mux output.
17914 * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
17916 * Lane2 Ref Clock Selection Register
17917 * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U)
17919 PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET,
17920 0x00000080U, 0x00000080U);
17921 /*##################################################################### */
17924 * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C
17926 * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
17927 * ut. Set to 0 to select lane3 ref clock mux output.
17928 * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
17930 * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
17931 * cer output from ref clock network
17932 * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
17934 * Lane3 Ref Clock Selection Register
17935 * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U)
17937 PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET,
17938 0x00000082U, 0x00000002U);
17939 /*##################################################################### */
17942 * ENABLE SPREAD SPECTRUM
17945 * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094
17947 * Enable/Disable coarse code satureation limiting logic
17948 * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
17950 * Test mode register 37
17951 * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U)
17953 PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET,
17954 0x00000010U, 0x00000010U);
17955 /*##################################################################### */
17958 * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368
17960 * Spread Spectrum No of Steps [7:0]
17961 * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
17963 * Spread Spectrum No of Steps bits 7:0
17964 * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U)
17966 PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET,
17967 0x000000FFU, 0x00000038U);
17968 /*##################################################################### */
17971 * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C
17973 * Spread Spectrum No of Steps [10:8]
17974 * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
17976 * Spread Spectrum No of Steps bits 10:8
17977 * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U)
17979 PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET,
17980 0x00000007U, 0x00000003U);
17981 /*##################################################################### */
17984 * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368
17986 * Spread Spectrum No of Steps [7:0]
17987 * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
17989 * Spread Spectrum No of Steps bits 7:0
17990 * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U)
17992 PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET,
17993 0x000000FFU, 0x000000E0U);
17994 /*##################################################################### */
17997 * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C
17999 * Spread Spectrum No of Steps [10:8]
18000 * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
18002 * Spread Spectrum No of Steps bits 10:8
18003 * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
18005 PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET,
18006 0x00000007U, 0x00000003U);
18007 /*##################################################################### */
18010 * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368
18012 * Spread Spectrum No of Steps [7:0]
18013 * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
18015 * Spread Spectrum No of Steps bits 7:0
18016 * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
18018 PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET,
18019 0x000000FFU, 0x00000058U);
18020 /*##################################################################### */
18023 * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C
18025 * Spread Spectrum No of Steps [10:8]
18026 * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
18028 * Spread Spectrum No of Steps bits 10:8
18029 * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
18031 PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET,
18032 0x00000007U, 0x00000003U);
18033 /*##################################################################### */
18036 * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370
18038 * Step Size for Spread Spectrum [7:0]
18039 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
18041 * Step Size for Spread Spectrum LSB
18042 * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
18044 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18045 0x000000FFU, 0x0000007CU);
18046 /*##################################################################### */
18049 * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374
18051 * Step Size for Spread Spectrum [15:8]
18052 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
18054 * Step Size for Spread Spectrum 1
18055 * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
18057 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET,
18058 0x000000FFU, 0x00000033U);
18059 /*##################################################################### */
18062 * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378
18064 * Step Size for Spread Spectrum [23:16]
18065 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
18067 * Step Size for Spread Spectrum 2
18068 * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
18070 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET,
18071 0x000000FFU, 0x00000002U);
18072 /*##################################################################### */
18075 * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C
18077 * Step Size for Spread Spectrum [25:24]
18078 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18080 * Enable/Disable test mode force on SS step size
18081 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18083 * Enable/Disable test mode force on SS no of steps
18084 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18086 * Enable force on enable Spread Spectrum
18087 * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U)
18089 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18090 0x00000033U, 0x00000030U);
18091 /*##################################################################### */
18094 * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370
18096 * Step Size for Spread Spectrum [7:0]
18097 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
18099 * Step Size for Spread Spectrum LSB
18100 * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U)
18102 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18103 0x000000FFU, 0x000000F4U);
18104 /*##################################################################### */
18107 * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374
18109 * Step Size for Spread Spectrum [15:8]
18110 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
18112 * Step Size for Spread Spectrum 1
18113 * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U)
18115 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET,
18116 0x000000FFU, 0x00000031U);
18117 /*##################################################################### */
18120 * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378
18122 * Step Size for Spread Spectrum [23:16]
18123 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
18125 * Step Size for Spread Spectrum 2
18126 * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U)
18128 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET,
18129 0x000000FFU, 0x00000002U);
18130 /*##################################################################### */
18133 * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C
18135 * Step Size for Spread Spectrum [25:24]
18136 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18138 * Enable/Disable test mode force on SS step size
18139 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18141 * Enable/Disable test mode force on SS no of steps
18142 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18144 * Enable force on enable Spread Spectrum
18145 * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U)
18147 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18148 0x00000033U, 0x00000030U);
18149 /*##################################################################### */
18152 * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370
18154 * Step Size for Spread Spectrum [7:0]
18155 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
18157 * Step Size for Spread Spectrum LSB
18158 * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U)
18160 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18161 0x000000FFU, 0x000000C9U);
18162 /*##################################################################### */
18165 * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374
18167 * Step Size for Spread Spectrum [15:8]
18168 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
18170 * Step Size for Spread Spectrum 1
18171 * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U)
18173 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET,
18174 0x000000FFU, 0x000000D2U);
18175 /*##################################################################### */
18178 * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378
18180 * Step Size for Spread Spectrum [23:16]
18181 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
18183 * Step Size for Spread Spectrum 2
18184 * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U)
18186 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET,
18187 0x000000FFU, 0x00000001U);
18188 /*##################################################################### */
18191 * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C
18193 * Step Size for Spread Spectrum [25:24]
18194 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18196 * Enable/Disable test mode force on SS step size
18197 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18199 * Enable/Disable test mode force on SS no of steps
18200 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18202 * Enable test mode forcing on enable Spread Spectrum
18203 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
18205 * Enable force on enable Spread Spectrum
18206 * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U)
18208 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18209 0x000000B3U, 0x000000B0U);
18210 /*##################################################################### */
18213 * Register : L2_TM_DIG_6 @ 0XFD40906C
18215 * Bypass Descrambler
18216 * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
18218 * Enable Bypass for <1> TM_DIG_CTRL_6
18219 * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
18221 * Data path test modes in decoder and descram
18222 * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U)
18224 PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U);
18225 /*##################################################################### */
18228 * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4
18230 * Bypass scrambler signal
18231 * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
18233 * Enable/disable scrambler bypass signal
18234 * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
18236 * MPHY PLL Gear and bypass scrambler
18237 * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U)
18239 PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET,
18240 0x00000003U, 0x00000003U);
18241 /*##################################################################### */
18244 * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360
18246 * Enable test mode force on fractional mode enable
18247 * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
18249 * Fractional feedback division control and fractional value for feedback d
18250 * ivision bits 26:24
18251 * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U)
18253 PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET,
18254 0x00000040U, 0x00000040U);
18255 /*##################################################################### */
18258 * Register : L3_TM_DIG_6 @ 0XFD40D06C
18260 * Bypass 8b10b decoder
18261 * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
18263 * Enable Bypass for <3> TM_DIG_CTRL_6
18264 * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
18266 * Bypass Descrambler
18267 * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
18269 * Enable Bypass for <1> TM_DIG_CTRL_6
18270 * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
18272 * Data path test modes in decoder and descram
18273 * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU)
18275 PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU);
18276 /*##################################################################### */
18279 * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4
18281 * Enable/disable encoder bypass signal
18282 * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
18284 * Bypass scrambler signal
18285 * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
18287 * Enable/disable scrambler bypass signal
18288 * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
18290 * MPHY PLL Gear and bypass scrambler
18291 * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
18293 PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET,
18294 0x0000000BU, 0x0000000BU);
18295 /*##################################################################### */
18298 * ENABLE CHICKEN BIT FOR PCIE AND USB
18301 * Register : L0_TM_AUX_0 @ 0XFD4010CC
18304 * PSU_SERDES_L0_TM_AUX_0_BIT_2 1
18307 * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U)
18309 PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U);
18310 /*##################################################################### */
18313 * Register : L2_TM_AUX_0 @ 0XFD4090CC
18316 * PSU_SERDES_L2_TM_AUX_0_BIT_2 1
18319 * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
18321 PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U);
18322 /*##################################################################### */
18325 * ENABLING EYE SURF
18328 * Register : L0_TM_DIG_8 @ 0XFD401074
18331 * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
18333 * Test modes for Elastic buffer and enabling Eye Surf
18334 * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
18336 PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18337 /*##################################################################### */
18340 * Register : L1_TM_DIG_8 @ 0XFD405074
18343 * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
18345 * Test modes for Elastic buffer and enabling Eye Surf
18346 * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
18348 PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18349 /*##################################################################### */
18352 * Register : L2_TM_DIG_8 @ 0XFD409074
18355 * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
18357 * Test modes for Elastic buffer and enabling Eye Surf
18358 * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
18360 PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18361 /*##################################################################### */
18364 * Register : L3_TM_DIG_8 @ 0XFD40D074
18367 * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
18369 * Test modes for Elastic buffer and enabling Eye Surf
18370 * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
18372 PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18373 /*##################################################################### */
18376 * ILL SETTINGS FOR GAIN AND LOCK SETTINGS
18379 * Register : L0_TM_MISC2 @ 0XFD40189C
18381 * ILL calib counts BYPASSED with calcode bits
18382 * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18385 * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U)
18387 PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18388 /*##################################################################### */
18391 * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8
18393 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18395 * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
18398 * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U)
18400 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET,
18401 0x000000FFU, 0x00000064U);
18402 /*##################################################################### */
18405 * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC
18407 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18408 * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
18411 * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U)
18413 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET,
18414 0x000000FFU, 0x00000064U);
18415 /*##################################################################### */
18418 * Register : L0_TM_ILL12 @ 0XFD401990
18420 * G1A pll ctr bypass value
18421 * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
18423 * ill pll counter values
18424 * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U)
18426 PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U);
18427 /*##################################################################### */
18430 * Register : L0_TM_E_ILL1 @ 0XFD401924
18432 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18434 * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
18437 * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U)
18439 PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U);
18440 /*##################################################################### */
18443 * Register : L0_TM_E_ILL2 @ 0XFD401928
18445 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18446 * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
18449 * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU)
18451 PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU);
18452 /*##################################################################### */
18455 * Register : L0_TM_IQ_ILL3 @ 0XFD401900
18457 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18458 * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
18461 * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U)
18463 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET,
18464 0x000000FFU, 0x00000064U);
18465 /*##################################################################### */
18468 * Register : L0_TM_E_ILL3 @ 0XFD40192C
18470 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18471 * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
18474 * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U)
18476 PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U);
18477 /*##################################################################### */
18480 * Register : L0_TM_ILL8 @ 0XFD401980
18482 * ILL calibration code change wait time
18483 * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18485 * ILL cal routine control
18486 * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU)
18488 PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18489 /*##################################################################### */
18492 * Register : L0_TM_IQ_ILL8 @ 0XFD401914
18494 * IQ ILL polytrim bypass value
18495 * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18498 * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U)
18500 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET,
18501 0x000000FFU, 0x000000F7U);
18502 /*##################################################################### */
18505 * Register : L0_TM_IQ_ILL9 @ 0XFD401918
18507 * bypass IQ polytrim
18508 * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18510 * enables for lf,constant gm trim and polytirm
18511 * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U)
18513 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET,
18514 0x00000001U, 0x00000001U);
18515 /*##################################################################### */
18518 * Register : L0_TM_E_ILL8 @ 0XFD401940
18520 * E ILL polytrim bypass value
18521 * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18524 * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U)
18526 PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18527 /*##################################################################### */
18530 * Register : L0_TM_E_ILL9 @ 0XFD401944
18532 * bypass E polytrim
18533 * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18535 * enables for lf,constant gm trim and polytirm
18536 * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U)
18538 PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18539 /*##################################################################### */
18542 * Register : L0_TM_ILL13 @ 0XFD401994
18544 * ILL cal idle val refcnt
18545 * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18547 * ill cal idle value count
18548 * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U)
18550 PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18551 /*##################################################################### */
18554 * Register : L1_TM_ILL13 @ 0XFD405994
18556 * ILL cal idle val refcnt
18557 * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18559 * ill cal idle value count
18560 * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U)
18562 PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18563 /*##################################################################### */
18566 * Register : L2_TM_MISC2 @ 0XFD40989C
18568 * ILL calib counts BYPASSED with calcode bits
18569 * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18572 * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
18574 PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18575 /*##################################################################### */
18578 * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8
18580 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18582 * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
18585 * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
18587 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET,
18588 0x000000FFU, 0x0000001AU);
18589 /*##################################################################### */
18592 * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC
18594 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18595 * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
18598 * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
18600 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET,
18601 0x000000FFU, 0x0000001AU);
18602 /*##################################################################### */
18605 * Register : L2_TM_ILL12 @ 0XFD409990
18607 * G1A pll ctr bypass value
18608 * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
18610 * ill pll counter values
18611 * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
18613 PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U);
18614 /*##################################################################### */
18617 * Register : L2_TM_E_ILL1 @ 0XFD409924
18619 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18621 * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
18624 * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
18626 PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU);
18627 /*##################################################################### */
18630 * Register : L2_TM_E_ILL2 @ 0XFD409928
18632 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18633 * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
18636 * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
18638 PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U);
18639 /*##################################################################### */
18642 * Register : L2_TM_IQ_ILL3 @ 0XFD409900
18644 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18645 * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
18648 * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
18650 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET,
18651 0x000000FFU, 0x0000001AU);
18652 /*##################################################################### */
18655 * Register : L2_TM_E_ILL3 @ 0XFD40992C
18657 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18658 * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
18661 * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
18663 PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U);
18664 /*##################################################################### */
18667 * Register : L2_TM_ILL8 @ 0XFD409980
18669 * ILL calibration code change wait time
18670 * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18672 * ILL cal routine control
18673 * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
18675 PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18676 /*##################################################################### */
18679 * Register : L2_TM_IQ_ILL8 @ 0XFD409914
18681 * IQ ILL polytrim bypass value
18682 * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18685 * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
18687 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET,
18688 0x000000FFU, 0x000000F7U);
18689 /*##################################################################### */
18692 * Register : L2_TM_IQ_ILL9 @ 0XFD409918
18694 * bypass IQ polytrim
18695 * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18697 * enables for lf,constant gm trim and polytirm
18698 * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
18700 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET,
18701 0x00000001U, 0x00000001U);
18702 /*##################################################################### */
18705 * Register : L2_TM_E_ILL8 @ 0XFD409940
18707 * E ILL polytrim bypass value
18708 * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18711 * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
18713 PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18714 /*##################################################################### */
18717 * Register : L2_TM_E_ILL9 @ 0XFD409944
18719 * bypass E polytrim
18720 * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18722 * enables for lf,constant gm trim and polytirm
18723 * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
18725 PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18726 /*##################################################################### */
18729 * Register : L2_TM_ILL13 @ 0XFD409994
18731 * ILL cal idle val refcnt
18732 * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18734 * ill cal idle value count
18735 * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U)
18737 PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18738 /*##################################################################### */
18741 * Register : L3_TM_MISC2 @ 0XFD40D89C
18743 * ILL calib counts BYPASSED with calcode bits
18744 * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18747 * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
18749 PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18750 /*##################################################################### */
18753 * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8
18755 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18757 * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
18760 * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
18762 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET,
18763 0x000000FFU, 0x0000007DU);
18764 /*##################################################################### */
18767 * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC
18769 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18770 * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
18773 * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
18775 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET,
18776 0x000000FFU, 0x0000007DU);
18777 /*##################################################################### */
18780 * Register : L3_TM_ILL12 @ 0XFD40D990
18782 * G1A pll ctr bypass value
18783 * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
18785 * ill pll counter values
18786 * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
18788 PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U);
18789 /*##################################################################### */
18792 * Register : L3_TM_E_ILL1 @ 0XFD40D924
18794 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18796 * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
18799 * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
18801 PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU);
18802 /*##################################################################### */
18805 * Register : L3_TM_E_ILL2 @ 0XFD40D928
18807 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18808 * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
18811 * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
18813 PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U);
18814 /*##################################################################### */
18817 * Register : L3_TM_ILL11 @ 0XFD40D98C
18819 * G2A_PCIe1 PLL ctr bypass value
18820 * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
18822 * ill pll counter values
18823 * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
18825 PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U);
18826 /*##################################################################### */
18829 * Register : L3_TM_IQ_ILL3 @ 0XFD40D900
18831 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18832 * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
18835 * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU)
18837 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET,
18838 0x000000FFU, 0x0000007DU);
18839 /*##################################################################### */
18842 * Register : L3_TM_E_ILL3 @ 0XFD40D92C
18844 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18845 * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
18848 * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
18850 PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U);
18851 /*##################################################################### */
18854 * Register : L3_TM_ILL8 @ 0XFD40D980
18856 * ILL calibration code change wait time
18857 * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18859 * ILL cal routine control
18860 * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
18862 PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18863 /*##################################################################### */
18866 * Register : L3_TM_IQ_ILL8 @ 0XFD40D914
18868 * IQ ILL polytrim bypass value
18869 * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18872 * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
18874 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET,
18875 0x000000FFU, 0x000000F7U);
18876 /*##################################################################### */
18879 * Register : L3_TM_IQ_ILL9 @ 0XFD40D918
18881 * bypass IQ polytrim
18882 * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18884 * enables for lf,constant gm trim and polytirm
18885 * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
18887 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET,
18888 0x00000001U, 0x00000001U);
18889 /*##################################################################### */
18892 * Register : L3_TM_E_ILL8 @ 0XFD40D940
18894 * E ILL polytrim bypass value
18895 * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18898 * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
18900 PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18901 /*##################################################################### */
18904 * Register : L3_TM_E_ILL9 @ 0XFD40D944
18906 * bypass E polytrim
18907 * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18909 * enables for lf,constant gm trim and polytirm
18910 * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
18912 PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18913 /*##################################################################### */
18916 * Register : L3_TM_ILL13 @ 0XFD40D994
18918 * ILL cal idle val refcnt
18919 * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18921 * ill cal idle value count
18922 * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U)
18924 PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18925 /*##################################################################### */
18928 * SYMBOL LOCK AND WAIT
18931 * Register : L0_TM_DIG_10 @ 0XFD40107C
18933 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18934 * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18936 * test control for changing cdr lock wait time
18937 * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U)
18939 PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18940 /*##################################################################### */
18943 * Register : L1_TM_DIG_10 @ 0XFD40507C
18945 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18946 * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18948 * test control for changing cdr lock wait time
18949 * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U)
18951 PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18952 /*##################################################################### */
18955 * Register : L2_TM_DIG_10 @ 0XFD40907C
18957 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18958 * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18960 * test control for changing cdr lock wait time
18961 * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U)
18963 PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18964 /*##################################################################### */
18967 * Register : L3_TM_DIG_10 @ 0XFD40D07C
18969 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18970 * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18972 * test control for changing cdr lock wait time
18973 * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U)
18975 PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18976 /*##################################################################### */
18979 * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
18982 * Register : L0_TM_RST_DLY @ 0XFD4019A4
18984 * Delay apb reset by specified amount
18985 * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
18987 * reset delay for apb reset w.r.t pso of hsrx
18988 * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
18990 PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET,
18991 0x000000FFU, 0x000000FFU);
18992 /*##################################################################### */
18995 * Register : L0_TM_ANA_BYP_15 @ 0XFD401038
18997 * Enable Bypass for <7> of TM_ANA_BYPS_15
18998 * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19000 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19001 * d ps for samp c2c
19002 * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
19004 PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET,
19005 0x00000040U, 0x00000040U);
19006 /*##################################################################### */
19009 * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C
19011 * Enable Bypass for <7> of TM_ANA_BYPS_12
19012 * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19014 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19016 * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U)
19018 PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET,
19019 0x00000040U, 0x00000040U);
19020 /*##################################################################### */
19023 * Register : L1_TM_RST_DLY @ 0XFD4059A4
19025 * Delay apb reset by specified amount
19026 * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
19028 * reset delay for apb reset w.r.t pso of hsrx
19029 * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
19031 PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET,
19032 0x000000FFU, 0x000000FFU);
19033 /*##################################################################### */
19036 * Register : L1_TM_ANA_BYP_15 @ 0XFD405038
19038 * Enable Bypass for <7> of TM_ANA_BYPS_15
19039 * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19041 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19042 * d ps for samp c2c
19043 * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
19045 PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET,
19046 0x00000040U, 0x00000040U);
19047 /*##################################################################### */
19050 * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C
19052 * Enable Bypass for <7> of TM_ANA_BYPS_12
19053 * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19055 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19057 * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U)
19059 PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET,
19060 0x00000040U, 0x00000040U);
19061 /*##################################################################### */
19064 * Register : L2_TM_RST_DLY @ 0XFD4099A4
19066 * Delay apb reset by specified amount
19067 * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
19069 * reset delay for apb reset w.r.t pso of hsrx
19070 * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
19072 PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET,
19073 0x000000FFU, 0x000000FFU);
19074 /*##################################################################### */
19077 * Register : L2_TM_ANA_BYP_15 @ 0XFD409038
19079 * Enable Bypass for <7> of TM_ANA_BYPS_15
19080 * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19082 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19083 * d ps for samp c2c
19084 * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
19086 PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET,
19087 0x00000040U, 0x00000040U);
19088 /*##################################################################### */
19091 * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C
19093 * Enable Bypass for <7> of TM_ANA_BYPS_12
19094 * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19096 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19098 * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U)
19100 PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET,
19101 0x00000040U, 0x00000040U);
19102 /*##################################################################### */
19105 * Register : L3_TM_RST_DLY @ 0XFD40D9A4
19107 * Delay apb reset by specified amount
19108 * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
19110 * reset delay for apb reset w.r.t pso of hsrx
19111 * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
19113 PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET,
19114 0x000000FFU, 0x000000FFU);
19115 /*##################################################################### */
19118 * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038
19120 * Enable Bypass for <7> of TM_ANA_BYPS_15
19121 * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19123 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19124 * d ps for samp c2c
19125 * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
19127 PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET,
19128 0x00000040U, 0x00000040U);
19129 /*##################################################################### */
19132 * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C
19134 * Enable Bypass for <7> of TM_ANA_BYPS_12
19135 * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19137 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19139 * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U)
19141 PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET,
19142 0x00000040U, 0x00000040U);
19143 /*##################################################################### */
19149 * Register : L0_TM_MISC3 @ 0XFD4019AC
19151 * CDR fast phase lock control
19152 * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0
19154 * CDR fast frequency lock control
19155 * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0
19157 * debug bus selection bit, cdr fast phase and freq controls
19158 * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U)
19160 PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19161 /*##################################################################### */
19164 * Register : L1_TM_MISC3 @ 0XFD4059AC
19166 * CDR fast phase lock control
19167 * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0
19169 * CDR fast frequency lock control
19170 * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0
19172 * debug bus selection bit, cdr fast phase and freq controls
19173 * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U)
19175 PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19176 /*##################################################################### */
19179 * Register : L2_TM_MISC3 @ 0XFD4099AC
19181 * CDR fast phase lock control
19182 * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0
19184 * CDR fast frequency lock control
19185 * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0
19187 * debug bus selection bit, cdr fast phase and freq controls
19188 * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U)
19190 PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19191 /*##################################################################### */
19194 * Register : L3_TM_MISC3 @ 0XFD40D9AC
19196 * CDR fast phase lock control
19197 * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0
19199 * CDR fast frequency lock control
19200 * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0
19202 * debug bus selection bit, cdr fast phase and freq controls
19203 * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U)
19205 PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19206 /*##################################################################### */
19209 * DISABLE DYNAMIC OFFSET CALIBRATION
19212 * Register : L0_TM_EQ11 @ 0XFD401978
19214 * Force EQ offset correction algo off if not forced on
19215 * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19217 * eq dynamic offset correction
19218 * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U)
19220 PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19221 /*##################################################################### */
19224 * Register : L1_TM_EQ11 @ 0XFD405978
19226 * Force EQ offset correction algo off if not forced on
19227 * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19229 * eq dynamic offset correction
19230 * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U)
19232 PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19233 /*##################################################################### */
19236 * Register : L2_TM_EQ11 @ 0XFD409978
19238 * Force EQ offset correction algo off if not forced on
19239 * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19241 * eq dynamic offset correction
19242 * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U)
19244 PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19245 /*##################################################################### */
19248 * Register : L3_TM_EQ11 @ 0XFD40D978
19250 * Force EQ offset correction algo off if not forced on
19251 * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19253 * eq dynamic offset correction
19254 * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U)
19256 PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19257 /*##################################################################### */
19260 * DISABLE ECO FOR PCIE
19263 * Register : eco_0 @ 0XFD3D001C
19266 * PSU_SIOU_ECO_0_FIELD 0x1
19268 * ECO Register for future use
19269 * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U)
19271 PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U);
19272 /*##################################################################### */
19278 * Register : ICM_CFG0 @ 0XFD410010
19280 * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
19281 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
19282 * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
19284 * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
19285 * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
19286 * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
19288 * ICM Configuration Register 0
19289 * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U)
19291 PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U);
19292 /*##################################################################### */
19295 * Register : ICM_CFG1 @ 0XFD410014
19297 * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
19298 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
19299 * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
19301 * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
19302 * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
19303 * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
19305 * ICM Configuration Register 1
19306 * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U)
19308 PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U);
19309 /*##################################################################### */
19312 * CHECKING PLL LOCK
19315 * ENABLE SERIAL DATA MUX DEEMPH
19318 * Register : L1_TXPMD_TM_45 @ 0XFD404CB4
19320 * Enable/disable DP post2 path
19321 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
19323 * Override enable/disable of DP post2 path
19324 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
19326 * Override enable/disable of DP post1 path
19327 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
19329 * Enable/disable DP main path
19330 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
19332 * Override enable/disable of DP main path
19333 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
19335 * Post or pre or main DP path selection
19336 * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
19338 PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET,
19339 0x00000037U, 0x00000037U);
19340 /*##################################################################### */
19343 * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
19345 * Test register force for enabling/disablign TX deemphasis bits <17:0>
19346 * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
19348 * Enable Override of TX deemphasis
19349 * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
19351 PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET,
19352 0x00000001U, 0x00000001U);
19353 /*##################################################################### */
19356 * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8
19358 * Test register force for enabling/disablign TX deemphasis bits <17:0>
19359 * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
19361 * Enable Override of TX deemphasis
19362 * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
19364 PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET,
19365 0x00000001U, 0x00000001U);
19366 /*##################################################################### */
19369 * CDR AND RX EQUALIZATION SETTINGS
19372 * Register : L3_TM_CDR5 @ 0XFD40DC14
19374 * FPHL FSM accumulate cycles
19375 * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
19377 * FFL Phase0 int gain aka 2ol SD update rate
19378 * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
19380 * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in
19382 * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
19384 PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U);
19385 /*##################################################################### */
19388 * Register : L3_TM_CDR16 @ 0XFD40DC40
19390 * FFL Phase0 prop gain aka 1ol SD update rate
19391 * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
19393 * Fast phase lock controls -- phase 0 prop gain
19394 * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
19396 PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU);
19397 /*##################################################################### */
19400 * Register : L3_TM_EQ0 @ 0XFD40D94C
19402 * EQ stg 2 controls BYPASSED
19403 * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
19405 * eq stg1 and stg2 controls
19406 * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
19408 PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U);
19409 /*##################################################################### */
19412 * Register : L3_TM_EQ1 @ 0XFD40D950
19415 * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
19417 * EQ stg 2 preamp mode val
19418 * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
19420 * eq stg1 and stg2 controls
19421 * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
19423 PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U);
19424 /*##################################################################### */
19427 * GEM SERDES SETTINGS
19430 * ENABLE PRE EMPHAIS AND VOLTAGE SWING
19433 * Register : L1_TXPMD_TM_48 @ 0XFD404CC0
19435 * Margining factor value
19436 * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
19439 * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U)
19441 PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET,
19442 0x0000001FU, 0x00000000U);
19443 /*##################################################################### */
19446 * Register : L1_TX_ANA_TM_18 @ 0XFD404048
19448 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
19449 * phasis, Others: reserved
19450 * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
19452 * Override for PIPE TX de-emphasis
19453 * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U)
19455 PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET,
19456 0x000000FFU, 0x00000000U);
19457 /*##################################################################### */
19460 * Register : L3_TX_ANA_TM_18 @ 0XFD40C048
19462 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
19463 * phasis, Others: reserved
19464 * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
19466 * Override for PIPE TX de-emphasis
19467 * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
19469 PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET,
19470 0x000000FFU, 0x00000001U);
19471 /*##################################################################### */
19476 unsigned long psu_resetout_init_data(void)
19479 * TAKING SERDES PERIPHERAL OUT OF RESET RESET
19482 * PUTTING USB0 IN RESET
19485 * Register : RST_LPD_TOP @ 0XFF5E023C
19487 * USB 0 reset for control registers
19488 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
19490 * Software control register for the LPD block.
19491 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U)
19493 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U);
19494 /*##################################################################### */
19500 * Register : RST_LPD_TOP @ 0XFF5E023C
19502 * USB 0 sleep circuit reset
19503 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
19506 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
19508 * Software control register for the LPD block.
19509 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U)
19511 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U);
19512 /*##################################################################### */
19515 * PUTTING GEM0 IN RESET
19518 * Register : RST_LPD_IOU0 @ 0XFF5E0230
19521 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
19523 * Software controlled reset for the GEMs
19524 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
19526 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
19527 0x00000008U, 0x00000000U);
19528 /*##################################################################### */
19531 * PUTTING SATA IN RESET
19534 * Register : sata_misc_ctrl @ 0XFD3D0100
19536 * Sata PM clock control select
19537 * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
19539 * Misc Contorls for SATA.This register may only be modified during bootup
19540 * (while SATA block is disabled)
19541 * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U)
19543 PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U);
19544 /*##################################################################### */
19547 * Register : RST_FPD_TOP @ 0XFD1A0100
19549 * Sata block level reset
19550 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
19552 * FPD Block level software controlled reset
19553 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U)
19555 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U);
19556 /*##################################################################### */
19559 * PUTTING PCIE CFG AND BRIDGE IN RESET
19562 * Register : RST_FPD_TOP @ 0XFD1A0100
19564 * PCIE config reset
19565 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
19567 * PCIE bridge block level reset (AXI interface)
19568 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
19570 * FPD Block level software controlled reset
19571 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U)
19573 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U);
19574 /*##################################################################### */
19577 * PUTTING DP IN RESET
19580 * Register : RST_FPD_TOP @ 0XFD1A0100
19582 * Display Port block level reset (includes DPDMA)
19583 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
19585 * FPD Block level software controlled reset
19586 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U)
19588 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U);
19589 /*##################################################################### */
19592 * Register : DP_PHY_RESET @ 0XFD4A0200
19594 * Set to '1' to hold the GT in reset. Clear to release.
19595 * PSU_DP_DP_PHY_RESET_GT_RESET 0X0
19597 * Reset the transmitter PHY.
19598 * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U)
19600 PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U);
19601 /*##################################################################### */
19604 * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238
19606 * Two bits per lane. When set to 11, moves the GT to power down mode. When
19607 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
19609 * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
19611 * Control PHY Power down
19612 * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U)
19614 PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET,
19615 0x0000000FU, 0x00000000U);
19616 /*##################################################################### */
19622 * Register : GUSB2PHYCFG @ 0XFE20C200
19624 * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc
19625 * ks. Specifies the response time for a MAC request to the Packet FIFO Con
19626 * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th
19627 * e required values for the minimum SoC bus frequency of 60 MHz. USB turna
19628 * round time is a critical certification criteria when using long cables a
19629 * nd five hub levels. The required values for this field: - 4'h5: When the
19630 * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
19631 * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim
19632 * e is not critical, this field can be set to a larger value. Note: This f
19633 * ield is valid only in device mode.
19634 * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
19636 * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP
19637 * I Transceiver Select signal (for HS) and the assertion of the TxValid si
19638 * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima
19639 * tely 2.5 us) is introduced from the time when the Transceiver Select is
19640 * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the
19641 * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you
19642 * enable the hibernation feature when the device core comes out of power-
19643 * off, you must re-initialize this bit with the appropriate value because
19644 * the core does not save and restore this bit value during hibernation. -
19645 * This bit is valid only in device mode.
19646 * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
19648 * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use
19649 * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th
19650 * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert
19651 * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s
19652 * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t
19653 * he external PHY. Note: This bit must be set high for Port0 if PHY is use
19654 * d. Note: In Device mode - Before issuing any device endpoint command whe
19655 * n operating in 2.0 speeds, disable this bit and enable it after the comm
19656 * and completes. Without disabling this bit, if a command is issued when t
19657 * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
19658 * f, the command will not get completed.
19659 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
19661 * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T
19662 * he application uses this bit to select a high-speed PHY or a full-speed
19663 * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a
19664 * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans
19665 * ceiver. This bit is always 1, with Write Only access. If both interface
19666 * types are selected in coreConsultant (that is, parameters' values are no
19667 * t zero), the application uses this bit to select the active interface is
19668 * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
19669 * er is not supported. This bit always reads as 1'b0.
19670 * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
19672 * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend
19673 * mode if Suspend conditions are valid. For DRD/OTG configurations, it is
19674 * recommended that this bit is set to 0 during coreConsultant configurati
19675 * on. If it is set to 1, then the application must clear this bit after po
19676 * wer-on reset. Application needs to set it to 1 after the core initializa
19677 * tion completes. For all other configurations, this bit can be set to 1 d
19678 * uring core configuration. Note: - In host mode, on reset, this bit is se
19679 * t to 1. Software can override this bit after reset. - In device mode, be
19680 * fore issuing any device endpoint command when operating in 2.0 speeds, d
19681 * isable this bit and enable it after the command completes. If you issue
19682 * a command without disabling this bit when the device is in L2 state and
19683 * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
19685 * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1
19687 * Full-Speed Serial Interface Select (FSIntf) The application uses this bi
19688 * t to select a unidirectional or bidirectional USB 1.1 full-speed serial
19689 * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in
19690 * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir
19691 * ectional full-speed serial interface. This bit is set to 0 with Read Onl
19692 * y access. Note: USB 1.1 full-speed serial interface is not supported. Th
19693 * is bit always reads as 1'b0.
19694 * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
19696 * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se
19697 * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int
19698 * erface This bit is writable only if UTMI+ and ULPI is specified for High
19699 * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_
19700 * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
19701 * n the interface selected through DWC_USB3_HSPHY_INTERFACE.
19702 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
19704 * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi
19705 * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte
19706 * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en
19707 * abled 2.0 ports must have the same clock frequency as Port0 clock freque
19708 * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge
19709 * ther for different ports at the same time (that is, all the ports must b
19710 * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If
19711 * any of the USB 2.0 ports is selected as ULPI port for operation, then a
19712 * ll the USB 2.0 ports must be operating at 60 MHz.
19713 * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
19715 * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat
19716 * ed by the application in this field, is multiplied by a bit-time factor;
19717 * this factor is added to the high-speed/full-speed interpacket timeout d
19718 * uration in the core to account for additional delays introduced by the P
19719 * HY. This may be required, since the delay introduced by the PHY in gener
19720 * ating the linestate condition may vary among PHYs. The USB standard time
19721 * out value for high-speed operation is 736 to 816 (inclusive) bit times.
19722 * The USB standard timeout value for full-speed operation is 16 to 18 (inc
19723 * lusive) bit times. The application must program this field based on the
19724 * speed of connection. The number of bit times added per PHY clock are: Hi
19725 * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P
19726 * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.
19727 * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
19728 * k = 0.25 bit times
19729 * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
19731 * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive
19732 * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char
19733 * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
19734 * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
19735 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1
19737 * Global USB2 PHY Configuration Register The application must program this
19738 * register before starting any transactions on either the SoC bus or the
19739 * USB. In Device-only configurations, only one register is needed. In Host
19740 * mode, per-port registers are implemented.
19741 * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U)
19743 PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET,
19744 0x00023FFFU, 0x00022457U);
19745 /*##################################################################### */
19748 * Register : GFLADJ @ 0XFE20C630
19750 * This field indicates the frame length adjustment to be applied when SOF/
19751 * ITP counter is running on the ref_clk. This register value is used to ad
19752 * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i
19753 * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must
19754 * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t
19755 * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows:
19756 * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe
19757 * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege
19758 * r value of the ref_clk period got by truncating the decimal (fractional)
19759 * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c
19760 * lk_period is the ref_clk period including the fractional value. Examples
19761 * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA
19762 * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin
19763 * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE
19764 * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
19765 * 0.8333 = 5208 (ignoring the fractional value)
19766 * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
19768 * Global Frame Length Adjustment Register This register provides options f
19769 * or the software to control the core behavior with respect to SOF (Start
19770 * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer
19771 * functionality. It provides an option to override the fladj_30mhz_reg sid
19772 * eband signal. In addition, it enables running SOF or ITP frame timer cou
19773 * nters completely from the ref_clk. This facilitates hardware LPM in host
19774 * mode with the SOF or ITP counters being run from the ref_clk signal.
19775 * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U)
19777 PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U);
19778 /*##################################################################### */
19781 * Register : GUCTL1 @ 0XFE20C11C
19783 * When this bit is set to '0', termsel, xcvrsel will become 0 during end o
19784 * f resume while the opmode will become 0 once controller completes end of
19785 * resume and enters U0 state (2 separate commandswill be issued). When th
19786 * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
19787 * end of resume itself (only 1 command will be issued)
19788 * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1
19791 * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1
19793 * Global User Control Register 1
19794 * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U)
19796 PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U);
19797 /*##################################################################### */
19800 * Register : GUCTL @ 0XFE20C12C
19802 * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th
19803 * e Auto Retry feature. For IN transfers (non-isochronous) that encounter
19804 * data packets with CRC errors or internal overrun scenarios, the auto ret
19805 * ry feature causes the Host core to reply to the device with a non-termin
19806 * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N
19807 * umP != 0). If the Auto Retry feature is disabled (default), the core wil
19808 * l respond with a terminating retry ACK (that is, an ACK transaction pack
19809 * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
19810 * o Retry Enabled Note: This bit is also applicable to the device mode.
19811 * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1
19813 * Global User Control Register: This register provides a few options for t
19814 * he software to control the core behavior in the Host mode. Most of the o
19815 * ptions are used to improve host inter-operability with different devices
19817 * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U)
19819 PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U);
19820 /*##################################################################### */
19823 * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO
19824 * RRECT RESET VALUES IN SILICON.
19827 * Register : ATTR_25 @ 0XFD480064
19829 * If TRUE Completion Timeout Disable is supported. This is required to be
19830 * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
19831 * ce Capability 2 [4]; EP=0x0001; RP=0x0001
19832 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
19835 * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U)
19837 PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U);
19838 /*##################################################################### */
19844 * Register : ATTR_7 @ 0XFD48001C
19846 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
19847 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
19848 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
19849 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
19850 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
19851 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
19852 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
19853 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
19854 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
19855 * EP=0x0004; RP=0x0000
19856 * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0
19859 * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U)
19861 PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U);
19862 /*##################################################################### */
19865 * Register : ATTR_8 @ 0XFD480020
19867 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
19868 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
19869 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
19870 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
19871 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
19872 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
19873 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
19874 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
19875 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
19876 * EP=0xFFF0; RP=0x0000
19877 * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0
19880 * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U)
19882 PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U);
19883 /*##################################################################### */
19886 * Register : ATTR_9 @ 0XFD480024
19888 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
19889 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
19890 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
19891 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
19892 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
19893 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
19894 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19895 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
19896 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
19897 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
19898 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
19899 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19900 * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0
19903 * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U)
19905 PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U);
19906 /*##################################################################### */
19909 * Register : ATTR_10 @ 0XFD480028
19911 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
19912 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
19913 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
19914 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
19915 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
19916 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
19917 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19918 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
19919 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
19920 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
19921 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
19922 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19923 * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0
19926 * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U)
19928 PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U);
19929 /*##################################################################### */
19932 * Register : ATTR_11 @ 0XFD48002C
19934 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19935 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
19936 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19937 * et to 32'h00000000. See BAR1 description if this functions as the upper
19938 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
19939 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
19940 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
19941 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
19942 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
19943 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
19944 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
19945 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
19946 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
19947 * es.; EP=0x0004; RP=0xFFFF
19948 * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF
19951 * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)
19953 PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU);
19954 /*##################################################################### */
19957 * Register : ATTR_12 @ 0XFD480030
19959 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19960 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
19961 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19962 * et to 32'h00000000. See BAR1 description if this functions as the upper
19963 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
19964 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
19965 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
19966 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
19967 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
19968 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
19969 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
19970 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
19971 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
19972 * es.; EP=0xFFF0; RP=0x00FF
19973 * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF
19976 * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU)
19978 PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU);
19979 /*##################################################################### */
19982 * Register : ATTR_13 @ 0XFD480034
19984 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19985 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
19986 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19987 * et to 32'h00000000. See BAR2 description if this functions as the upper
19988 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
19989 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
19990 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
19991 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
19992 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
19993 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
19994 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
19995 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
19996 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
19997 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
19998 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
19999 * in bytes.; EP=0xFFFF; RP=0x0000
20000 * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0
20003 * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U)
20005 PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U);
20006 /*##################################################################### */
20009 * Register : ATTR_14 @ 0XFD480038
20011 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20012 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
20013 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20014 * et to 32'h00000000. See BAR2 description if this functions as the upper
20015 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
20016 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
20017 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
20018 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
20019 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
20020 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
20021 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
20022 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
20023 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
20024 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
20025 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
20026 * in bytes.; EP=0xFFFF; RP=0xFFFF
20027 * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF
20030 * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)
20032 PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU);
20033 /*##################################################################### */
20036 * Register : ATTR_15 @ 0XFD48003C
20038 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20039 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
20040 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20041 * et to 32'h00000000. See BAR3 description if this functions as the upper
20042 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
20043 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
20044 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
20045 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
20046 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
20047 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
20048 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
20049 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
20050 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
20051 * es.; EP=0x0004; RP=0xFFF0
20052 * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0
20055 * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)
20057 PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U);
20058 /*##################################################################### */
20061 * Register : ATTR_16 @ 0XFD480040
20063 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20064 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
20065 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20066 * et to 32'h00000000. See BAR3 description if this functions as the upper
20067 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
20068 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
20069 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
20070 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
20071 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
20072 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
20073 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
20074 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
20075 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
20076 * es.; EP=0xFFF0; RP=0xFFF0
20077 * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0
20080 * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)
20082 PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U);
20083 /*##################################################################### */
20086 * Register : ATTR_17 @ 0XFD480044
20088 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20089 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
20090 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20091 * et to 32'h00000000. See BAR4 description if this functions as the upper
20092 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
20093 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
20094 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
20095 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
20096 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
20097 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
20098 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
20099 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
20100 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
20101 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
20102 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
20104 * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1
20107 * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)
20109 PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U);
20110 /*##################################################################### */
20113 * Register : ATTR_18 @ 0XFD480048
20115 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20116 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
20117 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20118 * et to 32'h00000000. See BAR4 description if this functions as the upper
20119 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
20120 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
20121 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
20122 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
20123 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
20124 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
20125 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
20126 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
20127 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
20128 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
20129 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
20131 * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1
20134 * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)
20136 PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U);
20137 /*##################################################################### */
20140 * Register : ATTR_27 @ 0XFD48006C
20142 * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1
20143 * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa
20144 * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo
20145 * rted; EP=0x0001; RP=0x0001
20146 * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1
20148 * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca
20149 * n withstand on transitions from L1 state to L0 (if L1 state supported).
20150 * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to
20151 * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For
20152 * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
20153 * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0
20156 * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U)
20158 PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U);
20159 /*##################################################################### */
20162 * Register : ATTR_50 @ 0XFD4800C8
20164 * Identifies the type of device/port as follows: 0000b PCI Express Endpoin
20165 * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P
20166 * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110
20167 * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X
20168 * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre
20169 * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM
20170 * _FACING settings.; EP=0x0000; RP=0x0004
20171 * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4
20173 * PCIe Capability's Next Capability Offset pointer to the next item in the
20174 * capabilities list, or 00h if this is the final capability.; EP=0x009C;
20176 * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0
20179 * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U)
20181 PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U);
20182 /*##################################################################### */
20185 * Register : ATTR_105 @ 0XFD4801A4
20187 * Number of credits that should be advertised for Completion data received
20188 * on Virtual Channel 0. The bytes advertised must be less than or equal t
20189 * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
20190 * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD
20193 * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU)
20195 PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET,
20196 0x000007FFU, 0x000000CDU);
20197 /*##################################################################### */
20200 * Register : ATTR_106 @ 0XFD4801A8
20202 * Number of credits that should be advertised for Completion headers recei
20203 * ved on Virtual Channel 0. The sum of the posted, non posted, and complet
20204 * ion header credits must be <= 80; EP=0x0048; RP=0x0024
20205 * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24
20207 * Number of credits that should be advertised for Non-Posted headers recei
20208 * ved on Virtual Channel 0. The number of non posted data credits advertis
20209 * ed by the block is equal to the number of non posted header credits. The
20210 * sum of the posted, non posted, and completion header credits must be <=
20211 * 80; EP=0x0004; RP=0x000C
20212 * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC
20215 * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U)
20217 PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET,
20218 0x00003FFFU, 0x00000624U);
20219 /*##################################################################### */
20222 * Register : ATTR_107 @ 0XFD4801AC
20224 * Number of credits that should be advertised for Non-Posted data received
20225 * on Virtual Channel 0. The number of non posted data credits advertised
20226 * by the block is equal to two times the number of non posted header credi
20227 * ts if atomic operations are supported or is equal to the number of non p
20228 * osted header credits if atomic operations are not supported. The bytes a
20229 * dvertised must be less than or equal to the bram bytes available. See VC
20230 * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
20231 * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18
20234 * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U)
20236 PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET,
20237 0x000007FFU, 0x00000018U);
20238 /*##################################################################### */
20241 * Register : ATTR_108 @ 0XFD4801B0
20243 * Number of credits that should be advertised for Posted data received on
20244 * Virtual Channel 0. The bytes advertised must be less than or equal to th
20245 * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
20246 * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5
20249 * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U)
20251 PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET,
20252 0x000007FFU, 0x000000B5U);
20253 /*##################################################################### */
20256 * Register : ATTR_109 @ 0XFD4801B4
20258 * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_
20259 * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000
20260 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0
20262 * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim
20263 * TRUE == trim.; EP=0x0001; RP=0x0001
20264 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1
20266 * Enables ECRC check on received TLP's 0 == don't check 1 == always check
20267 * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP=
20268 * 0x0003; RP=0x0003
20269 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3
20271 * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1).
20272 * Calculated from max payload size supported and the number of brams conf
20273 * igured for transmit; EP=0x001C; RP=0x001C
20274 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c
20276 * Number of credits that should be advertised for Posted headers received
20277 * on Virtual Channel 0. The sum of the posted, non posted, and completion
20278 * header credits must be <= 80; EP=0x0004; RP=0x0020
20279 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20
20282 * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)
20284 PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET,
20285 0x0000FFFFU, 0x00007E20U);
20286 /*##################################################################### */
20289 * Register : ATTR_34 @ 0XFD480088
20291 * Specifies values to be transferred to Header Type register. Bit 7 should
20292 * be set to '0' indicating single-function device. Bit 0 identifies heade
20293 * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000;
20295 * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1
20298 * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U)
20300 PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U);
20301 /*##################################################################### */
20304 * Register : ATTR_53 @ 0XFD4800D4
20306 * PM Capability's Next Capability Offset pointer to the next item in the c
20307 * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP
20309 * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60
20312 * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U)
20314 PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U);
20315 /*##################################################################### */
20318 * Register : ATTR_41 @ 0XFD4800A4
20320 * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont
20321 * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure;
20322 * EP=0x0000; RP=0x0000
20323 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0
20325 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
20326 * structure cannot be accessed via either the link or the management port
20327 * .; EP=0x0001; RP=0x0000
20328 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
20330 * MSI Capability's Next Capability Offset pointer to the next item in the
20331 * capabilities list, or 00h if this is the final capability.; EP=0x0060; R
20333 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0
20335 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
20336 * structure cannot be accessed via either the link or the management port
20337 * .; EP=0x0001; RP=0x0000
20338 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
20341 * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U)
20343 PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U);
20344 /*##################################################################### */
20347 * Register : ATTR_97 @ 0XFD480184
20349 * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b
20350 * x4, 001000b x8.; EP=0x0004; RP=0x0004
20351 * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1
20353 * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1
20354 * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004
20355 * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1
20358 * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U)
20360 PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U);
20361 /*##################################################################### */
20364 * Register : ATTR_100 @ 0XFD480190
20366 * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p
20367 * ort.; EP=0x0001; RP=0x0000
20368 * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0
20371 * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U)
20373 PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET,
20374 0x00000040U, 0x00000000U);
20375 /*##################################################################### */
20378 * Register : ATTR_101 @ 0XFD480194
20380 * Enable the routing of message TLPs to the user through the TRN RX interf
20381 * ace. A bit value of 1 enables routing of the message TLP to the user. Me
20382 * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1
20383 * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I
20384 * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit
20385 * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF
20386 * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF
20388 * Disable BAR filtering. Does not change the behavior of the bar hit outpu
20389 * ts; EP=0x0000; RP=0x0001
20390 * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1
20393 * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)
20395 PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET,
20396 0x0000FFE2U, 0x0000FFE2U);
20397 /*##################################################################### */
20400 * Register : ATTR_37 @ 0XFD480094
20402 * Link Bandwidth notification capability. Indicates support for the link b
20403 * andwidth notification status and interrupt mechanism. Required for Root.
20404 * ; EP=0x0000; RP=0x0001
20405 * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
20407 * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op
20408 * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001
20410 * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
20413 * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U)
20415 PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U);
20416 /*##################################################################### */
20419 * Register : ATTR_93 @ 0XFD480174
20421 * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value
20422 * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU
20423 * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
20424 * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1
20426 * Sets a user-defined timeout for the Replay Timer to force cause the retr
20427 * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_
20428 * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att
20429 * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.;
20430 * EP=0x0000; RP=0x0000
20431 * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000
20434 * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U)
20436 PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U);
20437 /*##################################################################### */
20440 * Register : ID @ 0XFD480200
20442 * Device ID for the the PCIe Cap Structure Device ID field
20443 * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021
20445 * Vendor ID for the PCIe Cap Structure Vendor ID field
20446 * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee
20449 * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)
20451 PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U);
20452 /*##################################################################### */
20455 * Register : SUBSYS_ID @ 0XFD480204
20457 * Subsystem ID for the the PCIe Cap Structure Subsystem ID field
20458 * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7
20460 * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
20461 * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee
20464 * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)
20466 PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET,
20467 0xFFFFFFFFU, 0x10EE0007U);
20468 /*##################################################################### */
20471 * Register : REV_ID @ 0XFD480208
20473 * Revision ID for the the PCIe Cap Structure
20474 * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0
20477 * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U)
20479 PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U);
20480 /*##################################################################### */
20483 * Register : ATTR_24 @ 0XFD480060
20485 * Code identifying basic function, subclass and applicable programming int
20486 * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000
20487 * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400
20490 * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U)
20492 PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U);
20493 /*##################################################################### */
20496 * Register : ATTR_25 @ 0XFD480064
20498 * Code identifying basic function, subclass and applicable programming int
20499 * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006
20500 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6
20502 * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10]
20503 * to be hardwired to 0.; EP=0x0001; RP=0x0001
20504 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0
20507 * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U)
20509 PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U);
20510 /*##################################################################### */
20513 * Register : ATTR_4 @ 0XFD480010
20515 * Indicates that the AER structures exists. If this is FALSE, then the AER
20516 * structure cannot be accessed via either the link or the management port
20517 * , and AER will be considered to not be present for error management task
20518 * s (such as what types of error messages are sent if an error is detected
20519 * ).; EP=0x0001; RP=0x0001
20520 * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
20522 * Indicates that the AER structures exists. If this is FALSE, then the AER
20523 * structure cannot be accessed via either the link or the management port
20524 * , and AER will be considered to not be present for error management task
20525 * s (such as what types of error messages are sent if an error is detected
20526 * ).; EP=0x0001; RP=0x0001
20527 * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
20530 * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U)
20532 PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U);
20533 /*##################################################################### */
20536 * Register : ATTR_89 @ 0XFD480164
20538 * VSEC's Next Capability Offset pointer to the next item in the capabiliti
20539 * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140
20540 * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0
20543 * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U)
20545 PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U);
20546 /*##################################################################### */
20549 * Register : ATTR_79 @ 0XFD48013C
20551 * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the
20552 * Root Capabilities register.; EP=0x0000; RP=0x0000
20553 * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1
20556 * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U)
20558 PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U);
20559 /*##################################################################### */
20562 * Register : ATTR_43 @ 0XFD4800AC
20564 * Indicates that the MSIX structures exists. If this is FALSE, then the MS
20565 * IX structure cannot be accessed via either the link or the management po
20566 * rt.; EP=0x0001; RP=0x0000
20567 * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0
20570 * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U)
20572 PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U);
20573 /*##################################################################### */
20576 * Register : ATTR_48 @ 0XFD4800C0
20578 * MSI-X Table Size. This value is transferred to the MSI-X Message Control
20579 * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does
20580 * not implement the table; that must be implemented in user logic.; EP=0x0
20582 * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
20585 * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U)
20587 PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U);
20588 /*##################################################################### */
20591 * Register : ATTR_46 @ 0XFD4800B8
20593 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
20594 * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
20595 * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
20598 * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
20600 PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U);
20601 /*##################################################################### */
20604 * Register : ATTR_47 @ 0XFD4800BC
20606 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
20607 * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000
20608 * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
20611 * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U)
20613 PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U);
20614 /*##################################################################### */
20617 * Register : ATTR_44 @ 0XFD4800B0
20619 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
20620 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
20621 * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
20624 * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
20626 PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U);
20627 /*##################################################################### */
20630 * Register : ATTR_45 @ 0XFD4800B4
20632 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
20633 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000
20634 * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
20637 * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
20639 PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U);
20640 /*##################################################################### */
20643 * Register : CB @ 0XFD48031C
20646 * PSU_PCIE_ATTRIB_CB_CB1 0x0
20649 * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U)
20651 PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U);
20652 /*##################################################################### */
20655 * Register : ATTR_35 @ 0XFD48008C
20657 * Active State PM Support. Indicates the level of active state power manag
20658 * ement supported by the selected PCI Express Link, encoded as follows: 0
20659 * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte
20660 * d.; EP=0x0001; RP=0x0001
20661 * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
20664 * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U)
20666 PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U);
20667 /*##################################################################### */
20670 * PUTTING PCIE CONTROL IN RESET
20673 * Register : RST_FPD_TOP @ 0XFD1A0100
20675 * PCIE control block level reset
20676 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
20678 * FPD Block level software controlled reset
20679 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U)
20681 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U);
20682 /*##################################################################### */
20688 * MASK_DATA_0_LSW LOW BANK [15:0]
20691 * MASK_DATA_0_MSW LOW BANK [25:16]
20694 * MASK_DATA_1_LSW LOW BANK [41:26]
20697 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
20699 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
20700 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
20702 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
20703 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
20705 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
20706 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U)
20708 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
20709 0xFFFFFFFFU, 0xFFDF0020U);
20710 /*##################################################################### */
20713 * MASK_DATA_1_MSW HIGH BANK [51:42]
20716 * MASK_DATA_1_LSW HIGH BANK [67:52]
20719 * MASK_DATA_1_LSW HIGH BANK [77:68]
20722 * CHECK PLL LOCK FOR LANE0
20725 * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
20727 * Status Read value of PLL Lock
20728 * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20729 * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U)
20731 mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20733 /*##################################################################### */
20736 * CHECK PLL LOCK FOR LANE1
20739 * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
20741 * Status Read value of PLL Lock
20742 * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20743 * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U)
20745 mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20747 /*##################################################################### */
20750 * CHECK PLL LOCK FOR LANE2
20753 * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
20755 * Status Read value of PLL Lock
20756 * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20757 * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U)
20759 mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20761 /*##################################################################### */
20764 * CHECK PLL LOCK FOR LANE3
20767 * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
20769 * Status Read value of PLL Lock
20770 * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20771 * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U)
20773 mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20775 /*##################################################################### */
20778 * SATA AHCI VENDOR SETTING
20781 * Register : PP2C @ 0XFD0C00AC
20783 * CIBGMN: COMINIT Burst Gap Minimum.
20784 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
20786 * CIBGMX: COMINIT Burst Gap Maximum.
20787 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
20789 * CIBGN: COMINIT Burst Gap Nominal.
20790 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
20792 * CINMP: COMINIT Negate Minimum Period.
20793 * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
20795 * PP2C - Port Phy2Cfg Register. This register controls the configuration o
20796 * f the Phy Control OOB timing for the COMINIT parameters for either Port
20797 * 0 or Port 1. The Port configured is controlled by the value programmed i
20798 * nto the Port Config Register.
20799 * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
20801 PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET,
20802 0xFFFFFFFFU, 0x28184018U);
20803 /*##################################################################### */
20806 * Register : PP3C @ 0XFD0C00B0
20808 * CWBGMN: COMWAKE Burst Gap Minimum.
20809 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
20811 * CWBGMX: COMWAKE Burst Gap Maximum.
20812 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
20814 * CWBGN: COMWAKE Burst Gap Nominal.
20815 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
20817 * CWNMP: COMWAKE Negate Minimum Period.
20818 * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
20820 * PP3C - Port Phy3CfgRegister. This register controls the configuration of
20821 * the Phy Control OOB timing for the COMWAKE parameters for either Port 0
20822 * or Port 1. The Port configured is controlled by the value programmed in
20823 * to the Port Config Register.
20824 * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
20826 PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET,
20827 0xFFFFFFFFU, 0x0E081406U);
20828 /*##################################################################### */
20831 * Register : PP4C @ 0XFD0C00B4
20833 * BMX: COM Burst Maximum.
20834 * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
20836 * BNM: COM Burst Nominal.
20837 * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
20839 * SFD: Signal Failure Detection, if the signal detection de-asserts for a
20840 * time greater than this then the OOB detector will determine this is a li
20841 * ne idle and cause the PhyInit state machine to exit the Phy Ready State.
20842 * A value of zero disables the Signal Failure Detector. The value is base
20843 * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
20844 * a nominal time of 500ns based on a 150MHz PMCLK.
20845 * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
20847 * PTST: Partial to Slumber timer value, specific delay the controller shou
20848 * ld apply while in partial before entering slumber. The value is bases on
20849 * the system clock divided by 128, total delay = (Sys Clock Period) * PTS
20851 * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
20853 * PP4C - Port Phy4Cfg Register. This register controls the configuration o
20854 * f the Phy Control Burst timing for the COM parameters for either Port 0
20855 * or Port 1. The Port configured is controlled by the value programmed int
20856 * o the Port Config Register.
20857 * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
20859 PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET,
20860 0xFFFFFFFFU, 0x064A0813U);
20861 /*##################################################################### */
20864 * Register : PP5C @ 0XFD0C00B8
20866 * RIT: Retry Interval Timer. The calculated value divided by two, the lowe
20867 * r digit of precision is not needed.
20868 * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
20870 * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev
20871 * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
20872 * fast SERDES it is suggested that this value be 54.2us / 4
20873 * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
20875 * PP5C - Port Phy5Cfg Register. This register controls the configuration o
20876 * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The
20877 * Port configured is controlled by the value programmed into the Port Con
20879 * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
20881 PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET,
20882 0xFFFFFFFFU, 0x3FFC96A4U);
20883 /*##################################################################### */
20888 unsigned long psu_resetin_init_data(void)
20891 * PUTTING SERDES PERIPHERAL IN RESET
20894 * PUTTING USB0 IN RESET
20897 * Register : RST_LPD_TOP @ 0XFF5E023C
20899 * USB 0 reset for control registers
20900 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1
20902 * USB 0 sleep circuit reset
20903 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1
20906 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1
20908 * Software control register for the LPD block.
20909 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U)
20911 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U);
20912 /*##################################################################### */
20915 * PUTTING GEM0 IN RESET
20918 * Register : RST_LPD_IOU0 @ 0XFF5E0230
20921 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1
20923 * Software controlled reset for the GEMs
20924 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U)
20926 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
20927 0x00000008U, 0x00000008U);
20928 /*##################################################################### */
20931 * PUTTING SATA IN RESET
20934 * Register : RST_FPD_TOP @ 0XFD1A0100
20936 * Sata block level reset
20937 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1
20939 * FPD Block level software controlled reset
20940 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U)
20942 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U);
20943 /*##################################################################### */
20946 * PUTTING PCIE IN RESET
20949 * Register : RST_FPD_TOP @ 0XFD1A0100
20951 * PCIE config reset
20952 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1
20954 * PCIE control block level reset
20955 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1
20957 * PCIE bridge block level reset (AXI interface)
20958 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1
20960 * FPD Block level software controlled reset
20961 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U)
20963 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U);
20964 /*##################################################################### */
20967 * PUTTING DP IN RESET
20970 * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238
20972 * Two bits per lane. When set to 11, moves the GT to power down mode. When
20973 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
20975 * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA
20977 * Control PHY Power down
20978 * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU)
20980 PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET,
20981 0x0000000FU, 0x0000000AU);
20982 /*##################################################################### */
20985 * Register : DP_PHY_RESET @ 0XFD4A0200
20987 * Set to '1' to hold the GT in reset. Clear to release.
20988 * PSU_DP_DP_PHY_RESET_GT_RESET 0X1
20990 * Reset the transmitter PHY.
20991 * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U)
20993 PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U);
20994 /*##################################################################### */
20997 * Register : RST_FPD_TOP @ 0XFD1A0100
20999 * Display Port block level reset (includes DPDMA)
21000 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1
21002 * FPD Block level software controlled reset
21003 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U)
21005 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U);
21006 /*##################################################################### */
21011 unsigned long psu_ps_pl_isolation_removal_data(void)
21014 * PS-PL POWER UP REQUEST
21017 * Register : REQ_PWRUP_INT_EN @ 0XFFD80118
21019 * Power-up Request Interrupt Enable for PL
21020 * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1
21022 * Power-up Request Interrupt Enable Register. Writing a 1 to this location
21023 * will unmask the interrupt.
21024 * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U)
21026 PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET,
21027 0x00800000U, 0x00800000U);
21028 /*##################################################################### */
21031 * Register : REQ_PWRUP_TRIG @ 0XFFD80120
21033 * Power-up Request Trigger for PL
21034 * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1
21036 * Power-up Request Trigger Register. A write of one to this location will
21037 * generate a power-up request to the PMU.
21038 * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U)
21040 PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET,
21041 0x00800000U, 0x00800000U);
21042 /*##################################################################### */
21045 * POLL ON PL POWER STATUS
21048 * Register : REQ_PWRUP_STATUS @ 0XFFD80110
21050 * Power-up Request Status for PL
21051 * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1
21052 * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U)
21054 mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,
21055 0x00800000U, 0x00000000U);
21057 /*##################################################################### */
21062 unsigned long psu_afi_config(void)
21068 * Register : RST_FPD_TOP @ 0XFD1A0100
21070 * AF_FM0 block level reset
21071 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0
21073 * AF_FM1 block level reset
21074 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0
21076 * AF_FM2 block level reset
21077 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0
21079 * AF_FM3 block level reset
21080 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0
21082 * AF_FM4 block level reset
21083 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0
21085 * AF_FM5 block level reset
21086 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0
21088 * FPD Block level software controlled reset
21089 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U)
21091 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U);
21092 /*##################################################################### */
21095 * Register : RST_LPD_TOP @ 0XFF5E023C
21098 * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0
21100 * Software control register for the LPD block.
21101 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U)
21103 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U);
21104 /*##################################################################### */
21107 * AFIFM INTERFACE WIDTH
21110 * Register : afi_fs @ 0XFD615000
21112 * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit
21113 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
21114 * width 11: reserved
21115 * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2
21117 * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit
21118 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
21119 * width 11: reserved
21120 * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2
21122 * afi fs SLCR control register. This register is static and should not be
21123 * modified during operation.
21124 * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U)
21126 PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U);
21127 /*##################################################################### */
21132 unsigned long psu_ps_pl_reset_config_data(void)
21135 * PS PL RESET SEQUENCE
21138 * FABRIC RESET USING EMIO
21141 * Register : MASK_DATA_5_MSW @ 0XFF0A002C
21143 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
21144 * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000
21146 * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
21147 * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U)
21149 PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET,
21150 0xFFFF0000U, 0x80000000U);
21151 /*##################################################################### */
21154 * Register : DIRM_5 @ 0XFF0A0344
21156 * Operation is the same as DIRM_0[DIRECTION_0]
21157 * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000
21159 * Direction mode (GPIO Bank5, EMIO)
21160 * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)
21162 PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21163 /*##################################################################### */
21166 * Register : OEN_5 @ 0XFF0A0348
21168 * Operation is the same as OEN_0[OP_ENABLE_0]
21169 * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000
21171 * Output enable (GPIO Bank5, EMIO)
21172 * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)
21174 PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21175 /*##################################################################### */
21178 * Register : DATA_5 @ 0XFF0A0054
21181 * PSU_GPIO_DATA_5_DATA_5 0x80000000
21183 * Output Data (GPIO Bank5, EMIO)
21184 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
21186 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21187 /*##################################################################### */
21191 /*##################################################################### */
21194 * FABRIC RESET USING DATA_5 TOGGLE
21197 * Register : DATA_5 @ 0XFF0A0054
21200 * PSU_GPIO_DATA_5_DATA_5 0X00000000
21202 * Output Data (GPIO Bank5, EMIO)
21203 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)
21205 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U);
21206 /*##################################################################### */
21210 /*##################################################################### */
21213 * FABRIC RESET USING DATA_5 TOGGLE
21216 * Register : DATA_5 @ 0XFF0A0054
21219 * PSU_GPIO_DATA_5_DATA_5 0x80000000
21221 * Output Data (GPIO Bank5, EMIO)
21222 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
21224 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21225 /*##################################################################### */
21231 unsigned long psu_ddr_phybringup_data(void)
21235 unsigned int regval = 0;
21237 unsigned int pll_retry = 10;
21239 unsigned int pll_locked = 0;
21242 while ((pll_retry > 0) && (!pll_locked)) {
21244 Xil_Out32(0xFD080004, 0x00040010);/*PIR*/
21245 Xil_Out32(0xFD080004, 0x00040011);/*PIR*/
21247 while ((Xil_In32(0xFD080030) & 0x1) != 1) {
21250 /*TIMEOUT poll mechanism need to be inserted in this block*/
21255 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
21257 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
21259 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
21261 pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
21263 pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
21267 Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) |
21268 (pll_retry << 16));/*GPR0*/
21269 Xil_Out32(0xFD080004U, 0x00040063U);
21270 /* PHY BRINGUP SEQ */
21271 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) {
21274 /*TIMEOUT poll mechanism need to be inserted in this block*/
21278 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
21279 /* poll for PHY initialization to complete */
21280 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) {
21283 /*TIMEOUT poll mechanism need to be inserted in this block*/
21288 Xil_Out32(0xFD0701B0U, 0x00000001U);
21289 Xil_Out32(0xFD070320U, 0x00000001U);
21290 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) {
21293 /*TIMEOUT poll mechanism need to be inserted in this block*/
21297 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
21298 Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/
21299 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21300 while (regval != 0x80000FFF)
21301 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21303 /* Run Vref training in static read mode*/
21304 Xil_Out32(0xFD080200U, 0x100091C7U);
21305 Xil_Out32(0xFD080018U, 0x00F01EEFU);
21306 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
21307 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
21308 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
21309 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
21310 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
21311 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
21314 Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/
21315 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21316 while ((regval & 0x80004001) != 0x80004001) {
21318 regval = Xil_In32(0xFD080030);
21321 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
21322 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
21323 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
21324 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
21325 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
21326 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
21327 /*Vref training is complete, disabling static read mode*/
21328 Xil_Out32(0xFD080200U, 0x800091C7U);
21329 Xil_Out32(0xFD080018U, 0x00F122E7U);
21332 Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/
21333 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21334 while ((regval & 0x80000C01) != 0x80000C01) {
21336 regval = Xil_In32(0xFD080030);
21339 Xil_Out32(0xFD070180U, 0x01000040U);
21340 Xil_Out32(0xFD070060U, 0x00000000U);
21341 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
21347 * CRL_APB Base Address
21349 #define CRL_APB_BASEADDR 0XFF5E0000U
21350 #define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U)
21351 #define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U)
21352 #define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U)
21353 #define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU)
21354 #define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU)
21357 * CRF_APB Base Address
21359 #define CRF_APB_BASEADDR 0XFD1A0000U
21361 #define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U)
21362 #define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U)
21363 #define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U)
21364 #define PSU_MASK_POLL_TIME 1100000
21367 * * Register: CRF_APB_DPLL_CTRL
21369 #define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C)
21372 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
21373 #define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1
21375 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
21376 #define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7
21378 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
21379 #define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1
21381 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
21382 #define CRF_APB_DPLL_CTRL_RESET_WIDTH 1
21385 * * Register: CRF_APB_DPLL_CFG
21387 #define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030)
21389 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
21390 #define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7
21392 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
21393 #define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10
21395 #define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
21396 #define CRF_APB_DPLL_CFG_LFHF_WIDTH 2
21398 #define CRF_APB_DPLL_CFG_CP_SHIFT 5
21399 #define CRF_APB_DPLL_CFG_CP_WIDTH 4
21401 #define CRF_APB_DPLL_CFG_RES_SHIFT 0
21402 #define CRF_APB_DPLL_CFG_RES_WIDTH 4
21405 * Register: CRF_APB_PLL_STATUS
21407 #define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044)
21410 static int mask_pollOnValue(u32 add, u32 mask, u32 value)
21412 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21415 while ((*addr & mask) != value) {
21416 if (i == PSU_MASK_POLL_TIME)
21423 static int mask_poll(u32 add, u32 mask)
21425 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21428 while (!(*addr & mask)) {
21429 if (i == PSU_MASK_POLL_TIME)
21436 static void mask_delay(u32 delay)
21441 static u32 mask_read(u32 add, u32 mask)
21443 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21444 u32 val = (*addr & mask);
21448 static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
21449 int d_lfhf, int d_cp, int d_res) {
21451 unsigned int pll_ctrl_regval;
21452 unsigned int pll_status_regval;
21454 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21455 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK);
21456 pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT);
21457 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21459 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21460 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK);
21461 pll_ctrl_regval = pll_ctrl_regval |
21462 (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT);
21463 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21465 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21466 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK);
21467 pll_ctrl_regval = pll_ctrl_regval |
21468 (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT);
21469 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21471 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21472 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK);
21473 pll_ctrl_regval = pll_ctrl_regval |
21474 (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT);
21475 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21477 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21478 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK);
21479 pll_ctrl_regval = pll_ctrl_regval |
21480 (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT);
21481 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21483 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21484 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK);
21485 pll_ctrl_regval = pll_ctrl_regval |
21486 (d_res << CRF_APB_DPLL_CFG_RES_SHIFT);
21487 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21489 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21490 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK);
21491 pll_ctrl_regval = pll_ctrl_regval |
21492 (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT);
21493 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21495 /*Setting PLL BYPASS*/
21496 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21497 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK);
21498 pll_ctrl_regval = pll_ctrl_regval |
21499 (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT);
21500 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21502 /*Setting PLL RESET*/
21503 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21504 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK);
21505 pll_ctrl_regval = pll_ctrl_regval |
21506 (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT);
21507 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21509 /*Clearing PLL RESET*/
21510 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21511 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK);
21512 pll_ctrl_regval = pll_ctrl_regval |
21513 (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT);
21514 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21516 /*Checking PLL lock*/
21517 pll_status_regval = 0x00000000;
21518 while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) !=
21519 CRF_APB_PLL_STATUS_DPLL_LOCK_MASK)
21520 pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS);
21525 /*Clearing PLL BYPASS*/
21526 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21527 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK);
21528 pll_ctrl_regval = pll_ctrl_regval |
21529 (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT);
21530 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21534 /*Following SERDES programming sequences that a user need to follow to work
21535 * around the known limitation with SERDES. These sequences should done
21536 * before STEP 1 and STEP 2 as described in previous section. These
21537 * programming steps are *required for current silicon version and are
21538 * likely to undergo further changes with subsequent silicon versions.
21542 static int serdes_enb_coarse_saturation(void)
21544 /*Enable PLL Coarse Code saturation Logic*/
21545 Xil_Out32(0xFD402094, 0x00000010);
21546 Xil_Out32(0xFD406094, 0x00000010);
21547 Xil_Out32(0xFD40A094, 0x00000010);
21548 Xil_Out32(0xFD40E094, 0x00000010);
21552 int serdes_fixcal_code(void)
21554 int MaskStatus = 1;
21556 unsigned int rdata = 0;
21558 /*The valid codes are from 0x26 to 0x3C.
21559 *There are 23 valid codes in total.
21561 /*Each element of array stands for count of occurence of valid code.*/
21562 unsigned int match_pmos_code[23];
21563 /*Each element of array stands for count of occurence of valid code.*/
21564 /*The valid codes are from 0xC to 0x12.
21565 *There are 7 valid codes in total.
21567 unsigned int match_nmos_code[23];
21568 /*Each element of array stands for count of occurence of valid code.*/
21569 /*The valid codes are from 0x6 to 0xC.
21570 * There are 7 valid codes in total.
21572 unsigned int match_ical_code[7];
21573 /*Each element of array stands for count of occurence of valid code.*/
21574 unsigned int match_rcal_code[7];
21576 unsigned int p_code = 0;
21577 unsigned int n_code = 0;
21578 unsigned int i_code = 0;
21579 unsigned int r_code = 0;
21580 unsigned int repeat_count = 0;
21581 unsigned int L3_TM_CALIB_DIG20 = 0;
21582 unsigned int L3_TM_CALIB_DIG19 = 0;
21583 unsigned int L3_TM_CALIB_DIG18 = 0;
21584 unsigned int L3_TM_CALIB_DIG16 = 0;
21585 unsigned int L3_TM_CALIB_DIG15 = 0;
21586 unsigned int L3_TM_CALIB_DIG14 = 0;
21590 rdata = Xil_In32(0XFD40289C);
21591 rdata = rdata & ~0x03;
21592 rdata = rdata | 0x1;
21593 Xil_Out32(0XFD40289C, rdata);
21594 // check supply good status before starting AFE sequencing
21598 if (count == PSU_MASK_POLL_TIME)
21600 rdata = Xil_In32(0xFD402B1C);
21602 }while((rdata&0x0000000E) !=0x0000000E);
21604 for (i = 0; i < 23; i++) {
21605 match_pmos_code[i] = 0;
21606 match_nmos_code[i] = 0;
21608 for (i = 0; i < 7; i++) {
21609 match_ical_code[i] = 0;
21610 match_rcal_code[i] = 0;
21615 /*Clear ICM_CFG value*/
21616 Xil_Out32(0xFD410010, 0x00000000);
21617 Xil_Out32(0xFD410014, 0x00000000);
21619 /*Set ICM_CFG value*/
21620 /*This will trigger recalibration of all stages*/
21621 Xil_Out32(0xFD410010, 0x00000001);
21622 Xil_Out32(0xFD410014, 0x00000000);
21624 /*is calibration done? polling on L3_CALIB_DONE_STATUS*/
21625 MaskStatus = mask_poll(0xFD40EF14, 0x2);
21626 if (MaskStatus == 0) {
21627 /*failure here is because of calibration done timeout*/
21628 xil_printf("#SERDES initialization timed out\n\r");
21632 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/
21633 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/
21634 /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/
21635 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/
21636 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/
21637 /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/
21639 /*PMOS code in acceptable range*/
21640 if ((p_code >= 0x26) && (p_code <= 0x3C))
21641 match_pmos_code[p_code - 0x26] += 1;
21643 /*NMOS code in acceptable range*/
21644 if ((n_code >= 0x26) && (n_code <= 0x3C))
21645 match_nmos_code[n_code - 0x26] += 1;
21647 /*PMOS code in acceptable range*/
21648 if ((i_code >= 0xC) && (i_code <= 0x12))
21649 match_ical_code[i_code - 0xC] += 1;
21651 /*NMOS code in acceptable range*/
21652 if ((r_code >= 0x6) && (r_code <= 0xC))
21653 match_rcal_code[r_code - 0x6] += 1;
21656 } while (repeat_count++ < 10);
21658 /*find the valid code which resulted in maximum times in 10 iterations*/
21659 for (i = 0; i < 23; i++) {
21660 if (match_pmos_code[i] >= match_pmos_code[0]) {
21661 match_pmos_code[0] = match_pmos_code[i];
21664 if (match_nmos_code[i] >= match_nmos_code[0]) {
21665 match_nmos_code[0] = match_nmos_code[i];
21670 for (i = 0; i < 7; i++) {
21671 if (match_ical_code[i] >= match_ical_code[0]) {
21672 match_ical_code[0] = match_ical_code[i];
21675 if (match_rcal_code[i] >= match_rcal_code[0]) {
21676 match_rcal_code[0] = match_rcal_code[i];
21680 /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/
21681 /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/
21682 L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/
21683 L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
21686 /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/
21687 /*L3_TM_CALIB_DIG19[5] PSW Override*/
21688 /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/
21689 /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/
21690 L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/
21691 L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
21692 | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
21694 /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/
21695 /*L3_TM_CALIB_DIG18[4] NSW Override*/
21696 L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/
21697 L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
21700 /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/
21701 L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/
21702 L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
21704 /*L3_TM_CALIB_DIG15[7] RX Code [0]*/
21705 /*L3_TM_CALIB_DIG15[6] RX CODE Override*/
21706 /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/
21707 /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/
21708 L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/
21709 L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
21710 | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
21712 /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/
21713 /*L3_TM_CALIB_DIG14[6] ICAL Override*/
21714 L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/
21715 L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
21717 /*Forces the calibration values*/
21718 Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
21719 Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
21720 Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
21721 Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
21722 Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
21723 Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
21727 static int init_serdes(void)
21731 status &= psu_resetin_init_data();
21733 status &= serdes_fixcal_code();
21734 status &= serdes_enb_coarse_saturation();
21736 status &= psu_serdes_init_data();
21737 status &= psu_resetout_init_data();
21743 static void init_peripheral(void)
21745 /*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/
21746 PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
21749 static int psu_init_xppu_aper_ram(void)
21755 int psu_lpd_protection(void)
21757 psu_init_xppu_aper_ram();
21761 int psu_ddr_protection(void)
21763 psu_ddr_xmpu0_data();
21764 psu_ddr_xmpu1_data();
21765 psu_ddr_xmpu2_data();
21766 psu_ddr_xmpu3_data();
21767 psu_ddr_xmpu4_data();
21768 psu_ddr_xmpu5_data();
21771 int psu_ocm_protection(void)
21773 psu_ocm_xmpu_data();
21777 int psu_fpd_protection(void)
21779 psu_fpd_xmpu_data();
21783 int psu_protection_lock(void)
21785 psu_protection_lock_data();
21789 int psu_protection(void)
21791 psu_apply_master_tz();
21792 psu_ddr_protection();
21793 psu_ocm_protection();
21794 psu_fpd_protection();
21795 psu_lpd_protection();
21804 status &= psu_mio_init_data();
21805 status &= psu_pll_init_data();
21806 status &= psu_clock_init_data();
21807 status &= psu_ddr_init_data();
21808 status &= psu_ddr_phybringup_data();
21809 status &= psu_peripherals_init_data();
21810 status &= init_serdes();
21813 status &= psu_peripherals_powerdwn_data();
21814 status &= psu_afi_config();
21815 psu_ddr_qos_init_data();