1 #undef CRL_APB_RPLL_CTRL_OFFSET
\r
2 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
\r
3 #undef CRL_APB_RPLL_CTRL_OFFSET
\r
4 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
\r
5 #undef CRL_APB_RPLL_CTRL_OFFSET
\r
6 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
\r
7 #undef CRL_APB_RPLL_CTRL_OFFSET
\r
8 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
\r
9 #undef CRL_APB_RPLL_CTRL_OFFSET
\r
10 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
\r
11 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
\r
12 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048
\r
13 #undef CRL_APB_IOPLL_CTRL_OFFSET
\r
14 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
\r
15 #undef CRL_APB_IOPLL_CTRL_OFFSET
\r
16 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
\r
17 #undef CRL_APB_IOPLL_CTRL_OFFSET
\r
18 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
\r
19 #undef CRL_APB_IOPLL_CTRL_OFFSET
\r
20 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
\r
21 #undef CRL_APB_IOPLL_CTRL_OFFSET
\r
22 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
\r
23 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
\r
24 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044
\r
25 #undef CRF_APB_APLL_CTRL_OFFSET
\r
26 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
\r
27 #undef CRF_APB_APLL_CTRL_OFFSET
\r
28 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
\r
29 #undef CRF_APB_APLL_CTRL_OFFSET
\r
30 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
\r
31 #undef CRF_APB_APLL_CTRL_OFFSET
\r
32 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
\r
33 #undef CRF_APB_APLL_CTRL_OFFSET
\r
34 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
\r
35 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
\r
36 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048
\r
37 #undef CRF_APB_DPLL_CTRL_OFFSET
\r
38 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
\r
39 #undef CRF_APB_DPLL_CTRL_OFFSET
\r
40 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
\r
41 #undef CRF_APB_DPLL_CTRL_OFFSET
\r
42 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
\r
43 #undef CRF_APB_DPLL_CTRL_OFFSET
\r
44 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
\r
45 #undef CRF_APB_DPLL_CTRL_OFFSET
\r
46 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
\r
47 #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
\r
48 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C
\r
49 #undef CRF_APB_VPLL_CTRL_OFFSET
\r
50 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
\r
51 #undef CRF_APB_VPLL_CTRL_OFFSET
\r
52 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
\r
53 #undef CRF_APB_VPLL_CTRL_OFFSET
\r
54 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
\r
55 #undef CRF_APB_VPLL_CTRL_OFFSET
\r
56 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
\r
57 #undef CRF_APB_VPLL_CTRL_OFFSET
\r
58 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
\r
59 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
\r
60 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050
\r
62 /*The integer portion of the feedback divider to the PLL*/
\r
63 #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
\r
64 #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
\r
65 #undef CRL_APB_RPLL_CTRL_FBDIV_MASK
\r
66 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09
\r
67 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8
\r
68 #define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U
\r
70 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
\r
71 #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
\r
72 #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
\r
73 #undef CRL_APB_RPLL_CTRL_DIV2_MASK
\r
74 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09
\r
75 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16
\r
76 #define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U
\r
78 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
79 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
80 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
\r
81 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
\r
82 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
\r
83 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
84 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
\r
85 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
\r
87 /*Asserts Reset to the PLL*/
\r
88 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
\r
89 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
\r
90 #undef CRL_APB_RPLL_CTRL_RESET_MASK
\r
91 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
\r
92 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
\r
93 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
\r
95 /*Asserts Reset to the PLL*/
\r
96 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
\r
97 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
\r
98 #undef CRL_APB_RPLL_CTRL_RESET_MASK
\r
99 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
\r
100 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
\r
101 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
\r
104 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
\r
105 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
\r
106 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
\r
107 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018
\r
108 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1
\r
109 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U
\r
110 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
\r
112 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
113 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
114 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
\r
115 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
\r
116 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
\r
117 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
118 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
\r
119 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
\r
121 /*Divisor value for this clock.*/
\r
122 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
\r
123 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
\r
124 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
\r
125 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
\r
126 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
\r
127 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
129 /*The integer portion of the feedback divider to the PLL*/
\r
130 #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
\r
131 #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
\r
132 #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
\r
133 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09
\r
134 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8
\r
135 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U
\r
137 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
\r
138 #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
\r
139 #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
\r
140 #undef CRL_APB_IOPLL_CTRL_DIV2_MASK
\r
141 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09
\r
142 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16
\r
143 #define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U
\r
145 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
146 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
147 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
\r
148 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
\r
149 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
\r
150 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
151 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
\r
152 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
\r
154 /*Asserts Reset to the PLL*/
\r
155 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
\r
156 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
\r
157 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
\r
158 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
\r
159 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
\r
160 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
\r
162 /*Asserts Reset to the PLL*/
\r
163 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
\r
164 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
\r
165 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
\r
166 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
\r
167 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
\r
168 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
\r
170 /*IOPLL is locked*/
\r
171 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
\r
172 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
\r
173 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
\r
174 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018
\r
175 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0
\r
176 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U
\r
177 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
\r
179 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
180 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
181 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
\r
182 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
\r
183 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
\r
184 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
185 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
\r
186 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
\r
188 /*Divisor value for this clock.*/
\r
189 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
\r
190 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
\r
191 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
\r
192 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
\r
193 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
\r
194 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
196 /*The integer portion of the feedback divider to the PLL*/
\r
197 #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
\r
198 #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
\r
199 #undef CRF_APB_APLL_CTRL_FBDIV_MASK
\r
200 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09
\r
201 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8
\r
202 #define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U
\r
204 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
\r
205 #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
\r
206 #undef CRF_APB_APLL_CTRL_DIV2_SHIFT
\r
207 #undef CRF_APB_APLL_CTRL_DIV2_MASK
\r
208 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09
\r
209 #define CRF_APB_APLL_CTRL_DIV2_SHIFT 16
\r
210 #define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U
\r
212 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
213 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
214 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
\r
215 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
\r
216 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
\r
217 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
218 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
\r
219 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
\r
221 /*Asserts Reset to the PLL*/
\r
222 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
\r
223 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
\r
224 #undef CRF_APB_APLL_CTRL_RESET_MASK
\r
225 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
\r
226 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
\r
227 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
\r
229 /*Asserts Reset to the PLL*/
\r
230 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
\r
231 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
\r
232 #undef CRF_APB_APLL_CTRL_RESET_MASK
\r
233 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
\r
234 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
\r
235 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
\r
238 #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
\r
239 #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
\r
240 #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
\r
241 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038
\r
242 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0
\r
243 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U
\r
244 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
\r
246 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
247 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
248 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
\r
249 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
\r
250 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
\r
251 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
\r
252 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
\r
253 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
\r
255 /*Divisor value for this clock.*/
\r
256 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
\r
257 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
\r
258 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
\r
259 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
\r
260 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
\r
261 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
263 /*The integer portion of the feedback divider to the PLL*/
\r
264 #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
\r
265 #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
\r
266 #undef CRF_APB_DPLL_CTRL_FBDIV_MASK
\r
267 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09
\r
268 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
\r
269 #define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U
\r
271 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
\r
272 #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
\r
273 #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
\r
274 #undef CRF_APB_DPLL_CTRL_DIV2_MASK
\r
275 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09
\r
276 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
\r
277 #define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U
\r
279 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
280 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
281 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
\r
282 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
\r
283 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
\r
284 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
\r
285 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
\r
286 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
\r
288 /*Asserts Reset to the PLL*/
\r
289 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
\r
290 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
\r
291 #undef CRF_APB_DPLL_CTRL_RESET_MASK
\r
292 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
\r
293 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
\r
294 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
\r
296 /*Asserts Reset to the PLL*/
\r
297 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
\r
298 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
\r
299 #undef CRF_APB_DPLL_CTRL_RESET_MASK
\r
300 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
\r
301 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
\r
302 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
\r
305 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
\r
306 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
\r
307 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
\r
308 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038
\r
309 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1
\r
310 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U
\r
311 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
\r
313 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
314 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
315 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
\r
316 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
\r
317 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
\r
318 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
\r
319 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
\r
320 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
\r
322 /*Divisor value for this clock.*/
\r
323 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
\r
324 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
\r
325 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
\r
326 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
\r
327 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
\r
328 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
330 /*The integer portion of the feedback divider to the PLL*/
\r
331 #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
\r
332 #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
\r
333 #undef CRF_APB_VPLL_CTRL_FBDIV_MASK
\r
334 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809
\r
335 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8
\r
336 #define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U
\r
338 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
\r
339 #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
\r
340 #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
\r
341 #undef CRF_APB_VPLL_CTRL_DIV2_MASK
\r
342 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809
\r
343 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16
\r
344 #define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U
\r
346 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
347 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
348 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
\r
349 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
\r
350 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
\r
351 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
\r
352 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
\r
353 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
\r
355 /*Asserts Reset to the PLL*/
\r
356 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
\r
357 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
\r
358 #undef CRF_APB_VPLL_CTRL_RESET_MASK
\r
359 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
\r
360 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
\r
361 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
\r
363 /*Asserts Reset to the PLL*/
\r
364 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
\r
365 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
\r
366 #undef CRF_APB_VPLL_CTRL_RESET_MASK
\r
367 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
\r
368 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
\r
369 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
\r
372 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
\r
373 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
\r
374 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
\r
375 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038
\r
376 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2
\r
377 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U
\r
378 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
\r
380 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
\r
381 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
382 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
\r
383 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
\r
384 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
\r
385 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
\r
386 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
\r
387 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
\r
389 /*Divisor value for this clock.*/
\r
390 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
\r
391 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
\r
392 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
\r
393 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
\r
394 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
\r
395 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
396 #undef CRL_APB_GEM0_REF_CTRL_OFFSET
\r
397 #define CRL_APB_GEM0_REF_CTRL_OFFSET 0XFF5E0050
\r
398 #undef CRL_APB_GEM1_REF_CTRL_OFFSET
\r
399 #define CRL_APB_GEM1_REF_CTRL_OFFSET 0XFF5E0054
\r
400 #undef CRL_APB_GEM2_REF_CTRL_OFFSET
\r
401 #define CRL_APB_GEM2_REF_CTRL_OFFSET 0XFF5E0058
\r
402 #undef CRL_APB_GEM3_REF_CTRL_OFFSET
\r
403 #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
\r
404 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
\r
405 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
\r
406 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
\r
407 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
\r
408 #undef CRL_APB_QSPI_REF_CTRL_OFFSET
\r
409 #define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
\r
410 #undef CRL_APB_SDIO0_REF_CTRL_OFFSET
\r
411 #define CRL_APB_SDIO0_REF_CTRL_OFFSET 0XFF5E006C
\r
412 #undef CRL_APB_SDIO1_REF_CTRL_OFFSET
\r
413 #define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
\r
414 #undef CRL_APB_UART0_REF_CTRL_OFFSET
\r
415 #define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074
\r
416 #undef CRL_APB_UART1_REF_CTRL_OFFSET
\r
417 #define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078
\r
418 #undef CRL_APB_I2C0_REF_CTRL_OFFSET
\r
419 #define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
\r
420 #undef CRL_APB_I2C1_REF_CTRL_OFFSET
\r
421 #define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
\r
422 #undef CRL_APB_SPI0_REF_CTRL_OFFSET
\r
423 #define CRL_APB_SPI0_REF_CTRL_OFFSET 0XFF5E007C
\r
424 #undef CRL_APB_SPI1_REF_CTRL_OFFSET
\r
425 #define CRL_APB_SPI1_REF_CTRL_OFFSET 0XFF5E0080
\r
426 #undef CRL_APB_CAN0_REF_CTRL_OFFSET
\r
427 #define CRL_APB_CAN0_REF_CTRL_OFFSET 0XFF5E0084
\r
428 #undef CRL_APB_CAN1_REF_CTRL_OFFSET
\r
429 #define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
\r
430 #undef CRL_APB_CPU_R5_CTRL_OFFSET
\r
431 #define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
\r
432 #undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
\r
433 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
\r
434 #undef CRL_APB_PCAP_CTRL_OFFSET
\r
435 #define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
\r
436 #undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
\r
437 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8
\r
438 #undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
\r
439 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
\r
440 #undef CRL_APB_DBG_LPD_CTRL_OFFSET
\r
441 #define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
\r
442 #undef CRL_APB_NAND_REF_CTRL_OFFSET
\r
443 #define CRL_APB_NAND_REF_CTRL_OFFSET 0XFF5E00B4
\r
444 #undef CRL_APB_ADMA_REF_CTRL_OFFSET
\r
445 #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
\r
446 #undef CRL_APB_AMS_REF_CTRL_OFFSET
\r
447 #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108
\r
448 #undef CRL_APB_DLL_REF_CTRL_OFFSET
\r
449 #define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104
\r
450 #undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
\r
451 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128
\r
452 #undef CRF_APB_PCIE_REF_CTRL_OFFSET
\r
453 #define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4
\r
454 #undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
\r
455 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070
\r
456 #undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
\r
457 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074
\r
458 #undef CRF_APB_DP_STC_REF_CTRL_OFFSET
\r
459 #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C
\r
460 #undef CRF_APB_ACPU_CTRL_OFFSET
\r
461 #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060
\r
462 #undef CRF_APB_DBG_TRACE_CTRL_OFFSET
\r
463 #define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064
\r
464 #undef CRF_APB_DBG_FPD_CTRL_OFFSET
\r
465 #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068
\r
466 #undef CRF_APB_DDR_CTRL_OFFSET
\r
467 #define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080
\r
468 #undef CRF_APB_GPU_REF_CTRL_OFFSET
\r
469 #define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084
\r
470 #undef CRF_APB_GDMA_REF_CTRL_OFFSET
\r
471 #define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8
\r
472 #undef CRF_APB_DPDMA_REF_CTRL_OFFSET
\r
473 #define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC
\r
474 #undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
\r
475 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
\r
476 #undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
\r
477 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
\r
478 #undef CRF_APB_GTGREF0_REF_CTRL_OFFSET
\r
479 #define CRF_APB_GTGREF0_REF_CTRL_OFFSET 0XFD1A00C8
\r
480 #undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
\r
481 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
\r
483 /*Clock active for the RX channel*/
\r
484 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL
\r
485 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
\r
486 #undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK
\r
487 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
\r
488 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26
\r
489 #define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 0x04000000U
\r
491 /*Clock active signal. Switch to 0 to disable the clock*/
\r
492 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL
\r
493 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
\r
494 #undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK
\r
495 #define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 0x00002500
\r
496 #define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25
\r
497 #define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 0x02000000U
\r
500 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL
\r
501 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
\r
502 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK
\r
503 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
\r
504 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16
\r
505 #define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
508 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL
\r
509 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
\r
510 #undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK
\r
511 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
\r
512 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8
\r
513 #define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
515 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
516 clock. This is not usually an issue, but designers must be aware.)*/
\r
517 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL
\r
518 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
\r
519 #undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK
\r
520 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 0x00002500
\r
521 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0
\r
522 #define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
524 /*Clock active for the RX channel*/
\r
525 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL
\r
526 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
\r
527 #undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK
\r
528 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
\r
529 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26
\r
530 #define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 0x04000000U
\r
532 /*Clock active signal. Switch to 0 to disable the clock*/
\r
533 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL
\r
534 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
\r
535 #undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK
\r
536 #define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 0x00002500
\r
537 #define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25
\r
538 #define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 0x02000000U
\r
541 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL
\r
542 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
\r
543 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK
\r
544 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
\r
545 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16
\r
546 #define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
549 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL
\r
550 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
\r
551 #undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK
\r
552 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
\r
553 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8
\r
554 #define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
556 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
557 clock. This is not usually an issue, but designers must be aware.)*/
\r
558 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL
\r
559 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
\r
560 #undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK
\r
561 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 0x00002500
\r
562 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0
\r
563 #define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
565 /*Clock active for the RX channel*/
\r
566 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL
\r
567 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
\r
568 #undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK
\r
569 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
\r
570 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26
\r
571 #define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 0x04000000U
\r
573 /*Clock active signal. Switch to 0 to disable the clock*/
\r
574 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL
\r
575 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
\r
576 #undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK
\r
577 #define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 0x00002500
\r
578 #define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25
\r
579 #define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 0x02000000U
\r
582 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL
\r
583 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
\r
584 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK
\r
585 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
\r
586 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16
\r
587 #define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
590 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL
\r
591 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
\r
592 #undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK
\r
593 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
\r
594 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8
\r
595 #define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
597 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
598 clock. This is not usually an issue, but designers must be aware.)*/
\r
599 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL
\r
600 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
\r
601 #undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK
\r
602 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 0x00002500
\r
603 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0
\r
604 #define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
606 /*Clock active for the RX channel*/
\r
607 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
\r
608 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
\r
609 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
\r
610 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
\r
611 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26
\r
612 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U
\r
614 /*Clock active signal. Switch to 0 to disable the clock*/
\r
615 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
\r
616 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
\r
617 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
\r
618 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500
\r
619 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25
\r
620 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U
\r
623 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
\r
624 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
\r
625 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
\r
626 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
\r
627 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16
\r
628 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
631 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
\r
632 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
\r
633 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
\r
634 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
\r
635 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8
\r
636 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
638 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
639 clock. This is not usually an issue, but designers must be aware.)*/
\r
640 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
\r
641 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
\r
642 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
\r
643 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500
\r
644 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
\r
645 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
647 /*Clock active signal. Switch to 0 to disable the clock*/
\r
648 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
\r
649 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
\r
650 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
\r
651 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
\r
652 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25
\r
653 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
\r
656 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
\r
657 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
\r
658 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
\r
659 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
\r
660 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16
\r
661 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
664 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
\r
665 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
\r
666 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
\r
667 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
\r
668 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8
\r
669 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
671 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
672 clock. This is not usually an issue, but designers must be aware.)*/
\r
673 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
\r
674 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
\r
675 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
\r
676 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
\r
677 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
\r
678 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
680 /*Clock active signal. Switch to 0 to disable the clock*/
\r
681 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
\r
682 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
\r
683 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
\r
684 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000
\r
685 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25
\r
686 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U
\r
689 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
\r
690 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
\r
691 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
\r
692 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
\r
693 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16
\r
694 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
697 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
\r
698 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
\r
699 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
\r
700 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
\r
701 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8
\r
702 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
704 /*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
705 clock. This is not usually an issue, but designers must be aware.)*/
\r
706 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
\r
707 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
\r
708 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
\r
709 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000
\r
710 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0
\r
711 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
713 /*Clock active signal. Switch to 0 to disable the clock*/
\r
714 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
\r
715 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
\r
716 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
\r
717 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800
\r
718 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24
\r
719 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U
\r
722 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
\r
723 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
\r
724 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
\r
725 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800
\r
726 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16
\r
727 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
730 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
\r
731 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
\r
732 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
\r
733 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800
\r
734 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8
\r
735 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
737 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
738 clock. This is not usually an issue, but designers must be aware.)*/
\r
739 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
\r
740 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
\r
741 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
\r
742 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800
\r
743 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
\r
744 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
746 /*Clock active signal. Switch to 0 to disable the clock*/
\r
747 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL
\r
748 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
\r
749 #undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK
\r
750 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 0x01000F00
\r
751 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24
\r
752 #define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
755 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL
\r
756 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
\r
757 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK
\r
758 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
\r
759 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16
\r
760 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
763 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL
\r
764 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
\r
765 #undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK
\r
766 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
\r
767 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8
\r
768 #define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
770 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
771 clock. This is not usually an issue, but designers must be aware.)*/
\r
772 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL
\r
773 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
\r
774 #undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK
\r
775 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
\r
776 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0
\r
777 #define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
779 /*Clock active signal. Switch to 0 to disable the clock*/
\r
780 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
\r
781 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
\r
782 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
\r
783 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00
\r
784 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24
\r
785 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U
\r
788 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
\r
789 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
\r
790 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
\r
791 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
\r
792 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16
\r
793 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
796 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
\r
797 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
\r
798 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
\r
799 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
\r
800 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8
\r
801 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
803 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
804 clock. This is not usually an issue, but designers must be aware.)*/
\r
805 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
\r
806 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
\r
807 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
\r
808 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
\r
809 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0
\r
810 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
812 /*Clock active signal. Switch to 0 to disable the clock*/
\r
813 #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
\r
814 #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
\r
815 #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
\r
816 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
817 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24
\r
818 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
821 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
\r
822 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
\r
823 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
\r
824 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
825 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16
\r
826 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
829 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
\r
830 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
\r
831 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
\r
832 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
833 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8
\r
834 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
836 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
837 clock. This is not usually an issue, but designers must be aware.)*/
\r
838 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
\r
839 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
\r
840 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
\r
841 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
842 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0
\r
843 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
845 /*Clock active signal. Switch to 0 to disable the clock*/
\r
846 #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
\r
847 #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
\r
848 #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
\r
849 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
850 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24
\r
851 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U
\r
854 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
\r
855 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
\r
856 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
\r
857 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
858 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16
\r
859 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
862 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
\r
863 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
\r
864 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
\r
865 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
866 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8
\r
867 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
869 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
870 clock. This is not usually an issue, but designers must be aware.)*/
\r
871 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
\r
872 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
\r
873 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
\r
874 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
875 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0
\r
876 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
878 /*Clock active signal. Switch to 0 to disable the clock*/
\r
879 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
\r
880 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
\r
881 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
\r
882 #define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500
\r
883 #define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24
\r
884 #define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
887 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
\r
888 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
\r
889 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
\r
890 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
\r
891 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16
\r
892 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
895 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
\r
896 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
\r
897 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
\r
898 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
899 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8
\r
900 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
902 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
903 clock. This is not usually an issue, but designers must be aware.)*/
\r
904 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
\r
905 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
\r
906 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
\r
907 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500
\r
908 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0
\r
909 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
911 /*Clock active signal. Switch to 0 to disable the clock*/
\r
912 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
\r
913 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
\r
914 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
\r
915 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500
\r
916 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24
\r
917 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U
\r
920 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
\r
921 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
\r
922 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
\r
923 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
\r
924 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16
\r
925 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
928 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
\r
929 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
\r
930 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
\r
931 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
932 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8
\r
933 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
935 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
936 clock. This is not usually an issue, but designers must be aware.)*/
\r
937 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
\r
938 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
\r
939 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
\r
940 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500
\r
941 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
\r
942 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
944 /*Clock active signal. Switch to 0 to disable the clock*/
\r
945 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL
\r
946 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
\r
947 #undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK
\r
948 #define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
949 #define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24
\r
950 #define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
953 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL
\r
954 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
\r
955 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK
\r
956 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
957 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16
\r
958 #define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
961 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL
\r
962 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
\r
963 #undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK
\r
964 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
965 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8
\r
966 #define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
968 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
969 clock. This is not usually an issue, but designers must be aware.)*/
\r
970 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL
\r
971 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
\r
972 #undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK
\r
973 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
974 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0
\r
975 #define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
977 /*Clock active signal. Switch to 0 to disable the clock*/
\r
978 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL
\r
979 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
\r
980 #undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK
\r
981 #define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
982 #define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24
\r
983 #define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 0x01000000U
\r
986 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL
\r
987 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
\r
988 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK
\r
989 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
990 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16
\r
991 #define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
994 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL
\r
995 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
\r
996 #undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK
\r
997 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
998 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8
\r
999 #define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1001 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1002 clock. This is not usually an issue, but designers must be aware.)*/
\r
1003 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL
\r
1004 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
\r
1005 #undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK
\r
1006 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
1007 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0
\r
1008 #define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1010 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1011 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL
\r
1012 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
\r
1013 #undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK
\r
1014 #define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
1015 #define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24
\r
1016 #define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1019 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL
\r
1020 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
\r
1021 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK
\r
1022 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
1023 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16
\r
1024 #define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1027 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL
\r
1028 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
\r
1029 #undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK
\r
1030 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
1031 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8
\r
1032 #define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1034 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1035 clock. This is not usually an issue, but designers must be aware.)*/
\r
1036 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL
\r
1037 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
\r
1038 #undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK
\r
1039 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
1040 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0
\r
1041 #define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1043 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1044 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
\r
1045 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
\r
1046 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
\r
1047 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
1048 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24
\r
1049 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1052 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
\r
1053 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
\r
1054 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
\r
1055 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
1056 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16
\r
1057 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1060 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
\r
1061 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
\r
1062 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
\r
1063 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
1064 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8
\r
1065 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1067 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1068 clock. This is not usually an issue, but designers must be aware.)*/
\r
1069 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
\r
1070 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
\r
1071 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
\r
1072 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
1073 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0
\r
1074 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1076 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1077 #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
\r
1078 #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
\r
1079 #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
\r
1080 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600
\r
1081 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24
\r
1082 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U
\r
1085 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
\r
1086 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
\r
1087 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
\r
1088 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600
\r
1089 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8
\r
1090 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1092 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1093 clock. This is not usually an issue, but designers must be aware.)*/
\r
1094 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
\r
1095 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
\r
1096 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
\r
1097 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600
\r
1098 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0
\r
1099 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U
\r
1101 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1102 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
\r
1103 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
\r
1104 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
\r
1105 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500
\r
1106 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24
\r
1107 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U
\r
1110 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
\r
1111 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
\r
1112 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
\r
1113 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500
\r
1114 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
\r
1115 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1117 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1118 clock. This is not usually an issue, but designers must be aware.)*/
\r
1119 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
\r
1120 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
\r
1121 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
\r
1122 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500
\r
1123 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
\r
1124 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
\r
1126 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1127 #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
\r
1128 #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
\r
1129 #undef CRL_APB_PCAP_CTRL_CLKACT_MASK
\r
1130 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500
\r
1131 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24
\r
1132 #define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U
\r
1135 #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
\r
1136 #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
\r
1137 #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
\r
1138 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500
\r
1139 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8
\r
1140 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1142 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1143 clock. This is not usually an issue, but designers must be aware.)*/
\r
1144 #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
\r
1145 #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
\r
1146 #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
\r
1147 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500
\r
1148 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0
\r
1149 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U
\r
1151 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1152 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
\r
1153 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
\r
1154 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
\r
1155 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500
\r
1156 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24
\r
1157 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U
\r
1160 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
\r
1161 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
\r
1162 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
\r
1163 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
1164 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8
\r
1165 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1167 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1168 clock. This is not usually an issue, but designers must be aware.)*/
\r
1169 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
\r
1170 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
\r
1171 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
\r
1172 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500
\r
1173 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0
\r
1174 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
\r
1176 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1177 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
\r
1178 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
\r
1179 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
\r
1180 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800
\r
1181 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24
\r
1182 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U
\r
1185 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
\r
1186 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
\r
1187 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
\r
1188 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
1189 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8
\r
1190 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1192 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1193 clock. This is not usually an issue, but designers must be aware.)*/
\r
1194 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
\r
1195 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
\r
1196 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
\r
1197 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800
\r
1198 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0
\r
1199 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
\r
1201 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1202 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
\r
1203 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
\r
1204 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
\r
1205 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000
\r
1206 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24
\r
1207 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U
\r
1210 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
\r
1211 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
\r
1212 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
\r
1213 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000
\r
1214 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8
\r
1215 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1217 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1218 clock. This is not usually an issue, but designers must be aware.)*/
\r
1219 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
\r
1220 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
\r
1221 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
\r
1222 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000
\r
1223 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
\r
1224 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
\r
1226 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1227 #undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL
\r
1228 #undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
\r
1229 #undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK
\r
1230 #define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 0x00052000
\r
1231 #define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24
\r
1232 #define CRL_APB_NAND_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1235 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL
\r
1236 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
\r
1237 #undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK
\r
1238 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
\r
1239 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16
\r
1240 #define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1243 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL
\r
1244 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
\r
1245 #undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK
\r
1246 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
\r
1247 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8
\r
1248 #define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1250 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1251 clock. This is not usually an issue, but designers must be aware.)*/
\r
1252 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL
\r
1253 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
\r
1254 #undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK
\r
1255 #define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 0x00052000
\r
1256 #define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0
\r
1257 #define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1259 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1260 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
\r
1261 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
\r
1262 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
\r
1263 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000
\r
1264 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24
\r
1265 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1268 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
\r
1269 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
\r
1270 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
\r
1271 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000
\r
1272 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8
\r
1273 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1275 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1276 clock. This is not usually an issue, but designers must be aware.)*/
\r
1277 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
\r
1278 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
\r
1279 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
\r
1280 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000
\r
1281 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0
\r
1282 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1285 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
\r
1286 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
\r
1287 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
\r
1288 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
\r
1289 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
\r
1290 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1293 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
\r
1294 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
\r
1295 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
\r
1296 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
\r
1297 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
\r
1298 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1300 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1301 clock. This is not usually an issue, but designers must be aware.)*/
\r
1302 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
\r
1303 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
\r
1304 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
\r
1305 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800
\r
1306 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
\r
1307 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1309 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1310 #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
\r
1311 #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
\r
1312 #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
\r
1313 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800
\r
1314 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
\r
1315 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1317 /*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
\r
1318 is not usually an issue, but designers must be aware.)*/
\r
1319 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
\r
1320 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
\r
1321 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
\r
1322 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000
\r
1323 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0
\r
1324 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1327 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
\r
1328 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
\r
1329 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
\r
1330 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800
\r
1331 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8
\r
1332 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1334 /*1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
\r
1335 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
1336 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
\r
1337 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
\r
1338 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
\r
1339 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800
\r
1340 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0
\r
1341 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1343 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1344 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
\r
1345 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
\r
1346 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
\r
1347 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800
\r
1348 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24
\r
1349 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1351 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1352 clock. This is not usually an issue, but designers must be aware.)*/
\r
1353 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
\r
1354 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
\r
1355 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
\r
1356 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500
\r
1357 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
\r
1358 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1360 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1361 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
\r
1362 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
\r
1363 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
\r
1364 #define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500
\r
1365 #define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
\r
1366 #define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1369 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
\r
1370 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
\r
1371 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
\r
1372 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
\r
1373 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
\r
1374 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1377 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
\r
1378 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
\r
1379 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
\r
1380 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300
\r
1381 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
\r
1382 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1385 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
\r
1386 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
\r
1387 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
\r
1388 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300
\r
1389 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
\r
1390 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1392 /*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
\r
1393 k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
1394 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
\r
1395 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
\r
1396 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
\r
1397 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300
\r
1398 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0
\r
1399 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1401 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1402 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
\r
1403 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
\r
1404 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
\r
1405 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300
\r
1406 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24
\r
1407 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1410 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
\r
1411 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
\r
1412 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
\r
1413 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300
\r
1414 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16
\r
1415 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1418 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
\r
1419 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
\r
1420 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
\r
1421 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300
\r
1422 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8
\r
1423 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1425 /*000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo
\r
1426 k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
\r
1427 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
\r
1428 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
\r
1429 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
\r
1430 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300
\r
1431 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0
\r
1432 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1434 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1435 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
\r
1436 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
\r
1437 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
\r
1438 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300
\r
1439 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24
\r
1440 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1443 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
\r
1444 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
\r
1445 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
\r
1446 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200
\r
1447 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16
\r
1448 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U
\r
1451 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
\r
1452 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
\r
1453 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
\r
1454 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200
\r
1455 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8
\r
1456 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1458 /*000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1459 lock. This is not usually an issue, but designers must be aware.)*/
\r
1460 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
\r
1461 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
\r
1462 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
\r
1463 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200
\r
1464 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0
\r
1465 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1467 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1468 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
\r
1469 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
\r
1470 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
\r
1471 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200
\r
1472 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24
\r
1473 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1476 #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
\r
1477 #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
\r
1478 #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
\r
1479 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400
\r
1480 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8
\r
1481 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1483 /*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1484 lock. This is not usually an issue, but designers must be aware.)*/
\r
1485 #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
\r
1486 #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
\r
1487 #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
\r
1488 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400
\r
1489 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0
\r
1490 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U
\r
1492 /*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
\r
1493 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
\r
1494 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
\r
1495 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
\r
1496 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400
\r
1497 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25
\r
1498 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U
\r
1500 /*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
\r
1501 to the entire APU*/
\r
1502 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
\r
1503 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
\r
1504 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
\r
1505 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400
\r
1506 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24
\r
1507 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U
\r
1510 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL
\r
1511 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
\r
1512 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK
\r
1513 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500
\r
1514 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8
\r
1515 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1517 /*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1518 clock. This is not usually an issue, but designers must be aware.)*/
\r
1519 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL
\r
1520 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
\r
1521 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK
\r
1522 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500
\r
1523 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0
\r
1524 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U
\r
1526 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1527 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL
\r
1528 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
\r
1529 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK
\r
1530 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500
\r
1531 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24
\r
1532 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U
\r
1535 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
\r
1536 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
\r
1537 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
\r
1538 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500
\r
1539 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8
\r
1540 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1542 /*000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1543 clock. This is not usually an issue, but designers must be aware.)*/
\r
1544 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
\r
1545 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
\r
1546 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
\r
1547 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500
\r
1548 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0
\r
1549 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U
\r
1551 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1552 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
\r
1553 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
\r
1554 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
\r
1555 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500
\r
1556 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24
\r
1557 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U
\r
1560 #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
\r
1561 #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
\r
1562 #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
\r
1563 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
1564 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8
\r
1565 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1567 /*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
\r
1568 s not usually an issue, but designers must be aware.)*/
\r
1569 #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
\r
1570 #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
\r
1571 #undef CRF_APB_DDR_CTRL_SRCSEL_MASK
\r
1572 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500
\r
1573 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0
\r
1574 #define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U
\r
1577 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
\r
1578 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
\r
1579 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
\r
1580 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
\r
1581 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8
\r
1582 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1584 /*000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1585 clock. This is not usually an issue, but designers must be aware.)*/
\r
1586 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
\r
1587 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
\r
1588 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
\r
1589 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500
\r
1590 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0
\r
1591 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1593 /*Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below*/
\r
1594 #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
\r
1595 #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
\r
1596 #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
\r
1597 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500
\r
1598 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24
\r
1599 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1601 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
\r
1602 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
\r
1603 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
\r
1604 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
\r
1605 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500
\r
1606 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25
\r
1607 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U
\r
1609 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock*/
\r
1610 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
\r
1611 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
\r
1612 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
\r
1613 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500
\r
1614 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26
\r
1615 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U
\r
1618 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
\r
1619 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
\r
1620 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
\r
1621 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
1622 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8
\r
1623 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1625 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1626 lock. This is not usually an issue, but designers must be aware.)*/
\r
1627 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
\r
1628 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
\r
1629 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
\r
1630 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
\r
1631 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0
\r
1632 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1634 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1635 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
\r
1636 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
\r
1637 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
\r
1638 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
\r
1639 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24
\r
1640 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1643 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
\r
1644 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
\r
1645 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
\r
1646 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
\r
1647 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8
\r
1648 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1650 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1651 lock. This is not usually an issue, but designers must be aware.)*/
\r
1652 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
\r
1653 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
\r
1654 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
\r
1655 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
\r
1656 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0
\r
1657 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1659 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1660 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
\r
1661 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
\r
1662 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
\r
1663 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
\r
1664 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24
\r
1665 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1668 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
\r
1669 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
\r
1670 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
\r
1671 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400
\r
1672 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8
\r
1673 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1675 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1676 lock. This is not usually an issue, but designers must be aware.)*/
\r
1677 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
\r
1678 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
\r
1679 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
\r
1680 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400
\r
1681 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0
\r
1682 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U
\r
1684 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1685 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
\r
1686 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
\r
1687 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
\r
1688 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400
\r
1689 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24
\r
1690 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U
\r
1693 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
\r
1694 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
\r
1695 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
\r
1696 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800
\r
1697 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8
\r
1698 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1700 /*000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1701 clock. This is not usually an issue, but designers must be aware.)*/
\r
1702 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
\r
1703 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
\r
1704 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
\r
1705 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800
\r
1706 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0
\r
1707 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
\r
1709 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1710 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
\r
1711 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
\r
1712 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
\r
1713 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800
\r
1714 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
\r
1715 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
\r
1718 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL
\r
1719 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
\r
1720 #undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK
\r
1721 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 0x00000800
\r
1722 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8
\r
1723 #define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1725 /*000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1726 clock. This is not usually an issue, but designers must be aware.)*/
\r
1727 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL
\r
1728 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
\r
1729 #undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK
\r
1730 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 0x00000800
\r
1731 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0
\r
1732 #define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 0x00000007U
\r
1734 /*Clock active signal. Switch to 0 to disable the clock*/
\r
1735 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL
\r
1736 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
\r
1737 #undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK
\r
1738 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 0x00000800
\r
1739 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24
\r
1740 #define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 0x01000000U
\r
1743 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
\r
1744 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
\r
1745 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
\r
1746 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00
\r
1747 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8
\r
1748 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U
\r
1750 /*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
\r
1751 lock. This is not usually an issue, but designers must be aware.)*/
\r
1752 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
\r
1753 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
\r
1754 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
\r
1755 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00
\r
1756 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0
\r
1757 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U
\r
1758 #undef IOU_SLCR_MIO_PIN_0_OFFSET
\r
1759 #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000
\r
1760 #undef IOU_SLCR_MIO_PIN_1_OFFSET
\r
1761 #define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004
\r
1762 #undef IOU_SLCR_MIO_PIN_2_OFFSET
\r
1763 #define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008
\r
1764 #undef IOU_SLCR_MIO_PIN_3_OFFSET
\r
1765 #define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C
\r
1766 #undef IOU_SLCR_MIO_PIN_4_OFFSET
\r
1767 #define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010
\r
1768 #undef IOU_SLCR_MIO_PIN_5_OFFSET
\r
1769 #define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014
\r
1770 #undef IOU_SLCR_MIO_PIN_6_OFFSET
\r
1771 #define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018
\r
1772 #undef IOU_SLCR_MIO_PIN_7_OFFSET
\r
1773 #define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C
\r
1774 #undef IOU_SLCR_MIO_PIN_8_OFFSET
\r
1775 #define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020
\r
1776 #undef IOU_SLCR_MIO_PIN_9_OFFSET
\r
1777 #define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024
\r
1778 #undef IOU_SLCR_MIO_PIN_10_OFFSET
\r
1779 #define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028
\r
1780 #undef IOU_SLCR_MIO_PIN_11_OFFSET
\r
1781 #define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C
\r
1782 #undef IOU_SLCR_MIO_PIN_12_OFFSET
\r
1783 #define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030
\r
1784 #undef IOU_SLCR_MIO_PIN_13_OFFSET
\r
1785 #define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034
\r
1786 #undef IOU_SLCR_MIO_PIN_14_OFFSET
\r
1787 #define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038
\r
1788 #undef IOU_SLCR_MIO_PIN_15_OFFSET
\r
1789 #define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C
\r
1790 #undef IOU_SLCR_MIO_PIN_16_OFFSET
\r
1791 #define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040
\r
1792 #undef IOU_SLCR_MIO_PIN_17_OFFSET
\r
1793 #define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044
\r
1794 #undef IOU_SLCR_MIO_PIN_18_OFFSET
\r
1795 #define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048
\r
1796 #undef IOU_SLCR_MIO_PIN_19_OFFSET
\r
1797 #define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C
\r
1798 #undef IOU_SLCR_MIO_PIN_20_OFFSET
\r
1799 #define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050
\r
1800 #undef IOU_SLCR_MIO_PIN_21_OFFSET
\r
1801 #define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054
\r
1802 #undef IOU_SLCR_MIO_PIN_22_OFFSET
\r
1803 #define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058
\r
1804 #undef IOU_SLCR_MIO_PIN_23_OFFSET
\r
1805 #define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C
\r
1806 #undef IOU_SLCR_MIO_PIN_24_OFFSET
\r
1807 #define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060
\r
1808 #undef IOU_SLCR_MIO_PIN_25_OFFSET
\r
1809 #define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064
\r
1810 #undef IOU_SLCR_MIO_PIN_26_OFFSET
\r
1811 #define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068
\r
1812 #undef IOU_SLCR_MIO_PIN_27_OFFSET
\r
1813 #define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C
\r
1814 #undef IOU_SLCR_MIO_PIN_28_OFFSET
\r
1815 #define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070
\r
1816 #undef IOU_SLCR_MIO_PIN_29_OFFSET
\r
1817 #define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074
\r
1818 #undef IOU_SLCR_MIO_PIN_30_OFFSET
\r
1819 #define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078
\r
1820 #undef IOU_SLCR_MIO_PIN_31_OFFSET
\r
1821 #define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C
\r
1822 #undef IOU_SLCR_MIO_PIN_32_OFFSET
\r
1823 #define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080
\r
1824 #undef IOU_SLCR_MIO_PIN_33_OFFSET
\r
1825 #define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084
\r
1826 #undef IOU_SLCR_MIO_PIN_34_OFFSET
\r
1827 #define IOU_SLCR_MIO_PIN_34_OFFSET 0XFF180088
\r
1828 #undef IOU_SLCR_MIO_PIN_35_OFFSET
\r
1829 #define IOU_SLCR_MIO_PIN_35_OFFSET 0XFF18008C
\r
1830 #undef IOU_SLCR_MIO_PIN_36_OFFSET
\r
1831 #define IOU_SLCR_MIO_PIN_36_OFFSET 0XFF180090
\r
1832 #undef IOU_SLCR_MIO_PIN_37_OFFSET
\r
1833 #define IOU_SLCR_MIO_PIN_37_OFFSET 0XFF180094
\r
1834 #undef IOU_SLCR_MIO_PIN_38_OFFSET
\r
1835 #define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098
\r
1836 #undef IOU_SLCR_MIO_PIN_39_OFFSET
\r
1837 #define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C
\r
1838 #undef IOU_SLCR_MIO_PIN_40_OFFSET
\r
1839 #define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0
\r
1840 #undef IOU_SLCR_MIO_PIN_41_OFFSET
\r
1841 #define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4
\r
1842 #undef IOU_SLCR_MIO_PIN_42_OFFSET
\r
1843 #define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8
\r
1844 #undef IOU_SLCR_MIO_PIN_43_OFFSET
\r
1845 #define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC
\r
1846 #undef IOU_SLCR_MIO_PIN_44_OFFSET
\r
1847 #define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0
\r
1848 #undef IOU_SLCR_MIO_PIN_45_OFFSET
\r
1849 #define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4
\r
1850 #undef IOU_SLCR_MIO_PIN_46_OFFSET
\r
1851 #define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8
\r
1852 #undef IOU_SLCR_MIO_PIN_47_OFFSET
\r
1853 #define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC
\r
1854 #undef IOU_SLCR_MIO_PIN_48_OFFSET
\r
1855 #define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0
\r
1856 #undef IOU_SLCR_MIO_PIN_49_OFFSET
\r
1857 #define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4
\r
1858 #undef IOU_SLCR_MIO_PIN_50_OFFSET
\r
1859 #define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8
\r
1860 #undef IOU_SLCR_MIO_PIN_51_OFFSET
\r
1861 #define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC
\r
1862 #undef IOU_SLCR_MIO_PIN_52_OFFSET
\r
1863 #define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0
\r
1864 #undef IOU_SLCR_MIO_PIN_53_OFFSET
\r
1865 #define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4
\r
1866 #undef IOU_SLCR_MIO_PIN_54_OFFSET
\r
1867 #define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8
\r
1868 #undef IOU_SLCR_MIO_PIN_55_OFFSET
\r
1869 #define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC
\r
1870 #undef IOU_SLCR_MIO_PIN_56_OFFSET
\r
1871 #define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0
\r
1872 #undef IOU_SLCR_MIO_PIN_57_OFFSET
\r
1873 #define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4
\r
1874 #undef IOU_SLCR_MIO_PIN_58_OFFSET
\r
1875 #define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8
\r
1876 #undef IOU_SLCR_MIO_PIN_59_OFFSET
\r
1877 #define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC
\r
1878 #undef IOU_SLCR_MIO_PIN_60_OFFSET
\r
1879 #define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0
\r
1880 #undef IOU_SLCR_MIO_PIN_61_OFFSET
\r
1881 #define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4
\r
1882 #undef IOU_SLCR_MIO_PIN_62_OFFSET
\r
1883 #define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8
\r
1884 #undef IOU_SLCR_MIO_PIN_63_OFFSET
\r
1885 #define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC
\r
1886 #undef IOU_SLCR_MIO_PIN_64_OFFSET
\r
1887 #define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100
\r
1888 #undef IOU_SLCR_MIO_PIN_65_OFFSET
\r
1889 #define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104
\r
1890 #undef IOU_SLCR_MIO_PIN_66_OFFSET
\r
1891 #define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108
\r
1892 #undef IOU_SLCR_MIO_PIN_67_OFFSET
\r
1893 #define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C
\r
1894 #undef IOU_SLCR_MIO_PIN_68_OFFSET
\r
1895 #define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110
\r
1896 #undef IOU_SLCR_MIO_PIN_69_OFFSET
\r
1897 #define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114
\r
1898 #undef IOU_SLCR_MIO_PIN_70_OFFSET
\r
1899 #define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118
\r
1900 #undef IOU_SLCR_MIO_PIN_71_OFFSET
\r
1901 #define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C
\r
1902 #undef IOU_SLCR_MIO_PIN_72_OFFSET
\r
1903 #define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120
\r
1904 #undef IOU_SLCR_MIO_PIN_73_OFFSET
\r
1905 #define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124
\r
1906 #undef IOU_SLCR_MIO_PIN_74_OFFSET
\r
1907 #define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128
\r
1908 #undef IOU_SLCR_MIO_PIN_75_OFFSET
\r
1909 #define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C
\r
1910 #undef IOU_SLCR_MIO_PIN_76_OFFSET
\r
1911 #define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130
\r
1912 #undef IOU_SLCR_MIO_PIN_77_OFFSET
\r
1913 #define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134
\r
1914 #undef IOU_SLCR_MIO_MST_TRI0_OFFSET
\r
1915 #define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204
\r
1916 #undef IOU_SLCR_MIO_MST_TRI1_OFFSET
\r
1917 #define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208
\r
1918 #undef IOU_SLCR_MIO_MST_TRI2_OFFSET
\r
1919 #define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C
\r
1920 #undef IOU_SLCR_MIO_LOOPBACK_OFFSET
\r
1921 #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200
\r
1923 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
\r
1924 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
\r
1925 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
\r
1926 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
\r
1927 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000
\r
1928 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1
\r
1929 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U
\r
1931 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
1932 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
\r
1933 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
\r
1934 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
\r
1935 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000
\r
1936 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2
\r
1937 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U
\r
1939 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
\r
1940 t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
\r
1941 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
\r
1942 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
\r
1943 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
\r
1944 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000
\r
1945 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3
\r
1946 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U
\r
1948 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
\r
1949 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
1950 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
\r
1951 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
\r
1952 lk- (Trace Port Clock)*/
\r
1953 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
\r
1954 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
\r
1955 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
\r
1956 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000
\r
1957 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5
\r
1958 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U
\r
1960 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
\r
1962 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
\r
1963 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
\r
1964 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
\r
1965 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000
\r
1966 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1
\r
1967 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U
\r
1969 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
1970 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
\r
1971 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
\r
1972 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
\r
1973 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000
\r
1974 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2
\r
1975 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U
\r
1977 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
\r
1978 t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
\r
1979 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
\r
1980 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
\r
1981 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
\r
1982 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000
\r
1983 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3
\r
1984 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U
\r
1986 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
\r
1987 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
1988 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
\r
1989 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
\r
1991 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
\r
1992 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
\r
1993 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
\r
1994 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000
\r
1995 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5
\r
1996 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U
\r
1998 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
\r
1999 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
\r
2000 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
\r
2001 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
\r
2002 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000
\r
2003 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1
\r
2004 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U
\r
2006 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2007 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
\r
2008 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
\r
2009 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
\r
2010 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000
\r
2011 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2
\r
2012 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U
\r
2014 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
\r
2015 t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
\r
2016 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
\r
2017 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
\r
2018 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
\r
2019 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000
\r
2020 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3
\r
2021 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U
\r
2023 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
\r
2024 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
2025 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
\r
2026 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
\r
2027 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
\r
2028 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
\r
2029 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
\r
2030 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000
\r
2031 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5
\r
2032 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U
\r
2034 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
\r
2035 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
\r
2036 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
\r
2037 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
\r
2038 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000
\r
2039 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1
\r
2040 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U
\r
2042 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2043 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
\r
2044 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
\r
2045 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
\r
2046 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000
\r
2047 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2
\r
2048 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U
\r
2050 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
\r
2051 t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
\r
2052 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
\r
2053 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
\r
2054 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
\r
2055 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000
\r
2056 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3
\r
2057 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U
\r
2059 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
\r
2060 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
2061 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
\r
2062 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
\r
2063 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
\r
2064 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
\r
2065 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
\r
2066 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
\r
2067 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000
\r
2068 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5
\r
2069 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U
\r
2071 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
\r
2073 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
\r
2074 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
\r
2075 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
\r
2076 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000
\r
2077 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1
\r
2078 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U
\r
2080 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2081 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
\r
2082 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
\r
2083 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
\r
2084 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000
\r
2085 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2
\r
2086 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U
\r
2088 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
\r
2089 t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
\r
2090 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
\r
2091 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
\r
2092 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
\r
2093 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000
\r
2094 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3
\r
2095 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U
\r
2097 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
\r
2098 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
2099 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
\r
2100 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
\r
2101 utput, tracedq[2]- (Trace Port Databus)*/
\r
2102 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
\r
2103 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
\r
2104 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
\r
2105 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000
\r
2106 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5
\r
2107 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U
\r
2109 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
\r
2110 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
\r
2111 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
\r
2112 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
\r
2113 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000
\r
2114 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1
\r
2115 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U
\r
2117 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2118 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
\r
2119 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
\r
2120 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
\r
2121 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000
\r
2122 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2
\r
2123 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U
\r
2125 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
\r
2126 t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
\r
2127 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
\r
2128 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
\r
2129 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
\r
2130 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000
\r
2131 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3
\r
2132 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U
\r
2134 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
\r
2135 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
2136 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
\r
2137 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
\r
2138 trace, Output, tracedq[3]- (Trace Port Databus)*/
\r
2139 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
\r
2140 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
\r
2141 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
\r
2142 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000
\r
2143 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5
\r
2144 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U
\r
2146 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
\r
2147 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL
\r
2148 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
\r
2149 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK
\r
2150 #define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000
\r
2151 #define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1
\r
2152 #define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U
\r
2154 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2155 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL
\r
2156 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
\r
2157 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK
\r
2158 #define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000
\r
2159 #define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2
\r
2160 #define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U
\r
2162 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
\r
2163 t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
\r
2164 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL
\r
2165 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
\r
2166 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK
\r
2167 #define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000
\r
2168 #define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3
\r
2169 #define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U
\r
2171 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
\r
2172 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
2173 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
\r
2174 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
\r
2175 Output, tracedq[4]- (Trace Port Databus)*/
\r
2176 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL
\r
2177 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
\r
2178 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK
\r
2179 #define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000
\r
2180 #define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5
\r
2181 #define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U
\r
2183 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
\r
2184 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL
\r
2185 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
\r
2186 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK
\r
2187 #define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000
\r
2188 #define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1
\r
2189 #define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U
\r
2191 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2192 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL
\r
2193 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
\r
2194 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK
\r
2195 #define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000
\r
2196 #define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2
\r
2197 #define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U
\r
2199 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
\r
2200 t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
\r
2201 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL
\r
2202 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
\r
2203 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK
\r
2204 #define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000
\r
2205 #define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3
\r
2206 #define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U
\r
2208 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
\r
2209 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
2210 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
\r
2211 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
\r
2212 racedq[5]- (Trace Port Databus)*/
\r
2213 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL
\r
2214 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
\r
2215 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK
\r
2216 #define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000
\r
2217 #define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5
\r
2218 #define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U
\r
2220 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
\r
2221 [0]- (QSPI Upper Databus)*/
\r
2222 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL
\r
2223 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
\r
2224 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK
\r
2225 #define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000
\r
2226 #define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1
\r
2227 #define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U
\r
2229 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
2230 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL
\r
2231 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
\r
2232 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK
\r
2233 #define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000
\r
2234 #define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2
\r
2235 #define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U
\r
2237 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
\r
2238 t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
\r
2239 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL
\r
2240 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
\r
2241 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK
\r
2242 #define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000
\r
2243 #define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3
\r
2244 #define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U
\r
2246 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
\r
2247 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
2248 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
\r
2249 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
\r
2250 ce Port Databus)*/
\r
2251 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL
\r
2252 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
\r
2253 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK
\r
2254 #define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000
\r
2255 #define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5
\r
2256 #define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U
\r
2258 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
\r
2259 [1]- (QSPI Upper Databus)*/
\r
2260 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL
\r
2261 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
\r
2262 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK
\r
2263 #define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000
\r
2264 #define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1
\r
2265 #define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U
\r
2267 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
\r
2268 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL
\r
2269 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
\r
2270 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK
\r
2271 #define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000
\r
2272 #define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2
\r
2273 #define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U
\r
2275 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
\r
2276 t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
\r
2277 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL
\r
2278 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
\r
2279 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK
\r
2280 #define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000
\r
2281 #define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3
\r
2282 #define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U
\r
2284 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
\r
2285 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
2286 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
\r
2287 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
\r
2288 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
\r
2289 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL
\r
2290 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
\r
2291 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK
\r
2292 #define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000
\r
2293 #define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5
\r
2294 #define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U
\r
2296 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
\r
2297 [2]- (QSPI Upper Databus)*/
\r
2298 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL
\r
2299 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
\r
2300 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK
\r
2301 #define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000
\r
2302 #define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1
\r
2303 #define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U
\r
2305 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
\r
2306 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL
\r
2307 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
\r
2308 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK
\r
2309 #define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000
\r
2310 #define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2
\r
2311 #define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U
\r
2313 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
\r
2314 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
\r
2315 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL
\r
2316 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
\r
2317 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK
\r
2318 #define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000
\r
2319 #define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3
\r
2320 #define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U
\r
2322 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
\r
2323 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
2324 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
\r
2325 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
\r
2326 t, tracedq[8]- (Trace Port Databus)*/
\r
2327 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL
\r
2328 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
\r
2329 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK
\r
2330 #define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000
\r
2331 #define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5
\r
2332 #define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U
\r
2334 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
\r
2335 [3]- (QSPI Upper Databus)*/
\r
2336 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL
\r
2337 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
\r
2338 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK
\r
2339 #define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000
\r
2340 #define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1
\r
2341 #define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U
\r
2343 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
\r
2344 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL
\r
2345 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
\r
2346 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK
\r
2347 #define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000
\r
2348 #define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2
\r
2349 #define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U
\r
2351 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
\r
2352 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
\r
2353 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL
\r
2354 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
\r
2355 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK
\r
2356 #define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000
\r
2357 #define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3
\r
2358 #define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U
\r
2360 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
\r
2361 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
2362 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
\r
2363 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
\r
2364 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
\r
2365 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL
\r
2366 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
\r
2367 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK
\r
2368 #define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000
\r
2369 #define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5
\r
2370 #define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U
\r
2372 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
\r
2373 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL
\r
2374 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
\r
2375 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK
\r
2376 #define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000
\r
2377 #define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1
\r
2378 #define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U
\r
2380 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
\r
2382 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL
\r
2383 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
\r
2384 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK
\r
2385 #define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000
\r
2386 #define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2
\r
2387 #define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U
\r
2389 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
\r
2390 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
\r
2391 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL
\r
2392 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
\r
2393 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK
\r
2394 #define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000
\r
2395 #define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3
\r
2396 #define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U
\r
2398 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
\r
2399 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
2400 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
\r
2401 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
\r
2402 dq[10]- (Trace Port Databus)*/
\r
2403 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL
\r
2404 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
\r
2405 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK
\r
2406 #define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000
\r
2407 #define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5
\r
2408 #define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U
\r
2410 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2411 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL
\r
2412 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
\r
2413 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK
\r
2414 #define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000
\r
2415 #define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1
\r
2416 #define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U
\r
2418 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
\r
2419 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL
\r
2420 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
\r
2421 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK
\r
2422 #define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000
\r
2423 #define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2
\r
2424 #define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U
\r
2426 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
\r
2427 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
\r
2429 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL
\r
2430 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
\r
2431 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK
\r
2432 #define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000
\r
2433 #define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3
\r
2434 #define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U
\r
2436 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
\r
2437 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
2438 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
\r
2439 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
\r
2441 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL
\r
2442 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
\r
2443 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK
\r
2444 #define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000
\r
2445 #define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5
\r
2446 #define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U
\r
2448 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2449 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL
\r
2450 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
\r
2451 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK
\r
2452 #define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000
\r
2453 #define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1
\r
2454 #define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U
\r
2456 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
\r
2457 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL
\r
2458 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
\r
2459 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK
\r
2460 #define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000
\r
2461 #define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2
\r
2462 #define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U
\r
2464 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
\r
2465 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
\r
2467 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL
\r
2468 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
\r
2469 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK
\r
2470 #define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000
\r
2471 #define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3
\r
2472 #define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U
\r
2474 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
\r
2475 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
2476 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
\r
2477 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
\r
2478 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL
\r
2479 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
\r
2480 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK
\r
2481 #define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000
\r
2482 #define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5
\r
2483 #define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U
\r
2485 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2486 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL
\r
2487 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
\r
2488 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK
\r
2489 #define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000
\r
2490 #define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1
\r
2491 #define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U
\r
2493 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
\r
2494 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL
\r
2495 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
\r
2496 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK
\r
2497 #define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000
\r
2498 #define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2
\r
2499 #define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U
\r
2501 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
\r
2502 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
\r
2504 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL
\r
2505 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
\r
2506 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK
\r
2507 #define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000
\r
2508 #define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3
\r
2509 #define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U
\r
2511 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
\r
2512 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
2513 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
\r
2514 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
\r
2515 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
\r
2516 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL
\r
2517 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
\r
2518 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK
\r
2519 #define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000
\r
2520 #define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5
\r
2521 #define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U
\r
2523 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2524 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
\r
2525 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
\r
2526 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
\r
2527 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000
\r
2528 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1
\r
2529 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U
\r
2531 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
\r
2533 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
\r
2534 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
\r
2535 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
\r
2536 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000
\r
2537 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2
\r
2538 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U
\r
2540 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
\r
2541 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
\r
2543 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
\r
2544 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
\r
2545 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
\r
2546 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000
\r
2547 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3
\r
2548 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U
\r
2550 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
\r
2551 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
2552 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
\r
2553 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
\r
2554 Output, tracedq[14]- (Trace Port Databus)*/
\r
2555 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
\r
2556 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
\r
2557 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
\r
2558 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000
\r
2559 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5
\r
2560 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U
\r
2562 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2563 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
\r
2564 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
\r
2565 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
\r
2566 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000
\r
2567 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1
\r
2568 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U
\r
2570 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
\r
2572 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
\r
2573 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
\r
2574 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
\r
2575 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000
\r
2576 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2
\r
2577 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U
\r
2579 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
\r
2580 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
\r
2582 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
\r
2583 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
\r
2584 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
\r
2585 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000
\r
2586 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3
\r
2587 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U
\r
2589 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
\r
2590 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
2591 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
\r
2592 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
\r
2593 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
\r
2594 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
\r
2595 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
\r
2596 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
\r
2597 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000
\r
2598 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5
\r
2599 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U
\r
2601 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2602 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
\r
2603 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
\r
2604 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
\r
2605 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000
\r
2606 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1
\r
2607 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U
\r
2609 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
\r
2611 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
\r
2612 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
\r
2613 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
\r
2614 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000
\r
2615 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2
\r
2616 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U
\r
2618 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
\r
2619 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
\r
2620 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2621 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
\r
2622 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
\r
2623 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
\r
2624 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000
\r
2625 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3
\r
2626 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U
\r
2628 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
\r
2629 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
2630 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
\r
2631 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
\r
2632 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
\r
2633 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
\r
2634 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
\r
2635 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000
\r
2636 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5
\r
2637 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U
\r
2639 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2640 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
\r
2641 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
\r
2642 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
\r
2643 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000
\r
2644 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1
\r
2645 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U
\r
2647 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
\r
2649 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
\r
2650 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
\r
2651 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
\r
2652 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000
\r
2653 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2
\r
2654 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U
\r
2656 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
\r
2657 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
\r
2658 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2659 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
\r
2660 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
\r
2661 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
\r
2662 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000
\r
2663 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3
\r
2664 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U
\r
2666 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
\r
2667 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
2668 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
\r
2669 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
\r
2670 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
\r
2671 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
\r
2672 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
\r
2673 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000
\r
2674 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5
\r
2675 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U
\r
2677 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2678 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
\r
2679 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
\r
2680 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
\r
2681 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000
\r
2682 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1
\r
2683 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U
\r
2685 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
\r
2687 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
\r
2688 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
\r
2689 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
\r
2690 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000
\r
2691 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2
\r
2692 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U
\r
2694 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
\r
2695 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
\r
2696 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2697 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
\r
2698 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
\r
2699 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
\r
2700 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000
\r
2701 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3
\r
2702 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U
\r
2704 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
\r
2705 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
2706 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
\r
2707 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
\r
2708 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
\r
2709 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
\r
2710 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
\r
2711 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000
\r
2712 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5
\r
2713 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U
\r
2715 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2716 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
\r
2717 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
\r
2718 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
\r
2719 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000
\r
2720 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1
\r
2721 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U
\r
2723 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
\r
2725 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
\r
2726 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
\r
2727 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
\r
2728 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000
\r
2729 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2
\r
2730 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U
\r
2732 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
\r
2733 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
\r
2734 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2735 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
\r
2736 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
\r
2737 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
\r
2738 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000
\r
2739 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3
\r
2740 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U
\r
2742 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
\r
2743 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
2744 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
\r
2745 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
\r
2746 UART receiver serial input) 7= Not Used*/
\r
2747 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
\r
2748 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
\r
2749 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
\r
2750 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000
\r
2751 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5
\r
2752 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U
\r
2754 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2755 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL
\r
2756 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
\r
2757 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK
\r
2758 #define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000
\r
2759 #define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1
\r
2760 #define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U
\r
2762 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
\r
2763 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL
\r
2764 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
\r
2765 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK
\r
2766 #define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000
\r
2767 #define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2
\r
2768 #define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U
\r
2770 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
\r
2771 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2772 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL
\r
2773 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
\r
2774 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK
\r
2775 #define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000
\r
2776 #define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3
\r
2777 #define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U
\r
2779 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
\r
2780 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
2781 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
\r
2782 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
\r
2784 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL
\r
2785 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
\r
2786 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK
\r
2787 #define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000
\r
2788 #define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5
\r
2789 #define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U
\r
2791 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2792 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL
\r
2793 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
\r
2794 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK
\r
2795 #define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000
\r
2796 #define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1
\r
2797 #define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U
\r
2799 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
\r
2801 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL
\r
2802 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
\r
2803 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK
\r
2804 #define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000
\r
2805 #define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2
\r
2806 #define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U
\r
2808 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
\r
2809 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
\r
2811 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL
\r
2812 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
\r
2813 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK
\r
2814 #define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000
\r
2815 #define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3
\r
2816 #define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U
\r
2818 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
\r
2819 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
2820 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
\r
2821 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
\r
2822 tput) 7= Not Used*/
\r
2823 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL
\r
2824 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
\r
2825 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK
\r
2826 #define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000
\r
2827 #define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5
\r
2828 #define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U
\r
2830 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2831 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
\r
2832 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
\r
2833 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
\r
2834 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000
\r
2835 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1
\r
2836 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U
\r
2838 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
\r
2840 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
\r
2841 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
\r
2842 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
\r
2843 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000
\r
2844 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2
\r
2845 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U
\r
2847 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
\r
2848 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
\r
2850 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
\r
2851 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
\r
2852 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
\r
2853 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000
\r
2854 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3
\r
2855 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U
\r
2857 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
\r
2858 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
2859 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
\r
2860 Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
\r
2861 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
\r
2862 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
\r
2863 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
\r
2864 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000
\r
2865 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5
\r
2866 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U
\r
2868 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
2869 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
\r
2870 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
\r
2871 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
\r
2872 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000
\r
2873 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1
\r
2874 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U
\r
2876 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
\r
2877 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
\r
2878 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
\r
2879 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
\r
2880 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000
\r
2881 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2
\r
2882 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U
\r
2884 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
\r
2885 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
\r
2887 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
\r
2888 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
\r
2889 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
\r
2890 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000
\r
2891 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3
\r
2892 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U
\r
2894 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
\r
2895 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
2896 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
\r
2897 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
\r
2898 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
\r
2899 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
\r
2900 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
\r
2901 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000
\r
2902 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5
\r
2903 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U
\r
2905 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
\r
2906 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL
\r
2907 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
\r
2908 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK
\r
2909 #define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000
\r
2910 #define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1
\r
2911 #define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U
\r
2913 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
\r
2914 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL
\r
2915 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
\r
2916 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK
\r
2917 #define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000
\r
2918 #define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2
\r
2919 #define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U
\r
2921 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
\r
2922 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
2923 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL
\r
2924 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
\r
2925 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK
\r
2926 #define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000
\r
2927 #define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3
\r
2928 #define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U
\r
2930 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
\r
2931 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
2932 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
\r
2933 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
\r
2934 Trace Port Databus)*/
\r
2935 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL
\r
2936 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
\r
2937 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK
\r
2938 #define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000
\r
2939 #define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5
\r
2940 #define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U
\r
2942 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
\r
2943 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
\r
2944 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
\r
2945 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
\r
2946 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000
\r
2947 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1
\r
2948 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U
\r
2950 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
\r
2951 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
\r
2952 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
\r
2953 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
\r
2954 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000
\r
2955 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2
\r
2956 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U
\r
2958 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
\r
2959 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
\r
2960 t, dp_aux_data_out- (Dp Aux Data)*/
\r
2961 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
\r
2962 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
\r
2963 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
\r
2964 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000
\r
2965 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3
\r
2966 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U
\r
2968 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
\r
2969 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
2970 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
\r
2971 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
\r
2973 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
\r
2974 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
\r
2975 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
\r
2976 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000
\r
2977 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5
\r
2978 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U
\r
2980 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
\r
2981 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
\r
2982 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
\r
2983 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
\r
2984 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000
\r
2985 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1
\r
2986 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U
\r
2988 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
\r
2989 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
\r
2990 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
\r
2991 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
\r
2992 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000
\r
2993 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2
\r
2994 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U
\r
2996 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
\r
2997 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
\r
2998 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
\r
2999 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
\r
3000 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
\r
3001 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000
\r
3002 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3
\r
3003 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U
\r
3005 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
\r
3006 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
3007 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
\r
3008 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
\r
3009 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
\r
3010 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
\r
3011 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
\r
3012 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000
\r
3013 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5
\r
3014 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U
\r
3016 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
\r
3017 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
\r
3018 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
\r
3019 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
\r
3020 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000
\r
3021 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1
\r
3022 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U
\r
3024 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3025 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
\r
3026 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
\r
3027 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
\r
3028 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000
\r
3029 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2
\r
3030 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U
\r
3032 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
\r
3033 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
\r
3034 t, dp_aux_data_out- (Dp Aux Data)*/
\r
3035 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
\r
3036 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
\r
3037 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
\r
3038 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000
\r
3039 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3
\r
3040 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U
\r
3042 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
\r
3043 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
3044 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
\r
3045 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
\r
3046 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
\r
3047 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
\r
3048 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
\r
3049 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
\r
3050 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000
\r
3051 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5
\r
3052 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U
\r
3054 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
\r
3055 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
\r
3056 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
\r
3057 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
\r
3058 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000
\r
3059 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1
\r
3060 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U
\r
3062 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3063 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
\r
3064 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
\r
3065 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
\r
3066 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000
\r
3067 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2
\r
3068 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U
\r
3070 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
\r
3071 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
\r
3072 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
\r
3073 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
\r
3074 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
\r
3075 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000
\r
3076 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3
\r
3077 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U
\r
3079 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
\r
3080 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
3081 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
\r
3082 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
\r
3083 tracedq[8]- (Trace Port Databus)*/
\r
3084 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
\r
3085 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
\r
3086 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
\r
3087 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000
\r
3088 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5
\r
3089 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U
\r
3091 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
\r
3092 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL
\r
3093 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
\r
3094 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK
\r
3095 #define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000
\r
3096 #define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1
\r
3097 #define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U
\r
3099 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3100 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL
\r
3101 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
\r
3102 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK
\r
3103 #define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000
\r
3104 #define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2
\r
3105 #define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U
\r
3107 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
\r
3108 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
3109 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL
\r
3110 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
\r
3111 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK
\r
3112 #define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000
\r
3113 #define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3
\r
3114 #define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U
\r
3116 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
\r
3117 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
3118 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
\r
3119 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
\r
3120 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
\r
3121 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL
\r
3122 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
\r
3123 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK
\r
3124 #define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000
\r
3125 #define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5
\r
3126 #define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U
\r
3128 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
\r
3129 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL
\r
3130 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
\r
3131 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK
\r
3132 #define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000
\r
3133 #define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1
\r
3134 #define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U
\r
3136 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
\r
3138 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL
\r
3139 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
\r
3140 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK
\r
3141 #define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000
\r
3142 #define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2
\r
3143 #define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U
\r
3145 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc
\r
3146 n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
3147 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL
\r
3148 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
\r
3149 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK
\r
3150 #define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000
\r
3151 #define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3
\r
3152 #define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U
\r
3154 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
\r
3155 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
3156 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
\r
3157 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
\r
3158 race, Output, tracedq[10]- (Trace Port Databus)*/
\r
3159 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL
\r
3160 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
\r
3161 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK
\r
3162 #define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000
\r
3163 #define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5
\r
3164 #define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U
\r
3166 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
\r
3167 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL
\r
3168 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
\r
3169 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK
\r
3170 #define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000
\r
3171 #define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1
\r
3172 #define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U
\r
3174 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3175 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL
\r
3176 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
\r
3177 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK
\r
3178 #define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000
\r
3179 #define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2
\r
3180 #define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U
\r
3182 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc
\r
3183 n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
\r
3184 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL
\r
3185 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
\r
3186 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK
\r
3187 #define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000
\r
3188 #define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3
\r
3189 #define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U
\r
3191 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
\r
3192 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
3193 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
\r
3194 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
\r
3195 [11]- (Trace Port Databus)*/
\r
3196 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL
\r
3197 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
\r
3198 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK
\r
3199 #define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000
\r
3200 #define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5
\r
3201 #define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U
\r
3203 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
\r
3204 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL
\r
3205 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
\r
3206 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK
\r
3207 #define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000
\r
3208 #define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1
\r
3209 #define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U
\r
3211 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3212 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL
\r
3213 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
\r
3214 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK
\r
3215 #define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000
\r
3216 #define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2
\r
3217 #define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U
\r
3219 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc
\r
3220 n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
\r
3221 t, dp_aux_data_out- (Dp Aux Data)*/
\r
3222 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL
\r
3223 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
\r
3224 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK
\r
3225 #define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000
\r
3226 #define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3
\r
3227 #define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U
\r
3229 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
\r
3230 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
3231 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
\r
3232 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
\r
3234 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL
\r
3235 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
\r
3236 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK
\r
3237 #define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000
\r
3238 #define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5
\r
3239 #define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U
\r
3241 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
\r
3242 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL
\r
3243 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
\r
3244 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK
\r
3245 #define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000
\r
3246 #define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1
\r
3247 #define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U
\r
3249 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3250 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL
\r
3251 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
\r
3252 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK
\r
3253 #define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000
\r
3254 #define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2
\r
3255 #define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U
\r
3257 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc
\r
3258 n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
\r
3259 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL
\r
3260 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
\r
3261 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK
\r
3262 #define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000
\r
3263 #define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3
\r
3264 #define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U
\r
3266 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
\r
3267 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
3268 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
\r
3269 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
\r
3270 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
\r
3271 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL
\r
3272 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
\r
3273 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK
\r
3274 #define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000
\r
3275 #define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5
\r
3276 #define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U
\r
3278 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
\r
3279 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL
\r
3280 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
\r
3281 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK
\r
3282 #define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000
\r
3283 #define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1
\r
3284 #define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U
\r
3286 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3287 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL
\r
3288 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
\r
3289 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK
\r
3290 #define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000
\r
3291 #define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2
\r
3292 #define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U
\r
3294 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc
\r
3295 n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
\r
3296 t, dp_aux_data_out- (Dp Aux Data)*/
\r
3297 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL
\r
3298 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
\r
3299 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK
\r
3300 #define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000
\r
3301 #define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3
\r
3302 #define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U
\r
3304 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
\r
3305 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
3306 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
\r
3307 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
\r
3308 Output, tracedq[14]- (Trace Port Databus)*/
\r
3309 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL
\r
3310 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
\r
3311 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK
\r
3312 #define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000
\r
3313 #define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5
\r
3314 #define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U
\r
3316 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
\r
3317 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL
\r
3318 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
\r
3319 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK
\r
3320 #define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000
\r
3321 #define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1
\r
3322 #define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U
\r
3324 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
\r
3325 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL
\r
3326 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
\r
3327 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK
\r
3328 #define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000
\r
3329 #define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2
\r
3330 #define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U
\r
3332 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc
\r
3333 n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
\r
3334 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL
\r
3335 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
\r
3336 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK
\r
3337 #define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000
\r
3338 #define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3
\r
3339 #define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U
\r
3341 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
\r
3342 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
3343 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
\r
3344 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
\r
3345 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
\r
3346 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL
\r
3347 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
\r
3348 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK
\r
3349 #define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000
\r
3350 #define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5
\r
3351 #define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U
\r
3353 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
\r
3354 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL
\r
3355 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
\r
3356 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK
\r
3357 #define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000
\r
3358 #define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1
\r
3359 #define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U
\r
3361 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3362 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL
\r
3363 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
\r
3364 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK
\r
3365 #define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000
\r
3366 #define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2
\r
3367 #define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U
\r
3369 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
\r
3370 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL
\r
3371 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
\r
3372 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK
\r
3373 #define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000
\r
3374 #define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3
\r
3375 #define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U
\r
3377 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
\r
3378 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
3379 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
\r
3380 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
\r
3381 (Trace Port Clock)*/
\r
3382 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL
\r
3383 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
\r
3384 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK
\r
3385 #define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000
\r
3386 #define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5
\r
3387 #define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U
\r
3389 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
\r
3390 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL
\r
3391 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
\r
3392 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
\r
3393 #define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000
\r
3394 #define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1
\r
3395 #define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U
\r
3397 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3398 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL
\r
3399 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
\r
3400 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK
\r
3401 #define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000
\r
3402 #define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2
\r
3403 #define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U
\r
3405 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
\r
3406 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
\r
3407 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL
\r
3408 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
\r
3409 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK
\r
3410 #define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000
\r
3411 #define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3
\r
3412 #define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U
\r
3414 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
\r
3415 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
3416 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
\r
3417 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
\r
3419 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL
\r
3420 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
\r
3421 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK
\r
3422 #define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000
\r
3423 #define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5
\r
3424 #define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U
\r
3426 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
\r
3427 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL
\r
3428 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
\r
3429 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK
\r
3430 #define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000
\r
3431 #define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1
\r
3432 #define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U
\r
3434 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3435 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL
\r
3436 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
\r
3437 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK
\r
3438 #define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000
\r
3439 #define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2
\r
3440 #define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U
\r
3442 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
\r
3443 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
\r
3444 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL
\r
3445 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
\r
3446 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK
\r
3447 #define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000
\r
3448 #define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3
\r
3449 #define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U
\r
3451 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
\r
3452 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
3453 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
\r
3454 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
\r
3455 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL
\r
3456 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
\r
3457 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK
\r
3458 #define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000
\r
3459 #define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5
\r
3460 #define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U
\r
3462 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
\r
3463 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL
\r
3464 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
\r
3465 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK
\r
3466 #define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000
\r
3467 #define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1
\r
3468 #define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U
\r
3470 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3471 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL
\r
3472 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
\r
3473 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK
\r
3474 #define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000
\r
3475 #define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2
\r
3476 #define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U
\r
3478 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
\r
3479 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
\r
3480 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL
\r
3481 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
\r
3482 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK
\r
3483 #define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000
\r
3484 #define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3
\r
3485 #define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U
\r
3487 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
\r
3488 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
3489 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
\r
3490 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
\r
3491 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
\r
3492 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL
\r
3493 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
\r
3494 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK
\r
3495 #define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000
\r
3496 #define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5
\r
3497 #define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U
\r
3499 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
\r
3500 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL
\r
3501 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
\r
3502 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK
\r
3503 #define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000
\r
3504 #define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1
\r
3505 #define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U
\r
3507 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3508 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL
\r
3509 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
\r
3510 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK
\r
3511 #define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000
\r
3512 #define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2
\r
3513 #define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U
\r
3515 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
\r
3516 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
\r
3517 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL
\r
3518 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
\r
3519 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK
\r
3520 #define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000
\r
3521 #define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3
\r
3522 #define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U
\r
3524 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
\r
3525 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
3526 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
\r
3527 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
\r
3528 t, tracedq[2]- (Trace Port Databus)*/
\r
3529 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL
\r
3530 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
\r
3531 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK
\r
3532 #define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000
\r
3533 #define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5
\r
3534 #define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U
\r
3536 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
\r
3537 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL
\r
3538 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
\r
3539 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK
\r
3540 #define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000
\r
3541 #define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1
\r
3542 #define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U
\r
3544 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3545 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL
\r
3546 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
\r
3547 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK
\r
3548 #define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000
\r
3549 #define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2
\r
3550 #define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U
\r
3552 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
\r
3553 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
\r
3554 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL
\r
3555 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
\r
3556 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK
\r
3557 #define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000
\r
3558 #define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3
\r
3559 #define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U
\r
3561 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
\r
3562 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
3563 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
\r
3564 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
\r
3565 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
\r
3566 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL
\r
3567 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
\r
3568 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK
\r
3569 #define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000
\r
3570 #define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5
\r
3571 #define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U
\r
3573 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
\r
3574 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL
\r
3575 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
\r
3576 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK
\r
3577 #define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000
\r
3578 #define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1
\r
3579 #define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U
\r
3581 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3582 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL
\r
3583 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
\r
3584 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK
\r
3585 #define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000
\r
3586 #define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2
\r
3587 #define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U
\r
3589 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
\r
3590 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
\r
3591 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL
\r
3592 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
\r
3593 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK
\r
3594 #define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000
\r
3595 #define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3
\r
3596 #define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U
\r
3598 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
\r
3599 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
3600 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
\r
3601 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
\r
3603 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL
\r
3604 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
\r
3605 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK
\r
3606 #define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000
\r
3607 #define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5
\r
3608 #define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U
\r
3610 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
\r
3611 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
\r
3612 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
\r
3613 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
\r
3614 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000
\r
3615 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1
\r
3616 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U
\r
3618 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3619 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
\r
3620 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
\r
3621 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
\r
3622 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000
\r
3623 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2
\r
3624 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U
\r
3626 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
\r
3627 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
\r
3628 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
\r
3629 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
\r
3630 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
\r
3631 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000
\r
3632 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3
\r
3633 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U
\r
3635 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
\r
3636 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
3637 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
\r
3638 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
\r
3639 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
\r
3640 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
\r
3641 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
\r
3642 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000
\r
3643 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5
\r
3644 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U
\r
3646 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
\r
3647 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
\r
3648 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
\r
3649 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
\r
3650 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000
\r
3651 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1
\r
3652 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U
\r
3654 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3655 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
\r
3656 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
\r
3657 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
\r
3658 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000
\r
3659 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2
\r
3660 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U
\r
3662 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
\r
3663 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
\r
3664 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
\r
3665 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
\r
3666 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
\r
3667 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000
\r
3668 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3
\r
3669 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U
\r
3671 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
\r
3672 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
3673 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
\r
3674 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
\r
3675 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
\r
3676 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
\r
3677 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
\r
3678 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000
\r
3679 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5
\r
3680 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U
\r
3682 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
\r
3683 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
\r
3684 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
\r
3685 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
\r
3686 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000
\r
3687 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1
\r
3688 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U
\r
3690 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3691 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
\r
3692 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
\r
3693 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
\r
3694 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000
\r
3695 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2
\r
3696 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U
\r
3698 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
\r
3699 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
\r
3700 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
\r
3701 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
\r
3702 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
\r
3703 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000
\r
3704 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3
\r
3705 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U
\r
3707 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
\r
3708 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
3709 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
\r
3710 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
\r
3711 (UART transmitter serial output) 7= Not Used*/
\r
3712 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
\r
3713 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
\r
3714 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
\r
3715 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000
\r
3716 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5
\r
3717 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U
\r
3719 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
\r
3720 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
\r
3721 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
\r
3722 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
\r
3723 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000
\r
3724 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1
\r
3725 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U
\r
3727 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3728 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
\r
3729 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
\r
3730 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
\r
3731 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000
\r
3732 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2
\r
3733 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U
\r
3735 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
\r
3736 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
\r
3737 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
\r
3738 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
\r
3739 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
\r
3740 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000
\r
3741 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3
\r
3742 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U
\r
3744 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
\r
3745 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
3746 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
\r
3747 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
\r
3749 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
\r
3750 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
\r
3751 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
\r
3752 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000
\r
3753 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5
\r
3754 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U
\r
3756 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
\r
3757 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
\r
3758 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
\r
3759 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
\r
3760 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000
\r
3761 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1
\r
3762 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U
\r
3764 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3765 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
\r
3766 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
\r
3767 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
\r
3768 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000
\r
3769 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2
\r
3770 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U
\r
3772 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
\r
3773 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
\r
3774 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
\r
3775 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
\r
3776 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
\r
3777 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000
\r
3778 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3
\r
3779 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U
\r
3781 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
\r
3782 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
3783 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
\r
3784 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
\r
3786 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
\r
3787 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
\r
3788 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
\r
3789 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000
\r
3790 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5
\r
3791 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U
\r
3793 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
\r
3794 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
\r
3795 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
\r
3796 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
\r
3797 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000
\r
3798 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1
\r
3799 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U
\r
3801 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3802 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
\r
3803 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
\r
3804 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
\r
3805 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000
\r
3806 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2
\r
3807 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U
\r
3809 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
\r
3810 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
\r
3811 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
\r
3812 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
\r
3813 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
\r
3814 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000
\r
3815 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3
\r
3816 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U
\r
3818 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
\r
3819 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
3820 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
\r
3821 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
\r
3822 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
\r
3823 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
\r
3824 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
\r
3825 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000
\r
3826 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5
\r
3827 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U
\r
3829 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
\r
3830 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
\r
3831 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
\r
3832 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
\r
3833 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000
\r
3834 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1
\r
3835 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U
\r
3837 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
3838 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
\r
3839 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
\r
3840 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
\r
3841 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000
\r
3842 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2
\r
3843 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U
\r
3845 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
\r
3846 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
\r
3847 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
\r
3848 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
\r
3849 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000
\r
3850 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3
\r
3851 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U
\r
3853 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
\r
3854 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
3855 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
\r
3856 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
\r
3857 serial output) 7= Not Used*/
\r
3858 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
\r
3859 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
\r
3860 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
\r
3861 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000
\r
3862 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5
\r
3863 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U
\r
3865 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
\r
3866 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
\r
3867 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
\r
3868 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
\r
3869 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000
\r
3870 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1
\r
3871 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U
\r
3873 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
\r
3874 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
\r
3875 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
\r
3876 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
\r
3877 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000
\r
3878 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2
\r
3879 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U
\r
3881 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
3882 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
\r
3883 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
\r
3884 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
\r
3885 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000
\r
3886 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3
\r
3887 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U
\r
3889 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
\r
3890 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
3891 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
\r
3892 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
\r
3893 lk- (Trace Port Clock)*/
\r
3894 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
\r
3895 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
\r
3896 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
\r
3897 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000
\r
3898 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5
\r
3899 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U
\r
3901 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
\r
3902 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
\r
3903 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
\r
3904 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
\r
3905 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000
\r
3906 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1
\r
3907 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U
\r
3909 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
\r
3910 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
\r
3911 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
\r
3912 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
\r
3913 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000
\r
3914 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2
\r
3915 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U
\r
3917 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
3918 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
\r
3919 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
\r
3920 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
\r
3921 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000
\r
3922 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3
\r
3923 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U
\r
3925 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
\r
3926 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
3927 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
\r
3928 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
\r
3930 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
\r
3931 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
\r
3932 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
\r
3933 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000
\r
3934 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5
\r
3935 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U
\r
3937 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
\r
3938 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
\r
3939 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
\r
3940 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
\r
3941 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000
\r
3942 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1
\r
3943 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U
\r
3945 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
3946 ata[2]- (ULPI data bus)*/
\r
3947 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
\r
3948 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
\r
3949 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
\r
3950 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000
\r
3951 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2
\r
3952 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U
\r
3954 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
3955 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
\r
3956 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
\r
3957 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
\r
3958 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000
\r
3959 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3
\r
3960 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U
\r
3962 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
\r
3963 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
3964 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
\r
3965 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
\r
3966 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
\r
3967 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
\r
3968 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
\r
3969 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000
\r
3970 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5
\r
3971 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U
\r
3973 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
\r
3974 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
\r
3975 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
\r
3976 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
\r
3977 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000
\r
3978 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1
\r
3979 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U
\r
3981 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
\r
3982 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
\r
3983 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
\r
3984 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
\r
3985 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000
\r
3986 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2
\r
3987 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U
\r
3989 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
3990 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
\r
3991 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
\r
3992 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
\r
3993 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000
\r
3994 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3
\r
3995 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U
\r
3997 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
\r
3998 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
3999 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
\r
4000 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
\r
4001 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
\r
4002 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
\r
4003 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
\r
4004 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
\r
4005 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000
\r
4006 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5
\r
4007 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U
\r
4009 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
\r
4010 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
\r
4011 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
\r
4012 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
\r
4013 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000
\r
4014 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1
\r
4015 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U
\r
4017 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4018 ata[0]- (ULPI data bus)*/
\r
4019 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
\r
4020 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
\r
4021 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
\r
4022 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000
\r
4023 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2
\r
4024 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U
\r
4026 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4027 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
\r
4028 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
\r
4029 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
\r
4030 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000
\r
4031 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3
\r
4032 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U
\r
4034 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
\r
4035 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
4036 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
\r
4037 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
\r
4038 utput, tracedq[2]- (Trace Port Databus)*/
\r
4039 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
\r
4040 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
\r
4041 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
\r
4042 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000
\r
4043 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5
\r
4044 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U
\r
4046 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
\r
4047 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
\r
4048 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
\r
4049 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
\r
4050 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000
\r
4051 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1
\r
4052 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U
\r
4054 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4055 ata[1]- (ULPI data bus)*/
\r
4056 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
\r
4057 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
\r
4058 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
\r
4059 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000
\r
4060 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2
\r
4061 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U
\r
4063 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4064 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
\r
4065 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
\r
4066 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
\r
4067 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000
\r
4068 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3
\r
4069 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U
\r
4071 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
\r
4072 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
4073 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
\r
4074 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
\r
4075 trace, Output, tracedq[3]- (Trace Port Databus)*/
\r
4076 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
\r
4077 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
\r
4078 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
\r
4079 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000
\r
4080 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5
\r
4081 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U
\r
4083 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
\r
4084 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
\r
4085 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
\r
4086 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
\r
4087 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000
\r
4088 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1
\r
4089 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U
\r
4091 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
\r
4092 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
\r
4093 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
\r
4094 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
\r
4095 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000
\r
4096 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2
\r
4097 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U
\r
4099 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4100 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
\r
4101 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
\r
4102 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
\r
4103 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000
\r
4104 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3
\r
4105 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U
\r
4107 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
\r
4108 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
\r
4109 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
\r
4110 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
\r
4111 Trace Port Databus)*/
\r
4112 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
\r
4113 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
\r
4114 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
\r
4115 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000
\r
4116 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5
\r
4117 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U
\r
4119 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
\r
4120 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
\r
4121 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
\r
4122 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
\r
4123 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000
\r
4124 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1
\r
4125 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U
\r
4127 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4128 ata[3]- (ULPI data bus)*/
\r
4129 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
\r
4130 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
\r
4131 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
\r
4132 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000
\r
4133 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2
\r
4134 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U
\r
4136 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4137 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
\r
4138 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
\r
4139 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
\r
4140 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000
\r
4141 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3
\r
4142 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U
\r
4144 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
\r
4145 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
\r
4146 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
\r
4147 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
\r
4149 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
\r
4150 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
\r
4151 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
\r
4152 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000
\r
4153 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5
\r
4154 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U
\r
4156 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
\r
4157 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
\r
4158 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
\r
4159 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
\r
4160 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000
\r
4161 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1
\r
4162 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U
\r
4164 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4165 ata[4]- (ULPI data bus)*/
\r
4166 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
\r
4167 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
\r
4168 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
\r
4169 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000
\r
4170 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2
\r
4171 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U
\r
4173 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4174 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
\r
4175 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
\r
4176 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
\r
4177 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000
\r
4178 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3
\r
4179 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U
\r
4181 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
\r
4182 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
\r
4183 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
\r
4184 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
\r
4185 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
\r
4186 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
\r
4187 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
\r
4188 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000
\r
4189 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5
\r
4190 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U
\r
4192 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
\r
4193 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
\r
4194 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
\r
4195 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
\r
4196 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000
\r
4197 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1
\r
4198 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U
\r
4200 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4201 ata[5]- (ULPI data bus)*/
\r
4202 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
\r
4203 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
\r
4204 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
\r
4205 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000
\r
4206 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2
\r
4207 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U
\r
4209 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4210 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
\r
4211 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
\r
4212 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
\r
4213 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000
\r
4214 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3
\r
4215 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U
\r
4217 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
\r
4218 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
\r
4219 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
\r
4220 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
\r
4221 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
\r
4222 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
\r
4223 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
\r
4224 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
\r
4225 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000
\r
4226 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5
\r
4227 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U
\r
4229 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
\r
4230 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
\r
4231 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
\r
4232 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
\r
4233 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000
\r
4234 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1
\r
4235 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U
\r
4237 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4238 ata[6]- (ULPI data bus)*/
\r
4239 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
\r
4240 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
\r
4241 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
\r
4242 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000
\r
4243 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2
\r
4244 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U
\r
4246 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4247 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
\r
4248 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
\r
4249 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
\r
4250 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000
\r
4251 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3
\r
4252 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U
\r
4254 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
\r
4255 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
4256 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
\r
4257 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
\r
4258 t, tracedq[8]- (Trace Port Databus)*/
\r
4259 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
\r
4260 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
\r
4261 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
\r
4262 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000
\r
4263 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5
\r
4264 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U
\r
4266 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
\r
4267 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
\r
4268 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
\r
4269 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
\r
4270 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000
\r
4271 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1
\r
4272 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U
\r
4274 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
\r
4275 ata[7]- (ULPI data bus)*/
\r
4276 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
\r
4277 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
\r
4278 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
\r
4279 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000
\r
4280 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2
\r
4281 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U
\r
4283 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
\r
4284 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
\r
4285 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
\r
4286 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
\r
4287 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000
\r
4288 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3
\r
4289 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U
\r
4291 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
\r
4292 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
4293 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
\r
4294 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
\r
4295 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
\r
4296 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
\r
4297 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
\r
4298 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
\r
4299 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000
\r
4300 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5
\r
4301 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U
\r
4303 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
\r
4304 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
\r
4305 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
\r
4306 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
\r
4307 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000
\r
4308 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1
\r
4309 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U
\r
4311 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
\r
4312 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
\r
4313 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
\r
4314 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
\r
4315 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000
\r
4316 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2
\r
4317 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U
\r
4319 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
\r
4320 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
\r
4321 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
\r
4322 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
\r
4323 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000
\r
4324 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3
\r
4325 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U
\r
4327 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
\r
4328 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
4329 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
\r
4330 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
\r
4331 trace, Output, tracedq[10]- (Trace Port Databus)*/
\r
4332 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
\r
4333 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
\r
4334 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
\r
4335 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000
\r
4336 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5
\r
4337 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U
\r
4339 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
\r
4340 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
\r
4341 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
\r
4342 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
\r
4343 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000
\r
4344 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1
\r
4345 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U
\r
4347 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
\r
4348 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
\r
4349 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
\r
4350 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
\r
4351 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000
\r
4352 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2
\r
4353 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U
\r
4355 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
\r
4356 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
\r
4357 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
\r
4358 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
\r
4359 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000
\r
4360 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3
\r
4361 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U
\r
4363 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
\r
4364 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
4365 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
\r
4366 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
\r
4367 dq[11]- (Trace Port Databus)*/
\r
4368 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
\r
4369 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
\r
4370 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
\r
4371 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000
\r
4372 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5
\r
4373 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U
\r
4375 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
\r
4376 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
\r
4377 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
\r
4378 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
\r
4379 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000
\r
4380 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1
\r
4381 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U
\r
4383 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4384 ata[2]- (ULPI data bus)*/
\r
4385 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
\r
4386 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
\r
4387 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
\r
4388 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000
\r
4389 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2
\r
4390 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U
\r
4392 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
\r
4393 Indicator) 2= Not Used 3= Not Used*/
\r
4394 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
\r
4395 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
\r
4396 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
\r
4397 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000
\r
4398 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3
\r
4399 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U
\r
4401 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
\r
4402 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
4403 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
\r
4404 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
\r
4406 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
\r
4407 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
\r
4408 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
\r
4409 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000
\r
4410 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5
\r
4411 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U
\r
4413 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
\r
4414 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
\r
4415 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
\r
4416 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
\r
4417 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000
\r
4418 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1
\r
4419 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U
\r
4421 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
\r
4422 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
\r
4423 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
\r
4424 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
\r
4425 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000
\r
4426 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2
\r
4427 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U
\r
4429 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
\r
4430 bit Data bus) 2= Not Used 3= Not Used*/
\r
4431 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
\r
4432 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
\r
4433 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
\r
4434 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000
\r
4435 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3
\r
4436 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U
\r
4438 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
\r
4439 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
4440 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
\r
4441 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
\r
4442 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
\r
4443 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
\r
4444 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
\r
4445 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
\r
4446 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000
\r
4447 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5
\r
4448 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U
\r
4450 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
\r
4451 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
\r
4452 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
\r
4453 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
\r
4454 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000
\r
4455 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1
\r
4456 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U
\r
4458 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4459 ata[0]- (ULPI data bus)*/
\r
4460 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
\r
4461 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
\r
4462 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
\r
4463 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000
\r
4464 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2
\r
4465 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U
\r
4467 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
\r
4468 bit Data bus) 2= Not Used 3= Not Used*/
\r
4469 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
\r
4470 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
\r
4471 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
\r
4472 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000
\r
4473 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3
\r
4474 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U
\r
4476 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
\r
4477 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
4478 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
\r
4479 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
\r
4480 Output, tracedq[14]- (Trace Port Databus)*/
\r
4481 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
\r
4482 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
\r
4483 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
\r
4484 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000
\r
4485 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5
\r
4486 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U
\r
4488 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
\r
4489 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
\r
4490 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
\r
4491 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
\r
4492 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000
\r
4493 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1
\r
4494 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U
\r
4496 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4497 ata[1]- (ULPI data bus)*/
\r
4498 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
\r
4499 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
\r
4500 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
\r
4501 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000
\r
4502 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2
\r
4503 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U
\r
4505 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
\r
4506 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
\r
4507 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
\r
4508 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
\r
4509 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
\r
4510 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000
\r
4511 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3
\r
4512 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U
\r
4514 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
\r
4515 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
4516 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
\r
4517 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
\r
4518 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
\r
4519 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
\r
4520 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
\r
4521 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
\r
4522 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000
\r
4523 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5
\r
4524 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U
\r
4526 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
\r
4527 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
\r
4528 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
\r
4529 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
\r
4530 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000
\r
4531 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1
\r
4532 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U
\r
4534 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
\r
4535 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
\r
4536 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
\r
4537 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
\r
4538 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000
\r
4539 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2
\r
4540 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U
\r
4542 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
\r
4543 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
\r
4544 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
\r
4545 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
\r
4546 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
\r
4547 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000
\r
4548 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3
\r
4549 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U
\r
4551 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
\r
4552 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
4553 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
\r
4554 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
\r
4556 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
\r
4557 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
\r
4558 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
\r
4559 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000
\r
4560 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5
\r
4561 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U
\r
4563 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
\r
4564 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
\r
4565 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
\r
4566 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
\r
4567 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000
\r
4568 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1
\r
4569 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U
\r
4571 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4572 ata[3]- (ULPI data bus)*/
\r
4573 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
\r
4574 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
\r
4575 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
\r
4576 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000
\r
4577 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2
\r
4578 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U
\r
4580 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
\r
4581 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
\r
4582 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
\r
4583 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
\r
4584 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
\r
4585 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000
\r
4586 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3
\r
4587 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U
\r
4589 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
\r
4590 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
4591 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
\r
4592 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
\r
4593 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
\r
4594 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
\r
4595 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
\r
4596 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000
\r
4597 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5
\r
4598 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U
\r
4600 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
\r
4601 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
\r
4602 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
\r
4603 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
\r
4604 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000
\r
4605 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1
\r
4606 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U
\r
4608 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4609 ata[4]- (ULPI data bus)*/
\r
4610 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
\r
4611 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
\r
4612 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
\r
4613 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000
\r
4614 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2
\r
4615 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U
\r
4617 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
\r
4618 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
\r
4619 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
\r
4620 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
\r
4621 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
\r
4622 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000
\r
4623 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3
\r
4624 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U
\r
4626 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
\r
4627 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
4628 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
\r
4629 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
\r
4630 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
\r
4631 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
\r
4632 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
\r
4633 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000
\r
4634 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5
\r
4635 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U
\r
4637 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
\r
4638 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
\r
4639 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
\r
4640 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
\r
4641 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000
\r
4642 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1
\r
4643 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U
\r
4645 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4646 ata[5]- (ULPI data bus)*/
\r
4647 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
\r
4648 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
\r
4649 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
\r
4650 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000
\r
4651 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2
\r
4652 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U
\r
4654 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
\r
4655 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
\r
4656 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
\r
4657 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
\r
4658 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
\r
4659 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000
\r
4660 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3
\r
4661 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U
\r
4663 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
\r
4664 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
4665 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
\r
4666 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
\r
4667 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
\r
4668 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
\r
4669 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
\r
4670 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000
\r
4671 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5
\r
4672 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U
\r
4674 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
\r
4675 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
\r
4676 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
\r
4677 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
\r
4678 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000
\r
4679 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1
\r
4680 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U
\r
4682 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4683 ata[6]- (ULPI data bus)*/
\r
4684 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
\r
4685 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
\r
4686 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
\r
4687 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000
\r
4688 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2
\r
4689 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U
\r
4691 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
\r
4692 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
\r
4693 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
\r
4694 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
\r
4695 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
\r
4696 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000
\r
4697 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3
\r
4698 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U
\r
4700 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
\r
4701 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
\r
4702 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
\r
4703 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
\r
4704 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
\r
4705 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
\r
4706 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
\r
4707 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000
\r
4708 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5
\r
4709 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U
\r
4711 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
\r
4712 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
\r
4713 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
\r
4714 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
\r
4715 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000
\r
4716 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1
\r
4717 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U
\r
4719 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
\r
4720 ata[7]- (ULPI data bus)*/
\r
4721 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
\r
4722 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
\r
4723 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
\r
4724 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000
\r
4725 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2
\r
4726 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U
\r
4728 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
\r
4729 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
\r
4730 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
\r
4731 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
\r
4732 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
\r
4733 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000
\r
4734 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3
\r
4735 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U
\r
4737 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
\r
4738 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
\r
4739 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
\r
4740 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
\r
4741 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
\r
4742 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
\r
4743 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
\r
4744 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000
\r
4745 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5
\r
4746 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U
\r
4748 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
4749 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
\r
4750 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
\r
4751 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
\r
4752 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000
\r
4753 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1
\r
4754 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U
\r
4756 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
4757 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
\r
4758 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
\r
4759 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
\r
4760 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000
\r
4761 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2
\r
4762 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U
\r
4764 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
\r
4765 _clk_out- (SDSDIO clock) 3= Not Used*/
\r
4766 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
\r
4767 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
\r
4768 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
\r
4769 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000
\r
4770 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3
\r
4771 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U
\r
4773 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
\r
4774 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
\r
4775 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
\r
4776 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
\r
4777 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
\r
4778 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
\r
4779 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
\r
4780 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000
\r
4781 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5
\r
4782 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U
\r
4784 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
\r
4785 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
\r
4786 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
\r
4787 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
\r
4788 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000
\r
4789 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1
\r
4790 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U
\r
4792 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
\r
4793 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
\r
4794 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
\r
4795 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
\r
4796 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000
\r
4797 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2
\r
4798 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U
\r
4800 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
\r
4801 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
\r
4802 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
\r
4803 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
\r
4804 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000
\r
4805 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3
\r
4806 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U
\r
4808 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
\r
4809 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
\r
4810 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
\r
4811 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
\r
4812 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
\r
4813 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
\r
4814 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
\r
4815 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
\r
4816 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000
\r
4817 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5
\r
4818 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U
\r
4820 /*Master Tri-state Enable for pin 0, active high*/
\r
4821 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
\r
4822 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
\r
4823 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
\r
4824 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF
\r
4825 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0
\r
4826 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U
\r
4828 /*Master Tri-state Enable for pin 1, active high*/
\r
4829 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
\r
4830 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
\r
4831 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
\r
4832 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF
\r
4833 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1
\r
4834 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U
\r
4836 /*Master Tri-state Enable for pin 2, active high*/
\r
4837 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
\r
4838 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
\r
4839 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
\r
4840 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF
\r
4841 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2
\r
4842 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U
\r
4844 /*Master Tri-state Enable for pin 3, active high*/
\r
4845 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
\r
4846 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
\r
4847 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
\r
4848 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF
\r
4849 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3
\r
4850 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U
\r
4852 /*Master Tri-state Enable for pin 4, active high*/
\r
4853 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
\r
4854 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
\r
4855 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
\r
4856 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF
\r
4857 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4
\r
4858 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U
\r
4860 /*Master Tri-state Enable for pin 5, active high*/
\r
4861 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
\r
4862 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
\r
4863 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
\r
4864 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF
\r
4865 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5
\r
4866 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U
\r
4868 /*Master Tri-state Enable for pin 6, active high*/
\r
4869 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL
\r
4870 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
\r
4871 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK
\r
4872 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF
\r
4873 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6
\r
4874 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U
\r
4876 /*Master Tri-state Enable for pin 7, active high*/
\r
4877 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL
\r
4878 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
\r
4879 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK
\r
4880 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF
\r
4881 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7
\r
4882 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U
\r
4884 /*Master Tri-state Enable for pin 8, active high*/
\r
4885 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL
\r
4886 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
\r
4887 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK
\r
4888 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF
\r
4889 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8
\r
4890 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U
\r
4892 /*Master Tri-state Enable for pin 9, active high*/
\r
4893 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL
\r
4894 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
\r
4895 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK
\r
4896 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF
\r
4897 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9
\r
4898 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U
\r
4900 /*Master Tri-state Enable for pin 10, active high*/
\r
4901 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL
\r
4902 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
\r
4903 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK
\r
4904 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF
\r
4905 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10
\r
4906 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U
\r
4908 /*Master Tri-state Enable for pin 11, active high*/
\r
4909 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL
\r
4910 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
\r
4911 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK
\r
4912 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF
\r
4913 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11
\r
4914 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U
\r
4916 /*Master Tri-state Enable for pin 12, active high*/
\r
4917 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL
\r
4918 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
\r
4919 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK
\r
4920 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF
\r
4921 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12
\r
4922 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U
\r
4924 /*Master Tri-state Enable for pin 13, active high*/
\r
4925 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL
\r
4926 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
\r
4927 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK
\r
4928 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF
\r
4929 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13
\r
4930 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U
\r
4932 /*Master Tri-state Enable for pin 14, active high*/
\r
4933 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL
\r
4934 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
\r
4935 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK
\r
4936 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF
\r
4937 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14
\r
4938 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U
\r
4940 /*Master Tri-state Enable for pin 15, active high*/
\r
4941 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL
\r
4942 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
\r
4943 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK
\r
4944 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF
\r
4945 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15
\r
4946 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U
\r
4948 /*Master Tri-state Enable for pin 16, active high*/
\r
4949 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
\r
4950 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
\r
4951 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
\r
4952 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF
\r
4953 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16
\r
4954 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U
\r
4956 /*Master Tri-state Enable for pin 17, active high*/
\r
4957 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
\r
4958 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
\r
4959 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
\r
4960 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF
\r
4961 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17
\r
4962 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U
\r
4964 /*Master Tri-state Enable for pin 18, active high*/
\r
4965 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
\r
4966 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
\r
4967 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
\r
4968 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF
\r
4969 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18
\r
4970 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U
\r
4972 /*Master Tri-state Enable for pin 19, active high*/
\r
4973 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
\r
4974 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
\r
4975 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
\r
4976 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF
\r
4977 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19
\r
4978 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U
\r
4980 /*Master Tri-state Enable for pin 20, active high*/
\r
4981 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
\r
4982 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
\r
4983 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
\r
4984 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF
\r
4985 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20
\r
4986 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U
\r
4988 /*Master Tri-state Enable for pin 21, active high*/
\r
4989 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
\r
4990 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
\r
4991 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
\r
4992 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF
\r
4993 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21
\r
4994 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U
\r
4996 /*Master Tri-state Enable for pin 22, active high*/
\r
4997 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL
\r
4998 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
\r
4999 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK
\r
5000 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF
\r
5001 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22
\r
5002 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U
\r
5004 /*Master Tri-state Enable for pin 23, active high*/
\r
5005 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL
\r
5006 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
\r
5007 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK
\r
5008 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF
\r
5009 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23
\r
5010 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U
\r
5012 /*Master Tri-state Enable for pin 24, active high*/
\r
5013 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
\r
5014 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
\r
5015 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
\r
5016 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF
\r
5017 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24
\r
5018 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U
\r
5020 /*Master Tri-state Enable for pin 25, active high*/
\r
5021 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
\r
5022 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
\r
5023 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
\r
5024 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF
\r
5025 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25
\r
5026 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U
\r
5028 /*Master Tri-state Enable for pin 26, active high*/
\r
5029 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL
\r
5030 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
\r
5031 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK
\r
5032 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF
\r
5033 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26
\r
5034 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U
\r
5036 /*Master Tri-state Enable for pin 27, active high*/
\r
5037 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
\r
5038 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
\r
5039 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
\r
5040 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF
\r
5041 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27
\r
5042 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U
\r
5044 /*Master Tri-state Enable for pin 28, active high*/
\r
5045 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
\r
5046 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
\r
5047 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
\r
5048 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF
\r
5049 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28
\r
5050 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U
\r
5052 /*Master Tri-state Enable for pin 29, active high*/
\r
5053 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
\r
5054 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
\r
5055 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
\r
5056 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF
\r
5057 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29
\r
5058 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U
\r
5060 /*Master Tri-state Enable for pin 30, active high*/
\r
5061 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
\r
5062 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
\r
5063 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
\r
5064 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF
\r
5065 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30
\r
5066 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U
\r
5068 /*Master Tri-state Enable for pin 31, active high*/
\r
5069 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL
\r
5070 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
\r
5071 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK
\r
5072 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF
\r
5073 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31
\r
5074 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U
\r
5076 /*Master Tri-state Enable for pin 32, active high*/
\r
5077 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL
\r
5078 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
\r
5079 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK
\r
5080 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF
\r
5081 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0
\r
5082 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U
\r
5084 /*Master Tri-state Enable for pin 33, active high*/
\r
5085 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL
\r
5086 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
\r
5087 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK
\r
5088 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF
\r
5089 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1
\r
5090 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U
\r
5092 /*Master Tri-state Enable for pin 34, active high*/
\r
5093 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL
\r
5094 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
\r
5095 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK
\r
5096 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF
\r
5097 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2
\r
5098 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U
\r
5100 /*Master Tri-state Enable for pin 35, active high*/
\r
5101 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL
\r
5102 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
\r
5103 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK
\r
5104 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF
\r
5105 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3
\r
5106 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U
\r
5108 /*Master Tri-state Enable for pin 36, active high*/
\r
5109 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL
\r
5110 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
\r
5111 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK
\r
5112 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF
\r
5113 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4
\r
5114 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U
\r
5116 /*Master Tri-state Enable for pin 37, active high*/
\r
5117 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL
\r
5118 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
\r
5119 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK
\r
5120 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF
\r
5121 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5
\r
5122 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U
\r
5124 /*Master Tri-state Enable for pin 38, active high*/
\r
5125 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL
\r
5126 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
\r
5127 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK
\r
5128 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF
\r
5129 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6
\r
5130 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U
\r
5132 /*Master Tri-state Enable for pin 39, active high*/
\r
5133 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL
\r
5134 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
\r
5135 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK
\r
5136 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF
\r
5137 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7
\r
5138 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U
\r
5140 /*Master Tri-state Enable for pin 40, active high*/
\r
5141 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL
\r
5142 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
\r
5143 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK
\r
5144 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF
\r
5145 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8
\r
5146 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U
\r
5148 /*Master Tri-state Enable for pin 41, active high*/
\r
5149 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL
\r
5150 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
\r
5151 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK
\r
5152 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF
\r
5153 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9
\r
5154 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U
\r
5156 /*Master Tri-state Enable for pin 42, active high*/
\r
5157 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL
\r
5158 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
\r
5159 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK
\r
5160 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF
\r
5161 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10
\r
5162 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U
\r
5164 /*Master Tri-state Enable for pin 43, active high*/
\r
5165 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL
\r
5166 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
\r
5167 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK
\r
5168 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF
\r
5169 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11
\r
5170 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U
\r
5172 /*Master Tri-state Enable for pin 44, active high*/
\r
5173 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL
\r
5174 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
\r
5175 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK
\r
5176 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF
\r
5177 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12
\r
5178 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U
\r
5180 /*Master Tri-state Enable for pin 45, active high*/
\r
5181 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
\r
5182 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
\r
5183 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
\r
5184 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF
\r
5185 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13
\r
5186 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U
\r
5188 /*Master Tri-state Enable for pin 46, active high*/
\r
5189 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
\r
5190 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
\r
5191 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
\r
5192 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF
\r
5193 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14
\r
5194 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U
\r
5196 /*Master Tri-state Enable for pin 47, active high*/
\r
5197 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
\r
5198 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
\r
5199 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
\r
5200 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF
\r
5201 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15
\r
5202 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U
\r
5204 /*Master Tri-state Enable for pin 48, active high*/
\r
5205 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
\r
5206 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
\r
5207 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
\r
5208 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF
\r
5209 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16
\r
5210 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U
\r
5212 /*Master Tri-state Enable for pin 49, active high*/
\r
5213 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
\r
5214 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
\r
5215 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
\r
5216 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF
\r
5217 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17
\r
5218 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U
\r
5220 /*Master Tri-state Enable for pin 50, active high*/
\r
5221 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
\r
5222 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
\r
5223 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
\r
5224 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF
\r
5225 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18
\r
5226 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U
\r
5228 /*Master Tri-state Enable for pin 51, active high*/
\r
5229 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
\r
5230 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
\r
5231 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
\r
5232 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF
\r
5233 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19
\r
5234 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U
\r
5236 /*Master Tri-state Enable for pin 52, active high*/
\r
5237 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
\r
5238 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
\r
5239 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
\r
5240 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF
\r
5241 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20
\r
5242 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U
\r
5244 /*Master Tri-state Enable for pin 53, active high*/
\r
5245 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
\r
5246 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
\r
5247 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
\r
5248 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF
\r
5249 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21
\r
5250 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U
\r
5252 /*Master Tri-state Enable for pin 54, active high*/
\r
5253 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
\r
5254 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
\r
5255 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
\r
5256 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF
\r
5257 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22
\r
5258 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U
\r
5260 /*Master Tri-state Enable for pin 55, active high*/
\r
5261 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
\r
5262 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
\r
5263 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
\r
5264 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF
\r
5265 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23
\r
5266 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U
\r
5268 /*Master Tri-state Enable for pin 56, active high*/
\r
5269 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
\r
5270 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
\r
5271 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
\r
5272 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF
\r
5273 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24
\r
5274 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U
\r
5276 /*Master Tri-state Enable for pin 57, active high*/
\r
5277 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
\r
5278 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
\r
5279 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
\r
5280 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF
\r
5281 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25
\r
5282 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U
\r
5284 /*Master Tri-state Enable for pin 58, active high*/
\r
5285 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
\r
5286 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
\r
5287 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
\r
5288 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF
\r
5289 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26
\r
5290 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U
\r
5292 /*Master Tri-state Enable for pin 59, active high*/
\r
5293 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
\r
5294 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
\r
5295 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
\r
5296 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF
\r
5297 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27
\r
5298 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U
\r
5300 /*Master Tri-state Enable for pin 60, active high*/
\r
5301 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
\r
5302 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
\r
5303 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
\r
5304 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF
\r
5305 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28
\r
5306 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U
\r
5308 /*Master Tri-state Enable for pin 61, active high*/
\r
5309 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
\r
5310 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
\r
5311 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
\r
5312 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF
\r
5313 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29
\r
5314 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U
\r
5316 /*Master Tri-state Enable for pin 62, active high*/
\r
5317 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
\r
5318 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
\r
5319 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
\r
5320 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF
\r
5321 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30
\r
5322 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U
\r
5324 /*Master Tri-state Enable for pin 63, active high*/
\r
5325 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
\r
5326 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
\r
5327 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
\r
5328 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF
\r
5329 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31
\r
5330 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U
\r
5332 /*Master Tri-state Enable for pin 64, active high*/
\r
5333 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
\r
5334 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
\r
5335 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
\r
5336 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF
\r
5337 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0
\r
5338 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U
\r
5340 /*Master Tri-state Enable for pin 65, active high*/
\r
5341 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
\r
5342 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
\r
5343 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
\r
5344 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF
\r
5345 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1
\r
5346 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U
\r
5348 /*Master Tri-state Enable for pin 66, active high*/
\r
5349 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
\r
5350 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
\r
5351 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
\r
5352 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF
\r
5353 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2
\r
5354 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U
\r
5356 /*Master Tri-state Enable for pin 67, active high*/
\r
5357 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
\r
5358 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
\r
5359 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
\r
5360 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF
\r
5361 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3
\r
5362 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U
\r
5364 /*Master Tri-state Enable for pin 68, active high*/
\r
5365 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
\r
5366 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
\r
5367 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
\r
5368 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF
\r
5369 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4
\r
5370 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U
\r
5372 /*Master Tri-state Enable for pin 69, active high*/
\r
5373 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
\r
5374 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
\r
5375 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
\r
5376 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF
\r
5377 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5
\r
5378 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U
\r
5380 /*Master Tri-state Enable for pin 70, active high*/
\r
5381 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
\r
5382 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
\r
5383 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
\r
5384 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF
\r
5385 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6
\r
5386 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U
\r
5388 /*Master Tri-state Enable for pin 71, active high*/
\r
5389 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
\r
5390 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
\r
5391 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
\r
5392 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF
\r
5393 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7
\r
5394 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U
\r
5396 /*Master Tri-state Enable for pin 72, active high*/
\r
5397 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
\r
5398 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
\r
5399 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
\r
5400 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF
\r
5401 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8
\r
5402 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U
\r
5404 /*Master Tri-state Enable for pin 73, active high*/
\r
5405 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
\r
5406 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
\r
5407 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
\r
5408 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF
\r
5409 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9
\r
5410 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U
\r
5412 /*Master Tri-state Enable for pin 74, active high*/
\r
5413 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
\r
5414 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
\r
5415 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
\r
5416 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF
\r
5417 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10
\r
5418 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U
\r
5420 /*Master Tri-state Enable for pin 75, active high*/
\r
5421 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
\r
5422 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
\r
5423 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
\r
5424 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF
\r
5425 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11
\r
5426 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U
\r
5428 /*Master Tri-state Enable for pin 76, active high*/
\r
5429 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
\r
5430 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
\r
5431 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
\r
5432 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF
\r
5433 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12
\r
5434 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U
\r
5436 /*Master Tri-state Enable for pin 77, active high*/
\r
5437 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
\r
5438 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
\r
5439 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
\r
5440 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF
\r
5441 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13
\r
5442 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U
\r
5444 /*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
\r
5445 ts to I2C 0 inputs.*/
\r
5446 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
\r
5447 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
\r
5448 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
\r
5449 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000
\r
5450 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3
\r
5451 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U
\r
5453 /*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
\r
5455 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
\r
5456 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
\r
5457 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
\r
5458 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000
\r
5459 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2
\r
5460 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U
\r
5462 /*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
\r
5463 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
\r
5464 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
\r
5465 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
\r
5466 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
\r
5467 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000
\r
5468 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1
\r
5469 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U
\r
5471 /*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
\r
5472 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
\r
5473 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
\r
5474 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
\r
5475 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
\r
5476 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000
\r
5477 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0
\r
5478 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U
\r
5479 #undef CRL_APB_RST_LPD_IOU0_OFFSET
\r
5480 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
\r
5481 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5482 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5483 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5484 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5485 #undef CRL_APB_RST_LPD_TOP_OFFSET
\r
5486 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
\r
5487 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5488 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5489 #undef IOU_SLCR_CTRL_REG_SD_OFFSET
\r
5490 #define IOU_SLCR_CTRL_REG_SD_OFFSET 0XFF180310
\r
5491 #undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
\r
5492 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320
\r
5493 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5494 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5495 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5496 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5497 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5498 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5499 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5500 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5501 #undef CRL_APB_RST_LPD_IOU2_OFFSET
\r
5502 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
\r
5503 #undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
\r
5504 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034
\r
5505 #undef UART0_BAUD_RATE_GEN_REG0_OFFSET
\r
5506 #define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018
\r
5507 #undef UART0_CONTROL_REG0_OFFSET
\r
5508 #define UART0_CONTROL_REG0_OFFSET 0XFF000000
\r
5509 #undef UART0_MODE_REG0_OFFSET
\r
5510 #define UART0_MODE_REG0_OFFSET 0XFF000004
\r
5511 #undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
\r
5512 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034
\r
5513 #undef UART1_BAUD_RATE_GEN_REG0_OFFSET
\r
5514 #define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018
\r
5515 #undef UART1_CONTROL_REG0_OFFSET
\r
5516 #define UART1_CONTROL_REG0_OFFSET 0XFF010000
\r
5517 #undef UART1_MODE_REG0_OFFSET
\r
5518 #define UART1_MODE_REG0_OFFSET 0XFF010004
\r
5519 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
\r
5520 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024
\r
5521 #undef CSU_TAMPER_STATUS_OFFSET
\r
5522 #define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000
\r
5525 #undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL
\r
5526 #undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT
\r
5527 #undef CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK
\r
5528 #define CRL_APB_RST_LPD_IOU0_GEM0_RESET_DEFVAL 0x0000000F
\r
5529 #define CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT 0
\r
5530 #define CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK 0x00000001U
\r
5533 #undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL
\r
5534 #undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT
\r
5535 #undef CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK
\r
5536 #define CRL_APB_RST_LPD_IOU0_GEM1_RESET_DEFVAL 0x0000000F
\r
5537 #define CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT 1
\r
5538 #define CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK 0x00000002U
\r
5541 #undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL
\r
5542 #undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT
\r
5543 #undef CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK
\r
5544 #define CRL_APB_RST_LPD_IOU0_GEM2_RESET_DEFVAL 0x0000000F
\r
5545 #define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2
\r
5546 #define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK 0x00000004U
\r
5549 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
\r
5550 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
\r
5551 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
\r
5552 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
\r
5553 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
\r
5554 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
\r
5556 /*Block level reset*/
\r
5557 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
\r
5558 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
\r
5559 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
\r
5560 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF
\r
5561 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
\r
5562 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U
\r
5564 /*Block level reset*/
\r
5565 #undef CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL
\r
5566 #undef CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT
\r
5567 #undef CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK
\r
5568 #define CRL_APB_RST_LPD_IOU2_NAND_RESET_DEFVAL 0x0017FFFF
\r
5569 #define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 16
\r
5570 #define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK 0x00010000U
\r
5572 /*USB 0 reset for control registers*/
\r
5573 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
\r
5574 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
\r
5575 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
\r
5576 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
\r
5577 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
\r
5578 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
\r
5580 /*USB 0 sleep circuit reset*/
\r
5581 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
\r
5582 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
\r
5583 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
\r
5584 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
\r
5585 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
\r
5586 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
\r
5589 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
\r
5590 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
\r
5591 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
\r
5592 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
\r
5593 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
\r
5594 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
\r
5596 /*Block level reset*/
\r
5597 #undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL
\r
5598 #undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT
\r
5599 #undef CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK
\r
5600 #define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_DEFVAL 0x0017FFFF
\r
5601 #define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT 5
\r
5602 #define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK 0x00000020U
\r
5604 /*Block level reset*/
\r
5605 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
\r
5606 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
\r
5607 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
\r
5608 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF
\r
5609 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6
\r
5610 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U
\r
5612 /*SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled*/
\r
5613 #undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL
\r
5614 #undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT
\r
5615 #undef IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK
\r
5616 #define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_DEFVAL 0x00000000
\r
5617 #define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT 0
\r
5618 #define IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK 0x00000001U
\r
5620 /*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
\r
5621 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
\r
5622 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
\r
5623 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
\r
5624 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000
\r
5625 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15
\r
5626 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U
\r
5628 /*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
\r
5630 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL
\r
5631 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT
\r
5632 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK
\r
5633 #define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_DEFVAL 0x0FFC0FFC
\r
5634 #define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT 12
\r
5635 #define IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK 0x00003000U
\r
5637 /*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
\r
5639 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
\r
5640 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
\r
5641 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
\r
5642 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC
\r
5643 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28
\r
5644 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U
\r
5646 /*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
\r
5647 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL
\r
5648 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT
\r
5649 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK
\r
5650 #define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_DEFVAL 0x0FFC0FFC
\r
5651 #define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT 9
\r
5652 #define IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK 0x00000200U
\r
5654 /*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
\r
5655 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL
\r
5656 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT
\r
5657 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK
\r
5658 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_DEFVAL 0x0FFC0FFC
\r
5659 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT 8
\r
5660 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK 0x00000100U
\r
5662 /*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
\r
5663 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL
\r
5664 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT
\r
5665 #undef IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK
\r
5666 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_DEFVAL 0x0FFC0FFC
\r
5667 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT 7
\r
5668 #define IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK 0x00000080U
\r
5670 /*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
\r
5671 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
\r
5672 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
\r
5673 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
\r
5674 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC
\r
5675 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25
\r
5676 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U
\r
5678 /*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
\r
5679 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
\r
5680 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
\r
5681 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
\r
5682 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC
\r
5683 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24
\r
5684 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U
\r
5686 /*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
\r
5687 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
\r
5688 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
\r
5689 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
\r
5690 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC
\r
5691 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23
\r
5692 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U
\r
5694 /*Block level reset*/
\r
5695 #undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL
\r
5696 #undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT
\r
5697 #undef CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK
\r
5698 #define CRL_APB_RST_LPD_IOU2_CAN0_RESET_DEFVAL 0x0017FFFF
\r
5699 #define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 7
\r
5700 #define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK 0x00000080U
\r
5702 /*Block level reset*/
\r
5703 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
\r
5704 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
\r
5705 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
\r
5706 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF
\r
5707 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8
\r
5708 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U
\r
5710 /*Block level reset*/
\r
5711 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL
\r
5712 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
\r
5713 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK
\r
5714 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF
\r
5715 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9
\r
5716 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U
\r
5718 /*Block level reset*/
\r
5719 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
\r
5720 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
\r
5721 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
\r
5722 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF
\r
5723 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10
\r
5724 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U
\r
5726 /*Block level reset*/
\r
5727 #undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL
\r
5728 #undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT
\r
5729 #undef CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK
\r
5730 #define CRL_APB_RST_LPD_IOU2_SPI0_RESET_DEFVAL 0x0017FFFF
\r
5731 #define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 3
\r
5732 #define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK 0x00000008U
\r
5734 /*Block level reset*/
\r
5735 #undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL
\r
5736 #undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT
\r
5737 #undef CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK
\r
5738 #define CRL_APB_RST_LPD_IOU2_SPI1_RESET_DEFVAL 0x0017FFFF
\r
5739 #define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 4
\r
5740 #define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK 0x00000010U
\r
5742 /*Block level reset*/
\r
5743 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
\r
5744 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
\r
5745 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
\r
5746 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF
\r
5747 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11
\r
5748 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U
\r
5750 /*Block level reset*/
\r
5751 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
\r
5752 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
\r
5753 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
\r
5754 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF
\r
5755 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12
\r
5756 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U
\r
5758 /*Block level reset*/
\r
5759 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
\r
5760 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
\r
5761 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
\r
5762 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF
\r
5763 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13
\r
5764 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U
\r
5766 /*Block level reset*/
\r
5767 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
\r
5768 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
\r
5769 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
\r
5770 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF
\r
5771 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14
\r
5772 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U
\r
5774 /*Block level reset*/
\r
5775 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
\r
5776 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
\r
5777 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
\r
5778 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF
\r
5779 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1
\r
5780 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U
\r
5782 /*Block level reset*/
\r
5783 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
\r
5784 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
\r
5785 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
\r
5786 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF
\r
5787 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2
\r
5788 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U
\r
5790 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
\r
5791 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
\r
5792 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
\r
5793 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
\r
5794 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
\r
5795 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
\r
5796 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
\r
5798 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
\r
5799 #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
\r
5800 #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
\r
5801 #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
\r
5802 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
\r
5803 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0
\r
5804 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
\r
5806 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
\r
5807 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
\r
5808 #undef UART0_CONTROL_REG0_STPBRK_DEFVAL
\r
5809 #undef UART0_CONTROL_REG0_STPBRK_SHIFT
\r
5810 #undef UART0_CONTROL_REG0_STPBRK_MASK
\r
5811 #define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
\r
5812 #define UART0_CONTROL_REG0_STPBRK_SHIFT 8
\r
5813 #define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U
\r
5815 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
\r
5816 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
\r
5817 #undef UART0_CONTROL_REG0_STTBRK_DEFVAL
\r
5818 #undef UART0_CONTROL_REG0_STTBRK_SHIFT
\r
5819 #undef UART0_CONTROL_REG0_STTBRK_MASK
\r
5820 #define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
\r
5821 #define UART0_CONTROL_REG0_STTBRK_SHIFT 7
\r
5822 #define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U
\r
5824 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
\r
5826 #undef UART0_CONTROL_REG0_RSTTO_DEFVAL
\r
5827 #undef UART0_CONTROL_REG0_RSTTO_SHIFT
\r
5828 #undef UART0_CONTROL_REG0_RSTTO_MASK
\r
5829 #define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
\r
5830 #define UART0_CONTROL_REG0_RSTTO_SHIFT 6
\r
5831 #define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U
\r
5833 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
\r
5834 #undef UART0_CONTROL_REG0_TXDIS_DEFVAL
\r
5835 #undef UART0_CONTROL_REG0_TXDIS_SHIFT
\r
5836 #undef UART0_CONTROL_REG0_TXDIS_MASK
\r
5837 #define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
\r
5838 #define UART0_CONTROL_REG0_TXDIS_SHIFT 5
\r
5839 #define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U
\r
5841 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
\r
5842 #undef UART0_CONTROL_REG0_TXEN_DEFVAL
\r
5843 #undef UART0_CONTROL_REG0_TXEN_SHIFT
\r
5844 #undef UART0_CONTROL_REG0_TXEN_MASK
\r
5845 #define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128
\r
5846 #define UART0_CONTROL_REG0_TXEN_SHIFT 4
\r
5847 #define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U
\r
5849 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
\r
5850 #undef UART0_CONTROL_REG0_RXDIS_DEFVAL
\r
5851 #undef UART0_CONTROL_REG0_RXDIS_SHIFT
\r
5852 #undef UART0_CONTROL_REG0_RXDIS_MASK
\r
5853 #define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
\r
5854 #define UART0_CONTROL_REG0_RXDIS_SHIFT 3
\r
5855 #define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U
\r
5857 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
\r
5858 #undef UART0_CONTROL_REG0_RXEN_DEFVAL
\r
5859 #undef UART0_CONTROL_REG0_RXEN_SHIFT
\r
5860 #undef UART0_CONTROL_REG0_RXEN_MASK
\r
5861 #define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128
\r
5862 #define UART0_CONTROL_REG0_RXEN_SHIFT 2
\r
5863 #define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U
\r
5865 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
\r
5866 bit is self clearing once the reset has completed.*/
\r
5867 #undef UART0_CONTROL_REG0_TXRES_DEFVAL
\r
5868 #undef UART0_CONTROL_REG0_TXRES_SHIFT
\r
5869 #undef UART0_CONTROL_REG0_TXRES_MASK
\r
5870 #define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128
\r
5871 #define UART0_CONTROL_REG0_TXRES_SHIFT 1
\r
5872 #define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U
\r
5874 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
\r
5875 is self clearing once the reset has completed.*/
\r
5876 #undef UART0_CONTROL_REG0_RXRES_DEFVAL
\r
5877 #undef UART0_CONTROL_REG0_RXRES_SHIFT
\r
5878 #undef UART0_CONTROL_REG0_RXRES_MASK
\r
5879 #define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128
\r
5880 #define UART0_CONTROL_REG0_RXRES_SHIFT 0
\r
5881 #define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U
\r
5883 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
\r
5884 #undef UART0_MODE_REG0_CHMODE_DEFVAL
\r
5885 #undef UART0_MODE_REG0_CHMODE_SHIFT
\r
5886 #undef UART0_MODE_REG0_CHMODE_MASK
\r
5887 #define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000
\r
5888 #define UART0_MODE_REG0_CHMODE_SHIFT 8
\r
5889 #define UART0_MODE_REG0_CHMODE_MASK 0x00000300U
\r
5891 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
\r
5892 stop bits 10: 2 stop bits 11: reserved*/
\r
5893 #undef UART0_MODE_REG0_NBSTOP_DEFVAL
\r
5894 #undef UART0_MODE_REG0_NBSTOP_SHIFT
\r
5895 #undef UART0_MODE_REG0_NBSTOP_MASK
\r
5896 #define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000
\r
5897 #define UART0_MODE_REG0_NBSTOP_SHIFT 6
\r
5898 #define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U
\r
5900 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
\r
5901 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
\r
5902 #undef UART0_MODE_REG0_PAR_DEFVAL
\r
5903 #undef UART0_MODE_REG0_PAR_SHIFT
\r
5904 #undef UART0_MODE_REG0_PAR_MASK
\r
5905 #define UART0_MODE_REG0_PAR_DEFVAL 0x00000000
\r
5906 #define UART0_MODE_REG0_PAR_SHIFT 3
\r
5907 #define UART0_MODE_REG0_PAR_MASK 0x00000038U
\r
5909 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
\r
5910 #undef UART0_MODE_REG0_CHRL_DEFVAL
\r
5911 #undef UART0_MODE_REG0_CHRL_SHIFT
\r
5912 #undef UART0_MODE_REG0_CHRL_MASK
\r
5913 #define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000
\r
5914 #define UART0_MODE_REG0_CHRL_SHIFT 1
\r
5915 #define UART0_MODE_REG0_CHRL_MASK 0x00000006U
\r
5917 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
\r
5918 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
\r
5919 #undef UART0_MODE_REG0_CLKS_DEFVAL
\r
5920 #undef UART0_MODE_REG0_CLKS_SHIFT
\r
5921 #undef UART0_MODE_REG0_CLKS_MASK
\r
5922 #define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000
\r
5923 #define UART0_MODE_REG0_CLKS_SHIFT 0
\r
5924 #define UART0_MODE_REG0_CLKS_MASK 0x00000001U
\r
5926 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
\r
5927 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
\r
5928 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
\r
5929 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
\r
5930 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
\r
5931 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
\r
5932 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
\r
5934 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
\r
5935 #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
\r
5936 #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
\r
5937 #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
\r
5938 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
\r
5939 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0
\r
5940 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
\r
5942 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
\r
5943 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
\r
5944 #undef UART1_CONTROL_REG0_STPBRK_DEFVAL
\r
5945 #undef UART1_CONTROL_REG0_STPBRK_SHIFT
\r
5946 #undef UART1_CONTROL_REG0_STPBRK_MASK
\r
5947 #define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
\r
5948 #define UART1_CONTROL_REG0_STPBRK_SHIFT 8
\r
5949 #define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U
\r
5951 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
\r
5952 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
\r
5953 #undef UART1_CONTROL_REG0_STTBRK_DEFVAL
\r
5954 #undef UART1_CONTROL_REG0_STTBRK_SHIFT
\r
5955 #undef UART1_CONTROL_REG0_STTBRK_MASK
\r
5956 #define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
\r
5957 #define UART1_CONTROL_REG0_STTBRK_SHIFT 7
\r
5958 #define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U
\r
5960 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
\r
5962 #undef UART1_CONTROL_REG0_RSTTO_DEFVAL
\r
5963 #undef UART1_CONTROL_REG0_RSTTO_SHIFT
\r
5964 #undef UART1_CONTROL_REG0_RSTTO_MASK
\r
5965 #define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
\r
5966 #define UART1_CONTROL_REG0_RSTTO_SHIFT 6
\r
5967 #define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U
\r
5969 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
\r
5970 #undef UART1_CONTROL_REG0_TXDIS_DEFVAL
\r
5971 #undef UART1_CONTROL_REG0_TXDIS_SHIFT
\r
5972 #undef UART1_CONTROL_REG0_TXDIS_MASK
\r
5973 #define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
\r
5974 #define UART1_CONTROL_REG0_TXDIS_SHIFT 5
\r
5975 #define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U
\r
5977 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
\r
5978 #undef UART1_CONTROL_REG0_TXEN_DEFVAL
\r
5979 #undef UART1_CONTROL_REG0_TXEN_SHIFT
\r
5980 #undef UART1_CONTROL_REG0_TXEN_MASK
\r
5981 #define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128
\r
5982 #define UART1_CONTROL_REG0_TXEN_SHIFT 4
\r
5983 #define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U
\r
5985 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
\r
5986 #undef UART1_CONTROL_REG0_RXDIS_DEFVAL
\r
5987 #undef UART1_CONTROL_REG0_RXDIS_SHIFT
\r
5988 #undef UART1_CONTROL_REG0_RXDIS_MASK
\r
5989 #define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
\r
5990 #define UART1_CONTROL_REG0_RXDIS_SHIFT 3
\r
5991 #define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U
\r
5993 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
\r
5994 #undef UART1_CONTROL_REG0_RXEN_DEFVAL
\r
5995 #undef UART1_CONTROL_REG0_RXEN_SHIFT
\r
5996 #undef UART1_CONTROL_REG0_RXEN_MASK
\r
5997 #define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128
\r
5998 #define UART1_CONTROL_REG0_RXEN_SHIFT 2
\r
5999 #define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U
\r
6001 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
\r
6002 bit is self clearing once the reset has completed.*/
\r
6003 #undef UART1_CONTROL_REG0_TXRES_DEFVAL
\r
6004 #undef UART1_CONTROL_REG0_TXRES_SHIFT
\r
6005 #undef UART1_CONTROL_REG0_TXRES_MASK
\r
6006 #define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128
\r
6007 #define UART1_CONTROL_REG0_TXRES_SHIFT 1
\r
6008 #define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U
\r
6010 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
\r
6011 is self clearing once the reset has completed.*/
\r
6012 #undef UART1_CONTROL_REG0_RXRES_DEFVAL
\r
6013 #undef UART1_CONTROL_REG0_RXRES_SHIFT
\r
6014 #undef UART1_CONTROL_REG0_RXRES_MASK
\r
6015 #define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128
\r
6016 #define UART1_CONTROL_REG0_RXRES_SHIFT 0
\r
6017 #define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U
\r
6019 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
\r
6020 #undef UART1_MODE_REG0_CHMODE_DEFVAL
\r
6021 #undef UART1_MODE_REG0_CHMODE_SHIFT
\r
6022 #undef UART1_MODE_REG0_CHMODE_MASK
\r
6023 #define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000
\r
6024 #define UART1_MODE_REG0_CHMODE_SHIFT 8
\r
6025 #define UART1_MODE_REG0_CHMODE_MASK 0x00000300U
\r
6027 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
\r
6028 stop bits 10: 2 stop bits 11: reserved*/
\r
6029 #undef UART1_MODE_REG0_NBSTOP_DEFVAL
\r
6030 #undef UART1_MODE_REG0_NBSTOP_SHIFT
\r
6031 #undef UART1_MODE_REG0_NBSTOP_MASK
\r
6032 #define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000
\r
6033 #define UART1_MODE_REG0_NBSTOP_SHIFT 6
\r
6034 #define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U
\r
6036 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
\r
6037 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
\r
6038 #undef UART1_MODE_REG0_PAR_DEFVAL
\r
6039 #undef UART1_MODE_REG0_PAR_SHIFT
\r
6040 #undef UART1_MODE_REG0_PAR_MASK
\r
6041 #define UART1_MODE_REG0_PAR_DEFVAL 0x00000000
\r
6042 #define UART1_MODE_REG0_PAR_SHIFT 3
\r
6043 #define UART1_MODE_REG0_PAR_MASK 0x00000038U
\r
6045 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
\r
6046 #undef UART1_MODE_REG0_CHRL_DEFVAL
\r
6047 #undef UART1_MODE_REG0_CHRL_SHIFT
\r
6048 #undef UART1_MODE_REG0_CHRL_MASK
\r
6049 #define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000
\r
6050 #define UART1_MODE_REG0_CHRL_SHIFT 1
\r
6051 #define UART1_MODE_REG0_CHRL_MASK 0x00000006U
\r
6053 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
\r
6054 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
\r
6055 #undef UART1_MODE_REG0_CLKS_DEFVAL
\r
6056 #undef UART1_MODE_REG0_CLKS_SHIFT
\r
6057 #undef UART1_MODE_REG0_CLKS_MASK
\r
6058 #define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000
\r
6059 #define UART1_MODE_REG0_CLKS_SHIFT 0
\r
6060 #define UART1_MODE_REG0_CLKS_MASK 0x00000001U
\r
6062 /*TrustZone Classification for ADMA*/
\r
6063 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
\r
6064 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
\r
6065 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
\r
6066 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
\r
6067 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0
\r
6068 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU
\r
6071 #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
\r
6072 #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
\r
6073 #undef CSU_TAMPER_STATUS_TAMPER_0_MASK
\r
6074 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000
\r
6075 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0
\r
6076 #define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U
\r
6079 #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
\r
6080 #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
\r
6081 #undef CSU_TAMPER_STATUS_TAMPER_1_MASK
\r
6082 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000
\r
6083 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1
\r
6084 #define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U
\r
6086 /*JTAG toggle detect*/
\r
6087 #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
\r
6088 #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
\r
6089 #undef CSU_TAMPER_STATUS_TAMPER_2_MASK
\r
6090 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000
\r
6091 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2
\r
6092 #define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U
\r
6095 #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
\r
6096 #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
\r
6097 #undef CSU_TAMPER_STATUS_TAMPER_3_MASK
\r
6098 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000
\r
6099 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3
\r
6100 #define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U
\r
6102 /*AMS over temperature alarm for LPD*/
\r
6103 #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
\r
6104 #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
\r
6105 #undef CSU_TAMPER_STATUS_TAMPER_4_MASK
\r
6106 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000
\r
6107 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4
\r
6108 #define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U
\r
6110 /*AMS over temperature alarm for APU*/
\r
6111 #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
\r
6112 #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
\r
6113 #undef CSU_TAMPER_STATUS_TAMPER_5_MASK
\r
6114 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000
\r
6115 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5
\r
6116 #define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U
\r
6118 /*AMS voltage alarm for VCCPINT_FPD*/
\r
6119 #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
\r
6120 #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
\r
6121 #undef CSU_TAMPER_STATUS_TAMPER_6_MASK
\r
6122 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000
\r
6123 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6
\r
6124 #define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U
\r
6126 /*AMS voltage alarm for VCCPINT_LPD*/
\r
6127 #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
\r
6128 #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
\r
6129 #undef CSU_TAMPER_STATUS_TAMPER_7_MASK
\r
6130 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000
\r
6131 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7
\r
6132 #define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U
\r
6134 /*AMS voltage alarm for VCCPAUX*/
\r
6135 #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
\r
6136 #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
\r
6137 #undef CSU_TAMPER_STATUS_TAMPER_8_MASK
\r
6138 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000
\r
6139 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8
\r
6140 #define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U
\r
6142 /*AMS voltage alarm for DDRPHY*/
\r
6143 #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
\r
6144 #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
\r
6145 #undef CSU_TAMPER_STATUS_TAMPER_9_MASK
\r
6146 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000
\r
6147 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9
\r
6148 #define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U
\r
6150 /*AMS voltage alarm for PSIO bank 0/1/2*/
\r
6151 #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
\r
6152 #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
\r
6153 #undef CSU_TAMPER_STATUS_TAMPER_10_MASK
\r
6154 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000
\r
6155 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10
\r
6156 #define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U
\r
6158 /*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
\r
6159 #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
\r
6160 #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
\r
6161 #undef CSU_TAMPER_STATUS_TAMPER_11_MASK
\r
6162 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000
\r
6163 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11
\r
6164 #define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U
\r
6166 /*AMS voltaage alarm for GT*/
\r
6167 #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
\r
6168 #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
\r
6169 #undef CSU_TAMPER_STATUS_TAMPER_12_MASK
\r
6170 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000
\r
6171 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12
\r
6172 #define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U
\r
6173 #undef LPD_XPPU_CFG_MASTER_ID00_OFFSET
\r
6174 #define LPD_XPPU_CFG_MASTER_ID00_OFFSET 0XFF980100
\r
6175 #undef LPD_XPPU_CFG_MASTER_ID01_OFFSET
\r
6176 #define LPD_XPPU_CFG_MASTER_ID01_OFFSET 0XFF980104
\r
6177 #undef LPD_XPPU_CFG_MASTER_ID02_OFFSET
\r
6178 #define LPD_XPPU_CFG_MASTER_ID02_OFFSET 0XFF980108
\r
6179 #undef LPD_XPPU_CFG_MASTER_ID03_OFFSET
\r
6180 #define LPD_XPPU_CFG_MASTER_ID03_OFFSET 0XFF98010C
\r
6181 #undef LPD_XPPU_CFG_MASTER_ID04_OFFSET
\r
6182 #define LPD_XPPU_CFG_MASTER_ID04_OFFSET 0XFF980110
\r
6183 #undef LPD_XPPU_CFG_MASTER_ID05_OFFSET
\r
6184 #define LPD_XPPU_CFG_MASTER_ID05_OFFSET 0XFF980114
\r
6185 #undef LPD_XPPU_CFG_MASTER_ID06_OFFSET
\r
6186 #define LPD_XPPU_CFG_MASTER_ID06_OFFSET 0XFF980118
\r
6187 #undef LPD_XPPU_CFG_MASTER_ID07_OFFSET
\r
6188 #define LPD_XPPU_CFG_MASTER_ID07_OFFSET 0XFF98011C
\r
6189 #undef LPD_XPPU_CFG_MASTER_ID08_OFFSET
\r
6190 #define LPD_XPPU_CFG_MASTER_ID08_OFFSET 0XFF980120
\r
6191 #undef LPD_XPPU_CFG_MASTER_ID09_OFFSET
\r
6192 #define LPD_XPPU_CFG_MASTER_ID09_OFFSET 0XFF980124
\r
6193 #undef LPD_XPPU_CFG_MASTER_ID10_OFFSET
\r
6194 #define LPD_XPPU_CFG_MASTER_ID10_OFFSET 0XFF980128
\r
6195 #undef LPD_XPPU_CFG_MASTER_ID11_OFFSET
\r
6196 #define LPD_XPPU_CFG_MASTER_ID11_OFFSET 0XFF98012C
\r
6197 #undef LPD_XPPU_CFG_MASTER_ID12_OFFSET
\r
6198 #define LPD_XPPU_CFG_MASTER_ID12_OFFSET 0XFF980130
\r
6199 #undef LPD_XPPU_CFG_MASTER_ID13_OFFSET
\r
6200 #define LPD_XPPU_CFG_MASTER_ID13_OFFSET 0XFF980134
\r
6201 #undef LPD_XPPU_CFG_MASTER_ID14_OFFSET
\r
6202 #define LPD_XPPU_CFG_MASTER_ID14_OFFSET 0XFF980138
\r
6203 #undef LPD_XPPU_CFG_MASTER_ID15_OFFSET
\r
6204 #define LPD_XPPU_CFG_MASTER_ID15_OFFSET 0XFF98013C
\r
6205 #undef LPD_XPPU_CFG_MASTER_ID16_OFFSET
\r
6206 #define LPD_XPPU_CFG_MASTER_ID16_OFFSET 0XFF980140
\r
6207 #undef LPD_XPPU_CFG_MASTER_ID17_OFFSET
\r
6208 #define LPD_XPPU_CFG_MASTER_ID17_OFFSET 0XFF980144
\r
6209 #undef LPD_XPPU_CFG_MASTER_ID18_OFFSET
\r
6210 #define LPD_XPPU_CFG_MASTER_ID18_OFFSET 0XFF980148
\r
6211 #undef LPD_XPPU_CFG_MASTER_ID19_OFFSET
\r
6212 #define LPD_XPPU_CFG_MASTER_ID19_OFFSET 0XFF98014C
\r
6214 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6215 #undef LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL
\r
6216 #undef LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT
\r
6217 #undef LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK
\r
6218 #define LPD_XPPU_CFG_MASTER_ID00_MIDP_DEFVAL 0x83FF0040
\r
6219 #define LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT 31
\r
6220 #define LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK 0x80000000U
\r
6222 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6223 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL
\r
6224 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT
\r
6225 #undef LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK
\r
6226 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL 0x83FF0040
\r
6227 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT 30
\r
6228 #define LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK 0x40000000U
\r
6230 /*Mask to be applied before comparing*/
\r
6231 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL
\r
6232 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT
\r
6233 #undef LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK
\r
6234 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_DEFVAL 0x83FF0040
\r
6235 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT 16
\r
6236 #define LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK 0x03FF0000U
\r
6238 /*Predefined Master ID for PMU*/
\r
6239 #undef LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL
\r
6240 #undef LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT
\r
6241 #undef LPD_XPPU_CFG_MASTER_ID00_MID_MASK
\r
6242 #define LPD_XPPU_CFG_MASTER_ID00_MID_DEFVAL 0x83FF0040
\r
6243 #define LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT 0
\r
6244 #define LPD_XPPU_CFG_MASTER_ID00_MID_MASK 0x000003FFU
\r
6246 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6247 #undef LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL
\r
6248 #undef LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT
\r
6249 #undef LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK
\r
6250 #define LPD_XPPU_CFG_MASTER_ID01_MIDP_DEFVAL 0x03F00000
\r
6251 #define LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT 31
\r
6252 #define LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK 0x80000000U
\r
6254 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6255 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL
\r
6256 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT
\r
6257 #undef LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK
\r
6258 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_DEFVAL 0x03F00000
\r
6259 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT 30
\r
6260 #define LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK 0x40000000U
\r
6262 /*Mask to be applied before comparing*/
\r
6263 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL
\r
6264 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT
\r
6265 #undef LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK
\r
6266 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_DEFVAL 0x03F00000
\r
6267 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT 16
\r
6268 #define LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK 0x03FF0000U
\r
6270 /*Predefined Master ID for RPU0*/
\r
6271 #undef LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL
\r
6272 #undef LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT
\r
6273 #undef LPD_XPPU_CFG_MASTER_ID01_MID_MASK
\r
6274 #define LPD_XPPU_CFG_MASTER_ID01_MID_DEFVAL 0x03F00000
\r
6275 #define LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT 0
\r
6276 #define LPD_XPPU_CFG_MASTER_ID01_MID_MASK 0x000003FFU
\r
6278 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6279 #undef LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL
\r
6280 #undef LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT
\r
6281 #undef LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK
\r
6282 #define LPD_XPPU_CFG_MASTER_ID02_MIDP_DEFVAL 0x83F00010
\r
6283 #define LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT 31
\r
6284 #define LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK 0x80000000U
\r
6286 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6287 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL
\r
6288 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT
\r
6289 #undef LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK
\r
6290 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_DEFVAL 0x83F00010
\r
6291 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT 30
\r
6292 #define LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK 0x40000000U
\r
6294 /*Mask to be applied before comparing*/
\r
6295 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL
\r
6296 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT
\r
6297 #undef LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK
\r
6298 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_DEFVAL 0x83F00010
\r
6299 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT 16
\r
6300 #define LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK 0x03FF0000U
\r
6302 /*Predefined Master ID for RPU1*/
\r
6303 #undef LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL
\r
6304 #undef LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT
\r
6305 #undef LPD_XPPU_CFG_MASTER_ID02_MID_MASK
\r
6306 #define LPD_XPPU_CFG_MASTER_ID02_MID_DEFVAL 0x83F00010
\r
6307 #define LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT 0
\r
6308 #define LPD_XPPU_CFG_MASTER_ID02_MID_MASK 0x000003FFU
\r
6310 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6311 #undef LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL
\r
6312 #undef LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT
\r
6313 #undef LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK
\r
6314 #define LPD_XPPU_CFG_MASTER_ID03_MIDP_DEFVAL 0x83C00080
\r
6315 #define LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT 31
\r
6316 #define LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK 0x80000000U
\r
6318 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6319 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL
\r
6320 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT
\r
6321 #undef LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK
\r
6322 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_DEFVAL 0x83C00080
\r
6323 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT 30
\r
6324 #define LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK 0x40000000U
\r
6326 /*Mask to be applied before comparing*/
\r
6327 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL
\r
6328 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT
\r
6329 #undef LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK
\r
6330 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_DEFVAL 0x83C00080
\r
6331 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT 16
\r
6332 #define LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK 0x03FF0000U
\r
6334 /*Predefined Master ID for APU*/
\r
6335 #undef LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL
\r
6336 #undef LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT
\r
6337 #undef LPD_XPPU_CFG_MASTER_ID03_MID_MASK
\r
6338 #define LPD_XPPU_CFG_MASTER_ID03_MID_DEFVAL 0x83C00080
\r
6339 #define LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT 0
\r
6340 #define LPD_XPPU_CFG_MASTER_ID03_MID_MASK 0x000003FFU
\r
6342 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6343 #undef LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL
\r
6344 #undef LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT
\r
6345 #undef LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK
\r
6346 #define LPD_XPPU_CFG_MASTER_ID04_MIDP_DEFVAL 0x83C30080
\r
6347 #define LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT 31
\r
6348 #define LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK 0x80000000U
\r
6350 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6351 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL
\r
6352 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT
\r
6353 #undef LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK
\r
6354 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_DEFVAL 0x83C30080
\r
6355 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT 30
\r
6356 #define LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK 0x40000000U
\r
6358 /*Mask to be applied before comparing*/
\r
6359 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL
\r
6360 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT
\r
6361 #undef LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK
\r
6362 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_DEFVAL 0x83C30080
\r
6363 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT 16
\r
6364 #define LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK 0x03FF0000U
\r
6366 /*Predefined Master ID for A53 Core 0*/
\r
6367 #undef LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL
\r
6368 #undef LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT
\r
6369 #undef LPD_XPPU_CFG_MASTER_ID04_MID_MASK
\r
6370 #define LPD_XPPU_CFG_MASTER_ID04_MID_DEFVAL 0x83C30080
\r
6371 #define LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT 0
\r
6372 #define LPD_XPPU_CFG_MASTER_ID04_MID_MASK 0x000003FFU
\r
6374 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6375 #undef LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL
\r
6376 #undef LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT
\r
6377 #undef LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK
\r
6378 #define LPD_XPPU_CFG_MASTER_ID05_MIDP_DEFVAL 0x03C30081
\r
6379 #define LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT 31
\r
6380 #define LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK 0x80000000U
\r
6382 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6383 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL
\r
6384 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT
\r
6385 #undef LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK
\r
6386 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_DEFVAL 0x03C30081
\r
6387 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT 30
\r
6388 #define LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK 0x40000000U
\r
6390 /*Mask to be applied before comparing*/
\r
6391 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL
\r
6392 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT
\r
6393 #undef LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK
\r
6394 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_DEFVAL 0x03C30081
\r
6395 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT 16
\r
6396 #define LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK 0x03FF0000U
\r
6398 /*Predefined Master ID for A53 Core 1*/
\r
6399 #undef LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL
\r
6400 #undef LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT
\r
6401 #undef LPD_XPPU_CFG_MASTER_ID05_MID_MASK
\r
6402 #define LPD_XPPU_CFG_MASTER_ID05_MID_DEFVAL 0x03C30081
\r
6403 #define LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT 0
\r
6404 #define LPD_XPPU_CFG_MASTER_ID05_MID_MASK 0x000003FFU
\r
6406 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6407 #undef LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL
\r
6408 #undef LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT
\r
6409 #undef LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK
\r
6410 #define LPD_XPPU_CFG_MASTER_ID06_MIDP_DEFVAL 0x03C30082
\r
6411 #define LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT 31
\r
6412 #define LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK 0x80000000U
\r
6414 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6415 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL
\r
6416 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT
\r
6417 #undef LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK
\r
6418 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_DEFVAL 0x03C30082
\r
6419 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT 30
\r
6420 #define LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK 0x40000000U
\r
6422 /*Mask to be applied before comparing*/
\r
6423 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL
\r
6424 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT
\r
6425 #undef LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK
\r
6426 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_DEFVAL 0x03C30082
\r
6427 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT 16
\r
6428 #define LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK 0x03FF0000U
\r
6430 /*Predefined Master ID for A53 Core 2*/
\r
6431 #undef LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL
\r
6432 #undef LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT
\r
6433 #undef LPD_XPPU_CFG_MASTER_ID06_MID_MASK
\r
6434 #define LPD_XPPU_CFG_MASTER_ID06_MID_DEFVAL 0x03C30082
\r
6435 #define LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT 0
\r
6436 #define LPD_XPPU_CFG_MASTER_ID06_MID_MASK 0x000003FFU
\r
6438 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6439 #undef LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL
\r
6440 #undef LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT
\r
6441 #undef LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK
\r
6442 #define LPD_XPPU_CFG_MASTER_ID07_MIDP_DEFVAL 0x83C30083
\r
6443 #define LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT 31
\r
6444 #define LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK 0x80000000U
\r
6446 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6447 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL
\r
6448 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT
\r
6449 #undef LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK
\r
6450 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_DEFVAL 0x83C30083
\r
6451 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT 30
\r
6452 #define LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK 0x40000000U
\r
6454 /*Mask to be applied before comparing*/
\r
6455 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL
\r
6456 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT
\r
6457 #undef LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK
\r
6458 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_DEFVAL 0x83C30083
\r
6459 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT 16
\r
6460 #define LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK 0x03FF0000U
\r
6462 /*Predefined Master ID for A53 Core 3*/
\r
6463 #undef LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL
\r
6464 #undef LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT
\r
6465 #undef LPD_XPPU_CFG_MASTER_ID07_MID_MASK
\r
6466 #define LPD_XPPU_CFG_MASTER_ID07_MID_DEFVAL 0x83C30083
\r
6467 #define LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT 0
\r
6468 #define LPD_XPPU_CFG_MASTER_ID07_MID_MASK 0x000003FFU
\r
6470 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6471 #undef LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL
\r
6472 #undef LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT
\r
6473 #undef LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK
\r
6474 #define LPD_XPPU_CFG_MASTER_ID08_MIDP_DEFVAL 0x00000000
\r
6475 #define LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT 31
\r
6476 #define LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK 0x80000000U
\r
6478 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6479 #undef LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL
\r
6480 #undef LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT
\r
6481 #undef LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK
\r
6482 #define LPD_XPPU_CFG_MASTER_ID08_MIDR_DEFVAL 0x00000000
\r
6483 #define LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT 30
\r
6484 #define LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK 0x40000000U
\r
6486 /*Mask to be applied before comparing*/
\r
6487 #undef LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL
\r
6488 #undef LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT
\r
6489 #undef LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK
\r
6490 #define LPD_XPPU_CFG_MASTER_ID08_MIDM_DEFVAL 0x00000000
\r
6491 #define LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT 16
\r
6492 #define LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK 0x03FF0000U
\r
6494 /*Programmable Master ID*/
\r
6495 #undef LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL
\r
6496 #undef LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT
\r
6497 #undef LPD_XPPU_CFG_MASTER_ID08_MID_MASK
\r
6498 #define LPD_XPPU_CFG_MASTER_ID08_MID_DEFVAL 0x00000000
\r
6499 #define LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT 0
\r
6500 #define LPD_XPPU_CFG_MASTER_ID08_MID_MASK 0x000003FFU
\r
6502 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6503 #undef LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL
\r
6504 #undef LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT
\r
6505 #undef LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK
\r
6506 #define LPD_XPPU_CFG_MASTER_ID09_MIDP_DEFVAL 0x00000000
\r
6507 #define LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT 31
\r
6508 #define LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK 0x80000000U
\r
6510 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6511 #undef LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL
\r
6512 #undef LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT
\r
6513 #undef LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK
\r
6514 #define LPD_XPPU_CFG_MASTER_ID09_MIDR_DEFVAL 0x00000000
\r
6515 #define LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT 30
\r
6516 #define LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK 0x40000000U
\r
6518 /*Mask to be applied before comparing*/
\r
6519 #undef LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL
\r
6520 #undef LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT
\r
6521 #undef LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK
\r
6522 #define LPD_XPPU_CFG_MASTER_ID09_MIDM_DEFVAL 0x00000000
\r
6523 #define LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT 16
\r
6524 #define LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK 0x03FF0000U
\r
6526 /*Programmable Master ID*/
\r
6527 #undef LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL
\r
6528 #undef LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT
\r
6529 #undef LPD_XPPU_CFG_MASTER_ID09_MID_MASK
\r
6530 #define LPD_XPPU_CFG_MASTER_ID09_MID_DEFVAL 0x00000000
\r
6531 #define LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT 0
\r
6532 #define LPD_XPPU_CFG_MASTER_ID09_MID_MASK 0x000003FFU
\r
6534 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6535 #undef LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL
\r
6536 #undef LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT
\r
6537 #undef LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK
\r
6538 #define LPD_XPPU_CFG_MASTER_ID10_MIDP_DEFVAL 0x00000000
\r
6539 #define LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT 31
\r
6540 #define LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK 0x80000000U
\r
6542 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6543 #undef LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL
\r
6544 #undef LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT
\r
6545 #undef LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK
\r
6546 #define LPD_XPPU_CFG_MASTER_ID10_MIDR_DEFVAL 0x00000000
\r
6547 #define LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT 30
\r
6548 #define LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK 0x40000000U
\r
6550 /*Mask to be applied before comparing*/
\r
6551 #undef LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL
\r
6552 #undef LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT
\r
6553 #undef LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK
\r
6554 #define LPD_XPPU_CFG_MASTER_ID10_MIDM_DEFVAL 0x00000000
\r
6555 #define LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT 16
\r
6556 #define LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK 0x03FF0000U
\r
6558 /*Programmable Master ID*/
\r
6559 #undef LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL
\r
6560 #undef LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT
\r
6561 #undef LPD_XPPU_CFG_MASTER_ID10_MID_MASK
\r
6562 #define LPD_XPPU_CFG_MASTER_ID10_MID_DEFVAL 0x00000000
\r
6563 #define LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT 0
\r
6564 #define LPD_XPPU_CFG_MASTER_ID10_MID_MASK 0x000003FFU
\r
6566 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6567 #undef LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL
\r
6568 #undef LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT
\r
6569 #undef LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK
\r
6570 #define LPD_XPPU_CFG_MASTER_ID11_MIDP_DEFVAL 0x00000000
\r
6571 #define LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT 31
\r
6572 #define LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK 0x80000000U
\r
6574 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6575 #undef LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL
\r
6576 #undef LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT
\r
6577 #undef LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK
\r
6578 #define LPD_XPPU_CFG_MASTER_ID11_MIDR_DEFVAL 0x00000000
\r
6579 #define LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT 30
\r
6580 #define LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK 0x40000000U
\r
6582 /*Mask to be applied before comparing*/
\r
6583 #undef LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL
\r
6584 #undef LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT
\r
6585 #undef LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK
\r
6586 #define LPD_XPPU_CFG_MASTER_ID11_MIDM_DEFVAL 0x00000000
\r
6587 #define LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT 16
\r
6588 #define LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK 0x03FF0000U
\r
6590 /*Programmable Master ID*/
\r
6591 #undef LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL
\r
6592 #undef LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT
\r
6593 #undef LPD_XPPU_CFG_MASTER_ID11_MID_MASK
\r
6594 #define LPD_XPPU_CFG_MASTER_ID11_MID_DEFVAL 0x00000000
\r
6595 #define LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT 0
\r
6596 #define LPD_XPPU_CFG_MASTER_ID11_MID_MASK 0x000003FFU
\r
6598 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6599 #undef LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL
\r
6600 #undef LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT
\r
6601 #undef LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK
\r
6602 #define LPD_XPPU_CFG_MASTER_ID12_MIDP_DEFVAL 0x00000000
\r
6603 #define LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT 31
\r
6604 #define LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK 0x80000000U
\r
6606 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6607 #undef LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL
\r
6608 #undef LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT
\r
6609 #undef LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK
\r
6610 #define LPD_XPPU_CFG_MASTER_ID12_MIDR_DEFVAL 0x00000000
\r
6611 #define LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT 30
\r
6612 #define LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK 0x40000000U
\r
6614 /*Mask to be applied before comparing*/
\r
6615 #undef LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL
\r
6616 #undef LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT
\r
6617 #undef LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK
\r
6618 #define LPD_XPPU_CFG_MASTER_ID12_MIDM_DEFVAL 0x00000000
\r
6619 #define LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT 16
\r
6620 #define LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK 0x03FF0000U
\r
6622 /*Programmable Master ID*/
\r
6623 #undef LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL
\r
6624 #undef LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT
\r
6625 #undef LPD_XPPU_CFG_MASTER_ID12_MID_MASK
\r
6626 #define LPD_XPPU_CFG_MASTER_ID12_MID_DEFVAL 0x00000000
\r
6627 #define LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT 0
\r
6628 #define LPD_XPPU_CFG_MASTER_ID12_MID_MASK 0x000003FFU
\r
6630 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6631 #undef LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL
\r
6632 #undef LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT
\r
6633 #undef LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK
\r
6634 #define LPD_XPPU_CFG_MASTER_ID13_MIDP_DEFVAL 0x00000000
\r
6635 #define LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT 31
\r
6636 #define LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK 0x80000000U
\r
6638 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6639 #undef LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL
\r
6640 #undef LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT
\r
6641 #undef LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK
\r
6642 #define LPD_XPPU_CFG_MASTER_ID13_MIDR_DEFVAL 0x00000000
\r
6643 #define LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT 30
\r
6644 #define LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK 0x40000000U
\r
6646 /*Mask to be applied before comparing*/
\r
6647 #undef LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL
\r
6648 #undef LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT
\r
6649 #undef LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK
\r
6650 #define LPD_XPPU_CFG_MASTER_ID13_MIDM_DEFVAL 0x00000000
\r
6651 #define LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT 16
\r
6652 #define LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK 0x03FF0000U
\r
6654 /*Programmable Master ID*/
\r
6655 #undef LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL
\r
6656 #undef LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT
\r
6657 #undef LPD_XPPU_CFG_MASTER_ID13_MID_MASK
\r
6658 #define LPD_XPPU_CFG_MASTER_ID13_MID_DEFVAL 0x00000000
\r
6659 #define LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT 0
\r
6660 #define LPD_XPPU_CFG_MASTER_ID13_MID_MASK 0x000003FFU
\r
6662 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6663 #undef LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL
\r
6664 #undef LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT
\r
6665 #undef LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK
\r
6666 #define LPD_XPPU_CFG_MASTER_ID14_MIDP_DEFVAL 0x00000000
\r
6667 #define LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT 31
\r
6668 #define LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK 0x80000000U
\r
6670 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6671 #undef LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL
\r
6672 #undef LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT
\r
6673 #undef LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK
\r
6674 #define LPD_XPPU_CFG_MASTER_ID14_MIDR_DEFVAL 0x00000000
\r
6675 #define LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT 30
\r
6676 #define LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK 0x40000000U
\r
6678 /*Mask to be applied before comparing*/
\r
6679 #undef LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL
\r
6680 #undef LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT
\r
6681 #undef LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK
\r
6682 #define LPD_XPPU_CFG_MASTER_ID14_MIDM_DEFVAL 0x00000000
\r
6683 #define LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT 16
\r
6684 #define LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK 0x03FF0000U
\r
6686 /*Programmable Master ID*/
\r
6687 #undef LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL
\r
6688 #undef LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT
\r
6689 #undef LPD_XPPU_CFG_MASTER_ID14_MID_MASK
\r
6690 #define LPD_XPPU_CFG_MASTER_ID14_MID_DEFVAL 0x00000000
\r
6691 #define LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT 0
\r
6692 #define LPD_XPPU_CFG_MASTER_ID14_MID_MASK 0x000003FFU
\r
6694 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6695 #undef LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL
\r
6696 #undef LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT
\r
6697 #undef LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK
\r
6698 #define LPD_XPPU_CFG_MASTER_ID15_MIDP_DEFVAL 0x00000000
\r
6699 #define LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT 31
\r
6700 #define LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK 0x80000000U
\r
6702 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6703 #undef LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL
\r
6704 #undef LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT
\r
6705 #undef LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK
\r
6706 #define LPD_XPPU_CFG_MASTER_ID15_MIDR_DEFVAL 0x00000000
\r
6707 #define LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT 30
\r
6708 #define LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK 0x40000000U
\r
6710 /*Mask to be applied before comparing*/
\r
6711 #undef LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL
\r
6712 #undef LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT
\r
6713 #undef LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK
\r
6714 #define LPD_XPPU_CFG_MASTER_ID15_MIDM_DEFVAL 0x00000000
\r
6715 #define LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT 16
\r
6716 #define LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK 0x03FF0000U
\r
6718 /*Programmable Master ID*/
\r
6719 #undef LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL
\r
6720 #undef LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT
\r
6721 #undef LPD_XPPU_CFG_MASTER_ID15_MID_MASK
\r
6722 #define LPD_XPPU_CFG_MASTER_ID15_MID_DEFVAL 0x00000000
\r
6723 #define LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT 0
\r
6724 #define LPD_XPPU_CFG_MASTER_ID15_MID_MASK 0x000003FFU
\r
6726 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6727 #undef LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL
\r
6728 #undef LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT
\r
6729 #undef LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK
\r
6730 #define LPD_XPPU_CFG_MASTER_ID16_MIDP_DEFVAL 0x00000000
\r
6731 #define LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT 31
\r
6732 #define LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK 0x80000000U
\r
6734 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6735 #undef LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL
\r
6736 #undef LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT
\r
6737 #undef LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK
\r
6738 #define LPD_XPPU_CFG_MASTER_ID16_MIDR_DEFVAL 0x00000000
\r
6739 #define LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT 30
\r
6740 #define LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK 0x40000000U
\r
6742 /*Mask to be applied before comparing*/
\r
6743 #undef LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL
\r
6744 #undef LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT
\r
6745 #undef LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK
\r
6746 #define LPD_XPPU_CFG_MASTER_ID16_MIDM_DEFVAL 0x00000000
\r
6747 #define LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT 16
\r
6748 #define LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK 0x03FF0000U
\r
6750 /*Programmable Master ID*/
\r
6751 #undef LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL
\r
6752 #undef LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT
\r
6753 #undef LPD_XPPU_CFG_MASTER_ID16_MID_MASK
\r
6754 #define LPD_XPPU_CFG_MASTER_ID16_MID_DEFVAL 0x00000000
\r
6755 #define LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT 0
\r
6756 #define LPD_XPPU_CFG_MASTER_ID16_MID_MASK 0x000003FFU
\r
6758 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6759 #undef LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL
\r
6760 #undef LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT
\r
6761 #undef LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK
\r
6762 #define LPD_XPPU_CFG_MASTER_ID17_MIDP_DEFVAL 0x00000000
\r
6763 #define LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT 31
\r
6764 #define LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK 0x80000000U
\r
6766 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6767 #undef LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL
\r
6768 #undef LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT
\r
6769 #undef LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK
\r
6770 #define LPD_XPPU_CFG_MASTER_ID17_MIDR_DEFVAL 0x00000000
\r
6771 #define LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT 30
\r
6772 #define LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK 0x40000000U
\r
6774 /*Mask to be applied before comparing*/
\r
6775 #undef LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL
\r
6776 #undef LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT
\r
6777 #undef LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK
\r
6778 #define LPD_XPPU_CFG_MASTER_ID17_MIDM_DEFVAL 0x00000000
\r
6779 #define LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT 16
\r
6780 #define LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK 0x03FF0000U
\r
6782 /*Programmable Master ID*/
\r
6783 #undef LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL
\r
6784 #undef LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT
\r
6785 #undef LPD_XPPU_CFG_MASTER_ID17_MID_MASK
\r
6786 #define LPD_XPPU_CFG_MASTER_ID17_MID_DEFVAL 0x00000000
\r
6787 #define LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT 0
\r
6788 #define LPD_XPPU_CFG_MASTER_ID17_MID_MASK 0x000003FFU
\r
6790 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6791 #undef LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL
\r
6792 #undef LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT
\r
6793 #undef LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK
\r
6794 #define LPD_XPPU_CFG_MASTER_ID18_MIDP_DEFVAL 0x00000000
\r
6795 #define LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT 31
\r
6796 #define LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK 0x80000000U
\r
6798 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6799 #undef LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL
\r
6800 #undef LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT
\r
6801 #undef LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK
\r
6802 #define LPD_XPPU_CFG_MASTER_ID18_MIDR_DEFVAL 0x00000000
\r
6803 #define LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT 30
\r
6804 #define LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK 0x40000000U
\r
6806 /*Mask to be applied before comparing*/
\r
6807 #undef LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL
\r
6808 #undef LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT
\r
6809 #undef LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK
\r
6810 #define LPD_XPPU_CFG_MASTER_ID18_MIDM_DEFVAL 0x00000000
\r
6811 #define LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT 16
\r
6812 #define LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK 0x03FF0000U
\r
6814 /*Programmable Master ID*/
\r
6815 #undef LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL
\r
6816 #undef LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT
\r
6817 #undef LPD_XPPU_CFG_MASTER_ID18_MID_MASK
\r
6818 #define LPD_XPPU_CFG_MASTER_ID18_MID_DEFVAL 0x00000000
\r
6819 #define LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT 0
\r
6820 #define LPD_XPPU_CFG_MASTER_ID18_MID_MASK 0x000003FFU
\r
6822 /*Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)*/
\r
6823 #undef LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL
\r
6824 #undef LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT
\r
6825 #undef LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK
\r
6826 #define LPD_XPPU_CFG_MASTER_ID19_MIDP_DEFVAL 0x00000000
\r
6827 #define LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT 31
\r
6828 #define LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK 0x80000000U
\r
6830 /*If set, only read transactions are allowed for the masters matching this register*/
\r
6831 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL
\r
6832 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT
\r
6833 #undef LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK
\r
6834 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_DEFVAL 0x00000000
\r
6835 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT 30
\r
6836 #define LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK 0x40000000U
\r
6838 /*Mask to be applied before comparing*/
\r
6839 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL
\r
6840 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT
\r
6841 #undef LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK
\r
6842 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_DEFVAL 0x00000000
\r
6843 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT 16
\r
6844 #define LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK 0x03FF0000U
\r
6846 /*Programmable Master ID*/
\r
6847 #undef LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL
\r
6848 #undef LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT
\r
6849 #undef LPD_XPPU_CFG_MASTER_ID19_MID_MASK
\r
6850 #define LPD_XPPU_CFG_MASTER_ID19_MID_DEFVAL 0x00000000
\r
6851 #define LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT 0
\r
6852 #define LPD_XPPU_CFG_MASTER_ID19_MID_MASK 0x000003FFU
\r
6853 #ifdef __cplusplus
\r
6857 #ifdef __cplusplus
\r
projects / freertos / blob