1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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4 <meta http-equiv="content-type" content="text/html;charset=UTF-8">
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5 <title>Zynq PS configuration detail</title>
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6 <style type="text/css">.sitename { background-color: #EEE;border:2px ridge #FFCF01;color: #B20838; font-size:22px; font-style:oblique; font-weight:bold;margin:0px 0px 10px 0px;padding:5px 0px; text-align:center; z-index: 3; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.navpath {color: #FFCF01; font-size:8px;padding: 7px 2px 2px 11px; text-transform: capitalize; z-index:2;}.navbar { background-color: #B20838; background-color: #EE3424;color: #fff;border: 1px solid #000; border-left: 0px solid #000; border-right: 0px solid #000; font-family: arial, sans-serif; font-weight: bold;height:50px; letter-spacing: 2px; text-transform: uppercase;position:fixed;top:0px;left:0px;right:0px; z-index: 0; /* -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px; */}.navlink_container { text-align:center;position: absolute;bottom:-1px;}.navbar a {color: #FFF;}.navbar a:hover {color: #EC891D;}.navbar ul { margin-left: 0px;height: 70px;overflow: hidden;}.navbar li { background-color: #B20838;padding: 4px 400px 4px 400px;float: left; font-size:24px;width: 800px;}.navbar li:hover { background-color: #000;color: #eee;}.navbar li#last { padding-right: 10px; border-right: 1px solid #050505; background-image: none;}.nav_splash {width: 80%;float:right; z-index: 0;}.search_form {position:fixed;top:25px;right:5px; z-index:2;}.action_tray {padding:5px;position: fixed;top: 57px;width: 210px;}.action_tray_header { text-align: center; background-color: #DDD;border: 2px groove #FFCF01; margin-bottom: 10px; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.action_tray_header:hover { background-color: #eee;}.action_container {padding:10px 5px; text-align: center;}.action { background-color: #FFF;border: 1px outset #B20838;padding: 5px 0px; font-weight:bolder; margin-bottom: 2px; -moz-border-radius: 7px; -webkit-border-radius: 7px; -khtml-border-radius: 7px; border-radius: 7px; text-transform:uppercase;color: #B20838; }.action:hover {border: 1px inset #000; background-color: #FFCF01;color: #000;}.content_container { background-color:#fff;border: 0px solid #000; border-left: 1px solid #000;color: #000;overflow:auto;padding: 10px;position:fixed;left: 224px;top: 52px;right: 0px;bottom:0px; text-align: left; padding-right:25px; z-index:1;}.SelectButtons { background-color:white; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 10px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.viewButtons { background-color:#F3F781; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 0px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.db_selector {margin:10px 0px 10px 0px;}.db_selector_title { background-color: #00FFFF;border: 1px solid #000; margin-bottom:5px; font-weight:bold;padding:5px 3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select { background-color: #FFEFC0; font-weight:bolder;padding:3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select:hover { background-color: #AFEFF0; }</style>
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7 <script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_3_0"; window.location = '#psu_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_2_0"; window.location = '#psu_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#psu_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_1_0"; window.location = '#psu_mio_init_data_1_0'; }}</script>
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10 <DIV class="navlink_container">
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11 <A id="Summary" href="#">
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13 <DIV class="navlink">Zynq PS Register Summary Viewer
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19 <DIV class="action_tray">
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20 <A id="Report" href="#">
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21 <DIV class="sitename">Zynq PS7 Summary Report
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24 <DIV class="viewButtons">User Configurations
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26 <DIV class="viewButtons">
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27 <A id="MIO_Configurations" href="#ZynqPerTab">
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28 <DIV class="viewButtonHalf">MIO Configurations
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31 <HR class="action_separator">
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32 <A id="CLK_Configurations" href="#ClockInfoTab">
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33 <DIV class="viewButtonHalf">CLK Configurations
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36 <HR class="action_separator">
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37 <A id="DDR_Configurations" href="#DDRInfoTab">
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38 <DIV class="viewButtonHalf">DDR Configurations
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41 <HR class="action_separator">
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42 <A id="SMC_Configurations" href="#SMCInfoTab">
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43 <DIV class="viewButtonHalf">SMC Configurations
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47 <DIV class="db_selector">
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48 <DIV class="db_selector_title">Select Version:
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49 <select id="db_selection" class="db_selection" onChange="ChangeSilRegLink(this.id)" width="210" style="width: 210px">
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50 <option value="Silicon3.0">Silicon 3.0</option>
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51 <option value="Silicon2.0">Silicon 2.0</option>
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52 <option value="Silicon1.0">Silicon 1.0</option>
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56 <DIV class="viewButtons">Zynq Register View
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58 <DIV class="action_container">
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59 <A id="MIO_Registers" href="#psu_mio_init_data">
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60 <DIV class="action">MIO Registers
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63 <A id="PLL_Registers" href="#psu_pll_init_data">
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64 <DIV class="action">PLL Registers
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67 <A id="Clock_Registers" href="#psu_clock_init_data">
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68 <DIV class="action">Clock Registers
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71 <A id="DDR_Registers" href="#psu_ddr_init_data">
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72 <DIV class="action">DDR Registers
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75 <A id="Peri_Registers" href="#psu_peripherals_init_data">
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76 <DIV class="action">Peripherals Registers
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80 <DIV class="content_container">This design is targeted for7vx485tboard (part number: )
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83 <H1>Zynq Design Summary</H1>
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84 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
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86 <TD width=20% BGCOLOR=#C0C0FF>
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89 <TD width=80% BGCOLOR=#E6E6E6>
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113 <TD width=80% BGCOLOR=#E6E6E6>
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114 Zynq PS Configuration Report with register details
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118 <TD width=20% BGCOLOR=#C0C0FF>
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121 <TD width=80% BGCOLOR=#E6E6E6>
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126 <H2><a name="ZynqPerTab">MIO Table View</a></H2>
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127 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
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156 Single Quad SPI (4bit)
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179 Single Quad SPI (4bit)
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202 Single Quad SPI (4bit)
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\r
957 <TD width=10% BGCOLOR=#FBF5EF>
\r
960 <TD width=10% BGCOLOR=#FBF5EF>
\r
963 <TD width=10% BGCOLOR=#FBF5EF>
\r
966 <TD width=10% BGCOLOR=#FBF5EF>
\r
969 <TD width=10% BGCOLOR=#FBF5EF>
\r
972 <TD width=10% BGCOLOR=#FBF5EF>
\r
975 <TD width=10% BGCOLOR=#FBF5EF>
\r
980 <TD width=10% BGCOLOR=#FBF5EF>
\r
983 <TD width=10% BGCOLOR=#FBF5EF>
\r
986 <TD width=10% BGCOLOR=#FBF5EF>
\r
989 <TD width=10% BGCOLOR=#FBF5EF>
\r
992 <TD width=10% BGCOLOR=#FBF5EF>
\r
995 <TD width=10% BGCOLOR=#FBF5EF>
\r
998 <TD width=10% BGCOLOR=#FBF5EF>
\r
1003 <TD width=10% BGCOLOR=#FBF5EF>
\r
1006 <TD width=10% BGCOLOR=#FBF5EF>
\r
1009 <TD width=10% BGCOLOR=#FBF5EF>
\r
1012 <TD width=10% BGCOLOR=#FBF5EF>
\r
1015 <TD width=10% BGCOLOR=#FBF5EF>
\r
1018 <TD width=10% BGCOLOR=#FBF5EF>
\r
1021 <TD width=10% BGCOLOR=#FBF5EF>
\r
1026 <TD width=10% BGCOLOR=#FBF5EF>
\r
1029 <TD width=10% BGCOLOR=#FBF5EF>
\r
1032 <TD width=10% BGCOLOR=#FBF5EF>
\r
1035 <TD width=10% BGCOLOR=#FBF5EF>
\r
1038 <TD width=10% BGCOLOR=#FBF5EF>
\r
1041 <TD width=10% BGCOLOR=#FBF5EF>
\r
1044 <TD width=10% BGCOLOR=#FBF5EF>
\r
1049 <TD width=10% BGCOLOR=#FBF5EF>
\r
1052 <TD width=10% BGCOLOR=#FBF5EF>
\r
1055 <TD width=10% BGCOLOR=#FBF5EF>
\r
1058 <TD width=10% BGCOLOR=#FBF5EF>
\r
1061 <TD width=10% BGCOLOR=#FBF5EF>
\r
1064 <TD width=10% BGCOLOR=#FBF5EF>
\r
1067 <TD width=10% BGCOLOR=#FBF5EF>
\r
1072 <TD width=10% BGCOLOR=#FBF5EF>
\r
1075 <TD width=10% BGCOLOR=#FBF5EF>
\r
1078 <TD width=10% BGCOLOR=#FBF5EF>
\r
1081 <TD width=10% BGCOLOR=#FBF5EF>
\r
1084 <TD width=10% BGCOLOR=#FBF5EF>
\r
1087 <TD width=10% BGCOLOR=#FBF5EF>
\r
1090 <TD width=10% BGCOLOR=#FBF5EF>
\r
1095 <TD width=10% BGCOLOR=#FBF5EF>
\r
1098 <TD width=10% BGCOLOR=#FBF5EF>
\r
1101 <TD width=10% BGCOLOR=#FBF5EF>
\r
1104 <TD width=10% BGCOLOR=#FBF5EF>
\r
1107 <TD width=10% BGCOLOR=#FBF5EF>
\r
1110 <TD width=10% BGCOLOR=#FBF5EF>
\r
1113 <TD width=10% BGCOLOR=#FBF5EF>
\r
1118 <TD width=10% BGCOLOR=#FBF5EF>
\r
1121 <TD width=10% BGCOLOR=#FBF5EF>
\r
1124 <TD width=10% BGCOLOR=#FBF5EF>
\r
1127 <TD width=10% BGCOLOR=#FBF5EF>
\r
1130 <TD width=10% BGCOLOR=#FBF5EF>
\r
1133 <TD width=10% BGCOLOR=#FBF5EF>
\r
1136 <TD width=10% BGCOLOR=#FBF5EF>
\r
1141 <TD width=10% BGCOLOR=#FBF5EF>
\r
1144 <TD width=10% BGCOLOR=#FBF5EF>
\r
1147 <TD width=10% BGCOLOR=#FBF5EF>
\r
1150 <TD width=10% BGCOLOR=#FBF5EF>
\r
1153 <TD width=10% BGCOLOR=#FBF5EF>
\r
1156 <TD width=10% BGCOLOR=#FBF5EF>
\r
1159 <TD width=10% BGCOLOR=#FBF5EF>
\r
1164 <TD width=10% BGCOLOR=#FBF5EF>
\r
1167 <TD width=10% BGCOLOR=#FBF5EF>
\r
1170 <TD width=10% BGCOLOR=#FBF5EF>
\r
1173 <TD width=10% BGCOLOR=#FBF5EF>
\r
1176 <TD width=10% BGCOLOR=#FBF5EF>
\r
1179 <TD width=10% BGCOLOR=#FBF5EF>
\r
1182 <TD width=10% BGCOLOR=#FBF5EF>
\r
1187 <TD width=10% BGCOLOR=#FBF5EF>
\r
1190 <TD width=10% BGCOLOR=#FBF5EF>
\r
1193 <TD width=10% BGCOLOR=#FBF5EF>
\r
1196 <TD width=10% BGCOLOR=#FBF5EF>
\r
1199 <TD width=10% BGCOLOR=#FBF5EF>
\r
1202 <TD width=10% BGCOLOR=#FBF5EF>
\r
1205 <TD width=10% BGCOLOR=#FBF5EF>
\r
1210 <TD width=10% BGCOLOR=#FBF5EF>
\r
1213 <TD width=10% BGCOLOR=#FBF5EF>
\r
1216 <TD width=10% BGCOLOR=#FBF5EF>
\r
1219 <TD width=10% BGCOLOR=#FBF5EF>
\r
1222 <TD width=10% BGCOLOR=#FBF5EF>
\r
1225 <TD width=10% BGCOLOR=#FBF5EF>
\r
1228 <TD width=10% BGCOLOR=#FBF5EF>
\r
1233 <TD width=10% BGCOLOR=#FBF5EF>
\r
1236 <TD width=10% BGCOLOR=#FBF5EF>
\r
1239 <TD width=10% BGCOLOR=#FBF5EF>
\r
1242 <TD width=10% BGCOLOR=#FBF5EF>
\r
1245 <TD width=10% BGCOLOR=#FBF5EF>
\r
1248 <TD width=10% BGCOLOR=#FBF5EF>
\r
1251 <TD width=10% BGCOLOR=#FBF5EF>
\r
1256 <TD width=10% BGCOLOR=#FBF5EF>
\r
1259 <TD width=10% BGCOLOR=#FBF5EF>
\r
1262 <TD width=10% BGCOLOR=#FBF5EF>
\r
1265 <TD width=10% BGCOLOR=#FBF5EF>
\r
1268 <TD width=10% BGCOLOR=#FBF5EF>
\r
1271 <TD width=10% BGCOLOR=#FBF5EF>
\r
1274 <TD width=10% BGCOLOR=#FBF5EF>
\r
1279 <TD width=10% BGCOLOR=#FBF5EF>
\r
1282 <TD width=10% BGCOLOR=#FBF5EF>
\r
1285 <TD width=10% BGCOLOR=#FBF5EF>
\r
1288 <TD width=10% BGCOLOR=#FBF5EF>
\r
1291 <TD width=10% BGCOLOR=#FBF5EF>
\r
1294 <TD width=10% BGCOLOR=#FBF5EF>
\r
1297 <TD width=10% BGCOLOR=#FBF5EF>
\r
1302 <TD width=10% BGCOLOR=#FBF5EF>
\r
1305 <TD width=10% BGCOLOR=#FBF5EF>
\r
1308 <TD width=10% BGCOLOR=#FBF5EF>
\r
1311 <TD width=10% BGCOLOR=#FBF5EF>
\r
1314 <TD width=10% BGCOLOR=#FBF5EF>
\r
1317 <TD width=10% BGCOLOR=#FBF5EF>
\r
1320 <TD width=10% BGCOLOR=#FBF5EF>
\r
1325 <TD width=10% BGCOLOR=#FBF5EF>
\r
1328 <TD width=10% BGCOLOR=#FBF5EF>
\r
1331 <TD width=10% BGCOLOR=#FBF5EF>
\r
1334 <TD width=10% BGCOLOR=#FBF5EF>
\r
1337 <TD width=10% BGCOLOR=#FBF5EF>
\r
1340 <TD width=10% BGCOLOR=#FBF5EF>
\r
1343 <TD width=10% BGCOLOR=#FBF5EF>
\r
1348 <TD width=10% BGCOLOR=#FBF5EF>
\r
1351 <TD width=10% BGCOLOR=#FBF5EF>
\r
1354 <TD width=10% BGCOLOR=#FBF5EF>
\r
1357 <TD width=10% BGCOLOR=#FBF5EF>
\r
1360 <TD width=10% BGCOLOR=#FBF5EF>
\r
1363 <TD width=10% BGCOLOR=#FBF5EF>
\r
1366 <TD width=10% BGCOLOR=#FBF5EF>
\r
1371 <TD width=10% BGCOLOR=#FBF5EF>
\r
1374 <TD width=10% BGCOLOR=#FBF5EF>
\r
1377 <TD width=10% BGCOLOR=#FBF5EF>
\r
1380 <TD width=10% BGCOLOR=#FBF5EF>
\r
1383 <TD width=10% BGCOLOR=#FBF5EF>
\r
1386 <TD width=10% BGCOLOR=#FBF5EF>
\r
1389 <TD width=10% BGCOLOR=#FBF5EF>
\r
1394 <H2><a name="psu_pll_init_data">psu_pll_init_data</a></H2>
\r
1395 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
1397 <TD width=15% BGCOLOR=#FFC0FF>
\r
1398 <B>Register Name</B>
\r
1400 <TD width=15% BGCOLOR=#FFC0FF>
\r
1403 <TD width=10% BGCOLOR=#FFC0FF>
\r
1406 <TD width=10% BGCOLOR=#FFC0FF>
\r
1409 <TD width=15% BGCOLOR=#FFC0FF>
\r
1410 <B>Reset Value</B>
\r
1412 <TD width=35% BGCOLOR=#FFC0FF>
\r
1413 <B>Description</B>
\r
1417 <TD width=15% BGCOLOR=#FBF5EF>
\r
1418 <A href="#PSU_CRL_APB_RPLL_CTRL">
\r
1419 PSU_CRL_APB_RPLL_CTRL
\r
1422 <TD width=15% BGCOLOR=#FBF5EF>
\r
1425 <TD width=10% BGCOLOR=#FBF5EF>
\r
1428 <TD width=10% BGCOLOR=#FBF5EF>
\r
1431 <TD width=15% BGCOLOR=#FBF5EF>
\r
1434 <TD width=35% BGCOLOR=#FBF5EF>
\r
1435 <B>PLL Basic Control</B>
\r
1439 <TD width=15% BGCOLOR=#FBF5EF>
\r
1440 <A href="#PSU_CRL_APB_RPLL_CTRL">
\r
1441 PSU_CRL_APB_RPLL_CTRL
\r
1444 <TD width=15% BGCOLOR=#FBF5EF>
\r
1447 <TD width=10% BGCOLOR=#FBF5EF>
\r
1450 <TD width=10% BGCOLOR=#FBF5EF>
\r
1453 <TD width=15% BGCOLOR=#FBF5EF>
\r
1456 <TD width=35% BGCOLOR=#FBF5EF>
\r
1457 <B>PLL Basic Control</B>
\r
1461 <TD width=15% BGCOLOR=#FBF5EF>
\r
1462 <A href="#PSU_CRL_APB_RPLL_CTRL">
\r
1463 PSU_CRL_APB_RPLL_CTRL
\r
1466 <TD width=15% BGCOLOR=#FBF5EF>
\r
1469 <TD width=10% BGCOLOR=#FBF5EF>
\r
1472 <TD width=10% BGCOLOR=#FBF5EF>
\r
1475 <TD width=15% BGCOLOR=#FBF5EF>
\r
1478 <TD width=35% BGCOLOR=#FBF5EF>
\r
1479 <B>PLL Basic Control</B>
\r
1483 <TD width=15% BGCOLOR=#FBF5EF>
\r
1484 <A href="#PSU_CRL_APB_RPLL_CTRL">
\r
1485 PSU_CRL_APB_RPLL_CTRL
\r
1488 <TD width=15% BGCOLOR=#FBF5EF>
\r
1491 <TD width=10% BGCOLOR=#FBF5EF>
\r
1494 <TD width=10% BGCOLOR=#FBF5EF>
\r
1497 <TD width=15% BGCOLOR=#FBF5EF>
\r
1500 <TD width=35% BGCOLOR=#FBF5EF>
\r
1501 <B>PLL Basic Control</B>
\r
1505 <TD width=15% BGCOLOR=#FBF5EF>
\r
1506 <A href="#PSU_CRL_APB_RPLL_CTRL">
\r
1507 PSU_CRL_APB_RPLL_CTRL
\r
1510 <TD width=15% BGCOLOR=#FBF5EF>
\r
1513 <TD width=10% BGCOLOR=#FBF5EF>
\r
1516 <TD width=10% BGCOLOR=#FBF5EF>
\r
1519 <TD width=15% BGCOLOR=#FBF5EF>
\r
1522 <TD width=35% BGCOLOR=#FBF5EF>
\r
1523 <B>PLL Basic Control</B>
\r
1527 <TD width=15% BGCOLOR=#FBF5EF>
\r
1528 <A href="#PSU_CRL_APB_RPLL_TO_FPD_CTRL">
\r
1529 PSU_CRL_APB_RPLL_TO_FPD_CTRL
\r
1532 <TD width=15% BGCOLOR=#FBF5EF>
\r
1535 <TD width=10% BGCOLOR=#FBF5EF>
\r
1538 <TD width=10% BGCOLOR=#FBF5EF>
\r
1541 <TD width=15% BGCOLOR=#FBF5EF>
\r
1544 <TD width=35% BGCOLOR=#FBF5EF>
\r
1545 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
1549 <TD width=15% BGCOLOR=#FBF5EF>
\r
1550 <A href="#PSU_CRL_APB_IOPLL_CTRL">
\r
1551 PSU_CRL_APB_IOPLL_CTRL
\r
1554 <TD width=15% BGCOLOR=#FBF5EF>
\r
1557 <TD width=10% BGCOLOR=#FBF5EF>
\r
1560 <TD width=10% BGCOLOR=#FBF5EF>
\r
1563 <TD width=15% BGCOLOR=#FBF5EF>
\r
1566 <TD width=35% BGCOLOR=#FBF5EF>
\r
1567 <B>PLL Basic Control</B>
\r
1571 <TD width=15% BGCOLOR=#FBF5EF>
\r
1572 <A href="#PSU_CRL_APB_IOPLL_CTRL">
\r
1573 PSU_CRL_APB_IOPLL_CTRL
\r
1576 <TD width=15% BGCOLOR=#FBF5EF>
\r
1579 <TD width=10% BGCOLOR=#FBF5EF>
\r
1582 <TD width=10% BGCOLOR=#FBF5EF>
\r
1585 <TD width=15% BGCOLOR=#FBF5EF>
\r
1588 <TD width=35% BGCOLOR=#FBF5EF>
\r
1589 <B>PLL Basic Control</B>
\r
1593 <TD width=15% BGCOLOR=#FBF5EF>
\r
1594 <A href="#PSU_CRL_APB_IOPLL_CTRL">
\r
1595 PSU_CRL_APB_IOPLL_CTRL
\r
1598 <TD width=15% BGCOLOR=#FBF5EF>
\r
1601 <TD width=10% BGCOLOR=#FBF5EF>
\r
1604 <TD width=10% BGCOLOR=#FBF5EF>
\r
1607 <TD width=15% BGCOLOR=#FBF5EF>
\r
1610 <TD width=35% BGCOLOR=#FBF5EF>
\r
1611 <B>PLL Basic Control</B>
\r
1615 <TD width=15% BGCOLOR=#FBF5EF>
\r
1616 <A href="#PSU_CRL_APB_IOPLL_CTRL">
\r
1617 PSU_CRL_APB_IOPLL_CTRL
\r
1620 <TD width=15% BGCOLOR=#FBF5EF>
\r
1623 <TD width=10% BGCOLOR=#FBF5EF>
\r
1626 <TD width=10% BGCOLOR=#FBF5EF>
\r
1629 <TD width=15% BGCOLOR=#FBF5EF>
\r
1632 <TD width=35% BGCOLOR=#FBF5EF>
\r
1633 <B>PLL Basic Control</B>
\r
1637 <TD width=15% BGCOLOR=#FBF5EF>
\r
1638 <A href="#PSU_CRL_APB_IOPLL_CTRL">
\r
1639 PSU_CRL_APB_IOPLL_CTRL
\r
1642 <TD width=15% BGCOLOR=#FBF5EF>
\r
1645 <TD width=10% BGCOLOR=#FBF5EF>
\r
1648 <TD width=10% BGCOLOR=#FBF5EF>
\r
1651 <TD width=15% BGCOLOR=#FBF5EF>
\r
1654 <TD width=35% BGCOLOR=#FBF5EF>
\r
1655 <B>PLL Basic Control</B>
\r
1659 <TD width=15% BGCOLOR=#FBF5EF>
\r
1660 <A href="#PSU_CRL_APB_IOPLL_TO_FPD_CTRL">
\r
1661 PSU_CRL_APB_IOPLL_TO_FPD_CTRL
\r
1664 <TD width=15% BGCOLOR=#FBF5EF>
\r
1667 <TD width=10% BGCOLOR=#FBF5EF>
\r
1670 <TD width=10% BGCOLOR=#FBF5EF>
\r
1673 <TD width=15% BGCOLOR=#FBF5EF>
\r
1676 <TD width=35% BGCOLOR=#FBF5EF>
\r
1677 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
1681 <TD width=15% BGCOLOR=#FBF5EF>
\r
1682 <A href="#PSU_CRF_APB_APLL_CTRL">
\r
1683 PSU_CRF_APB_APLL_CTRL
\r
1686 <TD width=15% BGCOLOR=#FBF5EF>
\r
1689 <TD width=10% BGCOLOR=#FBF5EF>
\r
1692 <TD width=10% BGCOLOR=#FBF5EF>
\r
1695 <TD width=15% BGCOLOR=#FBF5EF>
\r
1698 <TD width=35% BGCOLOR=#FBF5EF>
\r
1699 <B>PLL Basic Control</B>
\r
1703 <TD width=15% BGCOLOR=#FBF5EF>
\r
1704 <A href="#PSU_CRF_APB_APLL_CTRL">
\r
1705 PSU_CRF_APB_APLL_CTRL
\r
1708 <TD width=15% BGCOLOR=#FBF5EF>
\r
1711 <TD width=10% BGCOLOR=#FBF5EF>
\r
1714 <TD width=10% BGCOLOR=#FBF5EF>
\r
1717 <TD width=15% BGCOLOR=#FBF5EF>
\r
1720 <TD width=35% BGCOLOR=#FBF5EF>
\r
1721 <B>PLL Basic Control</B>
\r
1725 <TD width=15% BGCOLOR=#FBF5EF>
\r
1726 <A href="#PSU_CRF_APB_APLL_CTRL">
\r
1727 PSU_CRF_APB_APLL_CTRL
\r
1730 <TD width=15% BGCOLOR=#FBF5EF>
\r
1733 <TD width=10% BGCOLOR=#FBF5EF>
\r
1736 <TD width=10% BGCOLOR=#FBF5EF>
\r
1739 <TD width=15% BGCOLOR=#FBF5EF>
\r
1742 <TD width=35% BGCOLOR=#FBF5EF>
\r
1743 <B>PLL Basic Control</B>
\r
1747 <TD width=15% BGCOLOR=#FBF5EF>
\r
1748 <A href="#PSU_CRF_APB_APLL_CTRL">
\r
1749 PSU_CRF_APB_APLL_CTRL
\r
1752 <TD width=15% BGCOLOR=#FBF5EF>
\r
1755 <TD width=10% BGCOLOR=#FBF5EF>
\r
1758 <TD width=10% BGCOLOR=#FBF5EF>
\r
1761 <TD width=15% BGCOLOR=#FBF5EF>
\r
1764 <TD width=35% BGCOLOR=#FBF5EF>
\r
1765 <B>PLL Basic Control</B>
\r
1769 <TD width=15% BGCOLOR=#FBF5EF>
\r
1770 <A href="#PSU_CRF_APB_APLL_CTRL">
\r
1771 PSU_CRF_APB_APLL_CTRL
\r
1774 <TD width=15% BGCOLOR=#FBF5EF>
\r
1777 <TD width=10% BGCOLOR=#FBF5EF>
\r
1780 <TD width=10% BGCOLOR=#FBF5EF>
\r
1783 <TD width=15% BGCOLOR=#FBF5EF>
\r
1786 <TD width=35% BGCOLOR=#FBF5EF>
\r
1787 <B>PLL Basic Control</B>
\r
1791 <TD width=15% BGCOLOR=#FBF5EF>
\r
1792 <A href="#PSU_CRF_APB_APLL_TO_LPD_CTRL">
\r
1793 PSU_CRF_APB_APLL_TO_LPD_CTRL
\r
1796 <TD width=15% BGCOLOR=#FBF5EF>
\r
1799 <TD width=10% BGCOLOR=#FBF5EF>
\r
1802 <TD width=10% BGCOLOR=#FBF5EF>
\r
1805 <TD width=15% BGCOLOR=#FBF5EF>
\r
1808 <TD width=35% BGCOLOR=#FBF5EF>
\r
1809 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
1813 <TD width=15% BGCOLOR=#FBF5EF>
\r
1814 <A href="#PSU_CRF_APB_DPLL_CTRL">
\r
1815 PSU_CRF_APB_DPLL_CTRL
\r
1818 <TD width=15% BGCOLOR=#FBF5EF>
\r
1821 <TD width=10% BGCOLOR=#FBF5EF>
\r
1824 <TD width=10% BGCOLOR=#FBF5EF>
\r
1827 <TD width=15% BGCOLOR=#FBF5EF>
\r
1830 <TD width=35% BGCOLOR=#FBF5EF>
\r
1831 <B>PLL Basic Control</B>
\r
1835 <TD width=15% BGCOLOR=#FBF5EF>
\r
1836 <A href="#PSU_CRF_APB_DPLL_CTRL">
\r
1837 PSU_CRF_APB_DPLL_CTRL
\r
1840 <TD width=15% BGCOLOR=#FBF5EF>
\r
1843 <TD width=10% BGCOLOR=#FBF5EF>
\r
1846 <TD width=10% BGCOLOR=#FBF5EF>
\r
1849 <TD width=15% BGCOLOR=#FBF5EF>
\r
1852 <TD width=35% BGCOLOR=#FBF5EF>
\r
1853 <B>PLL Basic Control</B>
\r
1857 <TD width=15% BGCOLOR=#FBF5EF>
\r
1858 <A href="#PSU_CRF_APB_DPLL_CTRL">
\r
1859 PSU_CRF_APB_DPLL_CTRL
\r
1862 <TD width=15% BGCOLOR=#FBF5EF>
\r
1865 <TD width=10% BGCOLOR=#FBF5EF>
\r
1868 <TD width=10% BGCOLOR=#FBF5EF>
\r
1871 <TD width=15% BGCOLOR=#FBF5EF>
\r
1874 <TD width=35% BGCOLOR=#FBF5EF>
\r
1875 <B>PLL Basic Control</B>
\r
1879 <TD width=15% BGCOLOR=#FBF5EF>
\r
1880 <A href="#PSU_CRF_APB_DPLL_CTRL">
\r
1881 PSU_CRF_APB_DPLL_CTRL
\r
1884 <TD width=15% BGCOLOR=#FBF5EF>
\r
1887 <TD width=10% BGCOLOR=#FBF5EF>
\r
1890 <TD width=10% BGCOLOR=#FBF5EF>
\r
1893 <TD width=15% BGCOLOR=#FBF5EF>
\r
1896 <TD width=35% BGCOLOR=#FBF5EF>
\r
1897 <B>PLL Basic Control</B>
\r
1901 <TD width=15% BGCOLOR=#FBF5EF>
\r
1902 <A href="#PSU_CRF_APB_DPLL_CTRL">
\r
1903 PSU_CRF_APB_DPLL_CTRL
\r
1906 <TD width=15% BGCOLOR=#FBF5EF>
\r
1909 <TD width=10% BGCOLOR=#FBF5EF>
\r
1912 <TD width=10% BGCOLOR=#FBF5EF>
\r
1915 <TD width=15% BGCOLOR=#FBF5EF>
\r
1918 <TD width=35% BGCOLOR=#FBF5EF>
\r
1919 <B>PLL Basic Control</B>
\r
1923 <TD width=15% BGCOLOR=#FBF5EF>
\r
1924 <A href="#PSU_CRF_APB_DPLL_TO_LPD_CTRL">
\r
1925 PSU_CRF_APB_DPLL_TO_LPD_CTRL
\r
1928 <TD width=15% BGCOLOR=#FBF5EF>
\r
1931 <TD width=10% BGCOLOR=#FBF5EF>
\r
1934 <TD width=10% BGCOLOR=#FBF5EF>
\r
1937 <TD width=15% BGCOLOR=#FBF5EF>
\r
1940 <TD width=35% BGCOLOR=#FBF5EF>
\r
1941 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
1945 <TD width=15% BGCOLOR=#FBF5EF>
\r
1946 <A href="#PSU_CRF_APB_VPLL_CTRL">
\r
1947 PSU_CRF_APB_VPLL_CTRL
\r
1950 <TD width=15% BGCOLOR=#FBF5EF>
\r
1953 <TD width=10% BGCOLOR=#FBF5EF>
\r
1956 <TD width=10% BGCOLOR=#FBF5EF>
\r
1959 <TD width=15% BGCOLOR=#FBF5EF>
\r
1962 <TD width=35% BGCOLOR=#FBF5EF>
\r
1963 <B>PLL Basic Control</B>
\r
1967 <TD width=15% BGCOLOR=#FBF5EF>
\r
1968 <A href="#PSU_CRF_APB_VPLL_CTRL">
\r
1969 PSU_CRF_APB_VPLL_CTRL
\r
1972 <TD width=15% BGCOLOR=#FBF5EF>
\r
1975 <TD width=10% BGCOLOR=#FBF5EF>
\r
1978 <TD width=10% BGCOLOR=#FBF5EF>
\r
1981 <TD width=15% BGCOLOR=#FBF5EF>
\r
1984 <TD width=35% BGCOLOR=#FBF5EF>
\r
1985 <B>PLL Basic Control</B>
\r
1989 <TD width=15% BGCOLOR=#FBF5EF>
\r
1990 <A href="#PSU_CRF_APB_VPLL_CTRL">
\r
1991 PSU_CRF_APB_VPLL_CTRL
\r
1994 <TD width=15% BGCOLOR=#FBF5EF>
\r
1997 <TD width=10% BGCOLOR=#FBF5EF>
\r
2000 <TD width=10% BGCOLOR=#FBF5EF>
\r
2003 <TD width=15% BGCOLOR=#FBF5EF>
\r
2006 <TD width=35% BGCOLOR=#FBF5EF>
\r
2007 <B>PLL Basic Control</B>
\r
2011 <TD width=15% BGCOLOR=#FBF5EF>
\r
2012 <A href="#PSU_CRF_APB_VPLL_CTRL">
\r
2013 PSU_CRF_APB_VPLL_CTRL
\r
2016 <TD width=15% BGCOLOR=#FBF5EF>
\r
2019 <TD width=10% BGCOLOR=#FBF5EF>
\r
2022 <TD width=10% BGCOLOR=#FBF5EF>
\r
2025 <TD width=15% BGCOLOR=#FBF5EF>
\r
2028 <TD width=35% BGCOLOR=#FBF5EF>
\r
2029 <B>PLL Basic Control</B>
\r
2033 <TD width=15% BGCOLOR=#FBF5EF>
\r
2034 <A href="#PSU_CRF_APB_VPLL_CTRL">
\r
2035 PSU_CRF_APB_VPLL_CTRL
\r
2038 <TD width=15% BGCOLOR=#FBF5EF>
\r
2041 <TD width=10% BGCOLOR=#FBF5EF>
\r
2044 <TD width=10% BGCOLOR=#FBF5EF>
\r
2047 <TD width=15% BGCOLOR=#FBF5EF>
\r
2050 <TD width=35% BGCOLOR=#FBF5EF>
\r
2051 <B>PLL Basic Control</B>
\r
2055 <TD width=15% BGCOLOR=#FBF5EF>
\r
2056 <A href="#PSU_CRF_APB_VPLL_TO_LPD_CTRL">
\r
2057 PSU_CRF_APB_VPLL_TO_LPD_CTRL
\r
2060 <TD width=15% BGCOLOR=#FBF5EF>
\r
2063 <TD width=10% BGCOLOR=#FBF5EF>
\r
2066 <TD width=10% BGCOLOR=#FBF5EF>
\r
2069 <TD width=15% BGCOLOR=#FBF5EF>
\r
2072 <TD width=35% BGCOLOR=#FBF5EF>
\r
2073 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
2078 <H2><a name="psu_pll_init_data">psu_pll_init_data</a></H2>
\r
2079 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2081 <TD width=15% BGCOLOR=#FFC0FF>
\r
2082 <B>Register Name</B>
\r
2084 <TD width=15% BGCOLOR=#FFC0FF>
\r
2087 <TD width=10% BGCOLOR=#FFC0FF>
\r
2090 <TD width=10% BGCOLOR=#FFC0FF>
\r
2093 <TD width=15% BGCOLOR=#FFC0FF>
\r
2094 <B>Reset Value</B>
\r
2096 <TD width=35% BGCOLOR=#FFC0FF>
\r
2097 <B>Description</B>
\r
2100 <H1>RPLL INIT</H1>
\r
2101 <H1>UPDATE FB_DIV</H1>
\r
2102 <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2>
\r
2103 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2105 <TD width=15% BGCOLOR=#FFFF00>
\r
2106 <B>Register Name</B>
\r
2108 <TD width=15% BGCOLOR=#FFFF00>
\r
2111 <TD width=10% BGCOLOR=#FFFF00>
\r
2114 <TD width=10% BGCOLOR=#FFFF00>
\r
2117 <TD width=15% BGCOLOR=#FFFF00>
\r
2118 <B>Reset Value</B>
\r
2120 <TD width=35% BGCOLOR=#FFFF00>
\r
2121 <B>Description</B>
\r
2125 <TD width=15% BGCOLOR=#FBF5EF>
\r
2128 <TD width=15% BGCOLOR=#FBF5EF>
\r
2131 <TD width=10% BGCOLOR=#FBF5EF>
\r
2134 <TD width=10% BGCOLOR=#FBF5EF>
\r
2137 <TD width=15% BGCOLOR=#FBF5EF>
\r
2140 <TD width=35% BGCOLOR=#FBF5EF>
\r
2146 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2148 <TD width=15% BGCOLOR=#C0FFC0>
\r
2151 <TD width=15% BGCOLOR=#C0FFC0>
\r
2154 <TD width=10% BGCOLOR=#C0FFC0>
\r
2157 <TD width=10% BGCOLOR=#C0FFC0>
\r
2160 <TD width=15% BGCOLOR=#C0FFC0>
\r
2161 <B>Shifted Value</B>
\r
2163 <TD width=35% BGCOLOR=#C0FFC0>
\r
2164 <B>Description</B>
\r
2168 <TD width=15% BGCOLOR=#FBF5EF>
\r
2169 <B>PSU_CRL_APB_RPLL_CTRL_FBDIV</B>
\r
2171 <TD width=15% BGCOLOR=#FBF5EF>
\r
2174 <TD width=10% BGCOLOR=#FBF5EF>
\r
2177 <TD width=10% BGCOLOR=#FBF5EF>
\r
2180 <TD width=15% BGCOLOR=#FBF5EF>
\r
2183 <TD width=35% BGCOLOR=#FBF5EF>
\r
2184 <B>The integer portion of the feedback divider to the PLL</B>
\r
2188 <TD width=15% BGCOLOR=#FBF5EF>
\r
2189 <B>PSU_CRL_APB_RPLL_CTRL_DIV2</B>
\r
2191 <TD width=15% BGCOLOR=#FBF5EF>
\r
2194 <TD width=10% BGCOLOR=#FBF5EF>
\r
2197 <TD width=10% BGCOLOR=#FBF5EF>
\r
2200 <TD width=15% BGCOLOR=#FBF5EF>
\r
2203 <TD width=35% BGCOLOR=#FBF5EF>
\r
2204 <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B>
\r
2208 <TD width=15% BGCOLOR=#C0C0C0>
\r
2209 <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B>
\r
2211 <TD width=15% BGCOLOR=#C0C0C0>
\r
2214 <TD width=10% BGCOLOR=#C0C0C0>
\r
2217 <TD width=10% BGCOLOR=#C0C0C0>
\r
2220 <TD width=15% BGCOLOR=#C0C0C0>
\r
2223 <TD width=35% BGCOLOR=#C0C0C0>
\r
2224 <B>PLL Basic Control</B>
\r
2229 <H1>BY PASS PLL</H1>
\r
2230 <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2>
\r
2231 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2233 <TD width=15% BGCOLOR=#FFFF00>
\r
2234 <B>Register Name</B>
\r
2236 <TD width=15% BGCOLOR=#FFFF00>
\r
2239 <TD width=10% BGCOLOR=#FFFF00>
\r
2242 <TD width=10% BGCOLOR=#FFFF00>
\r
2245 <TD width=15% BGCOLOR=#FFFF00>
\r
2246 <B>Reset Value</B>
\r
2248 <TD width=35% BGCOLOR=#FFFF00>
\r
2249 <B>Description</B>
\r
2253 <TD width=15% BGCOLOR=#FBF5EF>
\r
2256 <TD width=15% BGCOLOR=#FBF5EF>
\r
2259 <TD width=10% BGCOLOR=#FBF5EF>
\r
2262 <TD width=10% BGCOLOR=#FBF5EF>
\r
2265 <TD width=15% BGCOLOR=#FBF5EF>
\r
2268 <TD width=35% BGCOLOR=#FBF5EF>
\r
2274 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2276 <TD width=15% BGCOLOR=#C0FFC0>
\r
2279 <TD width=15% BGCOLOR=#C0FFC0>
\r
2282 <TD width=10% BGCOLOR=#C0FFC0>
\r
2285 <TD width=10% BGCOLOR=#C0FFC0>
\r
2288 <TD width=15% BGCOLOR=#C0FFC0>
\r
2289 <B>Shifted Value</B>
\r
2291 <TD width=35% BGCOLOR=#C0FFC0>
\r
2292 <B>Description</B>
\r
2296 <TD width=15% BGCOLOR=#FBF5EF>
\r
2297 <B>PSU_CRL_APB_RPLL_CTRL_BYPASS</B>
\r
2299 <TD width=15% BGCOLOR=#FBF5EF>
\r
2302 <TD width=10% BGCOLOR=#FBF5EF>
\r
2305 <TD width=10% BGCOLOR=#FBF5EF>
\r
2308 <TD width=15% BGCOLOR=#FBF5EF>
\r
2311 <TD width=35% BGCOLOR=#FBF5EF>
\r
2312 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
2316 <TD width=15% BGCOLOR=#C0C0C0>
\r
2317 <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B>
\r
2319 <TD width=15% BGCOLOR=#C0C0C0>
\r
2322 <TD width=10% BGCOLOR=#C0C0C0>
\r
2325 <TD width=10% BGCOLOR=#C0C0C0>
\r
2328 <TD width=15% BGCOLOR=#C0C0C0>
\r
2331 <TD width=35% BGCOLOR=#C0C0C0>
\r
2332 <B>PLL Basic Control</B>
\r
2337 <H1>ASSERT RESET</H1>
\r
2338 <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2>
\r
2339 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2341 <TD width=15% BGCOLOR=#FFFF00>
\r
2342 <B>Register Name</B>
\r
2344 <TD width=15% BGCOLOR=#FFFF00>
\r
2347 <TD width=10% BGCOLOR=#FFFF00>
\r
2350 <TD width=10% BGCOLOR=#FFFF00>
\r
2353 <TD width=15% BGCOLOR=#FFFF00>
\r
2354 <B>Reset Value</B>
\r
2356 <TD width=35% BGCOLOR=#FFFF00>
\r
2357 <B>Description</B>
\r
2361 <TD width=15% BGCOLOR=#FBF5EF>
\r
2364 <TD width=15% BGCOLOR=#FBF5EF>
\r
2367 <TD width=10% BGCOLOR=#FBF5EF>
\r
2370 <TD width=10% BGCOLOR=#FBF5EF>
\r
2373 <TD width=15% BGCOLOR=#FBF5EF>
\r
2376 <TD width=35% BGCOLOR=#FBF5EF>
\r
2382 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2384 <TD width=15% BGCOLOR=#C0FFC0>
\r
2387 <TD width=15% BGCOLOR=#C0FFC0>
\r
2390 <TD width=10% BGCOLOR=#C0FFC0>
\r
2393 <TD width=10% BGCOLOR=#C0FFC0>
\r
2396 <TD width=15% BGCOLOR=#C0FFC0>
\r
2397 <B>Shifted Value</B>
\r
2399 <TD width=35% BGCOLOR=#C0FFC0>
\r
2400 <B>Description</B>
\r
2404 <TD width=15% BGCOLOR=#FBF5EF>
\r
2405 <B>PSU_CRL_APB_RPLL_CTRL_RESET</B>
\r
2407 <TD width=15% BGCOLOR=#FBF5EF>
\r
2410 <TD width=10% BGCOLOR=#FBF5EF>
\r
2413 <TD width=10% BGCOLOR=#FBF5EF>
\r
2416 <TD width=15% BGCOLOR=#FBF5EF>
\r
2419 <TD width=35% BGCOLOR=#FBF5EF>
\r
2420 <B>Asserts Reset to the PLL</B>
\r
2424 <TD width=15% BGCOLOR=#C0C0C0>
\r
2425 <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B>
\r
2427 <TD width=15% BGCOLOR=#C0C0C0>
\r
2430 <TD width=10% BGCOLOR=#C0C0C0>
\r
2433 <TD width=10% BGCOLOR=#C0C0C0>
\r
2436 <TD width=15% BGCOLOR=#C0C0C0>
\r
2439 <TD width=35% BGCOLOR=#C0C0C0>
\r
2440 <B>PLL Basic Control</B>
\r
2445 <H1>DEASSERT RESET</H1>
\r
2446 <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2>
\r
2447 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2449 <TD width=15% BGCOLOR=#FFFF00>
\r
2450 <B>Register Name</B>
\r
2452 <TD width=15% BGCOLOR=#FFFF00>
\r
2455 <TD width=10% BGCOLOR=#FFFF00>
\r
2458 <TD width=10% BGCOLOR=#FFFF00>
\r
2461 <TD width=15% BGCOLOR=#FFFF00>
\r
2462 <B>Reset Value</B>
\r
2464 <TD width=35% BGCOLOR=#FFFF00>
\r
2465 <B>Description</B>
\r
2469 <TD width=15% BGCOLOR=#FBF5EF>
\r
2472 <TD width=15% BGCOLOR=#FBF5EF>
\r
2475 <TD width=10% BGCOLOR=#FBF5EF>
\r
2478 <TD width=10% BGCOLOR=#FBF5EF>
\r
2481 <TD width=15% BGCOLOR=#FBF5EF>
\r
2484 <TD width=35% BGCOLOR=#FBF5EF>
\r
2490 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2492 <TD width=15% BGCOLOR=#C0FFC0>
\r
2495 <TD width=15% BGCOLOR=#C0FFC0>
\r
2498 <TD width=10% BGCOLOR=#C0FFC0>
\r
2501 <TD width=10% BGCOLOR=#C0FFC0>
\r
2504 <TD width=15% BGCOLOR=#C0FFC0>
\r
2505 <B>Shifted Value</B>
\r
2507 <TD width=35% BGCOLOR=#C0FFC0>
\r
2508 <B>Description</B>
\r
2512 <TD width=15% BGCOLOR=#FBF5EF>
\r
2513 <B>PSU_CRL_APB_RPLL_CTRL_RESET</B>
\r
2515 <TD width=15% BGCOLOR=#FBF5EF>
\r
2518 <TD width=10% BGCOLOR=#FBF5EF>
\r
2521 <TD width=10% BGCOLOR=#FBF5EF>
\r
2524 <TD width=15% BGCOLOR=#FBF5EF>
\r
2527 <TD width=35% BGCOLOR=#FBF5EF>
\r
2528 <B>Asserts Reset to the PLL</B>
\r
2532 <TD width=15% BGCOLOR=#C0C0C0>
\r
2533 <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B>
\r
2535 <TD width=15% BGCOLOR=#C0C0C0>
\r
2538 <TD width=10% BGCOLOR=#C0C0C0>
\r
2541 <TD width=10% BGCOLOR=#C0C0C0>
\r
2544 <TD width=15% BGCOLOR=#C0C0C0>
\r
2547 <TD width=35% BGCOLOR=#C0C0C0>
\r
2548 <B>PLL Basic Control</B>
\r
2553 <H1>CHECK PLL STATUS</H1>
\r
2554 <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
\r
2555 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2557 <TD width=15% BGCOLOR=#FFFF00>
\r
2558 <B>Register Name</B>
\r
2560 <TD width=15% BGCOLOR=#FFFF00>
\r
2563 <TD width=10% BGCOLOR=#FFFF00>
\r
2566 <TD width=10% BGCOLOR=#FFFF00>
\r
2569 <TD width=15% BGCOLOR=#FFFF00>
\r
2570 <B>Reset Value</B>
\r
2572 <TD width=35% BGCOLOR=#FFFF00>
\r
2573 <B>Description</B>
\r
2577 <TD width=15% BGCOLOR=#FBF5EF>
\r
2580 <TD width=15% BGCOLOR=#FBF5EF>
\r
2583 <TD width=10% BGCOLOR=#FBF5EF>
\r
2586 <TD width=10% BGCOLOR=#FBF5EF>
\r
2589 <TD width=15% BGCOLOR=#FBF5EF>
\r
2592 <TD width=35% BGCOLOR=#FBF5EF>
\r
2598 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2600 <TD width=15% BGCOLOR=#C0FFC0>
\r
2603 <TD width=15% BGCOLOR=#C0FFC0>
\r
2606 <TD width=10% BGCOLOR=#C0FFC0>
\r
2609 <TD width=10% BGCOLOR=#C0FFC0>
\r
2612 <TD width=15% BGCOLOR=#C0FFC0>
\r
2613 <B>Shifted Value</B>
\r
2615 <TD width=35% BGCOLOR=#C0FFC0>
\r
2616 <B>Description</B>
\r
2620 <TD width=15% BGCOLOR=#FBF5EF>
\r
2621 <B>PSU_CRL_APB_PLL_STATUS_RPLL_LOCK</B>
\r
2623 <TD width=15% BGCOLOR=#FBF5EF>
\r
2626 <TD width=10% BGCOLOR=#FBF5EF>
\r
2629 <TD width=10% BGCOLOR=#FBF5EF>
\r
2632 <TD width=15% BGCOLOR=#FBF5EF>
\r
2635 <TD width=35% BGCOLOR=#FBF5EF>
\r
2636 <B>RPLL is locked</B>
\r
2640 <TD width=15% BGCOLOR=#C0C0C0>
\r
2641 <B>PSU_CRL_APB_PLL_STATUS@0XFF5E0040</B>
\r
2643 <TD width=15% BGCOLOR=#C0C0C0>
\r
2646 <TD width=10% BGCOLOR=#C0C0C0>
\r
2649 <TD width=10% BGCOLOR=#C0C0C0>
\r
2652 <TD width=15% BGCOLOR=#C0C0C0>
\r
2655 <TD width=35% BGCOLOR=#C0C0C0>
\r
2661 <H1>REMOVE PLL BY PASS</H1>
\r
2662 <H2><a name="RPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_CTRL</a></H2>
\r
2663 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2665 <TD width=15% BGCOLOR=#FFFF00>
\r
2666 <B>Register Name</B>
\r
2668 <TD width=15% BGCOLOR=#FFFF00>
\r
2671 <TD width=10% BGCOLOR=#FFFF00>
\r
2674 <TD width=10% BGCOLOR=#FFFF00>
\r
2677 <TD width=15% BGCOLOR=#FFFF00>
\r
2678 <B>Reset Value</B>
\r
2680 <TD width=35% BGCOLOR=#FFFF00>
\r
2681 <B>Description</B>
\r
2685 <TD width=15% BGCOLOR=#FBF5EF>
\r
2688 <TD width=15% BGCOLOR=#FBF5EF>
\r
2691 <TD width=10% BGCOLOR=#FBF5EF>
\r
2694 <TD width=10% BGCOLOR=#FBF5EF>
\r
2697 <TD width=15% BGCOLOR=#FBF5EF>
\r
2700 <TD width=35% BGCOLOR=#FBF5EF>
\r
2706 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2708 <TD width=15% BGCOLOR=#C0FFC0>
\r
2711 <TD width=15% BGCOLOR=#C0FFC0>
\r
2714 <TD width=10% BGCOLOR=#C0FFC0>
\r
2717 <TD width=10% BGCOLOR=#C0FFC0>
\r
2720 <TD width=15% BGCOLOR=#C0FFC0>
\r
2721 <B>Shifted Value</B>
\r
2723 <TD width=35% BGCOLOR=#C0FFC0>
\r
2724 <B>Description</B>
\r
2728 <TD width=15% BGCOLOR=#FBF5EF>
\r
2729 <B>PSU_CRL_APB_RPLL_CTRL_BYPASS</B>
\r
2731 <TD width=15% BGCOLOR=#FBF5EF>
\r
2734 <TD width=10% BGCOLOR=#FBF5EF>
\r
2737 <TD width=10% BGCOLOR=#FBF5EF>
\r
2740 <TD width=15% BGCOLOR=#FBF5EF>
\r
2743 <TD width=35% BGCOLOR=#FBF5EF>
\r
2744 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
2748 <TD width=15% BGCOLOR=#C0C0C0>
\r
2749 <B>PSU_CRL_APB_RPLL_CTRL@0XFF5E0030</B>
\r
2751 <TD width=15% BGCOLOR=#C0C0C0>
\r
2754 <TD width=10% BGCOLOR=#C0C0C0>
\r
2757 <TD width=10% BGCOLOR=#C0C0C0>
\r
2760 <TD width=15% BGCOLOR=#C0C0C0>
\r
2763 <TD width=35% BGCOLOR=#C0C0C0>
\r
2764 <B>PLL Basic Control</B>
\r
2769 <H2><a name="RPLL_TO_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)RPLL_TO_FPD_CTRL</a></H2>
\r
2770 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2772 <TD width=15% BGCOLOR=#FFFF00>
\r
2773 <B>Register Name</B>
\r
2775 <TD width=15% BGCOLOR=#FFFF00>
\r
2778 <TD width=10% BGCOLOR=#FFFF00>
\r
2781 <TD width=10% BGCOLOR=#FFFF00>
\r
2784 <TD width=15% BGCOLOR=#FFFF00>
\r
2785 <B>Reset Value</B>
\r
2787 <TD width=35% BGCOLOR=#FFFF00>
\r
2788 <B>Description</B>
\r
2792 <TD width=15% BGCOLOR=#FBF5EF>
\r
2793 <B>RPLL_TO_FPD_CTRL</B>
\r
2795 <TD width=15% BGCOLOR=#FBF5EF>
\r
2798 <TD width=10% BGCOLOR=#FBF5EF>
\r
2801 <TD width=10% BGCOLOR=#FBF5EF>
\r
2804 <TD width=15% BGCOLOR=#FBF5EF>
\r
2807 <TD width=35% BGCOLOR=#FBF5EF>
\r
2813 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2815 <TD width=15% BGCOLOR=#C0FFC0>
\r
2818 <TD width=15% BGCOLOR=#C0FFC0>
\r
2821 <TD width=10% BGCOLOR=#C0FFC0>
\r
2824 <TD width=10% BGCOLOR=#C0FFC0>
\r
2827 <TD width=15% BGCOLOR=#C0FFC0>
\r
2828 <B>Shifted Value</B>
\r
2830 <TD width=35% BGCOLOR=#C0FFC0>
\r
2831 <B>Description</B>
\r
2835 <TD width=15% BGCOLOR=#FBF5EF>
\r
2836 <B>PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0</B>
\r
2838 <TD width=15% BGCOLOR=#FBF5EF>
\r
2841 <TD width=10% BGCOLOR=#FBF5EF>
\r
2844 <TD width=10% BGCOLOR=#FBF5EF>
\r
2847 <TD width=15% BGCOLOR=#FBF5EF>
\r
2850 <TD width=35% BGCOLOR=#FBF5EF>
\r
2851 <B>Divisor value for this clock.</B>
\r
2855 <TD width=15% BGCOLOR=#C0C0C0>
\r
2856 <B>PSU_CRL_APB_RPLL_TO_FPD_CTRL@0XFF5E0048</B>
\r
2858 <TD width=15% BGCOLOR=#C0C0C0>
\r
2861 <TD width=10% BGCOLOR=#C0C0C0>
\r
2864 <TD width=10% BGCOLOR=#C0C0C0>
\r
2867 <TD width=15% BGCOLOR=#C0C0C0>
\r
2870 <TD width=35% BGCOLOR=#C0C0C0>
\r
2871 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
2876 <H1>RPLL FRAC CFG</H1>
\r
2877 <H1>IOPLL INIT</H1>
\r
2878 <H1>UPDATE FB_DIV</H1>
\r
2879 <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2>
\r
2880 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2882 <TD width=15% BGCOLOR=#FFFF00>
\r
2883 <B>Register Name</B>
\r
2885 <TD width=15% BGCOLOR=#FFFF00>
\r
2888 <TD width=10% BGCOLOR=#FFFF00>
\r
2891 <TD width=10% BGCOLOR=#FFFF00>
\r
2894 <TD width=15% BGCOLOR=#FFFF00>
\r
2895 <B>Reset Value</B>
\r
2897 <TD width=35% BGCOLOR=#FFFF00>
\r
2898 <B>Description</B>
\r
2902 <TD width=15% BGCOLOR=#FBF5EF>
\r
2905 <TD width=15% BGCOLOR=#FBF5EF>
\r
2908 <TD width=10% BGCOLOR=#FBF5EF>
\r
2911 <TD width=10% BGCOLOR=#FBF5EF>
\r
2914 <TD width=15% BGCOLOR=#FBF5EF>
\r
2917 <TD width=35% BGCOLOR=#FBF5EF>
\r
2923 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
2925 <TD width=15% BGCOLOR=#C0FFC0>
\r
2928 <TD width=15% BGCOLOR=#C0FFC0>
\r
2931 <TD width=10% BGCOLOR=#C0FFC0>
\r
2934 <TD width=10% BGCOLOR=#C0FFC0>
\r
2937 <TD width=15% BGCOLOR=#C0FFC0>
\r
2938 <B>Shifted Value</B>
\r
2940 <TD width=35% BGCOLOR=#C0FFC0>
\r
2941 <B>Description</B>
\r
2945 <TD width=15% BGCOLOR=#FBF5EF>
\r
2946 <B>PSU_CRL_APB_IOPLL_CTRL_FBDIV</B>
\r
2948 <TD width=15% BGCOLOR=#FBF5EF>
\r
2951 <TD width=10% BGCOLOR=#FBF5EF>
\r
2954 <TD width=10% BGCOLOR=#FBF5EF>
\r
2957 <TD width=15% BGCOLOR=#FBF5EF>
\r
2960 <TD width=35% BGCOLOR=#FBF5EF>
\r
2961 <B>The integer portion of the feedback divider to the PLL</B>
\r
2965 <TD width=15% BGCOLOR=#FBF5EF>
\r
2966 <B>PSU_CRL_APB_IOPLL_CTRL_DIV2</B>
\r
2968 <TD width=15% BGCOLOR=#FBF5EF>
\r
2971 <TD width=10% BGCOLOR=#FBF5EF>
\r
2974 <TD width=10% BGCOLOR=#FBF5EF>
\r
2977 <TD width=15% BGCOLOR=#FBF5EF>
\r
2980 <TD width=35% BGCOLOR=#FBF5EF>
\r
2981 <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B>
\r
2985 <TD width=15% BGCOLOR=#C0C0C0>
\r
2986 <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B>
\r
2988 <TD width=15% BGCOLOR=#C0C0C0>
\r
2991 <TD width=10% BGCOLOR=#C0C0C0>
\r
2994 <TD width=10% BGCOLOR=#C0C0C0>
\r
2997 <TD width=15% BGCOLOR=#C0C0C0>
\r
3000 <TD width=35% BGCOLOR=#C0C0C0>
\r
3001 <B>PLL Basic Control</B>
\r
3006 <H1>BY PASS PLL</H1>
\r
3007 <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2>
\r
3008 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3010 <TD width=15% BGCOLOR=#FFFF00>
\r
3011 <B>Register Name</B>
\r
3013 <TD width=15% BGCOLOR=#FFFF00>
\r
3016 <TD width=10% BGCOLOR=#FFFF00>
\r
3019 <TD width=10% BGCOLOR=#FFFF00>
\r
3022 <TD width=15% BGCOLOR=#FFFF00>
\r
3023 <B>Reset Value</B>
\r
3025 <TD width=35% BGCOLOR=#FFFF00>
\r
3026 <B>Description</B>
\r
3030 <TD width=15% BGCOLOR=#FBF5EF>
\r
3033 <TD width=15% BGCOLOR=#FBF5EF>
\r
3036 <TD width=10% BGCOLOR=#FBF5EF>
\r
3039 <TD width=10% BGCOLOR=#FBF5EF>
\r
3042 <TD width=15% BGCOLOR=#FBF5EF>
\r
3045 <TD width=35% BGCOLOR=#FBF5EF>
\r
3051 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3053 <TD width=15% BGCOLOR=#C0FFC0>
\r
3056 <TD width=15% BGCOLOR=#C0FFC0>
\r
3059 <TD width=10% BGCOLOR=#C0FFC0>
\r
3062 <TD width=10% BGCOLOR=#C0FFC0>
\r
3065 <TD width=15% BGCOLOR=#C0FFC0>
\r
3066 <B>Shifted Value</B>
\r
3068 <TD width=35% BGCOLOR=#C0FFC0>
\r
3069 <B>Description</B>
\r
3073 <TD width=15% BGCOLOR=#FBF5EF>
\r
3074 <B>PSU_CRL_APB_IOPLL_CTRL_BYPASS</B>
\r
3076 <TD width=15% BGCOLOR=#FBF5EF>
\r
3079 <TD width=10% BGCOLOR=#FBF5EF>
\r
3082 <TD width=10% BGCOLOR=#FBF5EF>
\r
3085 <TD width=15% BGCOLOR=#FBF5EF>
\r
3088 <TD width=35% BGCOLOR=#FBF5EF>
\r
3089 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
3093 <TD width=15% BGCOLOR=#C0C0C0>
\r
3094 <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B>
\r
3096 <TD width=15% BGCOLOR=#C0C0C0>
\r
3099 <TD width=10% BGCOLOR=#C0C0C0>
\r
3102 <TD width=10% BGCOLOR=#C0C0C0>
\r
3105 <TD width=15% BGCOLOR=#C0C0C0>
\r
3108 <TD width=35% BGCOLOR=#C0C0C0>
\r
3109 <B>PLL Basic Control</B>
\r
3114 <H1>ASSERT RESET</H1>
\r
3115 <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2>
\r
3116 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3118 <TD width=15% BGCOLOR=#FFFF00>
\r
3119 <B>Register Name</B>
\r
3121 <TD width=15% BGCOLOR=#FFFF00>
\r
3124 <TD width=10% BGCOLOR=#FFFF00>
\r
3127 <TD width=10% BGCOLOR=#FFFF00>
\r
3130 <TD width=15% BGCOLOR=#FFFF00>
\r
3131 <B>Reset Value</B>
\r
3133 <TD width=35% BGCOLOR=#FFFF00>
\r
3134 <B>Description</B>
\r
3138 <TD width=15% BGCOLOR=#FBF5EF>
\r
3141 <TD width=15% BGCOLOR=#FBF5EF>
\r
3144 <TD width=10% BGCOLOR=#FBF5EF>
\r
3147 <TD width=10% BGCOLOR=#FBF5EF>
\r
3150 <TD width=15% BGCOLOR=#FBF5EF>
\r
3153 <TD width=35% BGCOLOR=#FBF5EF>
\r
3159 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3161 <TD width=15% BGCOLOR=#C0FFC0>
\r
3164 <TD width=15% BGCOLOR=#C0FFC0>
\r
3167 <TD width=10% BGCOLOR=#C0FFC0>
\r
3170 <TD width=10% BGCOLOR=#C0FFC0>
\r
3173 <TD width=15% BGCOLOR=#C0FFC0>
\r
3174 <B>Shifted Value</B>
\r
3176 <TD width=35% BGCOLOR=#C0FFC0>
\r
3177 <B>Description</B>
\r
3181 <TD width=15% BGCOLOR=#FBF5EF>
\r
3182 <B>PSU_CRL_APB_IOPLL_CTRL_RESET</B>
\r
3184 <TD width=15% BGCOLOR=#FBF5EF>
\r
3187 <TD width=10% BGCOLOR=#FBF5EF>
\r
3190 <TD width=10% BGCOLOR=#FBF5EF>
\r
3193 <TD width=15% BGCOLOR=#FBF5EF>
\r
3196 <TD width=35% BGCOLOR=#FBF5EF>
\r
3197 <B>Asserts Reset to the PLL</B>
\r
3201 <TD width=15% BGCOLOR=#C0C0C0>
\r
3202 <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B>
\r
3204 <TD width=15% BGCOLOR=#C0C0C0>
\r
3207 <TD width=10% BGCOLOR=#C0C0C0>
\r
3210 <TD width=10% BGCOLOR=#C0C0C0>
\r
3213 <TD width=15% BGCOLOR=#C0C0C0>
\r
3216 <TD width=35% BGCOLOR=#C0C0C0>
\r
3217 <B>PLL Basic Control</B>
\r
3222 <H1>DEASSERT RESET</H1>
\r
3223 <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2>
\r
3224 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3226 <TD width=15% BGCOLOR=#FFFF00>
\r
3227 <B>Register Name</B>
\r
3229 <TD width=15% BGCOLOR=#FFFF00>
\r
3232 <TD width=10% BGCOLOR=#FFFF00>
\r
3235 <TD width=10% BGCOLOR=#FFFF00>
\r
3238 <TD width=15% BGCOLOR=#FFFF00>
\r
3239 <B>Reset Value</B>
\r
3241 <TD width=35% BGCOLOR=#FFFF00>
\r
3242 <B>Description</B>
\r
3246 <TD width=15% BGCOLOR=#FBF5EF>
\r
3249 <TD width=15% BGCOLOR=#FBF5EF>
\r
3252 <TD width=10% BGCOLOR=#FBF5EF>
\r
3255 <TD width=10% BGCOLOR=#FBF5EF>
\r
3258 <TD width=15% BGCOLOR=#FBF5EF>
\r
3261 <TD width=35% BGCOLOR=#FBF5EF>
\r
3267 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3269 <TD width=15% BGCOLOR=#C0FFC0>
\r
3272 <TD width=15% BGCOLOR=#C0FFC0>
\r
3275 <TD width=10% BGCOLOR=#C0FFC0>
\r
3278 <TD width=10% BGCOLOR=#C0FFC0>
\r
3281 <TD width=15% BGCOLOR=#C0FFC0>
\r
3282 <B>Shifted Value</B>
\r
3284 <TD width=35% BGCOLOR=#C0FFC0>
\r
3285 <B>Description</B>
\r
3289 <TD width=15% BGCOLOR=#FBF5EF>
\r
3290 <B>PSU_CRL_APB_IOPLL_CTRL_RESET</B>
\r
3292 <TD width=15% BGCOLOR=#FBF5EF>
\r
3295 <TD width=10% BGCOLOR=#FBF5EF>
\r
3298 <TD width=10% BGCOLOR=#FBF5EF>
\r
3301 <TD width=15% BGCOLOR=#FBF5EF>
\r
3304 <TD width=35% BGCOLOR=#FBF5EF>
\r
3305 <B>Asserts Reset to the PLL</B>
\r
3309 <TD width=15% BGCOLOR=#C0C0C0>
\r
3310 <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B>
\r
3312 <TD width=15% BGCOLOR=#C0C0C0>
\r
3315 <TD width=10% BGCOLOR=#C0C0C0>
\r
3318 <TD width=10% BGCOLOR=#C0C0C0>
\r
3321 <TD width=15% BGCOLOR=#C0C0C0>
\r
3324 <TD width=35% BGCOLOR=#C0C0C0>
\r
3325 <B>PLL Basic Control</B>
\r
3330 <H1>CHECK PLL STATUS</H1>
\r
3331 <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
\r
3332 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3334 <TD width=15% BGCOLOR=#FFFF00>
\r
3335 <B>Register Name</B>
\r
3337 <TD width=15% BGCOLOR=#FFFF00>
\r
3340 <TD width=10% BGCOLOR=#FFFF00>
\r
3343 <TD width=10% BGCOLOR=#FFFF00>
\r
3346 <TD width=15% BGCOLOR=#FFFF00>
\r
3347 <B>Reset Value</B>
\r
3349 <TD width=35% BGCOLOR=#FFFF00>
\r
3350 <B>Description</B>
\r
3354 <TD width=15% BGCOLOR=#FBF5EF>
\r
3357 <TD width=15% BGCOLOR=#FBF5EF>
\r
3360 <TD width=10% BGCOLOR=#FBF5EF>
\r
3363 <TD width=10% BGCOLOR=#FBF5EF>
\r
3366 <TD width=15% BGCOLOR=#FBF5EF>
\r
3369 <TD width=35% BGCOLOR=#FBF5EF>
\r
3375 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3377 <TD width=15% BGCOLOR=#C0FFC0>
\r
3380 <TD width=15% BGCOLOR=#C0FFC0>
\r
3383 <TD width=10% BGCOLOR=#C0FFC0>
\r
3386 <TD width=10% BGCOLOR=#C0FFC0>
\r
3389 <TD width=15% BGCOLOR=#C0FFC0>
\r
3390 <B>Shifted Value</B>
\r
3392 <TD width=35% BGCOLOR=#C0FFC0>
\r
3393 <B>Description</B>
\r
3397 <TD width=15% BGCOLOR=#FBF5EF>
\r
3398 <B>PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK</B>
\r
3400 <TD width=15% BGCOLOR=#FBF5EF>
\r
3403 <TD width=10% BGCOLOR=#FBF5EF>
\r
3406 <TD width=10% BGCOLOR=#FBF5EF>
\r
3409 <TD width=15% BGCOLOR=#FBF5EF>
\r
3412 <TD width=35% BGCOLOR=#FBF5EF>
\r
3413 <B>IOPLL is locked</B>
\r
3417 <TD width=15% BGCOLOR=#C0C0C0>
\r
3418 <B>PSU_CRL_APB_PLL_STATUS@0XFF5E0040</B>
\r
3420 <TD width=15% BGCOLOR=#C0C0C0>
\r
3423 <TD width=10% BGCOLOR=#C0C0C0>
\r
3426 <TD width=10% BGCOLOR=#C0C0C0>
\r
3429 <TD width=15% BGCOLOR=#C0C0C0>
\r
3432 <TD width=35% BGCOLOR=#C0C0C0>
\r
3438 <H1>REMOVE PLL BY PASS</H1>
\r
3439 <H2><a name="IOPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_CTRL</a></H2>
\r
3440 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3442 <TD width=15% BGCOLOR=#FFFF00>
\r
3443 <B>Register Name</B>
\r
3445 <TD width=15% BGCOLOR=#FFFF00>
\r
3448 <TD width=10% BGCOLOR=#FFFF00>
\r
3451 <TD width=10% BGCOLOR=#FFFF00>
\r
3454 <TD width=15% BGCOLOR=#FFFF00>
\r
3455 <B>Reset Value</B>
\r
3457 <TD width=35% BGCOLOR=#FFFF00>
\r
3458 <B>Description</B>
\r
3462 <TD width=15% BGCOLOR=#FBF5EF>
\r
3465 <TD width=15% BGCOLOR=#FBF5EF>
\r
3468 <TD width=10% BGCOLOR=#FBF5EF>
\r
3471 <TD width=10% BGCOLOR=#FBF5EF>
\r
3474 <TD width=15% BGCOLOR=#FBF5EF>
\r
3477 <TD width=35% BGCOLOR=#FBF5EF>
\r
3483 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3485 <TD width=15% BGCOLOR=#C0FFC0>
\r
3488 <TD width=15% BGCOLOR=#C0FFC0>
\r
3491 <TD width=10% BGCOLOR=#C0FFC0>
\r
3494 <TD width=10% BGCOLOR=#C0FFC0>
\r
3497 <TD width=15% BGCOLOR=#C0FFC0>
\r
3498 <B>Shifted Value</B>
\r
3500 <TD width=35% BGCOLOR=#C0FFC0>
\r
3501 <B>Description</B>
\r
3505 <TD width=15% BGCOLOR=#FBF5EF>
\r
3506 <B>PSU_CRL_APB_IOPLL_CTRL_BYPASS</B>
\r
3508 <TD width=15% BGCOLOR=#FBF5EF>
\r
3511 <TD width=10% BGCOLOR=#FBF5EF>
\r
3514 <TD width=10% BGCOLOR=#FBF5EF>
\r
3517 <TD width=15% BGCOLOR=#FBF5EF>
\r
3520 <TD width=35% BGCOLOR=#FBF5EF>
\r
3521 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
3525 <TD width=15% BGCOLOR=#C0C0C0>
\r
3526 <B>PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020</B>
\r
3528 <TD width=15% BGCOLOR=#C0C0C0>
\r
3531 <TD width=10% BGCOLOR=#C0C0C0>
\r
3534 <TD width=10% BGCOLOR=#C0C0C0>
\r
3537 <TD width=15% BGCOLOR=#C0C0C0>
\r
3540 <TD width=35% BGCOLOR=#C0C0C0>
\r
3541 <B>PLL Basic Control</B>
\r
3546 <H2><a name="IOPLL_TO_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOPLL_TO_FPD_CTRL</a></H2>
\r
3547 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3549 <TD width=15% BGCOLOR=#FFFF00>
\r
3550 <B>Register Name</B>
\r
3552 <TD width=15% BGCOLOR=#FFFF00>
\r
3555 <TD width=10% BGCOLOR=#FFFF00>
\r
3558 <TD width=10% BGCOLOR=#FFFF00>
\r
3561 <TD width=15% BGCOLOR=#FFFF00>
\r
3562 <B>Reset Value</B>
\r
3564 <TD width=35% BGCOLOR=#FFFF00>
\r
3565 <B>Description</B>
\r
3569 <TD width=15% BGCOLOR=#FBF5EF>
\r
3570 <B>IOPLL_TO_FPD_CTRL</B>
\r
3572 <TD width=15% BGCOLOR=#FBF5EF>
\r
3575 <TD width=10% BGCOLOR=#FBF5EF>
\r
3578 <TD width=10% BGCOLOR=#FBF5EF>
\r
3581 <TD width=15% BGCOLOR=#FBF5EF>
\r
3584 <TD width=35% BGCOLOR=#FBF5EF>
\r
3590 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3592 <TD width=15% BGCOLOR=#C0FFC0>
\r
3595 <TD width=15% BGCOLOR=#C0FFC0>
\r
3598 <TD width=10% BGCOLOR=#C0FFC0>
\r
3601 <TD width=10% BGCOLOR=#C0FFC0>
\r
3604 <TD width=15% BGCOLOR=#C0FFC0>
\r
3605 <B>Shifted Value</B>
\r
3607 <TD width=35% BGCOLOR=#C0FFC0>
\r
3608 <B>Description</B>
\r
3612 <TD width=15% BGCOLOR=#FBF5EF>
\r
3613 <B>PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0</B>
\r
3615 <TD width=15% BGCOLOR=#FBF5EF>
\r
3618 <TD width=10% BGCOLOR=#FBF5EF>
\r
3621 <TD width=10% BGCOLOR=#FBF5EF>
\r
3624 <TD width=15% BGCOLOR=#FBF5EF>
\r
3627 <TD width=35% BGCOLOR=#FBF5EF>
\r
3628 <B>Divisor value for this clock.</B>
\r
3632 <TD width=15% BGCOLOR=#C0C0C0>
\r
3633 <B>PSU_CRL_APB_IOPLL_TO_FPD_CTRL@0XFF5E0044</B>
\r
3635 <TD width=15% BGCOLOR=#C0C0C0>
\r
3638 <TD width=10% BGCOLOR=#C0C0C0>
\r
3641 <TD width=10% BGCOLOR=#C0C0C0>
\r
3644 <TD width=15% BGCOLOR=#C0C0C0>
\r
3647 <TD width=35% BGCOLOR=#C0C0C0>
\r
3648 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
3653 <H1>IOPLL FRAC CFG</H1>
\r
3654 <H1>APU_PLL INIT</H1>
\r
3655 <H1>UPDATE FB_DIV</H1>
\r
3656 <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2>
\r
3657 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3659 <TD width=15% BGCOLOR=#FFFF00>
\r
3660 <B>Register Name</B>
\r
3662 <TD width=15% BGCOLOR=#FFFF00>
\r
3665 <TD width=10% BGCOLOR=#FFFF00>
\r
3668 <TD width=10% BGCOLOR=#FFFF00>
\r
3671 <TD width=15% BGCOLOR=#FFFF00>
\r
3672 <B>Reset Value</B>
\r
3674 <TD width=35% BGCOLOR=#FFFF00>
\r
3675 <B>Description</B>
\r
3679 <TD width=15% BGCOLOR=#FBF5EF>
\r
3682 <TD width=15% BGCOLOR=#FBF5EF>
\r
3685 <TD width=10% BGCOLOR=#FBF5EF>
\r
3688 <TD width=10% BGCOLOR=#FBF5EF>
\r
3691 <TD width=15% BGCOLOR=#FBF5EF>
\r
3694 <TD width=35% BGCOLOR=#FBF5EF>
\r
3700 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3702 <TD width=15% BGCOLOR=#C0FFC0>
\r
3705 <TD width=15% BGCOLOR=#C0FFC0>
\r
3708 <TD width=10% BGCOLOR=#C0FFC0>
\r
3711 <TD width=10% BGCOLOR=#C0FFC0>
\r
3714 <TD width=15% BGCOLOR=#C0FFC0>
\r
3715 <B>Shifted Value</B>
\r
3717 <TD width=35% BGCOLOR=#C0FFC0>
\r
3718 <B>Description</B>
\r
3722 <TD width=15% BGCOLOR=#FBF5EF>
\r
3723 <B>PSU_CRF_APB_APLL_CTRL_FBDIV</B>
\r
3725 <TD width=15% BGCOLOR=#FBF5EF>
\r
3728 <TD width=10% BGCOLOR=#FBF5EF>
\r
3731 <TD width=10% BGCOLOR=#FBF5EF>
\r
3734 <TD width=15% BGCOLOR=#FBF5EF>
\r
3737 <TD width=35% BGCOLOR=#FBF5EF>
\r
3738 <B>The integer portion of the feedback divider to the PLL</B>
\r
3742 <TD width=15% BGCOLOR=#FBF5EF>
\r
3743 <B>PSU_CRF_APB_APLL_CTRL_DIV2</B>
\r
3745 <TD width=15% BGCOLOR=#FBF5EF>
\r
3748 <TD width=10% BGCOLOR=#FBF5EF>
\r
3751 <TD width=10% BGCOLOR=#FBF5EF>
\r
3754 <TD width=15% BGCOLOR=#FBF5EF>
\r
3757 <TD width=35% BGCOLOR=#FBF5EF>
\r
3758 <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B>
\r
3762 <TD width=15% BGCOLOR=#C0C0C0>
\r
3763 <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B>
\r
3765 <TD width=15% BGCOLOR=#C0C0C0>
\r
3768 <TD width=10% BGCOLOR=#C0C0C0>
\r
3771 <TD width=10% BGCOLOR=#C0C0C0>
\r
3774 <TD width=15% BGCOLOR=#C0C0C0>
\r
3777 <TD width=35% BGCOLOR=#C0C0C0>
\r
3778 <B>PLL Basic Control</B>
\r
3783 <H1>BY PASS PLL</H1>
\r
3784 <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2>
\r
3785 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3787 <TD width=15% BGCOLOR=#FFFF00>
\r
3788 <B>Register Name</B>
\r
3790 <TD width=15% BGCOLOR=#FFFF00>
\r
3793 <TD width=10% BGCOLOR=#FFFF00>
\r
3796 <TD width=10% BGCOLOR=#FFFF00>
\r
3799 <TD width=15% BGCOLOR=#FFFF00>
\r
3800 <B>Reset Value</B>
\r
3802 <TD width=35% BGCOLOR=#FFFF00>
\r
3803 <B>Description</B>
\r
3807 <TD width=15% BGCOLOR=#FBF5EF>
\r
3810 <TD width=15% BGCOLOR=#FBF5EF>
\r
3813 <TD width=10% BGCOLOR=#FBF5EF>
\r
3816 <TD width=10% BGCOLOR=#FBF5EF>
\r
3819 <TD width=15% BGCOLOR=#FBF5EF>
\r
3822 <TD width=35% BGCOLOR=#FBF5EF>
\r
3828 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3830 <TD width=15% BGCOLOR=#C0FFC0>
\r
3833 <TD width=15% BGCOLOR=#C0FFC0>
\r
3836 <TD width=10% BGCOLOR=#C0FFC0>
\r
3839 <TD width=10% BGCOLOR=#C0FFC0>
\r
3842 <TD width=15% BGCOLOR=#C0FFC0>
\r
3843 <B>Shifted Value</B>
\r
3845 <TD width=35% BGCOLOR=#C0FFC0>
\r
3846 <B>Description</B>
\r
3850 <TD width=15% BGCOLOR=#FBF5EF>
\r
3851 <B>PSU_CRF_APB_APLL_CTRL_BYPASS</B>
\r
3853 <TD width=15% BGCOLOR=#FBF5EF>
\r
3856 <TD width=10% BGCOLOR=#FBF5EF>
\r
3859 <TD width=10% BGCOLOR=#FBF5EF>
\r
3862 <TD width=15% BGCOLOR=#FBF5EF>
\r
3865 <TD width=35% BGCOLOR=#FBF5EF>
\r
3866 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
3870 <TD width=15% BGCOLOR=#C0C0C0>
\r
3871 <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B>
\r
3873 <TD width=15% BGCOLOR=#C0C0C0>
\r
3876 <TD width=10% BGCOLOR=#C0C0C0>
\r
3879 <TD width=10% BGCOLOR=#C0C0C0>
\r
3882 <TD width=15% BGCOLOR=#C0C0C0>
\r
3885 <TD width=35% BGCOLOR=#C0C0C0>
\r
3886 <B>PLL Basic Control</B>
\r
3891 <H1>ASSERT RESET</H1>
\r
3892 <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2>
\r
3893 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3895 <TD width=15% BGCOLOR=#FFFF00>
\r
3896 <B>Register Name</B>
\r
3898 <TD width=15% BGCOLOR=#FFFF00>
\r
3901 <TD width=10% BGCOLOR=#FFFF00>
\r
3904 <TD width=10% BGCOLOR=#FFFF00>
\r
3907 <TD width=15% BGCOLOR=#FFFF00>
\r
3908 <B>Reset Value</B>
\r
3910 <TD width=35% BGCOLOR=#FFFF00>
\r
3911 <B>Description</B>
\r
3915 <TD width=15% BGCOLOR=#FBF5EF>
\r
3918 <TD width=15% BGCOLOR=#FBF5EF>
\r
3921 <TD width=10% BGCOLOR=#FBF5EF>
\r
3924 <TD width=10% BGCOLOR=#FBF5EF>
\r
3927 <TD width=15% BGCOLOR=#FBF5EF>
\r
3930 <TD width=35% BGCOLOR=#FBF5EF>
\r
3936 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
3938 <TD width=15% BGCOLOR=#C0FFC0>
\r
3941 <TD width=15% BGCOLOR=#C0FFC0>
\r
3944 <TD width=10% BGCOLOR=#C0FFC0>
\r
3947 <TD width=10% BGCOLOR=#C0FFC0>
\r
3950 <TD width=15% BGCOLOR=#C0FFC0>
\r
3951 <B>Shifted Value</B>
\r
3953 <TD width=35% BGCOLOR=#C0FFC0>
\r
3954 <B>Description</B>
\r
3958 <TD width=15% BGCOLOR=#FBF5EF>
\r
3959 <B>PSU_CRF_APB_APLL_CTRL_RESET</B>
\r
3961 <TD width=15% BGCOLOR=#FBF5EF>
\r
3964 <TD width=10% BGCOLOR=#FBF5EF>
\r
3967 <TD width=10% BGCOLOR=#FBF5EF>
\r
3970 <TD width=15% BGCOLOR=#FBF5EF>
\r
3973 <TD width=35% BGCOLOR=#FBF5EF>
\r
3974 <B>Asserts Reset to the PLL</B>
\r
3978 <TD width=15% BGCOLOR=#C0C0C0>
\r
3979 <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B>
\r
3981 <TD width=15% BGCOLOR=#C0C0C0>
\r
3984 <TD width=10% BGCOLOR=#C0C0C0>
\r
3987 <TD width=10% BGCOLOR=#C0C0C0>
\r
3990 <TD width=15% BGCOLOR=#C0C0C0>
\r
3993 <TD width=35% BGCOLOR=#C0C0C0>
\r
3994 <B>PLL Basic Control</B>
\r
3999 <H1>DEASSERT RESET</H1>
\r
4000 <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2>
\r
4001 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4003 <TD width=15% BGCOLOR=#FFFF00>
\r
4004 <B>Register Name</B>
\r
4006 <TD width=15% BGCOLOR=#FFFF00>
\r
4009 <TD width=10% BGCOLOR=#FFFF00>
\r
4012 <TD width=10% BGCOLOR=#FFFF00>
\r
4015 <TD width=15% BGCOLOR=#FFFF00>
\r
4016 <B>Reset Value</B>
\r
4018 <TD width=35% BGCOLOR=#FFFF00>
\r
4019 <B>Description</B>
\r
4023 <TD width=15% BGCOLOR=#FBF5EF>
\r
4026 <TD width=15% BGCOLOR=#FBF5EF>
\r
4029 <TD width=10% BGCOLOR=#FBF5EF>
\r
4032 <TD width=10% BGCOLOR=#FBF5EF>
\r
4035 <TD width=15% BGCOLOR=#FBF5EF>
\r
4038 <TD width=35% BGCOLOR=#FBF5EF>
\r
4044 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4046 <TD width=15% BGCOLOR=#C0FFC0>
\r
4049 <TD width=15% BGCOLOR=#C0FFC0>
\r
4052 <TD width=10% BGCOLOR=#C0FFC0>
\r
4055 <TD width=10% BGCOLOR=#C0FFC0>
\r
4058 <TD width=15% BGCOLOR=#C0FFC0>
\r
4059 <B>Shifted Value</B>
\r
4061 <TD width=35% BGCOLOR=#C0FFC0>
\r
4062 <B>Description</B>
\r
4066 <TD width=15% BGCOLOR=#FBF5EF>
\r
4067 <B>PSU_CRF_APB_APLL_CTRL_RESET</B>
\r
4069 <TD width=15% BGCOLOR=#FBF5EF>
\r
4072 <TD width=10% BGCOLOR=#FBF5EF>
\r
4075 <TD width=10% BGCOLOR=#FBF5EF>
\r
4078 <TD width=15% BGCOLOR=#FBF5EF>
\r
4081 <TD width=35% BGCOLOR=#FBF5EF>
\r
4082 <B>Asserts Reset to the PLL</B>
\r
4086 <TD width=15% BGCOLOR=#C0C0C0>
\r
4087 <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B>
\r
4089 <TD width=15% BGCOLOR=#C0C0C0>
\r
4092 <TD width=10% BGCOLOR=#C0C0C0>
\r
4095 <TD width=10% BGCOLOR=#C0C0C0>
\r
4098 <TD width=15% BGCOLOR=#C0C0C0>
\r
4101 <TD width=35% BGCOLOR=#C0C0C0>
\r
4102 <B>PLL Basic Control</B>
\r
4107 <H1>CHECK PLL STATUS</H1>
\r
4108 <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
\r
4109 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4111 <TD width=15% BGCOLOR=#FFFF00>
\r
4112 <B>Register Name</B>
\r
4114 <TD width=15% BGCOLOR=#FFFF00>
\r
4117 <TD width=10% BGCOLOR=#FFFF00>
\r
4120 <TD width=10% BGCOLOR=#FFFF00>
\r
4123 <TD width=15% BGCOLOR=#FFFF00>
\r
4124 <B>Reset Value</B>
\r
4126 <TD width=35% BGCOLOR=#FFFF00>
\r
4127 <B>Description</B>
\r
4131 <TD width=15% BGCOLOR=#FBF5EF>
\r
4134 <TD width=15% BGCOLOR=#FBF5EF>
\r
4137 <TD width=10% BGCOLOR=#FBF5EF>
\r
4140 <TD width=10% BGCOLOR=#FBF5EF>
\r
4143 <TD width=15% BGCOLOR=#FBF5EF>
\r
4146 <TD width=35% BGCOLOR=#FBF5EF>
\r
4152 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4154 <TD width=15% BGCOLOR=#C0FFC0>
\r
4157 <TD width=15% BGCOLOR=#C0FFC0>
\r
4160 <TD width=10% BGCOLOR=#C0FFC0>
\r
4163 <TD width=10% BGCOLOR=#C0FFC0>
\r
4166 <TD width=15% BGCOLOR=#C0FFC0>
\r
4167 <B>Shifted Value</B>
\r
4169 <TD width=35% BGCOLOR=#C0FFC0>
\r
4170 <B>Description</B>
\r
4174 <TD width=15% BGCOLOR=#FBF5EF>
\r
4175 <B>PSU_CRF_APB_PLL_STATUS_APLL_LOCK</B>
\r
4177 <TD width=15% BGCOLOR=#FBF5EF>
\r
4180 <TD width=10% BGCOLOR=#FBF5EF>
\r
4183 <TD width=10% BGCOLOR=#FBF5EF>
\r
4186 <TD width=15% BGCOLOR=#FBF5EF>
\r
4189 <TD width=35% BGCOLOR=#FBF5EF>
\r
4190 <B>APLL is locked</B>
\r
4194 <TD width=15% BGCOLOR=#C0C0C0>
\r
4195 <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B>
\r
4197 <TD width=15% BGCOLOR=#C0C0C0>
\r
4200 <TD width=10% BGCOLOR=#C0C0C0>
\r
4203 <TD width=10% BGCOLOR=#C0C0C0>
\r
4206 <TD width=15% BGCOLOR=#C0C0C0>
\r
4209 <TD width=35% BGCOLOR=#C0C0C0>
\r
4215 <H1>REMOVE PLL BY PASS</H1>
\r
4216 <H2><a name="APLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_CTRL</a></H2>
\r
4217 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4219 <TD width=15% BGCOLOR=#FFFF00>
\r
4220 <B>Register Name</B>
\r
4222 <TD width=15% BGCOLOR=#FFFF00>
\r
4225 <TD width=10% BGCOLOR=#FFFF00>
\r
4228 <TD width=10% BGCOLOR=#FFFF00>
\r
4231 <TD width=15% BGCOLOR=#FFFF00>
\r
4232 <B>Reset Value</B>
\r
4234 <TD width=35% BGCOLOR=#FFFF00>
\r
4235 <B>Description</B>
\r
4239 <TD width=15% BGCOLOR=#FBF5EF>
\r
4242 <TD width=15% BGCOLOR=#FBF5EF>
\r
4245 <TD width=10% BGCOLOR=#FBF5EF>
\r
4248 <TD width=10% BGCOLOR=#FBF5EF>
\r
4251 <TD width=15% BGCOLOR=#FBF5EF>
\r
4254 <TD width=35% BGCOLOR=#FBF5EF>
\r
4260 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4262 <TD width=15% BGCOLOR=#C0FFC0>
\r
4265 <TD width=15% BGCOLOR=#C0FFC0>
\r
4268 <TD width=10% BGCOLOR=#C0FFC0>
\r
4271 <TD width=10% BGCOLOR=#C0FFC0>
\r
4274 <TD width=15% BGCOLOR=#C0FFC0>
\r
4275 <B>Shifted Value</B>
\r
4277 <TD width=35% BGCOLOR=#C0FFC0>
\r
4278 <B>Description</B>
\r
4282 <TD width=15% BGCOLOR=#FBF5EF>
\r
4283 <B>PSU_CRF_APB_APLL_CTRL_BYPASS</B>
\r
4285 <TD width=15% BGCOLOR=#FBF5EF>
\r
4288 <TD width=10% BGCOLOR=#FBF5EF>
\r
4291 <TD width=10% BGCOLOR=#FBF5EF>
\r
4294 <TD width=15% BGCOLOR=#FBF5EF>
\r
4297 <TD width=35% BGCOLOR=#FBF5EF>
\r
4298 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
4302 <TD width=15% BGCOLOR=#C0C0C0>
\r
4303 <B>PSU_CRF_APB_APLL_CTRL@0XFD1A0020</B>
\r
4305 <TD width=15% BGCOLOR=#C0C0C0>
\r
4308 <TD width=10% BGCOLOR=#C0C0C0>
\r
4311 <TD width=10% BGCOLOR=#C0C0C0>
\r
4314 <TD width=15% BGCOLOR=#C0C0C0>
\r
4317 <TD width=35% BGCOLOR=#C0C0C0>
\r
4318 <B>PLL Basic Control</B>
\r
4323 <H2><a name="APLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)APLL_TO_LPD_CTRL</a></H2>
\r
4324 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4326 <TD width=15% BGCOLOR=#FFFF00>
\r
4327 <B>Register Name</B>
\r
4329 <TD width=15% BGCOLOR=#FFFF00>
\r
4332 <TD width=10% BGCOLOR=#FFFF00>
\r
4335 <TD width=10% BGCOLOR=#FFFF00>
\r
4338 <TD width=15% BGCOLOR=#FFFF00>
\r
4339 <B>Reset Value</B>
\r
4341 <TD width=35% BGCOLOR=#FFFF00>
\r
4342 <B>Description</B>
\r
4346 <TD width=15% BGCOLOR=#FBF5EF>
\r
4347 <B>APLL_TO_LPD_CTRL</B>
\r
4349 <TD width=15% BGCOLOR=#FBF5EF>
\r
4352 <TD width=10% BGCOLOR=#FBF5EF>
\r
4355 <TD width=10% BGCOLOR=#FBF5EF>
\r
4358 <TD width=15% BGCOLOR=#FBF5EF>
\r
4361 <TD width=35% BGCOLOR=#FBF5EF>
\r
4367 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4369 <TD width=15% BGCOLOR=#C0FFC0>
\r
4372 <TD width=15% BGCOLOR=#C0FFC0>
\r
4375 <TD width=10% BGCOLOR=#C0FFC0>
\r
4378 <TD width=10% BGCOLOR=#C0FFC0>
\r
4381 <TD width=15% BGCOLOR=#C0FFC0>
\r
4382 <B>Shifted Value</B>
\r
4384 <TD width=35% BGCOLOR=#C0FFC0>
\r
4385 <B>Description</B>
\r
4389 <TD width=15% BGCOLOR=#FBF5EF>
\r
4390 <B>PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0</B>
\r
4392 <TD width=15% BGCOLOR=#FBF5EF>
\r
4395 <TD width=10% BGCOLOR=#FBF5EF>
\r
4398 <TD width=10% BGCOLOR=#FBF5EF>
\r
4401 <TD width=15% BGCOLOR=#FBF5EF>
\r
4404 <TD width=35% BGCOLOR=#FBF5EF>
\r
4405 <B>Divisor value for this clock.</B>
\r
4409 <TD width=15% BGCOLOR=#C0C0C0>
\r
4410 <B>PSU_CRF_APB_APLL_TO_LPD_CTRL@0XFD1A0048</B>
\r
4412 <TD width=15% BGCOLOR=#C0C0C0>
\r
4415 <TD width=10% BGCOLOR=#C0C0C0>
\r
4418 <TD width=10% BGCOLOR=#C0C0C0>
\r
4421 <TD width=15% BGCOLOR=#C0C0C0>
\r
4424 <TD width=35% BGCOLOR=#C0C0C0>
\r
4425 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
4430 <H1>APLL FRAC CFG</H1>
\r
4431 <H1>DDR_PLL INIT</H1>
\r
4432 <H1>UPDATE FB_DIV</H1>
\r
4433 <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2>
\r
4434 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4436 <TD width=15% BGCOLOR=#FFFF00>
\r
4437 <B>Register Name</B>
\r
4439 <TD width=15% BGCOLOR=#FFFF00>
\r
4442 <TD width=10% BGCOLOR=#FFFF00>
\r
4445 <TD width=10% BGCOLOR=#FFFF00>
\r
4448 <TD width=15% BGCOLOR=#FFFF00>
\r
4449 <B>Reset Value</B>
\r
4451 <TD width=35% BGCOLOR=#FFFF00>
\r
4452 <B>Description</B>
\r
4456 <TD width=15% BGCOLOR=#FBF5EF>
\r
4459 <TD width=15% BGCOLOR=#FBF5EF>
\r
4462 <TD width=10% BGCOLOR=#FBF5EF>
\r
4465 <TD width=10% BGCOLOR=#FBF5EF>
\r
4468 <TD width=15% BGCOLOR=#FBF5EF>
\r
4471 <TD width=35% BGCOLOR=#FBF5EF>
\r
4477 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4479 <TD width=15% BGCOLOR=#C0FFC0>
\r
4482 <TD width=15% BGCOLOR=#C0FFC0>
\r
4485 <TD width=10% BGCOLOR=#C0FFC0>
\r
4488 <TD width=10% BGCOLOR=#C0FFC0>
\r
4491 <TD width=15% BGCOLOR=#C0FFC0>
\r
4492 <B>Shifted Value</B>
\r
4494 <TD width=35% BGCOLOR=#C0FFC0>
\r
4495 <B>Description</B>
\r
4499 <TD width=15% BGCOLOR=#FBF5EF>
\r
4500 <B>PSU_CRF_APB_DPLL_CTRL_FBDIV</B>
\r
4502 <TD width=15% BGCOLOR=#FBF5EF>
\r
4505 <TD width=10% BGCOLOR=#FBF5EF>
\r
4508 <TD width=10% BGCOLOR=#FBF5EF>
\r
4511 <TD width=15% BGCOLOR=#FBF5EF>
\r
4514 <TD width=35% BGCOLOR=#FBF5EF>
\r
4515 <B>The integer portion of the feedback divider to the PLL</B>
\r
4519 <TD width=15% BGCOLOR=#FBF5EF>
\r
4520 <B>PSU_CRF_APB_DPLL_CTRL_DIV2</B>
\r
4522 <TD width=15% BGCOLOR=#FBF5EF>
\r
4525 <TD width=10% BGCOLOR=#FBF5EF>
\r
4528 <TD width=10% BGCOLOR=#FBF5EF>
\r
4531 <TD width=15% BGCOLOR=#FBF5EF>
\r
4534 <TD width=35% BGCOLOR=#FBF5EF>
\r
4535 <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B>
\r
4539 <TD width=15% BGCOLOR=#C0C0C0>
\r
4540 <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B>
\r
4542 <TD width=15% BGCOLOR=#C0C0C0>
\r
4545 <TD width=10% BGCOLOR=#C0C0C0>
\r
4548 <TD width=10% BGCOLOR=#C0C0C0>
\r
4551 <TD width=15% BGCOLOR=#C0C0C0>
\r
4554 <TD width=35% BGCOLOR=#C0C0C0>
\r
4555 <B>PLL Basic Control</B>
\r
4560 <H1>BY PASS PLL</H1>
\r
4561 <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2>
\r
4562 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4564 <TD width=15% BGCOLOR=#FFFF00>
\r
4565 <B>Register Name</B>
\r
4567 <TD width=15% BGCOLOR=#FFFF00>
\r
4570 <TD width=10% BGCOLOR=#FFFF00>
\r
4573 <TD width=10% BGCOLOR=#FFFF00>
\r
4576 <TD width=15% BGCOLOR=#FFFF00>
\r
4577 <B>Reset Value</B>
\r
4579 <TD width=35% BGCOLOR=#FFFF00>
\r
4580 <B>Description</B>
\r
4584 <TD width=15% BGCOLOR=#FBF5EF>
\r
4587 <TD width=15% BGCOLOR=#FBF5EF>
\r
4590 <TD width=10% BGCOLOR=#FBF5EF>
\r
4593 <TD width=10% BGCOLOR=#FBF5EF>
\r
4596 <TD width=15% BGCOLOR=#FBF5EF>
\r
4599 <TD width=35% BGCOLOR=#FBF5EF>
\r
4605 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4607 <TD width=15% BGCOLOR=#C0FFC0>
\r
4610 <TD width=15% BGCOLOR=#C0FFC0>
\r
4613 <TD width=10% BGCOLOR=#C0FFC0>
\r
4616 <TD width=10% BGCOLOR=#C0FFC0>
\r
4619 <TD width=15% BGCOLOR=#C0FFC0>
\r
4620 <B>Shifted Value</B>
\r
4622 <TD width=35% BGCOLOR=#C0FFC0>
\r
4623 <B>Description</B>
\r
4627 <TD width=15% BGCOLOR=#FBF5EF>
\r
4628 <B>PSU_CRF_APB_DPLL_CTRL_BYPASS</B>
\r
4630 <TD width=15% BGCOLOR=#FBF5EF>
\r
4633 <TD width=10% BGCOLOR=#FBF5EF>
\r
4636 <TD width=10% BGCOLOR=#FBF5EF>
\r
4639 <TD width=15% BGCOLOR=#FBF5EF>
\r
4642 <TD width=35% BGCOLOR=#FBF5EF>
\r
4643 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
4647 <TD width=15% BGCOLOR=#C0C0C0>
\r
4648 <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B>
\r
4650 <TD width=15% BGCOLOR=#C0C0C0>
\r
4653 <TD width=10% BGCOLOR=#C0C0C0>
\r
4656 <TD width=10% BGCOLOR=#C0C0C0>
\r
4659 <TD width=15% BGCOLOR=#C0C0C0>
\r
4662 <TD width=35% BGCOLOR=#C0C0C0>
\r
4663 <B>PLL Basic Control</B>
\r
4668 <H1>ASSERT RESET</H1>
\r
4669 <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2>
\r
4670 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4672 <TD width=15% BGCOLOR=#FFFF00>
\r
4673 <B>Register Name</B>
\r
4675 <TD width=15% BGCOLOR=#FFFF00>
\r
4678 <TD width=10% BGCOLOR=#FFFF00>
\r
4681 <TD width=10% BGCOLOR=#FFFF00>
\r
4684 <TD width=15% BGCOLOR=#FFFF00>
\r
4685 <B>Reset Value</B>
\r
4687 <TD width=35% BGCOLOR=#FFFF00>
\r
4688 <B>Description</B>
\r
4692 <TD width=15% BGCOLOR=#FBF5EF>
\r
4695 <TD width=15% BGCOLOR=#FBF5EF>
\r
4698 <TD width=10% BGCOLOR=#FBF5EF>
\r
4701 <TD width=10% BGCOLOR=#FBF5EF>
\r
4704 <TD width=15% BGCOLOR=#FBF5EF>
\r
4707 <TD width=35% BGCOLOR=#FBF5EF>
\r
4713 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4715 <TD width=15% BGCOLOR=#C0FFC0>
\r
4718 <TD width=15% BGCOLOR=#C0FFC0>
\r
4721 <TD width=10% BGCOLOR=#C0FFC0>
\r
4724 <TD width=10% BGCOLOR=#C0FFC0>
\r
4727 <TD width=15% BGCOLOR=#C0FFC0>
\r
4728 <B>Shifted Value</B>
\r
4730 <TD width=35% BGCOLOR=#C0FFC0>
\r
4731 <B>Description</B>
\r
4735 <TD width=15% BGCOLOR=#FBF5EF>
\r
4736 <B>PSU_CRF_APB_DPLL_CTRL_RESET</B>
\r
4738 <TD width=15% BGCOLOR=#FBF5EF>
\r
4741 <TD width=10% BGCOLOR=#FBF5EF>
\r
4744 <TD width=10% BGCOLOR=#FBF5EF>
\r
4747 <TD width=15% BGCOLOR=#FBF5EF>
\r
4750 <TD width=35% BGCOLOR=#FBF5EF>
\r
4751 <B>Asserts Reset to the PLL</B>
\r
4755 <TD width=15% BGCOLOR=#C0C0C0>
\r
4756 <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B>
\r
4758 <TD width=15% BGCOLOR=#C0C0C0>
\r
4761 <TD width=10% BGCOLOR=#C0C0C0>
\r
4764 <TD width=10% BGCOLOR=#C0C0C0>
\r
4767 <TD width=15% BGCOLOR=#C0C0C0>
\r
4770 <TD width=35% BGCOLOR=#C0C0C0>
\r
4771 <B>PLL Basic Control</B>
\r
4776 <H1>DEASSERT RESET</H1>
\r
4777 <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2>
\r
4778 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4780 <TD width=15% BGCOLOR=#FFFF00>
\r
4781 <B>Register Name</B>
\r
4783 <TD width=15% BGCOLOR=#FFFF00>
\r
4786 <TD width=10% BGCOLOR=#FFFF00>
\r
4789 <TD width=10% BGCOLOR=#FFFF00>
\r
4792 <TD width=15% BGCOLOR=#FFFF00>
\r
4793 <B>Reset Value</B>
\r
4795 <TD width=35% BGCOLOR=#FFFF00>
\r
4796 <B>Description</B>
\r
4800 <TD width=15% BGCOLOR=#FBF5EF>
\r
4803 <TD width=15% BGCOLOR=#FBF5EF>
\r
4806 <TD width=10% BGCOLOR=#FBF5EF>
\r
4809 <TD width=10% BGCOLOR=#FBF5EF>
\r
4812 <TD width=15% BGCOLOR=#FBF5EF>
\r
4815 <TD width=35% BGCOLOR=#FBF5EF>
\r
4821 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4823 <TD width=15% BGCOLOR=#C0FFC0>
\r
4826 <TD width=15% BGCOLOR=#C0FFC0>
\r
4829 <TD width=10% BGCOLOR=#C0FFC0>
\r
4832 <TD width=10% BGCOLOR=#C0FFC0>
\r
4835 <TD width=15% BGCOLOR=#C0FFC0>
\r
4836 <B>Shifted Value</B>
\r
4838 <TD width=35% BGCOLOR=#C0FFC0>
\r
4839 <B>Description</B>
\r
4843 <TD width=15% BGCOLOR=#FBF5EF>
\r
4844 <B>PSU_CRF_APB_DPLL_CTRL_RESET</B>
\r
4846 <TD width=15% BGCOLOR=#FBF5EF>
\r
4849 <TD width=10% BGCOLOR=#FBF5EF>
\r
4852 <TD width=10% BGCOLOR=#FBF5EF>
\r
4855 <TD width=15% BGCOLOR=#FBF5EF>
\r
4858 <TD width=35% BGCOLOR=#FBF5EF>
\r
4859 <B>Asserts Reset to the PLL</B>
\r
4863 <TD width=15% BGCOLOR=#C0C0C0>
\r
4864 <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B>
\r
4866 <TD width=15% BGCOLOR=#C0C0C0>
\r
4869 <TD width=10% BGCOLOR=#C0C0C0>
\r
4872 <TD width=10% BGCOLOR=#C0C0C0>
\r
4875 <TD width=15% BGCOLOR=#C0C0C0>
\r
4878 <TD width=35% BGCOLOR=#C0C0C0>
\r
4879 <B>PLL Basic Control</B>
\r
4884 <H1>CHECK PLL STATUS</H1>
\r
4885 <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
\r
4886 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4888 <TD width=15% BGCOLOR=#FFFF00>
\r
4889 <B>Register Name</B>
\r
4891 <TD width=15% BGCOLOR=#FFFF00>
\r
4894 <TD width=10% BGCOLOR=#FFFF00>
\r
4897 <TD width=10% BGCOLOR=#FFFF00>
\r
4900 <TD width=15% BGCOLOR=#FFFF00>
\r
4901 <B>Reset Value</B>
\r
4903 <TD width=35% BGCOLOR=#FFFF00>
\r
4904 <B>Description</B>
\r
4908 <TD width=15% BGCOLOR=#FBF5EF>
\r
4911 <TD width=15% BGCOLOR=#FBF5EF>
\r
4914 <TD width=10% BGCOLOR=#FBF5EF>
\r
4917 <TD width=10% BGCOLOR=#FBF5EF>
\r
4920 <TD width=15% BGCOLOR=#FBF5EF>
\r
4923 <TD width=35% BGCOLOR=#FBF5EF>
\r
4929 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4931 <TD width=15% BGCOLOR=#C0FFC0>
\r
4934 <TD width=15% BGCOLOR=#C0FFC0>
\r
4937 <TD width=10% BGCOLOR=#C0FFC0>
\r
4940 <TD width=10% BGCOLOR=#C0FFC0>
\r
4943 <TD width=15% BGCOLOR=#C0FFC0>
\r
4944 <B>Shifted Value</B>
\r
4946 <TD width=35% BGCOLOR=#C0FFC0>
\r
4947 <B>Description</B>
\r
4951 <TD width=15% BGCOLOR=#FBF5EF>
\r
4952 <B>PSU_CRF_APB_PLL_STATUS_DPLL_LOCK</B>
\r
4954 <TD width=15% BGCOLOR=#FBF5EF>
\r
4957 <TD width=10% BGCOLOR=#FBF5EF>
\r
4960 <TD width=10% BGCOLOR=#FBF5EF>
\r
4963 <TD width=15% BGCOLOR=#FBF5EF>
\r
4966 <TD width=35% BGCOLOR=#FBF5EF>
\r
4967 <B>DPLL is locked</B>
\r
4971 <TD width=15% BGCOLOR=#C0C0C0>
\r
4972 <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B>
\r
4974 <TD width=15% BGCOLOR=#C0C0C0>
\r
4977 <TD width=10% BGCOLOR=#C0C0C0>
\r
4980 <TD width=10% BGCOLOR=#C0C0C0>
\r
4983 <TD width=15% BGCOLOR=#C0C0C0>
\r
4986 <TD width=35% BGCOLOR=#C0C0C0>
\r
4992 <H1>REMOVE PLL BY PASS</H1>
\r
4993 <H2><a name="DPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_CTRL</a></H2>
\r
4994 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
4996 <TD width=15% BGCOLOR=#FFFF00>
\r
4997 <B>Register Name</B>
\r
4999 <TD width=15% BGCOLOR=#FFFF00>
\r
5002 <TD width=10% BGCOLOR=#FFFF00>
\r
5005 <TD width=10% BGCOLOR=#FFFF00>
\r
5008 <TD width=15% BGCOLOR=#FFFF00>
\r
5009 <B>Reset Value</B>
\r
5011 <TD width=35% BGCOLOR=#FFFF00>
\r
5012 <B>Description</B>
\r
5016 <TD width=15% BGCOLOR=#FBF5EF>
\r
5019 <TD width=15% BGCOLOR=#FBF5EF>
\r
5022 <TD width=10% BGCOLOR=#FBF5EF>
\r
5025 <TD width=10% BGCOLOR=#FBF5EF>
\r
5028 <TD width=15% BGCOLOR=#FBF5EF>
\r
5031 <TD width=35% BGCOLOR=#FBF5EF>
\r
5037 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5039 <TD width=15% BGCOLOR=#C0FFC0>
\r
5042 <TD width=15% BGCOLOR=#C0FFC0>
\r
5045 <TD width=10% BGCOLOR=#C0FFC0>
\r
5048 <TD width=10% BGCOLOR=#C0FFC0>
\r
5051 <TD width=15% BGCOLOR=#C0FFC0>
\r
5052 <B>Shifted Value</B>
\r
5054 <TD width=35% BGCOLOR=#C0FFC0>
\r
5055 <B>Description</B>
\r
5059 <TD width=15% BGCOLOR=#FBF5EF>
\r
5060 <B>PSU_CRF_APB_DPLL_CTRL_BYPASS</B>
\r
5062 <TD width=15% BGCOLOR=#FBF5EF>
\r
5065 <TD width=10% BGCOLOR=#FBF5EF>
\r
5068 <TD width=10% BGCOLOR=#FBF5EF>
\r
5071 <TD width=15% BGCOLOR=#FBF5EF>
\r
5074 <TD width=35% BGCOLOR=#FBF5EF>
\r
5075 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
5079 <TD width=15% BGCOLOR=#C0C0C0>
\r
5080 <B>PSU_CRF_APB_DPLL_CTRL@0XFD1A002C</B>
\r
5082 <TD width=15% BGCOLOR=#C0C0C0>
\r
5085 <TD width=10% BGCOLOR=#C0C0C0>
\r
5088 <TD width=10% BGCOLOR=#C0C0C0>
\r
5091 <TD width=15% BGCOLOR=#C0C0C0>
\r
5094 <TD width=35% BGCOLOR=#C0C0C0>
\r
5095 <B>PLL Basic Control</B>
\r
5100 <H2><a name="DPLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPLL_TO_LPD_CTRL</a></H2>
\r
5101 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5103 <TD width=15% BGCOLOR=#FFFF00>
\r
5104 <B>Register Name</B>
\r
5106 <TD width=15% BGCOLOR=#FFFF00>
\r
5109 <TD width=10% BGCOLOR=#FFFF00>
\r
5112 <TD width=10% BGCOLOR=#FFFF00>
\r
5115 <TD width=15% BGCOLOR=#FFFF00>
\r
5116 <B>Reset Value</B>
\r
5118 <TD width=35% BGCOLOR=#FFFF00>
\r
5119 <B>Description</B>
\r
5123 <TD width=15% BGCOLOR=#FBF5EF>
\r
5124 <B>DPLL_TO_LPD_CTRL</B>
\r
5126 <TD width=15% BGCOLOR=#FBF5EF>
\r
5129 <TD width=10% BGCOLOR=#FBF5EF>
\r
5132 <TD width=10% BGCOLOR=#FBF5EF>
\r
5135 <TD width=15% BGCOLOR=#FBF5EF>
\r
5138 <TD width=35% BGCOLOR=#FBF5EF>
\r
5144 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5146 <TD width=15% BGCOLOR=#C0FFC0>
\r
5149 <TD width=15% BGCOLOR=#C0FFC0>
\r
5152 <TD width=10% BGCOLOR=#C0FFC0>
\r
5155 <TD width=10% BGCOLOR=#C0FFC0>
\r
5158 <TD width=15% BGCOLOR=#C0FFC0>
\r
5159 <B>Shifted Value</B>
\r
5161 <TD width=35% BGCOLOR=#C0FFC0>
\r
5162 <B>Description</B>
\r
5166 <TD width=15% BGCOLOR=#FBF5EF>
\r
5167 <B>PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0</B>
\r
5169 <TD width=15% BGCOLOR=#FBF5EF>
\r
5172 <TD width=10% BGCOLOR=#FBF5EF>
\r
5175 <TD width=10% BGCOLOR=#FBF5EF>
\r
5178 <TD width=15% BGCOLOR=#FBF5EF>
\r
5181 <TD width=35% BGCOLOR=#FBF5EF>
\r
5182 <B>Divisor value for this clock.</B>
\r
5186 <TD width=15% BGCOLOR=#C0C0C0>
\r
5187 <B>PSU_CRF_APB_DPLL_TO_LPD_CTRL@0XFD1A004C</B>
\r
5189 <TD width=15% BGCOLOR=#C0C0C0>
\r
5192 <TD width=10% BGCOLOR=#C0C0C0>
\r
5195 <TD width=10% BGCOLOR=#C0C0C0>
\r
5198 <TD width=15% BGCOLOR=#C0C0C0>
\r
5201 <TD width=35% BGCOLOR=#C0C0C0>
\r
5202 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
5207 <H1>DPLL FRAC CFG</H1>
\r
5208 <H1>VIDEO_PLL INIT</H1>
\r
5209 <H1>UPDATE FB_DIV</H1>
\r
5210 <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2>
\r
5211 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5213 <TD width=15% BGCOLOR=#FFFF00>
\r
5214 <B>Register Name</B>
\r
5216 <TD width=15% BGCOLOR=#FFFF00>
\r
5219 <TD width=10% BGCOLOR=#FFFF00>
\r
5222 <TD width=10% BGCOLOR=#FFFF00>
\r
5225 <TD width=15% BGCOLOR=#FFFF00>
\r
5226 <B>Reset Value</B>
\r
5228 <TD width=35% BGCOLOR=#FFFF00>
\r
5229 <B>Description</B>
\r
5233 <TD width=15% BGCOLOR=#FBF5EF>
\r
5236 <TD width=15% BGCOLOR=#FBF5EF>
\r
5239 <TD width=10% BGCOLOR=#FBF5EF>
\r
5242 <TD width=10% BGCOLOR=#FBF5EF>
\r
5245 <TD width=15% BGCOLOR=#FBF5EF>
\r
5248 <TD width=35% BGCOLOR=#FBF5EF>
\r
5254 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5256 <TD width=15% BGCOLOR=#C0FFC0>
\r
5259 <TD width=15% BGCOLOR=#C0FFC0>
\r
5262 <TD width=10% BGCOLOR=#C0FFC0>
\r
5265 <TD width=10% BGCOLOR=#C0FFC0>
\r
5268 <TD width=15% BGCOLOR=#C0FFC0>
\r
5269 <B>Shifted Value</B>
\r
5271 <TD width=35% BGCOLOR=#C0FFC0>
\r
5272 <B>Description</B>
\r
5276 <TD width=15% BGCOLOR=#FBF5EF>
\r
5277 <B>PSU_CRF_APB_VPLL_CTRL_FBDIV</B>
\r
5279 <TD width=15% BGCOLOR=#FBF5EF>
\r
5282 <TD width=10% BGCOLOR=#FBF5EF>
\r
5285 <TD width=10% BGCOLOR=#FBF5EF>
\r
5288 <TD width=15% BGCOLOR=#FBF5EF>
\r
5291 <TD width=35% BGCOLOR=#FBF5EF>
\r
5292 <B>The integer portion of the feedback divider to the PLL</B>
\r
5296 <TD width=15% BGCOLOR=#FBF5EF>
\r
5297 <B>PSU_CRF_APB_VPLL_CTRL_DIV2</B>
\r
5299 <TD width=15% BGCOLOR=#FBF5EF>
\r
5302 <TD width=10% BGCOLOR=#FBF5EF>
\r
5305 <TD width=10% BGCOLOR=#FBF5EF>
\r
5308 <TD width=15% BGCOLOR=#FBF5EF>
\r
5311 <TD width=35% BGCOLOR=#FBF5EF>
\r
5312 <B>This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency</B>
\r
5316 <TD width=15% BGCOLOR=#C0C0C0>
\r
5317 <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B>
\r
5319 <TD width=15% BGCOLOR=#C0C0C0>
\r
5322 <TD width=10% BGCOLOR=#C0C0C0>
\r
5325 <TD width=10% BGCOLOR=#C0C0C0>
\r
5328 <TD width=15% BGCOLOR=#C0C0C0>
\r
5331 <TD width=35% BGCOLOR=#C0C0C0>
\r
5332 <B>PLL Basic Control</B>
\r
5337 <H1>BY PASS PLL</H1>
\r
5338 <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2>
\r
5339 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5341 <TD width=15% BGCOLOR=#FFFF00>
\r
5342 <B>Register Name</B>
\r
5344 <TD width=15% BGCOLOR=#FFFF00>
\r
5347 <TD width=10% BGCOLOR=#FFFF00>
\r
5350 <TD width=10% BGCOLOR=#FFFF00>
\r
5353 <TD width=15% BGCOLOR=#FFFF00>
\r
5354 <B>Reset Value</B>
\r
5356 <TD width=35% BGCOLOR=#FFFF00>
\r
5357 <B>Description</B>
\r
5361 <TD width=15% BGCOLOR=#FBF5EF>
\r
5364 <TD width=15% BGCOLOR=#FBF5EF>
\r
5367 <TD width=10% BGCOLOR=#FBF5EF>
\r
5370 <TD width=10% BGCOLOR=#FBF5EF>
\r
5373 <TD width=15% BGCOLOR=#FBF5EF>
\r
5376 <TD width=35% BGCOLOR=#FBF5EF>
\r
5382 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5384 <TD width=15% BGCOLOR=#C0FFC0>
\r
5387 <TD width=15% BGCOLOR=#C0FFC0>
\r
5390 <TD width=10% BGCOLOR=#C0FFC0>
\r
5393 <TD width=10% BGCOLOR=#C0FFC0>
\r
5396 <TD width=15% BGCOLOR=#C0FFC0>
\r
5397 <B>Shifted Value</B>
\r
5399 <TD width=35% BGCOLOR=#C0FFC0>
\r
5400 <B>Description</B>
\r
5404 <TD width=15% BGCOLOR=#FBF5EF>
\r
5405 <B>PSU_CRF_APB_VPLL_CTRL_BYPASS</B>
\r
5407 <TD width=15% BGCOLOR=#FBF5EF>
\r
5410 <TD width=10% BGCOLOR=#FBF5EF>
\r
5413 <TD width=10% BGCOLOR=#FBF5EF>
\r
5416 <TD width=15% BGCOLOR=#FBF5EF>
\r
5419 <TD width=35% BGCOLOR=#FBF5EF>
\r
5420 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
5424 <TD width=15% BGCOLOR=#C0C0C0>
\r
5425 <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B>
\r
5427 <TD width=15% BGCOLOR=#C0C0C0>
\r
5430 <TD width=10% BGCOLOR=#C0C0C0>
\r
5433 <TD width=10% BGCOLOR=#C0C0C0>
\r
5436 <TD width=15% BGCOLOR=#C0C0C0>
\r
5439 <TD width=35% BGCOLOR=#C0C0C0>
\r
5440 <B>PLL Basic Control</B>
\r
5445 <H1>ASSERT RESET</H1>
\r
5446 <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2>
\r
5447 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5449 <TD width=15% BGCOLOR=#FFFF00>
\r
5450 <B>Register Name</B>
\r
5452 <TD width=15% BGCOLOR=#FFFF00>
\r
5455 <TD width=10% BGCOLOR=#FFFF00>
\r
5458 <TD width=10% BGCOLOR=#FFFF00>
\r
5461 <TD width=15% BGCOLOR=#FFFF00>
\r
5462 <B>Reset Value</B>
\r
5464 <TD width=35% BGCOLOR=#FFFF00>
\r
5465 <B>Description</B>
\r
5469 <TD width=15% BGCOLOR=#FBF5EF>
\r
5472 <TD width=15% BGCOLOR=#FBF5EF>
\r
5475 <TD width=10% BGCOLOR=#FBF5EF>
\r
5478 <TD width=10% BGCOLOR=#FBF5EF>
\r
5481 <TD width=15% BGCOLOR=#FBF5EF>
\r
5484 <TD width=35% BGCOLOR=#FBF5EF>
\r
5490 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5492 <TD width=15% BGCOLOR=#C0FFC0>
\r
5495 <TD width=15% BGCOLOR=#C0FFC0>
\r
5498 <TD width=10% BGCOLOR=#C0FFC0>
\r
5501 <TD width=10% BGCOLOR=#C0FFC0>
\r
5504 <TD width=15% BGCOLOR=#C0FFC0>
\r
5505 <B>Shifted Value</B>
\r
5507 <TD width=35% BGCOLOR=#C0FFC0>
\r
5508 <B>Description</B>
\r
5512 <TD width=15% BGCOLOR=#FBF5EF>
\r
5513 <B>PSU_CRF_APB_VPLL_CTRL_RESET</B>
\r
5515 <TD width=15% BGCOLOR=#FBF5EF>
\r
5518 <TD width=10% BGCOLOR=#FBF5EF>
\r
5521 <TD width=10% BGCOLOR=#FBF5EF>
\r
5524 <TD width=15% BGCOLOR=#FBF5EF>
\r
5527 <TD width=35% BGCOLOR=#FBF5EF>
\r
5528 <B>Asserts Reset to the PLL</B>
\r
5532 <TD width=15% BGCOLOR=#C0C0C0>
\r
5533 <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B>
\r
5535 <TD width=15% BGCOLOR=#C0C0C0>
\r
5538 <TD width=10% BGCOLOR=#C0C0C0>
\r
5541 <TD width=10% BGCOLOR=#C0C0C0>
\r
5544 <TD width=15% BGCOLOR=#C0C0C0>
\r
5547 <TD width=35% BGCOLOR=#C0C0C0>
\r
5548 <B>PLL Basic Control</B>
\r
5553 <H1>DEASSERT RESET</H1>
\r
5554 <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2>
\r
5555 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5557 <TD width=15% BGCOLOR=#FFFF00>
\r
5558 <B>Register Name</B>
\r
5560 <TD width=15% BGCOLOR=#FFFF00>
\r
5563 <TD width=10% BGCOLOR=#FFFF00>
\r
5566 <TD width=10% BGCOLOR=#FFFF00>
\r
5569 <TD width=15% BGCOLOR=#FFFF00>
\r
5570 <B>Reset Value</B>
\r
5572 <TD width=35% BGCOLOR=#FFFF00>
\r
5573 <B>Description</B>
\r
5577 <TD width=15% BGCOLOR=#FBF5EF>
\r
5580 <TD width=15% BGCOLOR=#FBF5EF>
\r
5583 <TD width=10% BGCOLOR=#FBF5EF>
\r
5586 <TD width=10% BGCOLOR=#FBF5EF>
\r
5589 <TD width=15% BGCOLOR=#FBF5EF>
\r
5592 <TD width=35% BGCOLOR=#FBF5EF>
\r
5598 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5600 <TD width=15% BGCOLOR=#C0FFC0>
\r
5603 <TD width=15% BGCOLOR=#C0FFC0>
\r
5606 <TD width=10% BGCOLOR=#C0FFC0>
\r
5609 <TD width=10% BGCOLOR=#C0FFC0>
\r
5612 <TD width=15% BGCOLOR=#C0FFC0>
\r
5613 <B>Shifted Value</B>
\r
5615 <TD width=35% BGCOLOR=#C0FFC0>
\r
5616 <B>Description</B>
\r
5620 <TD width=15% BGCOLOR=#FBF5EF>
\r
5621 <B>PSU_CRF_APB_VPLL_CTRL_RESET</B>
\r
5623 <TD width=15% BGCOLOR=#FBF5EF>
\r
5626 <TD width=10% BGCOLOR=#FBF5EF>
\r
5629 <TD width=10% BGCOLOR=#FBF5EF>
\r
5632 <TD width=15% BGCOLOR=#FBF5EF>
\r
5635 <TD width=35% BGCOLOR=#FBF5EF>
\r
5636 <B>Asserts Reset to the PLL</B>
\r
5640 <TD width=15% BGCOLOR=#C0C0C0>
\r
5641 <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B>
\r
5643 <TD width=15% BGCOLOR=#C0C0C0>
\r
5646 <TD width=10% BGCOLOR=#C0C0C0>
\r
5649 <TD width=10% BGCOLOR=#C0C0C0>
\r
5652 <TD width=15% BGCOLOR=#C0C0C0>
\r
5655 <TD width=35% BGCOLOR=#C0C0C0>
\r
5656 <B>PLL Basic Control</B>
\r
5661 <H1>CHECK PLL STATUS</H1>
\r
5662 <H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
\r
5663 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5665 <TD width=15% BGCOLOR=#FFFF00>
\r
5666 <B>Register Name</B>
\r
5668 <TD width=15% BGCOLOR=#FFFF00>
\r
5671 <TD width=10% BGCOLOR=#FFFF00>
\r
5674 <TD width=10% BGCOLOR=#FFFF00>
\r
5677 <TD width=15% BGCOLOR=#FFFF00>
\r
5678 <B>Reset Value</B>
\r
5680 <TD width=35% BGCOLOR=#FFFF00>
\r
5681 <B>Description</B>
\r
5685 <TD width=15% BGCOLOR=#FBF5EF>
\r
5688 <TD width=15% BGCOLOR=#FBF5EF>
\r
5691 <TD width=10% BGCOLOR=#FBF5EF>
\r
5694 <TD width=10% BGCOLOR=#FBF5EF>
\r
5697 <TD width=15% BGCOLOR=#FBF5EF>
\r
5700 <TD width=35% BGCOLOR=#FBF5EF>
\r
5706 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5708 <TD width=15% BGCOLOR=#C0FFC0>
\r
5711 <TD width=15% BGCOLOR=#C0FFC0>
\r
5714 <TD width=10% BGCOLOR=#C0FFC0>
\r
5717 <TD width=10% BGCOLOR=#C0FFC0>
\r
5720 <TD width=15% BGCOLOR=#C0FFC0>
\r
5721 <B>Shifted Value</B>
\r
5723 <TD width=35% BGCOLOR=#C0FFC0>
\r
5724 <B>Description</B>
\r
5728 <TD width=15% BGCOLOR=#FBF5EF>
\r
5729 <B>PSU_CRF_APB_PLL_STATUS_VPLL_LOCK</B>
\r
5731 <TD width=15% BGCOLOR=#FBF5EF>
\r
5734 <TD width=10% BGCOLOR=#FBF5EF>
\r
5737 <TD width=10% BGCOLOR=#FBF5EF>
\r
5740 <TD width=15% BGCOLOR=#FBF5EF>
\r
5743 <TD width=35% BGCOLOR=#FBF5EF>
\r
5744 <B>VPLL is locked</B>
\r
5748 <TD width=15% BGCOLOR=#C0C0C0>
\r
5749 <B>PSU_CRF_APB_PLL_STATUS@0XFD1A0044</B>
\r
5751 <TD width=15% BGCOLOR=#C0C0C0>
\r
5754 <TD width=10% BGCOLOR=#C0C0C0>
\r
5757 <TD width=10% BGCOLOR=#C0C0C0>
\r
5760 <TD width=15% BGCOLOR=#C0C0C0>
\r
5763 <TD width=35% BGCOLOR=#C0C0C0>
\r
5769 <H1>REMOVE PLL BY PASS</H1>
\r
5770 <H2><a name="VPLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_CTRL</a></H2>
\r
5771 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5773 <TD width=15% BGCOLOR=#FFFF00>
\r
5774 <B>Register Name</B>
\r
5776 <TD width=15% BGCOLOR=#FFFF00>
\r
5779 <TD width=10% BGCOLOR=#FFFF00>
\r
5782 <TD width=10% BGCOLOR=#FFFF00>
\r
5785 <TD width=15% BGCOLOR=#FFFF00>
\r
5786 <B>Reset Value</B>
\r
5788 <TD width=35% BGCOLOR=#FFFF00>
\r
5789 <B>Description</B>
\r
5793 <TD width=15% BGCOLOR=#FBF5EF>
\r
5796 <TD width=15% BGCOLOR=#FBF5EF>
\r
5799 <TD width=10% BGCOLOR=#FBF5EF>
\r
5802 <TD width=10% BGCOLOR=#FBF5EF>
\r
5805 <TD width=15% BGCOLOR=#FBF5EF>
\r
5808 <TD width=35% BGCOLOR=#FBF5EF>
\r
5814 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5816 <TD width=15% BGCOLOR=#C0FFC0>
\r
5819 <TD width=15% BGCOLOR=#C0FFC0>
\r
5822 <TD width=10% BGCOLOR=#C0FFC0>
\r
5825 <TD width=10% BGCOLOR=#C0FFC0>
\r
5828 <TD width=15% BGCOLOR=#C0FFC0>
\r
5829 <B>Shifted Value</B>
\r
5831 <TD width=35% BGCOLOR=#C0FFC0>
\r
5832 <B>Description</B>
\r
5836 <TD width=15% BGCOLOR=#FBF5EF>
\r
5837 <B>PSU_CRF_APB_VPLL_CTRL_BYPASS</B>
\r
5839 <TD width=15% BGCOLOR=#FBF5EF>
\r
5842 <TD width=10% BGCOLOR=#FBF5EF>
\r
5845 <TD width=10% BGCOLOR=#FBF5EF>
\r
5848 <TD width=15% BGCOLOR=#FBF5EF>
\r
5851 <TD width=35% BGCOLOR=#FBF5EF>
\r
5852 <B>Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
5856 <TD width=15% BGCOLOR=#C0C0C0>
\r
5857 <B>PSU_CRF_APB_VPLL_CTRL@0XFD1A0038</B>
\r
5859 <TD width=15% BGCOLOR=#C0C0C0>
\r
5862 <TD width=10% BGCOLOR=#C0C0C0>
\r
5865 <TD width=10% BGCOLOR=#C0C0C0>
\r
5868 <TD width=15% BGCOLOR=#C0C0C0>
\r
5871 <TD width=35% BGCOLOR=#C0C0C0>
\r
5872 <B>PLL Basic Control</B>
\r
5877 <H2><a name="VPLL_TO_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)VPLL_TO_LPD_CTRL</a></H2>
\r
5878 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5880 <TD width=15% BGCOLOR=#FFFF00>
\r
5881 <B>Register Name</B>
\r
5883 <TD width=15% BGCOLOR=#FFFF00>
\r
5886 <TD width=10% BGCOLOR=#FFFF00>
\r
5889 <TD width=10% BGCOLOR=#FFFF00>
\r
5892 <TD width=15% BGCOLOR=#FFFF00>
\r
5893 <B>Reset Value</B>
\r
5895 <TD width=35% BGCOLOR=#FFFF00>
\r
5896 <B>Description</B>
\r
5900 <TD width=15% BGCOLOR=#FBF5EF>
\r
5901 <B>VPLL_TO_LPD_CTRL</B>
\r
5903 <TD width=15% BGCOLOR=#FBF5EF>
\r
5906 <TD width=10% BGCOLOR=#FBF5EF>
\r
5909 <TD width=10% BGCOLOR=#FBF5EF>
\r
5912 <TD width=15% BGCOLOR=#FBF5EF>
\r
5915 <TD width=35% BGCOLOR=#FBF5EF>
\r
5921 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5923 <TD width=15% BGCOLOR=#C0FFC0>
\r
5926 <TD width=15% BGCOLOR=#C0FFC0>
\r
5929 <TD width=10% BGCOLOR=#C0FFC0>
\r
5932 <TD width=10% BGCOLOR=#C0FFC0>
\r
5935 <TD width=15% BGCOLOR=#C0FFC0>
\r
5936 <B>Shifted Value</B>
\r
5938 <TD width=35% BGCOLOR=#C0FFC0>
\r
5939 <B>Description</B>
\r
5943 <TD width=15% BGCOLOR=#FBF5EF>
\r
5944 <B>PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0</B>
\r
5946 <TD width=15% BGCOLOR=#FBF5EF>
\r
5949 <TD width=10% BGCOLOR=#FBF5EF>
\r
5952 <TD width=10% BGCOLOR=#FBF5EF>
\r
5955 <TD width=15% BGCOLOR=#FBF5EF>
\r
5958 <TD width=35% BGCOLOR=#FBF5EF>
\r
5959 <B>Divisor value for this clock.</B>
\r
5963 <TD width=15% BGCOLOR=#C0C0C0>
\r
5964 <B>PSU_CRF_APB_VPLL_TO_LPD_CTRL@0XFD1A0050</B>
\r
5966 <TD width=15% BGCOLOR=#C0C0C0>
\r
5969 <TD width=10% BGCOLOR=#C0C0C0>
\r
5972 <TD width=10% BGCOLOR=#C0C0C0>
\r
5975 <TD width=15% BGCOLOR=#C0C0C0>
\r
5978 <TD width=35% BGCOLOR=#C0C0C0>
\r
5979 <B>Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.</B>
\r
5984 <H1>VIDEO FRAC CFG</H1>
\r
5987 <H2><a name="psu_clock_init_data">psu_clock_init_data</a></H2>
\r
5988 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
5990 <TD width=15% BGCOLOR=#FFC0FF>
\r
5991 <B>Register Name</B>
\r
5993 <TD width=15% BGCOLOR=#FFC0FF>
\r
5996 <TD width=10% BGCOLOR=#FFC0FF>
\r
5999 <TD width=10% BGCOLOR=#FFC0FF>
\r
6002 <TD width=15% BGCOLOR=#FFC0FF>
\r
6003 <B>Reset Value</B>
\r
6005 <TD width=35% BGCOLOR=#FFC0FF>
\r
6006 <B>Description</B>
\r
6010 <TD width=15% BGCOLOR=#FBF5EF>
\r
6011 <A href="#PSU_CRL_APB_GEM0_REF_CTRL">
\r
6012 PSU_CRL_APB_GEM0_REF_CTRL
\r
6015 <TD width=15% BGCOLOR=#FBF5EF>
\r
6018 <TD width=10% BGCOLOR=#FBF5EF>
\r
6021 <TD width=10% BGCOLOR=#FBF5EF>
\r
6024 <TD width=15% BGCOLOR=#FBF5EF>
\r
6027 <TD width=35% BGCOLOR=#FBF5EF>
\r
6028 <B>This register controls this reference clock</B>
\r
6032 <TD width=15% BGCOLOR=#FBF5EF>
\r
6033 <A href="#PSU_CRL_APB_GEM1_REF_CTRL">
\r
6034 PSU_CRL_APB_GEM1_REF_CTRL
\r
6037 <TD width=15% BGCOLOR=#FBF5EF>
\r
6040 <TD width=10% BGCOLOR=#FBF5EF>
\r
6043 <TD width=10% BGCOLOR=#FBF5EF>
\r
6046 <TD width=15% BGCOLOR=#FBF5EF>
\r
6049 <TD width=35% BGCOLOR=#FBF5EF>
\r
6050 <B>This register controls this reference clock</B>
\r
6054 <TD width=15% BGCOLOR=#FBF5EF>
\r
6055 <A href="#PSU_CRL_APB_GEM2_REF_CTRL">
\r
6056 PSU_CRL_APB_GEM2_REF_CTRL
\r
6059 <TD width=15% BGCOLOR=#FBF5EF>
\r
6062 <TD width=10% BGCOLOR=#FBF5EF>
\r
6065 <TD width=10% BGCOLOR=#FBF5EF>
\r
6068 <TD width=15% BGCOLOR=#FBF5EF>
\r
6071 <TD width=35% BGCOLOR=#FBF5EF>
\r
6072 <B>This register controls this reference clock</B>
\r
6076 <TD width=15% BGCOLOR=#FBF5EF>
\r
6077 <A href="#PSU_CRL_APB_GEM3_REF_CTRL">
\r
6078 PSU_CRL_APB_GEM3_REF_CTRL
\r
6081 <TD width=15% BGCOLOR=#FBF5EF>
\r
6084 <TD width=10% BGCOLOR=#FBF5EF>
\r
6087 <TD width=10% BGCOLOR=#FBF5EF>
\r
6090 <TD width=15% BGCOLOR=#FBF5EF>
\r
6093 <TD width=35% BGCOLOR=#FBF5EF>
\r
6094 <B>This register controls this reference clock</B>
\r
6098 <TD width=15% BGCOLOR=#FBF5EF>
\r
6099 <A href="#PSU_CRL_APB_USB0_BUS_REF_CTRL">
\r
6100 PSU_CRL_APB_USB0_BUS_REF_CTRL
\r
6103 <TD width=15% BGCOLOR=#FBF5EF>
\r
6106 <TD width=10% BGCOLOR=#FBF5EF>
\r
6109 <TD width=10% BGCOLOR=#FBF5EF>
\r
6112 <TD width=15% BGCOLOR=#FBF5EF>
\r
6115 <TD width=35% BGCOLOR=#FBF5EF>
\r
6116 <B>This register controls this reference clock</B>
\r
6120 <TD width=15% BGCOLOR=#FBF5EF>
\r
6121 <A href="#PSU_CRL_APB_USB3_DUAL_REF_CTRL">
\r
6122 PSU_CRL_APB_USB3_DUAL_REF_CTRL
\r
6125 <TD width=15% BGCOLOR=#FBF5EF>
\r
6128 <TD width=10% BGCOLOR=#FBF5EF>
\r
6131 <TD width=10% BGCOLOR=#FBF5EF>
\r
6134 <TD width=15% BGCOLOR=#FBF5EF>
\r
6137 <TD width=35% BGCOLOR=#FBF5EF>
\r
6138 <B>This register controls this reference clock</B>
\r
6142 <TD width=15% BGCOLOR=#FBF5EF>
\r
6143 <A href="#PSU_CRL_APB_QSPI_REF_CTRL">
\r
6144 PSU_CRL_APB_QSPI_REF_CTRL
\r
6147 <TD width=15% BGCOLOR=#FBF5EF>
\r
6150 <TD width=10% BGCOLOR=#FBF5EF>
\r
6153 <TD width=10% BGCOLOR=#FBF5EF>
\r
6156 <TD width=15% BGCOLOR=#FBF5EF>
\r
6159 <TD width=35% BGCOLOR=#FBF5EF>
\r
6160 <B>This register controls this reference clock</B>
\r
6164 <TD width=15% BGCOLOR=#FBF5EF>
\r
6165 <A href="#PSU_CRL_APB_SDIO0_REF_CTRL">
\r
6166 PSU_CRL_APB_SDIO0_REF_CTRL
\r
6169 <TD width=15% BGCOLOR=#FBF5EF>
\r
6172 <TD width=10% BGCOLOR=#FBF5EF>
\r
6175 <TD width=10% BGCOLOR=#FBF5EF>
\r
6178 <TD width=15% BGCOLOR=#FBF5EF>
\r
6181 <TD width=35% BGCOLOR=#FBF5EF>
\r
6182 <B>This register controls this reference clock</B>
\r
6186 <TD width=15% BGCOLOR=#FBF5EF>
\r
6187 <A href="#PSU_CRL_APB_SDIO1_REF_CTRL">
\r
6188 PSU_CRL_APB_SDIO1_REF_CTRL
\r
6191 <TD width=15% BGCOLOR=#FBF5EF>
\r
6194 <TD width=10% BGCOLOR=#FBF5EF>
\r
6197 <TD width=10% BGCOLOR=#FBF5EF>
\r
6200 <TD width=15% BGCOLOR=#FBF5EF>
\r
6203 <TD width=35% BGCOLOR=#FBF5EF>
\r
6204 <B>This register controls this reference clock</B>
\r
6208 <TD width=15% BGCOLOR=#FBF5EF>
\r
6209 <A href="#PSU_CRL_APB_UART0_REF_CTRL">
\r
6210 PSU_CRL_APB_UART0_REF_CTRL
\r
6213 <TD width=15% BGCOLOR=#FBF5EF>
\r
6216 <TD width=10% BGCOLOR=#FBF5EF>
\r
6219 <TD width=10% BGCOLOR=#FBF5EF>
\r
6222 <TD width=15% BGCOLOR=#FBF5EF>
\r
6225 <TD width=35% BGCOLOR=#FBF5EF>
\r
6226 <B>This register controls this reference clock</B>
\r
6230 <TD width=15% BGCOLOR=#FBF5EF>
\r
6231 <A href="#PSU_CRL_APB_UART1_REF_CTRL">
\r
6232 PSU_CRL_APB_UART1_REF_CTRL
\r
6235 <TD width=15% BGCOLOR=#FBF5EF>
\r
6238 <TD width=10% BGCOLOR=#FBF5EF>
\r
6241 <TD width=10% BGCOLOR=#FBF5EF>
\r
6244 <TD width=15% BGCOLOR=#FBF5EF>
\r
6247 <TD width=35% BGCOLOR=#FBF5EF>
\r
6248 <B>This register controls this reference clock</B>
\r
6252 <TD width=15% BGCOLOR=#FBF5EF>
\r
6253 <A href="#PSU_CRL_APB_I2C0_REF_CTRL">
\r
6254 PSU_CRL_APB_I2C0_REF_CTRL
\r
6257 <TD width=15% BGCOLOR=#FBF5EF>
\r
6260 <TD width=10% BGCOLOR=#FBF5EF>
\r
6263 <TD width=10% BGCOLOR=#FBF5EF>
\r
6266 <TD width=15% BGCOLOR=#FBF5EF>
\r
6269 <TD width=35% BGCOLOR=#FBF5EF>
\r
6270 <B>This register controls this reference clock</B>
\r
6274 <TD width=15% BGCOLOR=#FBF5EF>
\r
6275 <A href="#PSU_CRL_APB_I2C1_REF_CTRL">
\r
6276 PSU_CRL_APB_I2C1_REF_CTRL
\r
6279 <TD width=15% BGCOLOR=#FBF5EF>
\r
6282 <TD width=10% BGCOLOR=#FBF5EF>
\r
6285 <TD width=10% BGCOLOR=#FBF5EF>
\r
6288 <TD width=15% BGCOLOR=#FBF5EF>
\r
6291 <TD width=35% BGCOLOR=#FBF5EF>
\r
6292 <B>This register controls this reference clock</B>
\r
6296 <TD width=15% BGCOLOR=#FBF5EF>
\r
6297 <A href="#PSU_CRL_APB_SPI0_REF_CTRL">
\r
6298 PSU_CRL_APB_SPI0_REF_CTRL
\r
6301 <TD width=15% BGCOLOR=#FBF5EF>
\r
6304 <TD width=10% BGCOLOR=#FBF5EF>
\r
6307 <TD width=10% BGCOLOR=#FBF5EF>
\r
6310 <TD width=15% BGCOLOR=#FBF5EF>
\r
6313 <TD width=35% BGCOLOR=#FBF5EF>
\r
6314 <B>This register controls this reference clock</B>
\r
6318 <TD width=15% BGCOLOR=#FBF5EF>
\r
6319 <A href="#PSU_CRL_APB_SPI1_REF_CTRL">
\r
6320 PSU_CRL_APB_SPI1_REF_CTRL
\r
6323 <TD width=15% BGCOLOR=#FBF5EF>
\r
6326 <TD width=10% BGCOLOR=#FBF5EF>
\r
6329 <TD width=10% BGCOLOR=#FBF5EF>
\r
6332 <TD width=15% BGCOLOR=#FBF5EF>
\r
6335 <TD width=35% BGCOLOR=#FBF5EF>
\r
6336 <B>This register controls this reference clock</B>
\r
6340 <TD width=15% BGCOLOR=#FBF5EF>
\r
6341 <A href="#PSU_CRL_APB_CAN0_REF_CTRL">
\r
6342 PSU_CRL_APB_CAN0_REF_CTRL
\r
6345 <TD width=15% BGCOLOR=#FBF5EF>
\r
6348 <TD width=10% BGCOLOR=#FBF5EF>
\r
6351 <TD width=10% BGCOLOR=#FBF5EF>
\r
6354 <TD width=15% BGCOLOR=#FBF5EF>
\r
6357 <TD width=35% BGCOLOR=#FBF5EF>
\r
6358 <B>This register controls this reference clock</B>
\r
6362 <TD width=15% BGCOLOR=#FBF5EF>
\r
6363 <A href="#PSU_CRL_APB_CAN1_REF_CTRL">
\r
6364 PSU_CRL_APB_CAN1_REF_CTRL
\r
6367 <TD width=15% BGCOLOR=#FBF5EF>
\r
6370 <TD width=10% BGCOLOR=#FBF5EF>
\r
6373 <TD width=10% BGCOLOR=#FBF5EF>
\r
6376 <TD width=15% BGCOLOR=#FBF5EF>
\r
6379 <TD width=35% BGCOLOR=#FBF5EF>
\r
6380 <B>This register controls this reference clock</B>
\r
6384 <TD width=15% BGCOLOR=#FBF5EF>
\r
6385 <A href="#PSU_CRL_APB_CPU_R5_CTRL">
\r
6386 PSU_CRL_APB_CPU_R5_CTRL
\r
6389 <TD width=15% BGCOLOR=#FBF5EF>
\r
6392 <TD width=10% BGCOLOR=#FBF5EF>
\r
6395 <TD width=10% BGCOLOR=#FBF5EF>
\r
6398 <TD width=15% BGCOLOR=#FBF5EF>
\r
6401 <TD width=35% BGCOLOR=#FBF5EF>
\r
6402 <B>This register controls this reference clock</B>
\r
6406 <TD width=15% BGCOLOR=#FBF5EF>
\r
6407 <A href="#PSU_CRL_APB_IOU_SWITCH_CTRL">
\r
6408 PSU_CRL_APB_IOU_SWITCH_CTRL
\r
6411 <TD width=15% BGCOLOR=#FBF5EF>
\r
6414 <TD width=10% BGCOLOR=#FBF5EF>
\r
6417 <TD width=10% BGCOLOR=#FBF5EF>
\r
6420 <TD width=15% BGCOLOR=#FBF5EF>
\r
6423 <TD width=35% BGCOLOR=#FBF5EF>
\r
6424 <B>This register controls this reference clock</B>
\r
6428 <TD width=15% BGCOLOR=#FBF5EF>
\r
6429 <A href="#PSU_CRL_APB_PCAP_CTRL">
\r
6430 PSU_CRL_APB_PCAP_CTRL
\r
6433 <TD width=15% BGCOLOR=#FBF5EF>
\r
6436 <TD width=10% BGCOLOR=#FBF5EF>
\r
6439 <TD width=10% BGCOLOR=#FBF5EF>
\r
6442 <TD width=15% BGCOLOR=#FBF5EF>
\r
6445 <TD width=35% BGCOLOR=#FBF5EF>
\r
6446 <B>This register controls this reference clock</B>
\r
6450 <TD width=15% BGCOLOR=#FBF5EF>
\r
6451 <A href="#PSU_CRL_APB_LPD_SWITCH_CTRL">
\r
6452 PSU_CRL_APB_LPD_SWITCH_CTRL
\r
6455 <TD width=15% BGCOLOR=#FBF5EF>
\r
6458 <TD width=10% BGCOLOR=#FBF5EF>
\r
6461 <TD width=10% BGCOLOR=#FBF5EF>
\r
6464 <TD width=15% BGCOLOR=#FBF5EF>
\r
6467 <TD width=35% BGCOLOR=#FBF5EF>
\r
6468 <B>This register controls this reference clock</B>
\r
6472 <TD width=15% BGCOLOR=#FBF5EF>
\r
6473 <A href="#PSU_CRL_APB_LPD_LSBUS_CTRL">
\r
6474 PSU_CRL_APB_LPD_LSBUS_CTRL
\r
6477 <TD width=15% BGCOLOR=#FBF5EF>
\r
6480 <TD width=10% BGCOLOR=#FBF5EF>
\r
6483 <TD width=10% BGCOLOR=#FBF5EF>
\r
6486 <TD width=15% BGCOLOR=#FBF5EF>
\r
6489 <TD width=35% BGCOLOR=#FBF5EF>
\r
6490 <B>This register controls this reference clock</B>
\r
6494 <TD width=15% BGCOLOR=#FBF5EF>
\r
6495 <A href="#PSU_CRL_APB_DBG_LPD_CTRL">
\r
6496 PSU_CRL_APB_DBG_LPD_CTRL
\r
6499 <TD width=15% BGCOLOR=#FBF5EF>
\r
6502 <TD width=10% BGCOLOR=#FBF5EF>
\r
6505 <TD width=10% BGCOLOR=#FBF5EF>
\r
6508 <TD width=15% BGCOLOR=#FBF5EF>
\r
6511 <TD width=35% BGCOLOR=#FBF5EF>
\r
6512 <B>This register controls this reference clock</B>
\r
6516 <TD width=15% BGCOLOR=#FBF5EF>
\r
6517 <A href="#PSU_CRL_APB_NAND_REF_CTRL">
\r
6518 PSU_CRL_APB_NAND_REF_CTRL
\r
6521 <TD width=15% BGCOLOR=#FBF5EF>
\r
6524 <TD width=10% BGCOLOR=#FBF5EF>
\r
6527 <TD width=10% BGCOLOR=#FBF5EF>
\r
6530 <TD width=15% BGCOLOR=#FBF5EF>
\r
6533 <TD width=35% BGCOLOR=#FBF5EF>
\r
6534 <B>This register controls this reference clock</B>
\r
6538 <TD width=15% BGCOLOR=#FBF5EF>
\r
6539 <A href="#PSU_CRL_APB_ADMA_REF_CTRL">
\r
6540 PSU_CRL_APB_ADMA_REF_CTRL
\r
6543 <TD width=15% BGCOLOR=#FBF5EF>
\r
6546 <TD width=10% BGCOLOR=#FBF5EF>
\r
6549 <TD width=10% BGCOLOR=#FBF5EF>
\r
6552 <TD width=15% BGCOLOR=#FBF5EF>
\r
6555 <TD width=35% BGCOLOR=#FBF5EF>
\r
6556 <B>This register controls this reference clock</B>
\r
6560 <TD width=15% BGCOLOR=#FBF5EF>
\r
6561 <A href="#PSU_CRL_APB_AMS_REF_CTRL">
\r
6562 PSU_CRL_APB_AMS_REF_CTRL
\r
6565 <TD width=15% BGCOLOR=#FBF5EF>
\r
6568 <TD width=10% BGCOLOR=#FBF5EF>
\r
6571 <TD width=10% BGCOLOR=#FBF5EF>
\r
6574 <TD width=15% BGCOLOR=#FBF5EF>
\r
6577 <TD width=35% BGCOLOR=#FBF5EF>
\r
6578 <B>This register controls this reference clock</B>
\r
6582 <TD width=15% BGCOLOR=#FBF5EF>
\r
6583 <A href="#PSU_CRL_APB_DLL_REF_CTRL">
\r
6584 PSU_CRL_APB_DLL_REF_CTRL
\r
6587 <TD width=15% BGCOLOR=#FBF5EF>
\r
6590 <TD width=10% BGCOLOR=#FBF5EF>
\r
6593 <TD width=10% BGCOLOR=#FBF5EF>
\r
6596 <TD width=15% BGCOLOR=#FBF5EF>
\r
6599 <TD width=35% BGCOLOR=#FBF5EF>
\r
6600 <B>This register controls this reference clock</B>
\r
6604 <TD width=15% BGCOLOR=#FBF5EF>
\r
6605 <A href="#PSU_CRL_APB_TIMESTAMP_REF_CTRL">
\r
6606 PSU_CRL_APB_TIMESTAMP_REF_CTRL
\r
6609 <TD width=15% BGCOLOR=#FBF5EF>
\r
6612 <TD width=10% BGCOLOR=#FBF5EF>
\r
6615 <TD width=10% BGCOLOR=#FBF5EF>
\r
6618 <TD width=15% BGCOLOR=#FBF5EF>
\r
6621 <TD width=35% BGCOLOR=#FBF5EF>
\r
6622 <B>This register controls this reference clock</B>
\r
6626 <TD width=15% BGCOLOR=#FBF5EF>
\r
6627 <A href="#PSU_CRF_APB_PCIE_REF_CTRL">
\r
6628 PSU_CRF_APB_PCIE_REF_CTRL
\r
6631 <TD width=15% BGCOLOR=#FBF5EF>
\r
6634 <TD width=10% BGCOLOR=#FBF5EF>
\r
6637 <TD width=10% BGCOLOR=#FBF5EF>
\r
6640 <TD width=15% BGCOLOR=#FBF5EF>
\r
6643 <TD width=35% BGCOLOR=#FBF5EF>
\r
6644 <B>This register controls this reference clock</B>
\r
6648 <TD width=15% BGCOLOR=#FBF5EF>
\r
6649 <A href="#PSU_CRF_APB_DP_VIDEO_REF_CTRL">
\r
6650 PSU_CRF_APB_DP_VIDEO_REF_CTRL
\r
6653 <TD width=15% BGCOLOR=#FBF5EF>
\r
6656 <TD width=10% BGCOLOR=#FBF5EF>
\r
6659 <TD width=10% BGCOLOR=#FBF5EF>
\r
6662 <TD width=15% BGCOLOR=#FBF5EF>
\r
6665 <TD width=35% BGCOLOR=#FBF5EF>
\r
6666 <B>This register controls this reference clock</B>
\r
6670 <TD width=15% BGCOLOR=#FBF5EF>
\r
6671 <A href="#PSU_CRF_APB_DP_AUDIO_REF_CTRL">
\r
6672 PSU_CRF_APB_DP_AUDIO_REF_CTRL
\r
6675 <TD width=15% BGCOLOR=#FBF5EF>
\r
6678 <TD width=10% BGCOLOR=#FBF5EF>
\r
6681 <TD width=10% BGCOLOR=#FBF5EF>
\r
6684 <TD width=15% BGCOLOR=#FBF5EF>
\r
6687 <TD width=35% BGCOLOR=#FBF5EF>
\r
6688 <B>This register controls this reference clock</B>
\r
6692 <TD width=15% BGCOLOR=#FBF5EF>
\r
6693 <A href="#PSU_CRF_APB_DP_STC_REF_CTRL">
\r
6694 PSU_CRF_APB_DP_STC_REF_CTRL
\r
6697 <TD width=15% BGCOLOR=#FBF5EF>
\r
6700 <TD width=10% BGCOLOR=#FBF5EF>
\r
6703 <TD width=10% BGCOLOR=#FBF5EF>
\r
6706 <TD width=15% BGCOLOR=#FBF5EF>
\r
6709 <TD width=35% BGCOLOR=#FBF5EF>
\r
6710 <B>This register controls this reference clock</B>
\r
6714 <TD width=15% BGCOLOR=#FBF5EF>
\r
6715 <A href="#PSU_CRF_APB_ACPU_CTRL">
\r
6716 PSU_CRF_APB_ACPU_CTRL
\r
6719 <TD width=15% BGCOLOR=#FBF5EF>
\r
6722 <TD width=10% BGCOLOR=#FBF5EF>
\r
6725 <TD width=10% BGCOLOR=#FBF5EF>
\r
6728 <TD width=15% BGCOLOR=#FBF5EF>
\r
6731 <TD width=35% BGCOLOR=#FBF5EF>
\r
6732 <B>This register controls this reference clock</B>
\r
6736 <TD width=15% BGCOLOR=#FBF5EF>
\r
6737 <A href="#PSU_CRF_APB_DBG_TRACE_CTRL">
\r
6738 PSU_CRF_APB_DBG_TRACE_CTRL
\r
6741 <TD width=15% BGCOLOR=#FBF5EF>
\r
6744 <TD width=10% BGCOLOR=#FBF5EF>
\r
6747 <TD width=10% BGCOLOR=#FBF5EF>
\r
6750 <TD width=15% BGCOLOR=#FBF5EF>
\r
6753 <TD width=35% BGCOLOR=#FBF5EF>
\r
6754 <B>This register controls this reference clock</B>
\r
6758 <TD width=15% BGCOLOR=#FBF5EF>
\r
6759 <A href="#PSU_CRF_APB_DBG_FPD_CTRL">
\r
6760 PSU_CRF_APB_DBG_FPD_CTRL
\r
6763 <TD width=15% BGCOLOR=#FBF5EF>
\r
6766 <TD width=10% BGCOLOR=#FBF5EF>
\r
6769 <TD width=10% BGCOLOR=#FBF5EF>
\r
6772 <TD width=15% BGCOLOR=#FBF5EF>
\r
6775 <TD width=35% BGCOLOR=#FBF5EF>
\r
6776 <B>This register controls this reference clock</B>
\r
6780 <TD width=15% BGCOLOR=#FBF5EF>
\r
6781 <A href="#PSU_CRF_APB_DDR_CTRL">
\r
6782 PSU_CRF_APB_DDR_CTRL
\r
6785 <TD width=15% BGCOLOR=#FBF5EF>
\r
6788 <TD width=10% BGCOLOR=#FBF5EF>
\r
6791 <TD width=10% BGCOLOR=#FBF5EF>
\r
6794 <TD width=15% BGCOLOR=#FBF5EF>
\r
6797 <TD width=35% BGCOLOR=#FBF5EF>
\r
6798 <B>This register controls this reference clock</B>
\r
6802 <TD width=15% BGCOLOR=#FBF5EF>
\r
6803 <A href="#PSU_CRF_APB_GPU_REF_CTRL">
\r
6804 PSU_CRF_APB_GPU_REF_CTRL
\r
6807 <TD width=15% BGCOLOR=#FBF5EF>
\r
6810 <TD width=10% BGCOLOR=#FBF5EF>
\r
6813 <TD width=10% BGCOLOR=#FBF5EF>
\r
6816 <TD width=15% BGCOLOR=#FBF5EF>
\r
6819 <TD width=35% BGCOLOR=#FBF5EF>
\r
6820 <B>This register controls this reference clock</B>
\r
6824 <TD width=15% BGCOLOR=#FBF5EF>
\r
6825 <A href="#PSU_CRF_APB_GDMA_REF_CTRL">
\r
6826 PSU_CRF_APB_GDMA_REF_CTRL
\r
6829 <TD width=15% BGCOLOR=#FBF5EF>
\r
6832 <TD width=10% BGCOLOR=#FBF5EF>
\r
6835 <TD width=10% BGCOLOR=#FBF5EF>
\r
6838 <TD width=15% BGCOLOR=#FBF5EF>
\r
6841 <TD width=35% BGCOLOR=#FBF5EF>
\r
6842 <B>This register controls this reference clock</B>
\r
6846 <TD width=15% BGCOLOR=#FBF5EF>
\r
6847 <A href="#PSU_CRF_APB_DPDMA_REF_CTRL">
\r
6848 PSU_CRF_APB_DPDMA_REF_CTRL
\r
6851 <TD width=15% BGCOLOR=#FBF5EF>
\r
6854 <TD width=10% BGCOLOR=#FBF5EF>
\r
6857 <TD width=10% BGCOLOR=#FBF5EF>
\r
6860 <TD width=15% BGCOLOR=#FBF5EF>
\r
6863 <TD width=35% BGCOLOR=#FBF5EF>
\r
6864 <B>This register controls this reference clock</B>
\r
6868 <TD width=15% BGCOLOR=#FBF5EF>
\r
6869 <A href="#PSU_CRF_APB_TOPSW_MAIN_CTRL">
\r
6870 PSU_CRF_APB_TOPSW_MAIN_CTRL
\r
6873 <TD width=15% BGCOLOR=#FBF5EF>
\r
6876 <TD width=10% BGCOLOR=#FBF5EF>
\r
6879 <TD width=10% BGCOLOR=#FBF5EF>
\r
6882 <TD width=15% BGCOLOR=#FBF5EF>
\r
6885 <TD width=35% BGCOLOR=#FBF5EF>
\r
6886 <B>This register controls this reference clock</B>
\r
6890 <TD width=15% BGCOLOR=#FBF5EF>
\r
6891 <A href="#PSU_CRF_APB_TOPSW_LSBUS_CTRL">
\r
6892 PSU_CRF_APB_TOPSW_LSBUS_CTRL
\r
6895 <TD width=15% BGCOLOR=#FBF5EF>
\r
6898 <TD width=10% BGCOLOR=#FBF5EF>
\r
6901 <TD width=10% BGCOLOR=#FBF5EF>
\r
6904 <TD width=15% BGCOLOR=#FBF5EF>
\r
6907 <TD width=35% BGCOLOR=#FBF5EF>
\r
6908 <B>This register controls this reference clock</B>
\r
6912 <TD width=15% BGCOLOR=#FBF5EF>
\r
6913 <A href="#PSU_CRF_APB_GTGREF0_REF_CTRL">
\r
6914 PSU_CRF_APB_GTGREF0_REF_CTRL
\r
6917 <TD width=15% BGCOLOR=#FBF5EF>
\r
6920 <TD width=10% BGCOLOR=#FBF5EF>
\r
6923 <TD width=10% BGCOLOR=#FBF5EF>
\r
6926 <TD width=15% BGCOLOR=#FBF5EF>
\r
6929 <TD width=35% BGCOLOR=#FBF5EF>
\r
6930 <B>This register controls this reference clock</B>
\r
6934 <TD width=15% BGCOLOR=#FBF5EF>
\r
6935 <A href="#PSU_CRF_APB_DBG_TSTMP_CTRL">
\r
6936 PSU_CRF_APB_DBG_TSTMP_CTRL
\r
6939 <TD width=15% BGCOLOR=#FBF5EF>
\r
6942 <TD width=10% BGCOLOR=#FBF5EF>
\r
6945 <TD width=10% BGCOLOR=#FBF5EF>
\r
6948 <TD width=15% BGCOLOR=#FBF5EF>
\r
6951 <TD width=35% BGCOLOR=#FBF5EF>
\r
6952 <B>This register controls this reference clock</B>
\r
6957 <H2><a name="psu_clock_init_data">psu_clock_init_data</a></H2>
\r
6958 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
6960 <TD width=15% BGCOLOR=#FFC0FF>
\r
6961 <B>Register Name</B>
\r
6963 <TD width=15% BGCOLOR=#FFC0FF>
\r
6966 <TD width=10% BGCOLOR=#FFC0FF>
\r
6969 <TD width=10% BGCOLOR=#FFC0FF>
\r
6972 <TD width=15% BGCOLOR=#FFC0FF>
\r
6973 <B>Reset Value</B>
\r
6975 <TD width=35% BGCOLOR=#FFC0FF>
\r
6976 <B>Description</B>
\r
6979 <H1>CLOCK CONTROL SLCR REGISTER</H1>
\r
6980 <H2><a name="GEM0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_REF_CTRL</a></H2>
\r
6981 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
6983 <TD width=15% BGCOLOR=#FFFF00>
\r
6984 <B>Register Name</B>
\r
6986 <TD width=15% BGCOLOR=#FFFF00>
\r
6989 <TD width=10% BGCOLOR=#FFFF00>
\r
6992 <TD width=10% BGCOLOR=#FFFF00>
\r
6995 <TD width=15% BGCOLOR=#FFFF00>
\r
6996 <B>Reset Value</B>
\r
6998 <TD width=35% BGCOLOR=#FFFF00>
\r
6999 <B>Description</B>
\r
7003 <TD width=15% BGCOLOR=#FBF5EF>
\r
7004 <B>GEM0_REF_CTRL</B>
\r
7006 <TD width=15% BGCOLOR=#FBF5EF>
\r
7009 <TD width=10% BGCOLOR=#FBF5EF>
\r
7012 <TD width=10% BGCOLOR=#FBF5EF>
\r
7015 <TD width=15% BGCOLOR=#FBF5EF>
\r
7018 <TD width=35% BGCOLOR=#FBF5EF>
\r
7024 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7026 <TD width=15% BGCOLOR=#C0FFC0>
\r
7029 <TD width=15% BGCOLOR=#C0FFC0>
\r
7032 <TD width=10% BGCOLOR=#C0FFC0>
\r
7035 <TD width=10% BGCOLOR=#C0FFC0>
\r
7038 <TD width=15% BGCOLOR=#C0FFC0>
\r
7039 <B>Shifted Value</B>
\r
7041 <TD width=35% BGCOLOR=#C0FFC0>
\r
7042 <B>Description</B>
\r
7046 <TD width=15% BGCOLOR=#FBF5EF>
\r
7047 <B>PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT</B>
\r
7049 <TD width=15% BGCOLOR=#FBF5EF>
\r
7052 <TD width=10% BGCOLOR=#FBF5EF>
\r
7055 <TD width=10% BGCOLOR=#FBF5EF>
\r
7058 <TD width=15% BGCOLOR=#FBF5EF>
\r
7061 <TD width=35% BGCOLOR=#FBF5EF>
\r
7062 <B>Clock active for the RX channel</B>
\r
7066 <TD width=15% BGCOLOR=#FBF5EF>
\r
7067 <B>PSU_CRL_APB_GEM0_REF_CTRL_CLKACT</B>
\r
7069 <TD width=15% BGCOLOR=#FBF5EF>
\r
7072 <TD width=10% BGCOLOR=#FBF5EF>
\r
7075 <TD width=10% BGCOLOR=#FBF5EF>
\r
7078 <TD width=15% BGCOLOR=#FBF5EF>
\r
7081 <TD width=35% BGCOLOR=#FBF5EF>
\r
7082 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7086 <TD width=15% BGCOLOR=#FBF5EF>
\r
7087 <B>PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1</B>
\r
7089 <TD width=15% BGCOLOR=#FBF5EF>
\r
7092 <TD width=10% BGCOLOR=#FBF5EF>
\r
7095 <TD width=10% BGCOLOR=#FBF5EF>
\r
7098 <TD width=15% BGCOLOR=#FBF5EF>
\r
7101 <TD width=35% BGCOLOR=#FBF5EF>
\r
7102 <B>6 bit divider</B>
\r
7106 <TD width=15% BGCOLOR=#FBF5EF>
\r
7107 <B>PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0</B>
\r
7109 <TD width=15% BGCOLOR=#FBF5EF>
\r
7112 <TD width=10% BGCOLOR=#FBF5EF>
\r
7115 <TD width=10% BGCOLOR=#FBF5EF>
\r
7118 <TD width=15% BGCOLOR=#FBF5EF>
\r
7121 <TD width=35% BGCOLOR=#FBF5EF>
\r
7122 <B>6 bit divider</B>
\r
7126 <TD width=15% BGCOLOR=#FBF5EF>
\r
7127 <B>PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL</B>
\r
7129 <TD width=15% BGCOLOR=#FBF5EF>
\r
7132 <TD width=10% BGCOLOR=#FBF5EF>
\r
7135 <TD width=10% BGCOLOR=#FBF5EF>
\r
7138 <TD width=15% BGCOLOR=#FBF5EF>
\r
7141 <TD width=35% BGCOLOR=#FBF5EF>
\r
7142 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
7146 <TD width=15% BGCOLOR=#C0C0C0>
\r
7147 <B>PSU_CRL_APB_GEM0_REF_CTRL@0XFF5E0050</B>
\r
7149 <TD width=15% BGCOLOR=#C0C0C0>
\r
7152 <TD width=10% BGCOLOR=#C0C0C0>
\r
7155 <TD width=10% BGCOLOR=#C0C0C0>
\r
7158 <TD width=15% BGCOLOR=#C0C0C0>
\r
7161 <TD width=35% BGCOLOR=#C0C0C0>
\r
7162 <B>This register controls this reference clock</B>
\r
7167 <H2><a name="GEM1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM1_REF_CTRL</a></H2>
\r
7168 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7170 <TD width=15% BGCOLOR=#FFFF00>
\r
7171 <B>Register Name</B>
\r
7173 <TD width=15% BGCOLOR=#FFFF00>
\r
7176 <TD width=10% BGCOLOR=#FFFF00>
\r
7179 <TD width=10% BGCOLOR=#FFFF00>
\r
7182 <TD width=15% BGCOLOR=#FFFF00>
\r
7183 <B>Reset Value</B>
\r
7185 <TD width=35% BGCOLOR=#FFFF00>
\r
7186 <B>Description</B>
\r
7190 <TD width=15% BGCOLOR=#FBF5EF>
\r
7191 <B>GEM1_REF_CTRL</B>
\r
7193 <TD width=15% BGCOLOR=#FBF5EF>
\r
7196 <TD width=10% BGCOLOR=#FBF5EF>
\r
7199 <TD width=10% BGCOLOR=#FBF5EF>
\r
7202 <TD width=15% BGCOLOR=#FBF5EF>
\r
7205 <TD width=35% BGCOLOR=#FBF5EF>
\r
7211 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7213 <TD width=15% BGCOLOR=#C0FFC0>
\r
7216 <TD width=15% BGCOLOR=#C0FFC0>
\r
7219 <TD width=10% BGCOLOR=#C0FFC0>
\r
7222 <TD width=10% BGCOLOR=#C0FFC0>
\r
7225 <TD width=15% BGCOLOR=#C0FFC0>
\r
7226 <B>Shifted Value</B>
\r
7228 <TD width=35% BGCOLOR=#C0FFC0>
\r
7229 <B>Description</B>
\r
7233 <TD width=15% BGCOLOR=#FBF5EF>
\r
7234 <B>PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT</B>
\r
7236 <TD width=15% BGCOLOR=#FBF5EF>
\r
7239 <TD width=10% BGCOLOR=#FBF5EF>
\r
7242 <TD width=10% BGCOLOR=#FBF5EF>
\r
7245 <TD width=15% BGCOLOR=#FBF5EF>
\r
7248 <TD width=35% BGCOLOR=#FBF5EF>
\r
7249 <B>Clock active for the RX channel</B>
\r
7253 <TD width=15% BGCOLOR=#FBF5EF>
\r
7254 <B>PSU_CRL_APB_GEM1_REF_CTRL_CLKACT</B>
\r
7256 <TD width=15% BGCOLOR=#FBF5EF>
\r
7259 <TD width=10% BGCOLOR=#FBF5EF>
\r
7262 <TD width=10% BGCOLOR=#FBF5EF>
\r
7265 <TD width=15% BGCOLOR=#FBF5EF>
\r
7268 <TD width=35% BGCOLOR=#FBF5EF>
\r
7269 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7273 <TD width=15% BGCOLOR=#FBF5EF>
\r
7274 <B>PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1</B>
\r
7276 <TD width=15% BGCOLOR=#FBF5EF>
\r
7279 <TD width=10% BGCOLOR=#FBF5EF>
\r
7282 <TD width=10% BGCOLOR=#FBF5EF>
\r
7285 <TD width=15% BGCOLOR=#FBF5EF>
\r
7288 <TD width=35% BGCOLOR=#FBF5EF>
\r
7289 <B>6 bit divider</B>
\r
7293 <TD width=15% BGCOLOR=#FBF5EF>
\r
7294 <B>PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0</B>
\r
7296 <TD width=15% BGCOLOR=#FBF5EF>
\r
7299 <TD width=10% BGCOLOR=#FBF5EF>
\r
7302 <TD width=10% BGCOLOR=#FBF5EF>
\r
7305 <TD width=15% BGCOLOR=#FBF5EF>
\r
7308 <TD width=35% BGCOLOR=#FBF5EF>
\r
7309 <B>6 bit divider</B>
\r
7313 <TD width=15% BGCOLOR=#FBF5EF>
\r
7314 <B>PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL</B>
\r
7316 <TD width=15% BGCOLOR=#FBF5EF>
\r
7319 <TD width=10% BGCOLOR=#FBF5EF>
\r
7322 <TD width=10% BGCOLOR=#FBF5EF>
\r
7325 <TD width=15% BGCOLOR=#FBF5EF>
\r
7328 <TD width=35% BGCOLOR=#FBF5EF>
\r
7329 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
7333 <TD width=15% BGCOLOR=#C0C0C0>
\r
7334 <B>PSU_CRL_APB_GEM1_REF_CTRL@0XFF5E0054</B>
\r
7336 <TD width=15% BGCOLOR=#C0C0C0>
\r
7339 <TD width=10% BGCOLOR=#C0C0C0>
\r
7342 <TD width=10% BGCOLOR=#C0C0C0>
\r
7345 <TD width=15% BGCOLOR=#C0C0C0>
\r
7348 <TD width=35% BGCOLOR=#C0C0C0>
\r
7349 <B>This register controls this reference clock</B>
\r
7354 <H2><a name="GEM2_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM2_REF_CTRL</a></H2>
\r
7355 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7357 <TD width=15% BGCOLOR=#FFFF00>
\r
7358 <B>Register Name</B>
\r
7360 <TD width=15% BGCOLOR=#FFFF00>
\r
7363 <TD width=10% BGCOLOR=#FFFF00>
\r
7366 <TD width=10% BGCOLOR=#FFFF00>
\r
7369 <TD width=15% BGCOLOR=#FFFF00>
\r
7370 <B>Reset Value</B>
\r
7372 <TD width=35% BGCOLOR=#FFFF00>
\r
7373 <B>Description</B>
\r
7377 <TD width=15% BGCOLOR=#FBF5EF>
\r
7378 <B>GEM2_REF_CTRL</B>
\r
7380 <TD width=15% BGCOLOR=#FBF5EF>
\r
7383 <TD width=10% BGCOLOR=#FBF5EF>
\r
7386 <TD width=10% BGCOLOR=#FBF5EF>
\r
7389 <TD width=15% BGCOLOR=#FBF5EF>
\r
7392 <TD width=35% BGCOLOR=#FBF5EF>
\r
7398 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7400 <TD width=15% BGCOLOR=#C0FFC0>
\r
7403 <TD width=15% BGCOLOR=#C0FFC0>
\r
7406 <TD width=10% BGCOLOR=#C0FFC0>
\r
7409 <TD width=10% BGCOLOR=#C0FFC0>
\r
7412 <TD width=15% BGCOLOR=#C0FFC0>
\r
7413 <B>Shifted Value</B>
\r
7415 <TD width=35% BGCOLOR=#C0FFC0>
\r
7416 <B>Description</B>
\r
7420 <TD width=15% BGCOLOR=#FBF5EF>
\r
7421 <B>PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT</B>
\r
7423 <TD width=15% BGCOLOR=#FBF5EF>
\r
7426 <TD width=10% BGCOLOR=#FBF5EF>
\r
7429 <TD width=10% BGCOLOR=#FBF5EF>
\r
7432 <TD width=15% BGCOLOR=#FBF5EF>
\r
7435 <TD width=35% BGCOLOR=#FBF5EF>
\r
7436 <B>Clock active for the RX channel</B>
\r
7440 <TD width=15% BGCOLOR=#FBF5EF>
\r
7441 <B>PSU_CRL_APB_GEM2_REF_CTRL_CLKACT</B>
\r
7443 <TD width=15% BGCOLOR=#FBF5EF>
\r
7446 <TD width=10% BGCOLOR=#FBF5EF>
\r
7449 <TD width=10% BGCOLOR=#FBF5EF>
\r
7452 <TD width=15% BGCOLOR=#FBF5EF>
\r
7455 <TD width=35% BGCOLOR=#FBF5EF>
\r
7456 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7460 <TD width=15% BGCOLOR=#FBF5EF>
\r
7461 <B>PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1</B>
\r
7463 <TD width=15% BGCOLOR=#FBF5EF>
\r
7466 <TD width=10% BGCOLOR=#FBF5EF>
\r
7469 <TD width=10% BGCOLOR=#FBF5EF>
\r
7472 <TD width=15% BGCOLOR=#FBF5EF>
\r
7475 <TD width=35% BGCOLOR=#FBF5EF>
\r
7476 <B>6 bit divider</B>
\r
7480 <TD width=15% BGCOLOR=#FBF5EF>
\r
7481 <B>PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0</B>
\r
7483 <TD width=15% BGCOLOR=#FBF5EF>
\r
7486 <TD width=10% BGCOLOR=#FBF5EF>
\r
7489 <TD width=10% BGCOLOR=#FBF5EF>
\r
7492 <TD width=15% BGCOLOR=#FBF5EF>
\r
7495 <TD width=35% BGCOLOR=#FBF5EF>
\r
7496 <B>6 bit divider</B>
\r
7500 <TD width=15% BGCOLOR=#FBF5EF>
\r
7501 <B>PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL</B>
\r
7503 <TD width=15% BGCOLOR=#FBF5EF>
\r
7506 <TD width=10% BGCOLOR=#FBF5EF>
\r
7509 <TD width=10% BGCOLOR=#FBF5EF>
\r
7512 <TD width=15% BGCOLOR=#FBF5EF>
\r
7515 <TD width=35% BGCOLOR=#FBF5EF>
\r
7516 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
7520 <TD width=15% BGCOLOR=#C0C0C0>
\r
7521 <B>PSU_CRL_APB_GEM2_REF_CTRL@0XFF5E0058</B>
\r
7523 <TD width=15% BGCOLOR=#C0C0C0>
\r
7526 <TD width=10% BGCOLOR=#C0C0C0>
\r
7529 <TD width=10% BGCOLOR=#C0C0C0>
\r
7532 <TD width=15% BGCOLOR=#C0C0C0>
\r
7535 <TD width=35% BGCOLOR=#C0C0C0>
\r
7536 <B>This register controls this reference clock</B>
\r
7541 <H2><a name="GEM3_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM3_REF_CTRL</a></H2>
\r
7542 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7544 <TD width=15% BGCOLOR=#FFFF00>
\r
7545 <B>Register Name</B>
\r
7547 <TD width=15% BGCOLOR=#FFFF00>
\r
7550 <TD width=10% BGCOLOR=#FFFF00>
\r
7553 <TD width=10% BGCOLOR=#FFFF00>
\r
7556 <TD width=15% BGCOLOR=#FFFF00>
\r
7557 <B>Reset Value</B>
\r
7559 <TD width=35% BGCOLOR=#FFFF00>
\r
7560 <B>Description</B>
\r
7564 <TD width=15% BGCOLOR=#FBF5EF>
\r
7565 <B>GEM3_REF_CTRL</B>
\r
7567 <TD width=15% BGCOLOR=#FBF5EF>
\r
7570 <TD width=10% BGCOLOR=#FBF5EF>
\r
7573 <TD width=10% BGCOLOR=#FBF5EF>
\r
7576 <TD width=15% BGCOLOR=#FBF5EF>
\r
7579 <TD width=35% BGCOLOR=#FBF5EF>
\r
7585 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7587 <TD width=15% BGCOLOR=#C0FFC0>
\r
7590 <TD width=15% BGCOLOR=#C0FFC0>
\r
7593 <TD width=10% BGCOLOR=#C0FFC0>
\r
7596 <TD width=10% BGCOLOR=#C0FFC0>
\r
7599 <TD width=15% BGCOLOR=#C0FFC0>
\r
7600 <B>Shifted Value</B>
\r
7602 <TD width=35% BGCOLOR=#C0FFC0>
\r
7603 <B>Description</B>
\r
7607 <TD width=15% BGCOLOR=#FBF5EF>
\r
7608 <B>PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT</B>
\r
7610 <TD width=15% BGCOLOR=#FBF5EF>
\r
7613 <TD width=10% BGCOLOR=#FBF5EF>
\r
7616 <TD width=10% BGCOLOR=#FBF5EF>
\r
7619 <TD width=15% BGCOLOR=#FBF5EF>
\r
7622 <TD width=35% BGCOLOR=#FBF5EF>
\r
7623 <B>Clock active for the RX channel</B>
\r
7627 <TD width=15% BGCOLOR=#FBF5EF>
\r
7628 <B>PSU_CRL_APB_GEM3_REF_CTRL_CLKACT</B>
\r
7630 <TD width=15% BGCOLOR=#FBF5EF>
\r
7633 <TD width=10% BGCOLOR=#FBF5EF>
\r
7636 <TD width=10% BGCOLOR=#FBF5EF>
\r
7639 <TD width=15% BGCOLOR=#FBF5EF>
\r
7642 <TD width=35% BGCOLOR=#FBF5EF>
\r
7643 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7647 <TD width=15% BGCOLOR=#FBF5EF>
\r
7648 <B>PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1</B>
\r
7650 <TD width=15% BGCOLOR=#FBF5EF>
\r
7653 <TD width=10% BGCOLOR=#FBF5EF>
\r
7656 <TD width=10% BGCOLOR=#FBF5EF>
\r
7659 <TD width=15% BGCOLOR=#FBF5EF>
\r
7662 <TD width=35% BGCOLOR=#FBF5EF>
\r
7663 <B>6 bit divider</B>
\r
7667 <TD width=15% BGCOLOR=#FBF5EF>
\r
7668 <B>PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0</B>
\r
7670 <TD width=15% BGCOLOR=#FBF5EF>
\r
7673 <TD width=10% BGCOLOR=#FBF5EF>
\r
7676 <TD width=10% BGCOLOR=#FBF5EF>
\r
7679 <TD width=15% BGCOLOR=#FBF5EF>
\r
7682 <TD width=35% BGCOLOR=#FBF5EF>
\r
7683 <B>6 bit divider</B>
\r
7687 <TD width=15% BGCOLOR=#FBF5EF>
\r
7688 <B>PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL</B>
\r
7690 <TD width=15% BGCOLOR=#FBF5EF>
\r
7693 <TD width=10% BGCOLOR=#FBF5EF>
\r
7696 <TD width=10% BGCOLOR=#FBF5EF>
\r
7699 <TD width=15% BGCOLOR=#FBF5EF>
\r
7702 <TD width=35% BGCOLOR=#FBF5EF>
\r
7703 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
7707 <TD width=15% BGCOLOR=#C0C0C0>
\r
7708 <B>PSU_CRL_APB_GEM3_REF_CTRL@0XFF5E005C</B>
\r
7710 <TD width=15% BGCOLOR=#C0C0C0>
\r
7713 <TD width=10% BGCOLOR=#C0C0C0>
\r
7716 <TD width=10% BGCOLOR=#C0C0C0>
\r
7719 <TD width=15% BGCOLOR=#C0C0C0>
\r
7722 <TD width=35% BGCOLOR=#C0C0C0>
\r
7723 <B>This register controls this reference clock</B>
\r
7728 <H2><a name="USB0_BUS_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)USB0_BUS_REF_CTRL</a></H2>
\r
7729 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7731 <TD width=15% BGCOLOR=#FFFF00>
\r
7732 <B>Register Name</B>
\r
7734 <TD width=15% BGCOLOR=#FFFF00>
\r
7737 <TD width=10% BGCOLOR=#FFFF00>
\r
7740 <TD width=10% BGCOLOR=#FFFF00>
\r
7743 <TD width=15% BGCOLOR=#FFFF00>
\r
7744 <B>Reset Value</B>
\r
7746 <TD width=35% BGCOLOR=#FFFF00>
\r
7747 <B>Description</B>
\r
7751 <TD width=15% BGCOLOR=#FBF5EF>
\r
7752 <B>USB0_BUS_REF_CTRL</B>
\r
7754 <TD width=15% BGCOLOR=#FBF5EF>
\r
7757 <TD width=10% BGCOLOR=#FBF5EF>
\r
7760 <TD width=10% BGCOLOR=#FBF5EF>
\r
7763 <TD width=15% BGCOLOR=#FBF5EF>
\r
7766 <TD width=35% BGCOLOR=#FBF5EF>
\r
7772 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7774 <TD width=15% BGCOLOR=#C0FFC0>
\r
7777 <TD width=15% BGCOLOR=#C0FFC0>
\r
7780 <TD width=10% BGCOLOR=#C0FFC0>
\r
7783 <TD width=10% BGCOLOR=#C0FFC0>
\r
7786 <TD width=15% BGCOLOR=#C0FFC0>
\r
7787 <B>Shifted Value</B>
\r
7789 <TD width=35% BGCOLOR=#C0FFC0>
\r
7790 <B>Description</B>
\r
7794 <TD width=15% BGCOLOR=#FBF5EF>
\r
7795 <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT</B>
\r
7797 <TD width=15% BGCOLOR=#FBF5EF>
\r
7800 <TD width=10% BGCOLOR=#FBF5EF>
\r
7803 <TD width=10% BGCOLOR=#FBF5EF>
\r
7806 <TD width=15% BGCOLOR=#FBF5EF>
\r
7809 <TD width=35% BGCOLOR=#FBF5EF>
\r
7810 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7814 <TD width=15% BGCOLOR=#FBF5EF>
\r
7815 <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1</B>
\r
7817 <TD width=15% BGCOLOR=#FBF5EF>
\r
7820 <TD width=10% BGCOLOR=#FBF5EF>
\r
7823 <TD width=10% BGCOLOR=#FBF5EF>
\r
7826 <TD width=15% BGCOLOR=#FBF5EF>
\r
7829 <TD width=35% BGCOLOR=#FBF5EF>
\r
7830 <B>6 bit divider</B>
\r
7834 <TD width=15% BGCOLOR=#FBF5EF>
\r
7835 <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0</B>
\r
7837 <TD width=15% BGCOLOR=#FBF5EF>
\r
7840 <TD width=10% BGCOLOR=#FBF5EF>
\r
7843 <TD width=10% BGCOLOR=#FBF5EF>
\r
7846 <TD width=15% BGCOLOR=#FBF5EF>
\r
7849 <TD width=35% BGCOLOR=#FBF5EF>
\r
7850 <B>6 bit divider</B>
\r
7854 <TD width=15% BGCOLOR=#FBF5EF>
\r
7855 <B>PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL</B>
\r
7857 <TD width=15% BGCOLOR=#FBF5EF>
\r
7860 <TD width=10% BGCOLOR=#FBF5EF>
\r
7863 <TD width=10% BGCOLOR=#FBF5EF>
\r
7866 <TD width=15% BGCOLOR=#FBF5EF>
\r
7869 <TD width=35% BGCOLOR=#FBF5EF>
\r
7870 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
7874 <TD width=15% BGCOLOR=#C0C0C0>
\r
7875 <B>PSU_CRL_APB_USB0_BUS_REF_CTRL@0XFF5E0060</B>
\r
7877 <TD width=15% BGCOLOR=#C0C0C0>
\r
7880 <TD width=10% BGCOLOR=#C0C0C0>
\r
7883 <TD width=10% BGCOLOR=#C0C0C0>
\r
7886 <TD width=15% BGCOLOR=#C0C0C0>
\r
7889 <TD width=35% BGCOLOR=#C0C0C0>
\r
7890 <B>This register controls this reference clock</B>
\r
7895 <H2><a name="USB3_DUAL_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)USB3_DUAL_REF_CTRL</a></H2>
\r
7896 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7898 <TD width=15% BGCOLOR=#FFFF00>
\r
7899 <B>Register Name</B>
\r
7901 <TD width=15% BGCOLOR=#FFFF00>
\r
7904 <TD width=10% BGCOLOR=#FFFF00>
\r
7907 <TD width=10% BGCOLOR=#FFFF00>
\r
7910 <TD width=15% BGCOLOR=#FFFF00>
\r
7911 <B>Reset Value</B>
\r
7913 <TD width=35% BGCOLOR=#FFFF00>
\r
7914 <B>Description</B>
\r
7918 <TD width=15% BGCOLOR=#FBF5EF>
\r
7919 <B>USB3_DUAL_REF_CTRL</B>
\r
7921 <TD width=15% BGCOLOR=#FBF5EF>
\r
7924 <TD width=10% BGCOLOR=#FBF5EF>
\r
7927 <TD width=10% BGCOLOR=#FBF5EF>
\r
7930 <TD width=15% BGCOLOR=#FBF5EF>
\r
7933 <TD width=35% BGCOLOR=#FBF5EF>
\r
7939 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
7941 <TD width=15% BGCOLOR=#C0FFC0>
\r
7944 <TD width=15% BGCOLOR=#C0FFC0>
\r
7947 <TD width=10% BGCOLOR=#C0FFC0>
\r
7950 <TD width=10% BGCOLOR=#C0FFC0>
\r
7953 <TD width=15% BGCOLOR=#C0FFC0>
\r
7954 <B>Shifted Value</B>
\r
7956 <TD width=35% BGCOLOR=#C0FFC0>
\r
7957 <B>Description</B>
\r
7961 <TD width=15% BGCOLOR=#FBF5EF>
\r
7962 <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT</B>
\r
7964 <TD width=15% BGCOLOR=#FBF5EF>
\r
7967 <TD width=10% BGCOLOR=#FBF5EF>
\r
7970 <TD width=10% BGCOLOR=#FBF5EF>
\r
7973 <TD width=15% BGCOLOR=#FBF5EF>
\r
7976 <TD width=35% BGCOLOR=#FBF5EF>
\r
7977 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
7981 <TD width=15% BGCOLOR=#FBF5EF>
\r
7982 <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1</B>
\r
7984 <TD width=15% BGCOLOR=#FBF5EF>
\r
7987 <TD width=10% BGCOLOR=#FBF5EF>
\r
7990 <TD width=10% BGCOLOR=#FBF5EF>
\r
7993 <TD width=15% BGCOLOR=#FBF5EF>
\r
7996 <TD width=35% BGCOLOR=#FBF5EF>
\r
7997 <B>6 bit divider</B>
\r
8001 <TD width=15% BGCOLOR=#FBF5EF>
\r
8002 <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0</B>
\r
8004 <TD width=15% BGCOLOR=#FBF5EF>
\r
8007 <TD width=10% BGCOLOR=#FBF5EF>
\r
8010 <TD width=10% BGCOLOR=#FBF5EF>
\r
8013 <TD width=15% BGCOLOR=#FBF5EF>
\r
8016 <TD width=35% BGCOLOR=#FBF5EF>
\r
8017 <B>6 bit divider</B>
\r
8021 <TD width=15% BGCOLOR=#FBF5EF>
\r
8022 <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL</B>
\r
8024 <TD width=15% BGCOLOR=#FBF5EF>
\r
8027 <TD width=10% BGCOLOR=#FBF5EF>
\r
8030 <TD width=10% BGCOLOR=#FBF5EF>
\r
8033 <TD width=15% BGCOLOR=#FBF5EF>
\r
8036 <TD width=35% BGCOLOR=#FBF5EF>
\r
8037 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8041 <TD width=15% BGCOLOR=#C0C0C0>
\r
8042 <B>PSU_CRL_APB_USB3_DUAL_REF_CTRL@0XFF5E004C</B>
\r
8044 <TD width=15% BGCOLOR=#C0C0C0>
\r
8047 <TD width=10% BGCOLOR=#C0C0C0>
\r
8050 <TD width=10% BGCOLOR=#C0C0C0>
\r
8053 <TD width=15% BGCOLOR=#C0C0C0>
\r
8056 <TD width=35% BGCOLOR=#C0C0C0>
\r
8057 <B>This register controls this reference clock</B>
\r
8062 <H2><a name="QSPI_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)QSPI_REF_CTRL</a></H2>
\r
8063 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8065 <TD width=15% BGCOLOR=#FFFF00>
\r
8066 <B>Register Name</B>
\r
8068 <TD width=15% BGCOLOR=#FFFF00>
\r
8071 <TD width=10% BGCOLOR=#FFFF00>
\r
8074 <TD width=10% BGCOLOR=#FFFF00>
\r
8077 <TD width=15% BGCOLOR=#FFFF00>
\r
8078 <B>Reset Value</B>
\r
8080 <TD width=35% BGCOLOR=#FFFF00>
\r
8081 <B>Description</B>
\r
8085 <TD width=15% BGCOLOR=#FBF5EF>
\r
8086 <B>QSPI_REF_CTRL</B>
\r
8088 <TD width=15% BGCOLOR=#FBF5EF>
\r
8091 <TD width=10% BGCOLOR=#FBF5EF>
\r
8094 <TD width=10% BGCOLOR=#FBF5EF>
\r
8097 <TD width=15% BGCOLOR=#FBF5EF>
\r
8100 <TD width=35% BGCOLOR=#FBF5EF>
\r
8106 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8108 <TD width=15% BGCOLOR=#C0FFC0>
\r
8111 <TD width=15% BGCOLOR=#C0FFC0>
\r
8114 <TD width=10% BGCOLOR=#C0FFC0>
\r
8117 <TD width=10% BGCOLOR=#C0FFC0>
\r
8120 <TD width=15% BGCOLOR=#C0FFC0>
\r
8121 <B>Shifted Value</B>
\r
8123 <TD width=35% BGCOLOR=#C0FFC0>
\r
8124 <B>Description</B>
\r
8128 <TD width=15% BGCOLOR=#FBF5EF>
\r
8129 <B>PSU_CRL_APB_QSPI_REF_CTRL_CLKACT</B>
\r
8131 <TD width=15% BGCOLOR=#FBF5EF>
\r
8134 <TD width=10% BGCOLOR=#FBF5EF>
\r
8137 <TD width=10% BGCOLOR=#FBF5EF>
\r
8140 <TD width=15% BGCOLOR=#FBF5EF>
\r
8143 <TD width=35% BGCOLOR=#FBF5EF>
\r
8144 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8148 <TD width=15% BGCOLOR=#FBF5EF>
\r
8149 <B>PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1</B>
\r
8151 <TD width=15% BGCOLOR=#FBF5EF>
\r
8154 <TD width=10% BGCOLOR=#FBF5EF>
\r
8157 <TD width=10% BGCOLOR=#FBF5EF>
\r
8160 <TD width=15% BGCOLOR=#FBF5EF>
\r
8163 <TD width=35% BGCOLOR=#FBF5EF>
\r
8164 <B>6 bit divider</B>
\r
8168 <TD width=15% BGCOLOR=#FBF5EF>
\r
8169 <B>PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0</B>
\r
8171 <TD width=15% BGCOLOR=#FBF5EF>
\r
8174 <TD width=10% BGCOLOR=#FBF5EF>
\r
8177 <TD width=10% BGCOLOR=#FBF5EF>
\r
8180 <TD width=15% BGCOLOR=#FBF5EF>
\r
8183 <TD width=35% BGCOLOR=#FBF5EF>
\r
8184 <B>6 bit divider</B>
\r
8188 <TD width=15% BGCOLOR=#FBF5EF>
\r
8189 <B>PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL</B>
\r
8191 <TD width=15% BGCOLOR=#FBF5EF>
\r
8194 <TD width=10% BGCOLOR=#FBF5EF>
\r
8197 <TD width=10% BGCOLOR=#FBF5EF>
\r
8200 <TD width=15% BGCOLOR=#FBF5EF>
\r
8203 <TD width=35% BGCOLOR=#FBF5EF>
\r
8204 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8208 <TD width=15% BGCOLOR=#C0C0C0>
\r
8209 <B>PSU_CRL_APB_QSPI_REF_CTRL@0XFF5E0068</B>
\r
8211 <TD width=15% BGCOLOR=#C0C0C0>
\r
8214 <TD width=10% BGCOLOR=#C0C0C0>
\r
8217 <TD width=10% BGCOLOR=#C0C0C0>
\r
8220 <TD width=15% BGCOLOR=#C0C0C0>
\r
8223 <TD width=35% BGCOLOR=#C0C0C0>
\r
8224 <B>This register controls this reference clock</B>
\r
8229 <H2><a name="SDIO0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO0_REF_CTRL</a></H2>
\r
8230 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8232 <TD width=15% BGCOLOR=#FFFF00>
\r
8233 <B>Register Name</B>
\r
8235 <TD width=15% BGCOLOR=#FFFF00>
\r
8238 <TD width=10% BGCOLOR=#FFFF00>
\r
8241 <TD width=10% BGCOLOR=#FFFF00>
\r
8244 <TD width=15% BGCOLOR=#FFFF00>
\r
8245 <B>Reset Value</B>
\r
8247 <TD width=35% BGCOLOR=#FFFF00>
\r
8248 <B>Description</B>
\r
8252 <TD width=15% BGCOLOR=#FBF5EF>
\r
8253 <B>SDIO0_REF_CTRL</B>
\r
8255 <TD width=15% BGCOLOR=#FBF5EF>
\r
8258 <TD width=10% BGCOLOR=#FBF5EF>
\r
8261 <TD width=10% BGCOLOR=#FBF5EF>
\r
8264 <TD width=15% BGCOLOR=#FBF5EF>
\r
8267 <TD width=35% BGCOLOR=#FBF5EF>
\r
8273 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8275 <TD width=15% BGCOLOR=#C0FFC0>
\r
8278 <TD width=15% BGCOLOR=#C0FFC0>
\r
8281 <TD width=10% BGCOLOR=#C0FFC0>
\r
8284 <TD width=10% BGCOLOR=#C0FFC0>
\r
8287 <TD width=15% BGCOLOR=#C0FFC0>
\r
8288 <B>Shifted Value</B>
\r
8290 <TD width=35% BGCOLOR=#C0FFC0>
\r
8291 <B>Description</B>
\r
8295 <TD width=15% BGCOLOR=#FBF5EF>
\r
8296 <B>PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT</B>
\r
8298 <TD width=15% BGCOLOR=#FBF5EF>
\r
8301 <TD width=10% BGCOLOR=#FBF5EF>
\r
8304 <TD width=10% BGCOLOR=#FBF5EF>
\r
8307 <TD width=15% BGCOLOR=#FBF5EF>
\r
8310 <TD width=35% BGCOLOR=#FBF5EF>
\r
8311 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8315 <TD width=15% BGCOLOR=#FBF5EF>
\r
8316 <B>PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1</B>
\r
8318 <TD width=15% BGCOLOR=#FBF5EF>
\r
8321 <TD width=10% BGCOLOR=#FBF5EF>
\r
8324 <TD width=10% BGCOLOR=#FBF5EF>
\r
8327 <TD width=15% BGCOLOR=#FBF5EF>
\r
8330 <TD width=35% BGCOLOR=#FBF5EF>
\r
8331 <B>6 bit divider</B>
\r
8335 <TD width=15% BGCOLOR=#FBF5EF>
\r
8336 <B>PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0</B>
\r
8338 <TD width=15% BGCOLOR=#FBF5EF>
\r
8341 <TD width=10% BGCOLOR=#FBF5EF>
\r
8344 <TD width=10% BGCOLOR=#FBF5EF>
\r
8347 <TD width=15% BGCOLOR=#FBF5EF>
\r
8350 <TD width=35% BGCOLOR=#FBF5EF>
\r
8351 <B>6 bit divider</B>
\r
8355 <TD width=15% BGCOLOR=#FBF5EF>
\r
8356 <B>PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL</B>
\r
8358 <TD width=15% BGCOLOR=#FBF5EF>
\r
8361 <TD width=10% BGCOLOR=#FBF5EF>
\r
8364 <TD width=10% BGCOLOR=#FBF5EF>
\r
8367 <TD width=15% BGCOLOR=#FBF5EF>
\r
8370 <TD width=35% BGCOLOR=#FBF5EF>
\r
8371 <B>000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8375 <TD width=15% BGCOLOR=#C0C0C0>
\r
8376 <B>PSU_CRL_APB_SDIO0_REF_CTRL@0XFF5E006C</B>
\r
8378 <TD width=15% BGCOLOR=#C0C0C0>
\r
8381 <TD width=10% BGCOLOR=#C0C0C0>
\r
8384 <TD width=10% BGCOLOR=#C0C0C0>
\r
8387 <TD width=15% BGCOLOR=#C0C0C0>
\r
8390 <TD width=35% BGCOLOR=#C0C0C0>
\r
8391 <B>This register controls this reference clock</B>
\r
8396 <H2><a name="SDIO1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO1_REF_CTRL</a></H2>
\r
8397 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8399 <TD width=15% BGCOLOR=#FFFF00>
\r
8400 <B>Register Name</B>
\r
8402 <TD width=15% BGCOLOR=#FFFF00>
\r
8405 <TD width=10% BGCOLOR=#FFFF00>
\r
8408 <TD width=10% BGCOLOR=#FFFF00>
\r
8411 <TD width=15% BGCOLOR=#FFFF00>
\r
8412 <B>Reset Value</B>
\r
8414 <TD width=35% BGCOLOR=#FFFF00>
\r
8415 <B>Description</B>
\r
8419 <TD width=15% BGCOLOR=#FBF5EF>
\r
8420 <B>SDIO1_REF_CTRL</B>
\r
8422 <TD width=15% BGCOLOR=#FBF5EF>
\r
8425 <TD width=10% BGCOLOR=#FBF5EF>
\r
8428 <TD width=10% BGCOLOR=#FBF5EF>
\r
8431 <TD width=15% BGCOLOR=#FBF5EF>
\r
8434 <TD width=35% BGCOLOR=#FBF5EF>
\r
8440 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8442 <TD width=15% BGCOLOR=#C0FFC0>
\r
8445 <TD width=15% BGCOLOR=#C0FFC0>
\r
8448 <TD width=10% BGCOLOR=#C0FFC0>
\r
8451 <TD width=10% BGCOLOR=#C0FFC0>
\r
8454 <TD width=15% BGCOLOR=#C0FFC0>
\r
8455 <B>Shifted Value</B>
\r
8457 <TD width=35% BGCOLOR=#C0FFC0>
\r
8458 <B>Description</B>
\r
8462 <TD width=15% BGCOLOR=#FBF5EF>
\r
8463 <B>PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT</B>
\r
8465 <TD width=15% BGCOLOR=#FBF5EF>
\r
8468 <TD width=10% BGCOLOR=#FBF5EF>
\r
8471 <TD width=10% BGCOLOR=#FBF5EF>
\r
8474 <TD width=15% BGCOLOR=#FBF5EF>
\r
8477 <TD width=35% BGCOLOR=#FBF5EF>
\r
8478 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8482 <TD width=15% BGCOLOR=#FBF5EF>
\r
8483 <B>PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1</B>
\r
8485 <TD width=15% BGCOLOR=#FBF5EF>
\r
8488 <TD width=10% BGCOLOR=#FBF5EF>
\r
8491 <TD width=10% BGCOLOR=#FBF5EF>
\r
8494 <TD width=15% BGCOLOR=#FBF5EF>
\r
8497 <TD width=35% BGCOLOR=#FBF5EF>
\r
8498 <B>6 bit divider</B>
\r
8502 <TD width=15% BGCOLOR=#FBF5EF>
\r
8503 <B>PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0</B>
\r
8505 <TD width=15% BGCOLOR=#FBF5EF>
\r
8508 <TD width=10% BGCOLOR=#FBF5EF>
\r
8511 <TD width=10% BGCOLOR=#FBF5EF>
\r
8514 <TD width=15% BGCOLOR=#FBF5EF>
\r
8517 <TD width=35% BGCOLOR=#FBF5EF>
\r
8518 <B>6 bit divider</B>
\r
8522 <TD width=15% BGCOLOR=#FBF5EF>
\r
8523 <B>PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL</B>
\r
8525 <TD width=15% BGCOLOR=#FBF5EF>
\r
8528 <TD width=10% BGCOLOR=#FBF5EF>
\r
8531 <TD width=10% BGCOLOR=#FBF5EF>
\r
8534 <TD width=15% BGCOLOR=#FBF5EF>
\r
8537 <TD width=35% BGCOLOR=#FBF5EF>
\r
8538 <B>000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8542 <TD width=15% BGCOLOR=#C0C0C0>
\r
8543 <B>PSU_CRL_APB_SDIO1_REF_CTRL@0XFF5E0070</B>
\r
8545 <TD width=15% BGCOLOR=#C0C0C0>
\r
8548 <TD width=10% BGCOLOR=#C0C0C0>
\r
8551 <TD width=10% BGCOLOR=#C0C0C0>
\r
8554 <TD width=15% BGCOLOR=#C0C0C0>
\r
8557 <TD width=35% BGCOLOR=#C0C0C0>
\r
8558 <B>This register controls this reference clock</B>
\r
8563 <H2><a name="UART0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART0_REF_CTRL</a></H2>
\r
8564 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8566 <TD width=15% BGCOLOR=#FFFF00>
\r
8567 <B>Register Name</B>
\r
8569 <TD width=15% BGCOLOR=#FFFF00>
\r
8572 <TD width=10% BGCOLOR=#FFFF00>
\r
8575 <TD width=10% BGCOLOR=#FFFF00>
\r
8578 <TD width=15% BGCOLOR=#FFFF00>
\r
8579 <B>Reset Value</B>
\r
8581 <TD width=35% BGCOLOR=#FFFF00>
\r
8582 <B>Description</B>
\r
8586 <TD width=15% BGCOLOR=#FBF5EF>
\r
8587 <B>UART0_REF_CTRL</B>
\r
8589 <TD width=15% BGCOLOR=#FBF5EF>
\r
8592 <TD width=10% BGCOLOR=#FBF5EF>
\r
8595 <TD width=10% BGCOLOR=#FBF5EF>
\r
8598 <TD width=15% BGCOLOR=#FBF5EF>
\r
8601 <TD width=35% BGCOLOR=#FBF5EF>
\r
8607 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8609 <TD width=15% BGCOLOR=#C0FFC0>
\r
8612 <TD width=15% BGCOLOR=#C0FFC0>
\r
8615 <TD width=10% BGCOLOR=#C0FFC0>
\r
8618 <TD width=10% BGCOLOR=#C0FFC0>
\r
8621 <TD width=15% BGCOLOR=#C0FFC0>
\r
8622 <B>Shifted Value</B>
\r
8624 <TD width=35% BGCOLOR=#C0FFC0>
\r
8625 <B>Description</B>
\r
8629 <TD width=15% BGCOLOR=#FBF5EF>
\r
8630 <B>PSU_CRL_APB_UART0_REF_CTRL_CLKACT</B>
\r
8632 <TD width=15% BGCOLOR=#FBF5EF>
\r
8635 <TD width=10% BGCOLOR=#FBF5EF>
\r
8638 <TD width=10% BGCOLOR=#FBF5EF>
\r
8641 <TD width=15% BGCOLOR=#FBF5EF>
\r
8644 <TD width=35% BGCOLOR=#FBF5EF>
\r
8645 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8649 <TD width=15% BGCOLOR=#FBF5EF>
\r
8650 <B>PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1</B>
\r
8652 <TD width=15% BGCOLOR=#FBF5EF>
\r
8655 <TD width=10% BGCOLOR=#FBF5EF>
\r
8658 <TD width=10% BGCOLOR=#FBF5EF>
\r
8661 <TD width=15% BGCOLOR=#FBF5EF>
\r
8664 <TD width=35% BGCOLOR=#FBF5EF>
\r
8665 <B>6 bit divider</B>
\r
8669 <TD width=15% BGCOLOR=#FBF5EF>
\r
8670 <B>PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0</B>
\r
8672 <TD width=15% BGCOLOR=#FBF5EF>
\r
8675 <TD width=10% BGCOLOR=#FBF5EF>
\r
8678 <TD width=10% BGCOLOR=#FBF5EF>
\r
8681 <TD width=15% BGCOLOR=#FBF5EF>
\r
8684 <TD width=35% BGCOLOR=#FBF5EF>
\r
8685 <B>6 bit divider</B>
\r
8689 <TD width=15% BGCOLOR=#FBF5EF>
\r
8690 <B>PSU_CRL_APB_UART0_REF_CTRL_SRCSEL</B>
\r
8692 <TD width=15% BGCOLOR=#FBF5EF>
\r
8695 <TD width=10% BGCOLOR=#FBF5EF>
\r
8698 <TD width=10% BGCOLOR=#FBF5EF>
\r
8701 <TD width=15% BGCOLOR=#FBF5EF>
\r
8704 <TD width=35% BGCOLOR=#FBF5EF>
\r
8705 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8709 <TD width=15% BGCOLOR=#C0C0C0>
\r
8710 <B>PSU_CRL_APB_UART0_REF_CTRL@0XFF5E0074</B>
\r
8712 <TD width=15% BGCOLOR=#C0C0C0>
\r
8715 <TD width=10% BGCOLOR=#C0C0C0>
\r
8718 <TD width=10% BGCOLOR=#C0C0C0>
\r
8721 <TD width=15% BGCOLOR=#C0C0C0>
\r
8724 <TD width=35% BGCOLOR=#C0C0C0>
\r
8725 <B>This register controls this reference clock</B>
\r
8730 <H2><a name="UART1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART1_REF_CTRL</a></H2>
\r
8731 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8733 <TD width=15% BGCOLOR=#FFFF00>
\r
8734 <B>Register Name</B>
\r
8736 <TD width=15% BGCOLOR=#FFFF00>
\r
8739 <TD width=10% BGCOLOR=#FFFF00>
\r
8742 <TD width=10% BGCOLOR=#FFFF00>
\r
8745 <TD width=15% BGCOLOR=#FFFF00>
\r
8746 <B>Reset Value</B>
\r
8748 <TD width=35% BGCOLOR=#FFFF00>
\r
8749 <B>Description</B>
\r
8753 <TD width=15% BGCOLOR=#FBF5EF>
\r
8754 <B>UART1_REF_CTRL</B>
\r
8756 <TD width=15% BGCOLOR=#FBF5EF>
\r
8759 <TD width=10% BGCOLOR=#FBF5EF>
\r
8762 <TD width=10% BGCOLOR=#FBF5EF>
\r
8765 <TD width=15% BGCOLOR=#FBF5EF>
\r
8768 <TD width=35% BGCOLOR=#FBF5EF>
\r
8774 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8776 <TD width=15% BGCOLOR=#C0FFC0>
\r
8779 <TD width=15% BGCOLOR=#C0FFC0>
\r
8782 <TD width=10% BGCOLOR=#C0FFC0>
\r
8785 <TD width=10% BGCOLOR=#C0FFC0>
\r
8788 <TD width=15% BGCOLOR=#C0FFC0>
\r
8789 <B>Shifted Value</B>
\r
8791 <TD width=35% BGCOLOR=#C0FFC0>
\r
8792 <B>Description</B>
\r
8796 <TD width=15% BGCOLOR=#FBF5EF>
\r
8797 <B>PSU_CRL_APB_UART1_REF_CTRL_CLKACT</B>
\r
8799 <TD width=15% BGCOLOR=#FBF5EF>
\r
8802 <TD width=10% BGCOLOR=#FBF5EF>
\r
8805 <TD width=10% BGCOLOR=#FBF5EF>
\r
8808 <TD width=15% BGCOLOR=#FBF5EF>
\r
8811 <TD width=35% BGCOLOR=#FBF5EF>
\r
8812 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8816 <TD width=15% BGCOLOR=#FBF5EF>
\r
8817 <B>PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1</B>
\r
8819 <TD width=15% BGCOLOR=#FBF5EF>
\r
8822 <TD width=10% BGCOLOR=#FBF5EF>
\r
8825 <TD width=10% BGCOLOR=#FBF5EF>
\r
8828 <TD width=15% BGCOLOR=#FBF5EF>
\r
8831 <TD width=35% BGCOLOR=#FBF5EF>
\r
8832 <B>6 bit divider</B>
\r
8836 <TD width=15% BGCOLOR=#FBF5EF>
\r
8837 <B>PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0</B>
\r
8839 <TD width=15% BGCOLOR=#FBF5EF>
\r
8842 <TD width=10% BGCOLOR=#FBF5EF>
\r
8845 <TD width=10% BGCOLOR=#FBF5EF>
\r
8848 <TD width=15% BGCOLOR=#FBF5EF>
\r
8851 <TD width=35% BGCOLOR=#FBF5EF>
\r
8852 <B>6 bit divider</B>
\r
8856 <TD width=15% BGCOLOR=#FBF5EF>
\r
8857 <B>PSU_CRL_APB_UART1_REF_CTRL_SRCSEL</B>
\r
8859 <TD width=15% BGCOLOR=#FBF5EF>
\r
8862 <TD width=10% BGCOLOR=#FBF5EF>
\r
8865 <TD width=10% BGCOLOR=#FBF5EF>
\r
8868 <TD width=15% BGCOLOR=#FBF5EF>
\r
8871 <TD width=35% BGCOLOR=#FBF5EF>
\r
8872 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
8876 <TD width=15% BGCOLOR=#C0C0C0>
\r
8877 <B>PSU_CRL_APB_UART1_REF_CTRL@0XFF5E0078</B>
\r
8879 <TD width=15% BGCOLOR=#C0C0C0>
\r
8882 <TD width=10% BGCOLOR=#C0C0C0>
\r
8885 <TD width=10% BGCOLOR=#C0C0C0>
\r
8888 <TD width=15% BGCOLOR=#C0C0C0>
\r
8891 <TD width=35% BGCOLOR=#C0C0C0>
\r
8892 <B>This register controls this reference clock</B>
\r
8897 <H2><a name="I2C0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)I2C0_REF_CTRL</a></H2>
\r
8898 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8900 <TD width=15% BGCOLOR=#FFFF00>
\r
8901 <B>Register Name</B>
\r
8903 <TD width=15% BGCOLOR=#FFFF00>
\r
8906 <TD width=10% BGCOLOR=#FFFF00>
\r
8909 <TD width=10% BGCOLOR=#FFFF00>
\r
8912 <TD width=15% BGCOLOR=#FFFF00>
\r
8913 <B>Reset Value</B>
\r
8915 <TD width=35% BGCOLOR=#FFFF00>
\r
8916 <B>Description</B>
\r
8920 <TD width=15% BGCOLOR=#FBF5EF>
\r
8921 <B>I2C0_REF_CTRL</B>
\r
8923 <TD width=15% BGCOLOR=#FBF5EF>
\r
8926 <TD width=10% BGCOLOR=#FBF5EF>
\r
8929 <TD width=10% BGCOLOR=#FBF5EF>
\r
8932 <TD width=15% BGCOLOR=#FBF5EF>
\r
8935 <TD width=35% BGCOLOR=#FBF5EF>
\r
8941 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
8943 <TD width=15% BGCOLOR=#C0FFC0>
\r
8946 <TD width=15% BGCOLOR=#C0FFC0>
\r
8949 <TD width=10% BGCOLOR=#C0FFC0>
\r
8952 <TD width=10% BGCOLOR=#C0FFC0>
\r
8955 <TD width=15% BGCOLOR=#C0FFC0>
\r
8956 <B>Shifted Value</B>
\r
8958 <TD width=35% BGCOLOR=#C0FFC0>
\r
8959 <B>Description</B>
\r
8963 <TD width=15% BGCOLOR=#FBF5EF>
\r
8964 <B>PSU_CRL_APB_I2C0_REF_CTRL_CLKACT</B>
\r
8966 <TD width=15% BGCOLOR=#FBF5EF>
\r
8969 <TD width=10% BGCOLOR=#FBF5EF>
\r
8972 <TD width=10% BGCOLOR=#FBF5EF>
\r
8975 <TD width=15% BGCOLOR=#FBF5EF>
\r
8978 <TD width=35% BGCOLOR=#FBF5EF>
\r
8979 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
8983 <TD width=15% BGCOLOR=#FBF5EF>
\r
8984 <B>PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1</B>
\r
8986 <TD width=15% BGCOLOR=#FBF5EF>
\r
8989 <TD width=10% BGCOLOR=#FBF5EF>
\r
8992 <TD width=10% BGCOLOR=#FBF5EF>
\r
8995 <TD width=15% BGCOLOR=#FBF5EF>
\r
8998 <TD width=35% BGCOLOR=#FBF5EF>
\r
8999 <B>6 bit divider</B>
\r
9003 <TD width=15% BGCOLOR=#FBF5EF>
\r
9004 <B>PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0</B>
\r
9006 <TD width=15% BGCOLOR=#FBF5EF>
\r
9009 <TD width=10% BGCOLOR=#FBF5EF>
\r
9012 <TD width=10% BGCOLOR=#FBF5EF>
\r
9015 <TD width=15% BGCOLOR=#FBF5EF>
\r
9018 <TD width=35% BGCOLOR=#FBF5EF>
\r
9019 <B>6 bit divider</B>
\r
9023 <TD width=15% BGCOLOR=#FBF5EF>
\r
9024 <B>PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL</B>
\r
9026 <TD width=15% BGCOLOR=#FBF5EF>
\r
9029 <TD width=10% BGCOLOR=#FBF5EF>
\r
9032 <TD width=10% BGCOLOR=#FBF5EF>
\r
9035 <TD width=15% BGCOLOR=#FBF5EF>
\r
9038 <TD width=35% BGCOLOR=#FBF5EF>
\r
9039 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9043 <TD width=15% BGCOLOR=#C0C0C0>
\r
9044 <B>PSU_CRL_APB_I2C0_REF_CTRL@0XFF5E0120</B>
\r
9046 <TD width=15% BGCOLOR=#C0C0C0>
\r
9049 <TD width=10% BGCOLOR=#C0C0C0>
\r
9052 <TD width=10% BGCOLOR=#C0C0C0>
\r
9055 <TD width=15% BGCOLOR=#C0C0C0>
\r
9058 <TD width=35% BGCOLOR=#C0C0C0>
\r
9059 <B>This register controls this reference clock</B>
\r
9064 <H2><a name="I2C1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)I2C1_REF_CTRL</a></H2>
\r
9065 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9067 <TD width=15% BGCOLOR=#FFFF00>
\r
9068 <B>Register Name</B>
\r
9070 <TD width=15% BGCOLOR=#FFFF00>
\r
9073 <TD width=10% BGCOLOR=#FFFF00>
\r
9076 <TD width=10% BGCOLOR=#FFFF00>
\r
9079 <TD width=15% BGCOLOR=#FFFF00>
\r
9080 <B>Reset Value</B>
\r
9082 <TD width=35% BGCOLOR=#FFFF00>
\r
9083 <B>Description</B>
\r
9087 <TD width=15% BGCOLOR=#FBF5EF>
\r
9088 <B>I2C1_REF_CTRL</B>
\r
9090 <TD width=15% BGCOLOR=#FBF5EF>
\r
9093 <TD width=10% BGCOLOR=#FBF5EF>
\r
9096 <TD width=10% BGCOLOR=#FBF5EF>
\r
9099 <TD width=15% BGCOLOR=#FBF5EF>
\r
9102 <TD width=35% BGCOLOR=#FBF5EF>
\r
9108 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9110 <TD width=15% BGCOLOR=#C0FFC0>
\r
9113 <TD width=15% BGCOLOR=#C0FFC0>
\r
9116 <TD width=10% BGCOLOR=#C0FFC0>
\r
9119 <TD width=10% BGCOLOR=#C0FFC0>
\r
9122 <TD width=15% BGCOLOR=#C0FFC0>
\r
9123 <B>Shifted Value</B>
\r
9125 <TD width=35% BGCOLOR=#C0FFC0>
\r
9126 <B>Description</B>
\r
9130 <TD width=15% BGCOLOR=#FBF5EF>
\r
9131 <B>PSU_CRL_APB_I2C1_REF_CTRL_CLKACT</B>
\r
9133 <TD width=15% BGCOLOR=#FBF5EF>
\r
9136 <TD width=10% BGCOLOR=#FBF5EF>
\r
9139 <TD width=10% BGCOLOR=#FBF5EF>
\r
9142 <TD width=15% BGCOLOR=#FBF5EF>
\r
9145 <TD width=35% BGCOLOR=#FBF5EF>
\r
9146 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9150 <TD width=15% BGCOLOR=#FBF5EF>
\r
9151 <B>PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1</B>
\r
9153 <TD width=15% BGCOLOR=#FBF5EF>
\r
9156 <TD width=10% BGCOLOR=#FBF5EF>
\r
9159 <TD width=10% BGCOLOR=#FBF5EF>
\r
9162 <TD width=15% BGCOLOR=#FBF5EF>
\r
9165 <TD width=35% BGCOLOR=#FBF5EF>
\r
9166 <B>6 bit divider</B>
\r
9170 <TD width=15% BGCOLOR=#FBF5EF>
\r
9171 <B>PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0</B>
\r
9173 <TD width=15% BGCOLOR=#FBF5EF>
\r
9176 <TD width=10% BGCOLOR=#FBF5EF>
\r
9179 <TD width=10% BGCOLOR=#FBF5EF>
\r
9182 <TD width=15% BGCOLOR=#FBF5EF>
\r
9185 <TD width=35% BGCOLOR=#FBF5EF>
\r
9186 <B>6 bit divider</B>
\r
9190 <TD width=15% BGCOLOR=#FBF5EF>
\r
9191 <B>PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL</B>
\r
9193 <TD width=15% BGCOLOR=#FBF5EF>
\r
9196 <TD width=10% BGCOLOR=#FBF5EF>
\r
9199 <TD width=10% BGCOLOR=#FBF5EF>
\r
9202 <TD width=15% BGCOLOR=#FBF5EF>
\r
9205 <TD width=35% BGCOLOR=#FBF5EF>
\r
9206 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9210 <TD width=15% BGCOLOR=#C0C0C0>
\r
9211 <B>PSU_CRL_APB_I2C1_REF_CTRL@0XFF5E0124</B>
\r
9213 <TD width=15% BGCOLOR=#C0C0C0>
\r
9216 <TD width=10% BGCOLOR=#C0C0C0>
\r
9219 <TD width=10% BGCOLOR=#C0C0C0>
\r
9222 <TD width=15% BGCOLOR=#C0C0C0>
\r
9225 <TD width=35% BGCOLOR=#C0C0C0>
\r
9226 <B>This register controls this reference clock</B>
\r
9231 <H2><a name="SPI0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SPI0_REF_CTRL</a></H2>
\r
9232 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9234 <TD width=15% BGCOLOR=#FFFF00>
\r
9235 <B>Register Name</B>
\r
9237 <TD width=15% BGCOLOR=#FFFF00>
\r
9240 <TD width=10% BGCOLOR=#FFFF00>
\r
9243 <TD width=10% BGCOLOR=#FFFF00>
\r
9246 <TD width=15% BGCOLOR=#FFFF00>
\r
9247 <B>Reset Value</B>
\r
9249 <TD width=35% BGCOLOR=#FFFF00>
\r
9250 <B>Description</B>
\r
9254 <TD width=15% BGCOLOR=#FBF5EF>
\r
9255 <B>SPI0_REF_CTRL</B>
\r
9257 <TD width=15% BGCOLOR=#FBF5EF>
\r
9260 <TD width=10% BGCOLOR=#FBF5EF>
\r
9263 <TD width=10% BGCOLOR=#FBF5EF>
\r
9266 <TD width=15% BGCOLOR=#FBF5EF>
\r
9269 <TD width=35% BGCOLOR=#FBF5EF>
\r
9275 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9277 <TD width=15% BGCOLOR=#C0FFC0>
\r
9280 <TD width=15% BGCOLOR=#C0FFC0>
\r
9283 <TD width=10% BGCOLOR=#C0FFC0>
\r
9286 <TD width=10% BGCOLOR=#C0FFC0>
\r
9289 <TD width=15% BGCOLOR=#C0FFC0>
\r
9290 <B>Shifted Value</B>
\r
9292 <TD width=35% BGCOLOR=#C0FFC0>
\r
9293 <B>Description</B>
\r
9297 <TD width=15% BGCOLOR=#FBF5EF>
\r
9298 <B>PSU_CRL_APB_SPI0_REF_CTRL_CLKACT</B>
\r
9300 <TD width=15% BGCOLOR=#FBF5EF>
\r
9303 <TD width=10% BGCOLOR=#FBF5EF>
\r
9306 <TD width=10% BGCOLOR=#FBF5EF>
\r
9309 <TD width=15% BGCOLOR=#FBF5EF>
\r
9312 <TD width=35% BGCOLOR=#FBF5EF>
\r
9313 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9317 <TD width=15% BGCOLOR=#FBF5EF>
\r
9318 <B>PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1</B>
\r
9320 <TD width=15% BGCOLOR=#FBF5EF>
\r
9323 <TD width=10% BGCOLOR=#FBF5EF>
\r
9326 <TD width=10% BGCOLOR=#FBF5EF>
\r
9329 <TD width=15% BGCOLOR=#FBF5EF>
\r
9332 <TD width=35% BGCOLOR=#FBF5EF>
\r
9333 <B>6 bit divider</B>
\r
9337 <TD width=15% BGCOLOR=#FBF5EF>
\r
9338 <B>PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0</B>
\r
9340 <TD width=15% BGCOLOR=#FBF5EF>
\r
9343 <TD width=10% BGCOLOR=#FBF5EF>
\r
9346 <TD width=10% BGCOLOR=#FBF5EF>
\r
9349 <TD width=15% BGCOLOR=#FBF5EF>
\r
9352 <TD width=35% BGCOLOR=#FBF5EF>
\r
9353 <B>6 bit divider</B>
\r
9357 <TD width=15% BGCOLOR=#FBF5EF>
\r
9358 <B>PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL</B>
\r
9360 <TD width=15% BGCOLOR=#FBF5EF>
\r
9363 <TD width=10% BGCOLOR=#FBF5EF>
\r
9366 <TD width=10% BGCOLOR=#FBF5EF>
\r
9369 <TD width=15% BGCOLOR=#FBF5EF>
\r
9372 <TD width=35% BGCOLOR=#FBF5EF>
\r
9373 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9377 <TD width=15% BGCOLOR=#C0C0C0>
\r
9378 <B>PSU_CRL_APB_SPI0_REF_CTRL@0XFF5E007C</B>
\r
9380 <TD width=15% BGCOLOR=#C0C0C0>
\r
9383 <TD width=10% BGCOLOR=#C0C0C0>
\r
9386 <TD width=10% BGCOLOR=#C0C0C0>
\r
9389 <TD width=15% BGCOLOR=#C0C0C0>
\r
9392 <TD width=35% BGCOLOR=#C0C0C0>
\r
9393 <B>This register controls this reference clock</B>
\r
9398 <H2><a name="SPI1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)SPI1_REF_CTRL</a></H2>
\r
9399 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9401 <TD width=15% BGCOLOR=#FFFF00>
\r
9402 <B>Register Name</B>
\r
9404 <TD width=15% BGCOLOR=#FFFF00>
\r
9407 <TD width=10% BGCOLOR=#FFFF00>
\r
9410 <TD width=10% BGCOLOR=#FFFF00>
\r
9413 <TD width=15% BGCOLOR=#FFFF00>
\r
9414 <B>Reset Value</B>
\r
9416 <TD width=35% BGCOLOR=#FFFF00>
\r
9417 <B>Description</B>
\r
9421 <TD width=15% BGCOLOR=#FBF5EF>
\r
9422 <B>SPI1_REF_CTRL</B>
\r
9424 <TD width=15% BGCOLOR=#FBF5EF>
\r
9427 <TD width=10% BGCOLOR=#FBF5EF>
\r
9430 <TD width=10% BGCOLOR=#FBF5EF>
\r
9433 <TD width=15% BGCOLOR=#FBF5EF>
\r
9436 <TD width=35% BGCOLOR=#FBF5EF>
\r
9442 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9444 <TD width=15% BGCOLOR=#C0FFC0>
\r
9447 <TD width=15% BGCOLOR=#C0FFC0>
\r
9450 <TD width=10% BGCOLOR=#C0FFC0>
\r
9453 <TD width=10% BGCOLOR=#C0FFC0>
\r
9456 <TD width=15% BGCOLOR=#C0FFC0>
\r
9457 <B>Shifted Value</B>
\r
9459 <TD width=35% BGCOLOR=#C0FFC0>
\r
9460 <B>Description</B>
\r
9464 <TD width=15% BGCOLOR=#FBF5EF>
\r
9465 <B>PSU_CRL_APB_SPI1_REF_CTRL_CLKACT</B>
\r
9467 <TD width=15% BGCOLOR=#FBF5EF>
\r
9470 <TD width=10% BGCOLOR=#FBF5EF>
\r
9473 <TD width=10% BGCOLOR=#FBF5EF>
\r
9476 <TD width=15% BGCOLOR=#FBF5EF>
\r
9479 <TD width=35% BGCOLOR=#FBF5EF>
\r
9480 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9484 <TD width=15% BGCOLOR=#FBF5EF>
\r
9485 <B>PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1</B>
\r
9487 <TD width=15% BGCOLOR=#FBF5EF>
\r
9490 <TD width=10% BGCOLOR=#FBF5EF>
\r
9493 <TD width=10% BGCOLOR=#FBF5EF>
\r
9496 <TD width=15% BGCOLOR=#FBF5EF>
\r
9499 <TD width=35% BGCOLOR=#FBF5EF>
\r
9500 <B>6 bit divider</B>
\r
9504 <TD width=15% BGCOLOR=#FBF5EF>
\r
9505 <B>PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0</B>
\r
9507 <TD width=15% BGCOLOR=#FBF5EF>
\r
9510 <TD width=10% BGCOLOR=#FBF5EF>
\r
9513 <TD width=10% BGCOLOR=#FBF5EF>
\r
9516 <TD width=15% BGCOLOR=#FBF5EF>
\r
9519 <TD width=35% BGCOLOR=#FBF5EF>
\r
9520 <B>6 bit divider</B>
\r
9524 <TD width=15% BGCOLOR=#FBF5EF>
\r
9525 <B>PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL</B>
\r
9527 <TD width=15% BGCOLOR=#FBF5EF>
\r
9530 <TD width=10% BGCOLOR=#FBF5EF>
\r
9533 <TD width=10% BGCOLOR=#FBF5EF>
\r
9536 <TD width=15% BGCOLOR=#FBF5EF>
\r
9539 <TD width=35% BGCOLOR=#FBF5EF>
\r
9540 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9544 <TD width=15% BGCOLOR=#C0C0C0>
\r
9545 <B>PSU_CRL_APB_SPI1_REF_CTRL@0XFF5E0080</B>
\r
9547 <TD width=15% BGCOLOR=#C0C0C0>
\r
9550 <TD width=10% BGCOLOR=#C0C0C0>
\r
9553 <TD width=10% BGCOLOR=#C0C0C0>
\r
9556 <TD width=15% BGCOLOR=#C0C0C0>
\r
9559 <TD width=35% BGCOLOR=#C0C0C0>
\r
9560 <B>This register controls this reference clock</B>
\r
9565 <H2><a name="CAN0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)CAN0_REF_CTRL</a></H2>
\r
9566 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9568 <TD width=15% BGCOLOR=#FFFF00>
\r
9569 <B>Register Name</B>
\r
9571 <TD width=15% BGCOLOR=#FFFF00>
\r
9574 <TD width=10% BGCOLOR=#FFFF00>
\r
9577 <TD width=10% BGCOLOR=#FFFF00>
\r
9580 <TD width=15% BGCOLOR=#FFFF00>
\r
9581 <B>Reset Value</B>
\r
9583 <TD width=35% BGCOLOR=#FFFF00>
\r
9584 <B>Description</B>
\r
9588 <TD width=15% BGCOLOR=#FBF5EF>
\r
9589 <B>CAN0_REF_CTRL</B>
\r
9591 <TD width=15% BGCOLOR=#FBF5EF>
\r
9594 <TD width=10% BGCOLOR=#FBF5EF>
\r
9597 <TD width=10% BGCOLOR=#FBF5EF>
\r
9600 <TD width=15% BGCOLOR=#FBF5EF>
\r
9603 <TD width=35% BGCOLOR=#FBF5EF>
\r
9609 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9611 <TD width=15% BGCOLOR=#C0FFC0>
\r
9614 <TD width=15% BGCOLOR=#C0FFC0>
\r
9617 <TD width=10% BGCOLOR=#C0FFC0>
\r
9620 <TD width=10% BGCOLOR=#C0FFC0>
\r
9623 <TD width=15% BGCOLOR=#C0FFC0>
\r
9624 <B>Shifted Value</B>
\r
9626 <TD width=35% BGCOLOR=#C0FFC0>
\r
9627 <B>Description</B>
\r
9631 <TD width=15% BGCOLOR=#FBF5EF>
\r
9632 <B>PSU_CRL_APB_CAN0_REF_CTRL_CLKACT</B>
\r
9634 <TD width=15% BGCOLOR=#FBF5EF>
\r
9637 <TD width=10% BGCOLOR=#FBF5EF>
\r
9640 <TD width=10% BGCOLOR=#FBF5EF>
\r
9643 <TD width=15% BGCOLOR=#FBF5EF>
\r
9646 <TD width=35% BGCOLOR=#FBF5EF>
\r
9647 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9651 <TD width=15% BGCOLOR=#FBF5EF>
\r
9652 <B>PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1</B>
\r
9654 <TD width=15% BGCOLOR=#FBF5EF>
\r
9657 <TD width=10% BGCOLOR=#FBF5EF>
\r
9660 <TD width=10% BGCOLOR=#FBF5EF>
\r
9663 <TD width=15% BGCOLOR=#FBF5EF>
\r
9666 <TD width=35% BGCOLOR=#FBF5EF>
\r
9667 <B>6 bit divider</B>
\r
9671 <TD width=15% BGCOLOR=#FBF5EF>
\r
9672 <B>PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0</B>
\r
9674 <TD width=15% BGCOLOR=#FBF5EF>
\r
9677 <TD width=10% BGCOLOR=#FBF5EF>
\r
9680 <TD width=10% BGCOLOR=#FBF5EF>
\r
9683 <TD width=15% BGCOLOR=#FBF5EF>
\r
9686 <TD width=35% BGCOLOR=#FBF5EF>
\r
9687 <B>6 bit divider</B>
\r
9691 <TD width=15% BGCOLOR=#FBF5EF>
\r
9692 <B>PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL</B>
\r
9694 <TD width=15% BGCOLOR=#FBF5EF>
\r
9697 <TD width=10% BGCOLOR=#FBF5EF>
\r
9700 <TD width=10% BGCOLOR=#FBF5EF>
\r
9703 <TD width=15% BGCOLOR=#FBF5EF>
\r
9706 <TD width=35% BGCOLOR=#FBF5EF>
\r
9707 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9711 <TD width=15% BGCOLOR=#C0C0C0>
\r
9712 <B>PSU_CRL_APB_CAN0_REF_CTRL@0XFF5E0084</B>
\r
9714 <TD width=15% BGCOLOR=#C0C0C0>
\r
9717 <TD width=10% BGCOLOR=#C0C0C0>
\r
9720 <TD width=10% BGCOLOR=#C0C0C0>
\r
9723 <TD width=15% BGCOLOR=#C0C0C0>
\r
9726 <TD width=35% BGCOLOR=#C0C0C0>
\r
9727 <B>This register controls this reference clock</B>
\r
9732 <H2><a name="CAN1_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)CAN1_REF_CTRL</a></H2>
\r
9733 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9735 <TD width=15% BGCOLOR=#FFFF00>
\r
9736 <B>Register Name</B>
\r
9738 <TD width=15% BGCOLOR=#FFFF00>
\r
9741 <TD width=10% BGCOLOR=#FFFF00>
\r
9744 <TD width=10% BGCOLOR=#FFFF00>
\r
9747 <TD width=15% BGCOLOR=#FFFF00>
\r
9748 <B>Reset Value</B>
\r
9750 <TD width=35% BGCOLOR=#FFFF00>
\r
9751 <B>Description</B>
\r
9755 <TD width=15% BGCOLOR=#FBF5EF>
\r
9756 <B>CAN1_REF_CTRL</B>
\r
9758 <TD width=15% BGCOLOR=#FBF5EF>
\r
9761 <TD width=10% BGCOLOR=#FBF5EF>
\r
9764 <TD width=10% BGCOLOR=#FBF5EF>
\r
9767 <TD width=15% BGCOLOR=#FBF5EF>
\r
9770 <TD width=35% BGCOLOR=#FBF5EF>
\r
9776 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9778 <TD width=15% BGCOLOR=#C0FFC0>
\r
9781 <TD width=15% BGCOLOR=#C0FFC0>
\r
9784 <TD width=10% BGCOLOR=#C0FFC0>
\r
9787 <TD width=10% BGCOLOR=#C0FFC0>
\r
9790 <TD width=15% BGCOLOR=#C0FFC0>
\r
9791 <B>Shifted Value</B>
\r
9793 <TD width=35% BGCOLOR=#C0FFC0>
\r
9794 <B>Description</B>
\r
9798 <TD width=15% BGCOLOR=#FBF5EF>
\r
9799 <B>PSU_CRL_APB_CAN1_REF_CTRL_CLKACT</B>
\r
9801 <TD width=15% BGCOLOR=#FBF5EF>
\r
9804 <TD width=10% BGCOLOR=#FBF5EF>
\r
9807 <TD width=10% BGCOLOR=#FBF5EF>
\r
9810 <TD width=15% BGCOLOR=#FBF5EF>
\r
9813 <TD width=35% BGCOLOR=#FBF5EF>
\r
9814 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9818 <TD width=15% BGCOLOR=#FBF5EF>
\r
9819 <B>PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1</B>
\r
9821 <TD width=15% BGCOLOR=#FBF5EF>
\r
9824 <TD width=10% BGCOLOR=#FBF5EF>
\r
9827 <TD width=10% BGCOLOR=#FBF5EF>
\r
9830 <TD width=15% BGCOLOR=#FBF5EF>
\r
9833 <TD width=35% BGCOLOR=#FBF5EF>
\r
9834 <B>6 bit divider</B>
\r
9838 <TD width=15% BGCOLOR=#FBF5EF>
\r
9839 <B>PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0</B>
\r
9841 <TD width=15% BGCOLOR=#FBF5EF>
\r
9844 <TD width=10% BGCOLOR=#FBF5EF>
\r
9847 <TD width=10% BGCOLOR=#FBF5EF>
\r
9850 <TD width=15% BGCOLOR=#FBF5EF>
\r
9853 <TD width=35% BGCOLOR=#FBF5EF>
\r
9854 <B>6 bit divider</B>
\r
9858 <TD width=15% BGCOLOR=#FBF5EF>
\r
9859 <B>PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL</B>
\r
9861 <TD width=15% BGCOLOR=#FBF5EF>
\r
9864 <TD width=10% BGCOLOR=#FBF5EF>
\r
9867 <TD width=10% BGCOLOR=#FBF5EF>
\r
9870 <TD width=15% BGCOLOR=#FBF5EF>
\r
9873 <TD width=35% BGCOLOR=#FBF5EF>
\r
9874 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
9878 <TD width=15% BGCOLOR=#C0C0C0>
\r
9879 <B>PSU_CRL_APB_CAN1_REF_CTRL@0XFF5E0088</B>
\r
9881 <TD width=15% BGCOLOR=#C0C0C0>
\r
9884 <TD width=10% BGCOLOR=#C0C0C0>
\r
9887 <TD width=10% BGCOLOR=#C0C0C0>
\r
9890 <TD width=15% BGCOLOR=#C0C0C0>
\r
9893 <TD width=35% BGCOLOR=#C0C0C0>
\r
9894 <B>This register controls this reference clock</B>
\r
9899 <H2><a name="CPU_R5_CTRL">Register (<A href=#mod___slcr> slcr </A>)CPU_R5_CTRL</a></H2>
\r
9900 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9902 <TD width=15% BGCOLOR=#FFFF00>
\r
9903 <B>Register Name</B>
\r
9905 <TD width=15% BGCOLOR=#FFFF00>
\r
9908 <TD width=10% BGCOLOR=#FFFF00>
\r
9911 <TD width=10% BGCOLOR=#FFFF00>
\r
9914 <TD width=15% BGCOLOR=#FFFF00>
\r
9915 <B>Reset Value</B>
\r
9917 <TD width=35% BGCOLOR=#FFFF00>
\r
9918 <B>Description</B>
\r
9922 <TD width=15% BGCOLOR=#FBF5EF>
\r
9923 <B>CPU_R5_CTRL</B>
\r
9925 <TD width=15% BGCOLOR=#FBF5EF>
\r
9928 <TD width=10% BGCOLOR=#FBF5EF>
\r
9931 <TD width=10% BGCOLOR=#FBF5EF>
\r
9934 <TD width=15% BGCOLOR=#FBF5EF>
\r
9937 <TD width=35% BGCOLOR=#FBF5EF>
\r
9943 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
9945 <TD width=15% BGCOLOR=#C0FFC0>
\r
9948 <TD width=15% BGCOLOR=#C0FFC0>
\r
9951 <TD width=10% BGCOLOR=#C0FFC0>
\r
9954 <TD width=10% BGCOLOR=#C0FFC0>
\r
9957 <TD width=15% BGCOLOR=#C0FFC0>
\r
9958 <B>Shifted Value</B>
\r
9960 <TD width=35% BGCOLOR=#C0FFC0>
\r
9961 <B>Description</B>
\r
9965 <TD width=15% BGCOLOR=#FBF5EF>
\r
9966 <B>PSU_CRL_APB_CPU_R5_CTRL_CLKACT</B>
\r
9968 <TD width=15% BGCOLOR=#FBF5EF>
\r
9971 <TD width=10% BGCOLOR=#FBF5EF>
\r
9974 <TD width=10% BGCOLOR=#FBF5EF>
\r
9977 <TD width=15% BGCOLOR=#FBF5EF>
\r
9980 <TD width=35% BGCOLOR=#FBF5EF>
\r
9981 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
9985 <TD width=15% BGCOLOR=#FBF5EF>
\r
9986 <B>PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0</B>
\r
9988 <TD width=15% BGCOLOR=#FBF5EF>
\r
9991 <TD width=10% BGCOLOR=#FBF5EF>
\r
9994 <TD width=10% BGCOLOR=#FBF5EF>
\r
9997 <TD width=15% BGCOLOR=#FBF5EF>
\r
10000 <TD width=35% BGCOLOR=#FBF5EF>
\r
10001 <B>6 bit divider</B>
\r
10004 <TR valign="top">
\r
10005 <TD width=15% BGCOLOR=#FBF5EF>
\r
10006 <B>PSU_CRL_APB_CPU_R5_CTRL_SRCSEL</B>
\r
10008 <TD width=15% BGCOLOR=#FBF5EF>
\r
10011 <TD width=10% BGCOLOR=#FBF5EF>
\r
10014 <TD width=10% BGCOLOR=#FBF5EF>
\r
10017 <TD width=15% BGCOLOR=#FBF5EF>
\r
10020 <TD width=35% BGCOLOR=#FBF5EF>
\r
10021 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10024 <TR valign="top">
\r
10025 <TD width=15% BGCOLOR=#C0C0C0>
\r
10026 <B>PSU_CRL_APB_CPU_R5_CTRL@0XFF5E0090</B>
\r
10028 <TD width=15% BGCOLOR=#C0C0C0>
\r
10031 <TD width=10% BGCOLOR=#C0C0C0>
\r
10034 <TD width=10% BGCOLOR=#C0C0C0>
\r
10037 <TD width=15% BGCOLOR=#C0C0C0>
\r
10040 <TD width=35% BGCOLOR=#C0C0C0>
\r
10041 <B>This register controls this reference clock</B>
\r
10046 <H2><a name="IOU_SWITCH_CTRL">Register (<A href=#mod___slcr> slcr </A>)IOU_SWITCH_CTRL</a></H2>
\r
10047 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10048 <TR valign="top">
\r
10049 <TD width=15% BGCOLOR=#FFFF00>
\r
10050 <B>Register Name</B>
\r
10052 <TD width=15% BGCOLOR=#FFFF00>
\r
10055 <TD width=10% BGCOLOR=#FFFF00>
\r
10058 <TD width=10% BGCOLOR=#FFFF00>
\r
10061 <TD width=15% BGCOLOR=#FFFF00>
\r
10062 <B>Reset Value</B>
\r
10064 <TD width=35% BGCOLOR=#FFFF00>
\r
10065 <B>Description</B>
\r
10068 <TR valign="top">
\r
10069 <TD width=15% BGCOLOR=#FBF5EF>
\r
10070 <B>IOU_SWITCH_CTRL</B>
\r
10072 <TD width=15% BGCOLOR=#FBF5EF>
\r
10073 <B>0XFF5E009C</B>
\r
10075 <TD width=10% BGCOLOR=#FBF5EF>
\r
10078 <TD width=10% BGCOLOR=#FBF5EF>
\r
10081 <TD width=15% BGCOLOR=#FBF5EF>
\r
10082 <B>0x00000000</B>
\r
10084 <TD width=35% BGCOLOR=#FBF5EF>
\r
10090 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10091 <TR valign="top">
\r
10092 <TD width=15% BGCOLOR=#C0FFC0>
\r
10093 <B>Field Name</B>
\r
10095 <TD width=15% BGCOLOR=#C0FFC0>
\r
10098 <TD width=10% BGCOLOR=#C0FFC0>
\r
10101 <TD width=10% BGCOLOR=#C0FFC0>
\r
10104 <TD width=15% BGCOLOR=#C0FFC0>
\r
10105 <B>Shifted Value</B>
\r
10107 <TD width=35% BGCOLOR=#C0FFC0>
\r
10108 <B>Description</B>
\r
10111 <TR valign="top">
\r
10112 <TD width=15% BGCOLOR=#FBF5EF>
\r
10113 <B>PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT</B>
\r
10115 <TD width=15% BGCOLOR=#FBF5EF>
\r
10118 <TD width=10% BGCOLOR=#FBF5EF>
\r
10121 <TD width=10% BGCOLOR=#FBF5EF>
\r
10124 <TD width=15% BGCOLOR=#FBF5EF>
\r
10127 <TD width=35% BGCOLOR=#FBF5EF>
\r
10128 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10131 <TR valign="top">
\r
10132 <TD width=15% BGCOLOR=#FBF5EF>
\r
10133 <B>PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0</B>
\r
10135 <TD width=15% BGCOLOR=#FBF5EF>
\r
10138 <TD width=10% BGCOLOR=#FBF5EF>
\r
10141 <TD width=10% BGCOLOR=#FBF5EF>
\r
10144 <TD width=15% BGCOLOR=#FBF5EF>
\r
10147 <TD width=35% BGCOLOR=#FBF5EF>
\r
10148 <B>6 bit divider</B>
\r
10151 <TR valign="top">
\r
10152 <TD width=15% BGCOLOR=#FBF5EF>
\r
10153 <B>PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL</B>
\r
10155 <TD width=15% BGCOLOR=#FBF5EF>
\r
10158 <TD width=10% BGCOLOR=#FBF5EF>
\r
10161 <TD width=10% BGCOLOR=#FBF5EF>
\r
10164 <TD width=15% BGCOLOR=#FBF5EF>
\r
10167 <TD width=35% BGCOLOR=#FBF5EF>
\r
10168 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10171 <TR valign="top">
\r
10172 <TD width=15% BGCOLOR=#C0C0C0>
\r
10173 <B>PSU_CRL_APB_IOU_SWITCH_CTRL@0XFF5E009C</B>
\r
10175 <TD width=15% BGCOLOR=#C0C0C0>
\r
10178 <TD width=10% BGCOLOR=#C0C0C0>
\r
10181 <TD width=10% BGCOLOR=#C0C0C0>
\r
10184 <TD width=15% BGCOLOR=#C0C0C0>
\r
10187 <TD width=35% BGCOLOR=#C0C0C0>
\r
10188 <B>This register controls this reference clock</B>
\r
10193 <H2><a name="PCAP_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CTRL</a></H2>
\r
10194 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10195 <TR valign="top">
\r
10196 <TD width=15% BGCOLOR=#FFFF00>
\r
10197 <B>Register Name</B>
\r
10199 <TD width=15% BGCOLOR=#FFFF00>
\r
10202 <TD width=10% BGCOLOR=#FFFF00>
\r
10205 <TD width=10% BGCOLOR=#FFFF00>
\r
10208 <TD width=15% BGCOLOR=#FFFF00>
\r
10209 <B>Reset Value</B>
\r
10211 <TD width=35% BGCOLOR=#FFFF00>
\r
10212 <B>Description</B>
\r
10215 <TR valign="top">
\r
10216 <TD width=15% BGCOLOR=#FBF5EF>
\r
10219 <TD width=15% BGCOLOR=#FBF5EF>
\r
10220 <B>0XFF5E00A4</B>
\r
10222 <TD width=10% BGCOLOR=#FBF5EF>
\r
10225 <TD width=10% BGCOLOR=#FBF5EF>
\r
10228 <TD width=15% BGCOLOR=#FBF5EF>
\r
10229 <B>0x00000000</B>
\r
10231 <TD width=35% BGCOLOR=#FBF5EF>
\r
10237 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10238 <TR valign="top">
\r
10239 <TD width=15% BGCOLOR=#C0FFC0>
\r
10240 <B>Field Name</B>
\r
10242 <TD width=15% BGCOLOR=#C0FFC0>
\r
10245 <TD width=10% BGCOLOR=#C0FFC0>
\r
10248 <TD width=10% BGCOLOR=#C0FFC0>
\r
10251 <TD width=15% BGCOLOR=#C0FFC0>
\r
10252 <B>Shifted Value</B>
\r
10254 <TD width=35% BGCOLOR=#C0FFC0>
\r
10255 <B>Description</B>
\r
10258 <TR valign="top">
\r
10259 <TD width=15% BGCOLOR=#FBF5EF>
\r
10260 <B>PSU_CRL_APB_PCAP_CTRL_CLKACT</B>
\r
10262 <TD width=15% BGCOLOR=#FBF5EF>
\r
10265 <TD width=10% BGCOLOR=#FBF5EF>
\r
10268 <TD width=10% BGCOLOR=#FBF5EF>
\r
10271 <TD width=15% BGCOLOR=#FBF5EF>
\r
10274 <TD width=35% BGCOLOR=#FBF5EF>
\r
10275 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10278 <TR valign="top">
\r
10279 <TD width=15% BGCOLOR=#FBF5EF>
\r
10280 <B>PSU_CRL_APB_PCAP_CTRL_DIVISOR0</B>
\r
10282 <TD width=15% BGCOLOR=#FBF5EF>
\r
10285 <TD width=10% BGCOLOR=#FBF5EF>
\r
10288 <TD width=10% BGCOLOR=#FBF5EF>
\r
10291 <TD width=15% BGCOLOR=#FBF5EF>
\r
10294 <TD width=35% BGCOLOR=#FBF5EF>
\r
10295 <B>6 bit divider</B>
\r
10298 <TR valign="top">
\r
10299 <TD width=15% BGCOLOR=#FBF5EF>
\r
10300 <B>PSU_CRL_APB_PCAP_CTRL_SRCSEL</B>
\r
10302 <TD width=15% BGCOLOR=#FBF5EF>
\r
10305 <TD width=10% BGCOLOR=#FBF5EF>
\r
10308 <TD width=10% BGCOLOR=#FBF5EF>
\r
10311 <TD width=15% BGCOLOR=#FBF5EF>
\r
10314 <TD width=35% BGCOLOR=#FBF5EF>
\r
10315 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10318 <TR valign="top">
\r
10319 <TD width=15% BGCOLOR=#C0C0C0>
\r
10320 <B>PSU_CRL_APB_PCAP_CTRL@0XFF5E00A4</B>
\r
10322 <TD width=15% BGCOLOR=#C0C0C0>
\r
10325 <TD width=10% BGCOLOR=#C0C0C0>
\r
10328 <TD width=10% BGCOLOR=#C0C0C0>
\r
10331 <TD width=15% BGCOLOR=#C0C0C0>
\r
10334 <TD width=35% BGCOLOR=#C0C0C0>
\r
10335 <B>This register controls this reference clock</B>
\r
10340 <H2><a name="LPD_SWITCH_CTRL">Register (<A href=#mod___slcr> slcr </A>)LPD_SWITCH_CTRL</a></H2>
\r
10341 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10342 <TR valign="top">
\r
10343 <TD width=15% BGCOLOR=#FFFF00>
\r
10344 <B>Register Name</B>
\r
10346 <TD width=15% BGCOLOR=#FFFF00>
\r
10349 <TD width=10% BGCOLOR=#FFFF00>
\r
10352 <TD width=10% BGCOLOR=#FFFF00>
\r
10355 <TD width=15% BGCOLOR=#FFFF00>
\r
10356 <B>Reset Value</B>
\r
10358 <TD width=35% BGCOLOR=#FFFF00>
\r
10359 <B>Description</B>
\r
10362 <TR valign="top">
\r
10363 <TD width=15% BGCOLOR=#FBF5EF>
\r
10364 <B>LPD_SWITCH_CTRL</B>
\r
10366 <TD width=15% BGCOLOR=#FBF5EF>
\r
10367 <B>0XFF5E00A8</B>
\r
10369 <TD width=10% BGCOLOR=#FBF5EF>
\r
10372 <TD width=10% BGCOLOR=#FBF5EF>
\r
10375 <TD width=15% BGCOLOR=#FBF5EF>
\r
10376 <B>0x00000000</B>
\r
10378 <TD width=35% BGCOLOR=#FBF5EF>
\r
10384 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10385 <TR valign="top">
\r
10386 <TD width=15% BGCOLOR=#C0FFC0>
\r
10387 <B>Field Name</B>
\r
10389 <TD width=15% BGCOLOR=#C0FFC0>
\r
10392 <TD width=10% BGCOLOR=#C0FFC0>
\r
10395 <TD width=10% BGCOLOR=#C0FFC0>
\r
10398 <TD width=15% BGCOLOR=#C0FFC0>
\r
10399 <B>Shifted Value</B>
\r
10401 <TD width=35% BGCOLOR=#C0FFC0>
\r
10402 <B>Description</B>
\r
10405 <TR valign="top">
\r
10406 <TD width=15% BGCOLOR=#FBF5EF>
\r
10407 <B>PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT</B>
\r
10409 <TD width=15% BGCOLOR=#FBF5EF>
\r
10412 <TD width=10% BGCOLOR=#FBF5EF>
\r
10415 <TD width=10% BGCOLOR=#FBF5EF>
\r
10418 <TD width=15% BGCOLOR=#FBF5EF>
\r
10421 <TD width=35% BGCOLOR=#FBF5EF>
\r
10422 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10425 <TR valign="top">
\r
10426 <TD width=15% BGCOLOR=#FBF5EF>
\r
10427 <B>PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0</B>
\r
10429 <TD width=15% BGCOLOR=#FBF5EF>
\r
10432 <TD width=10% BGCOLOR=#FBF5EF>
\r
10435 <TD width=10% BGCOLOR=#FBF5EF>
\r
10438 <TD width=15% BGCOLOR=#FBF5EF>
\r
10441 <TD width=35% BGCOLOR=#FBF5EF>
\r
10442 <B>6 bit divider</B>
\r
10445 <TR valign="top">
\r
10446 <TD width=15% BGCOLOR=#FBF5EF>
\r
10447 <B>PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL</B>
\r
10449 <TD width=15% BGCOLOR=#FBF5EF>
\r
10452 <TD width=10% BGCOLOR=#FBF5EF>
\r
10455 <TD width=10% BGCOLOR=#FBF5EF>
\r
10458 <TD width=15% BGCOLOR=#FBF5EF>
\r
10461 <TD width=35% BGCOLOR=#FBF5EF>
\r
10462 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10465 <TR valign="top">
\r
10466 <TD width=15% BGCOLOR=#C0C0C0>
\r
10467 <B>PSU_CRL_APB_LPD_SWITCH_CTRL@0XFF5E00A8</B>
\r
10469 <TD width=15% BGCOLOR=#C0C0C0>
\r
10472 <TD width=10% BGCOLOR=#C0C0C0>
\r
10475 <TD width=10% BGCOLOR=#C0C0C0>
\r
10478 <TD width=15% BGCOLOR=#C0C0C0>
\r
10481 <TD width=35% BGCOLOR=#C0C0C0>
\r
10482 <B>This register controls this reference clock</B>
\r
10487 <H2><a name="LPD_LSBUS_CTRL">Register (<A href=#mod___slcr> slcr </A>)LPD_LSBUS_CTRL</a></H2>
\r
10488 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10489 <TR valign="top">
\r
10490 <TD width=15% BGCOLOR=#FFFF00>
\r
10491 <B>Register Name</B>
\r
10493 <TD width=15% BGCOLOR=#FFFF00>
\r
10496 <TD width=10% BGCOLOR=#FFFF00>
\r
10499 <TD width=10% BGCOLOR=#FFFF00>
\r
10502 <TD width=15% BGCOLOR=#FFFF00>
\r
10503 <B>Reset Value</B>
\r
10505 <TD width=35% BGCOLOR=#FFFF00>
\r
10506 <B>Description</B>
\r
10509 <TR valign="top">
\r
10510 <TD width=15% BGCOLOR=#FBF5EF>
\r
10511 <B>LPD_LSBUS_CTRL</B>
\r
10513 <TD width=15% BGCOLOR=#FBF5EF>
\r
10514 <B>0XFF5E00AC</B>
\r
10516 <TD width=10% BGCOLOR=#FBF5EF>
\r
10519 <TD width=10% BGCOLOR=#FBF5EF>
\r
10522 <TD width=15% BGCOLOR=#FBF5EF>
\r
10523 <B>0x00000000</B>
\r
10525 <TD width=35% BGCOLOR=#FBF5EF>
\r
10531 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10532 <TR valign="top">
\r
10533 <TD width=15% BGCOLOR=#C0FFC0>
\r
10534 <B>Field Name</B>
\r
10536 <TD width=15% BGCOLOR=#C0FFC0>
\r
10539 <TD width=10% BGCOLOR=#C0FFC0>
\r
10542 <TD width=10% BGCOLOR=#C0FFC0>
\r
10545 <TD width=15% BGCOLOR=#C0FFC0>
\r
10546 <B>Shifted Value</B>
\r
10548 <TD width=35% BGCOLOR=#C0FFC0>
\r
10549 <B>Description</B>
\r
10552 <TR valign="top">
\r
10553 <TD width=15% BGCOLOR=#FBF5EF>
\r
10554 <B>PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT</B>
\r
10556 <TD width=15% BGCOLOR=#FBF5EF>
\r
10559 <TD width=10% BGCOLOR=#FBF5EF>
\r
10562 <TD width=10% BGCOLOR=#FBF5EF>
\r
10565 <TD width=15% BGCOLOR=#FBF5EF>
\r
10568 <TD width=35% BGCOLOR=#FBF5EF>
\r
10569 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10572 <TR valign="top">
\r
10573 <TD width=15% BGCOLOR=#FBF5EF>
\r
10574 <B>PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0</B>
\r
10576 <TD width=15% BGCOLOR=#FBF5EF>
\r
10579 <TD width=10% BGCOLOR=#FBF5EF>
\r
10582 <TD width=10% BGCOLOR=#FBF5EF>
\r
10585 <TD width=15% BGCOLOR=#FBF5EF>
\r
10588 <TD width=35% BGCOLOR=#FBF5EF>
\r
10589 <B>6 bit divider</B>
\r
10592 <TR valign="top">
\r
10593 <TD width=15% BGCOLOR=#FBF5EF>
\r
10594 <B>PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL</B>
\r
10596 <TD width=15% BGCOLOR=#FBF5EF>
\r
10599 <TD width=10% BGCOLOR=#FBF5EF>
\r
10602 <TD width=10% BGCOLOR=#FBF5EF>
\r
10605 <TD width=15% BGCOLOR=#FBF5EF>
\r
10608 <TD width=35% BGCOLOR=#FBF5EF>
\r
10609 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10612 <TR valign="top">
\r
10613 <TD width=15% BGCOLOR=#C0C0C0>
\r
10614 <B>PSU_CRL_APB_LPD_LSBUS_CTRL@0XFF5E00AC</B>
\r
10616 <TD width=15% BGCOLOR=#C0C0C0>
\r
10619 <TD width=10% BGCOLOR=#C0C0C0>
\r
10622 <TD width=10% BGCOLOR=#C0C0C0>
\r
10625 <TD width=15% BGCOLOR=#C0C0C0>
\r
10628 <TD width=35% BGCOLOR=#C0C0C0>
\r
10629 <B>This register controls this reference clock</B>
\r
10634 <H2><a name="DBG_LPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_LPD_CTRL</a></H2>
\r
10635 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10636 <TR valign="top">
\r
10637 <TD width=15% BGCOLOR=#FFFF00>
\r
10638 <B>Register Name</B>
\r
10640 <TD width=15% BGCOLOR=#FFFF00>
\r
10643 <TD width=10% BGCOLOR=#FFFF00>
\r
10646 <TD width=10% BGCOLOR=#FFFF00>
\r
10649 <TD width=15% BGCOLOR=#FFFF00>
\r
10650 <B>Reset Value</B>
\r
10652 <TD width=35% BGCOLOR=#FFFF00>
\r
10653 <B>Description</B>
\r
10656 <TR valign="top">
\r
10657 <TD width=15% BGCOLOR=#FBF5EF>
\r
10658 <B>DBG_LPD_CTRL</B>
\r
10660 <TD width=15% BGCOLOR=#FBF5EF>
\r
10661 <B>0XFF5E00B0</B>
\r
10663 <TD width=10% BGCOLOR=#FBF5EF>
\r
10666 <TD width=10% BGCOLOR=#FBF5EF>
\r
10669 <TD width=15% BGCOLOR=#FBF5EF>
\r
10670 <B>0x00000000</B>
\r
10672 <TD width=35% BGCOLOR=#FBF5EF>
\r
10678 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10679 <TR valign="top">
\r
10680 <TD width=15% BGCOLOR=#C0FFC0>
\r
10681 <B>Field Name</B>
\r
10683 <TD width=15% BGCOLOR=#C0FFC0>
\r
10686 <TD width=10% BGCOLOR=#C0FFC0>
\r
10689 <TD width=10% BGCOLOR=#C0FFC0>
\r
10692 <TD width=15% BGCOLOR=#C0FFC0>
\r
10693 <B>Shifted Value</B>
\r
10695 <TD width=35% BGCOLOR=#C0FFC0>
\r
10696 <B>Description</B>
\r
10699 <TR valign="top">
\r
10700 <TD width=15% BGCOLOR=#FBF5EF>
\r
10701 <B>PSU_CRL_APB_DBG_LPD_CTRL_CLKACT</B>
\r
10703 <TD width=15% BGCOLOR=#FBF5EF>
\r
10706 <TD width=10% BGCOLOR=#FBF5EF>
\r
10709 <TD width=10% BGCOLOR=#FBF5EF>
\r
10712 <TD width=15% BGCOLOR=#FBF5EF>
\r
10715 <TD width=35% BGCOLOR=#FBF5EF>
\r
10716 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10719 <TR valign="top">
\r
10720 <TD width=15% BGCOLOR=#FBF5EF>
\r
10721 <B>PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0</B>
\r
10723 <TD width=15% BGCOLOR=#FBF5EF>
\r
10726 <TD width=10% BGCOLOR=#FBF5EF>
\r
10729 <TD width=10% BGCOLOR=#FBF5EF>
\r
10732 <TD width=15% BGCOLOR=#FBF5EF>
\r
10735 <TD width=35% BGCOLOR=#FBF5EF>
\r
10736 <B>6 bit divider</B>
\r
10739 <TR valign="top">
\r
10740 <TD width=15% BGCOLOR=#FBF5EF>
\r
10741 <B>PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL</B>
\r
10743 <TD width=15% BGCOLOR=#FBF5EF>
\r
10746 <TD width=10% BGCOLOR=#FBF5EF>
\r
10749 <TD width=10% BGCOLOR=#FBF5EF>
\r
10752 <TD width=15% BGCOLOR=#FBF5EF>
\r
10755 <TD width=35% BGCOLOR=#FBF5EF>
\r
10756 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10759 <TR valign="top">
\r
10760 <TD width=15% BGCOLOR=#C0C0C0>
\r
10761 <B>PSU_CRL_APB_DBG_LPD_CTRL@0XFF5E00B0</B>
\r
10763 <TD width=15% BGCOLOR=#C0C0C0>
\r
10766 <TD width=10% BGCOLOR=#C0C0C0>
\r
10769 <TD width=10% BGCOLOR=#C0C0C0>
\r
10772 <TD width=15% BGCOLOR=#C0C0C0>
\r
10775 <TD width=35% BGCOLOR=#C0C0C0>
\r
10776 <B>This register controls this reference clock</B>
\r
10781 <H2><a name="NAND_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)NAND_REF_CTRL</a></H2>
\r
10782 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10783 <TR valign="top">
\r
10784 <TD width=15% BGCOLOR=#FFFF00>
\r
10785 <B>Register Name</B>
\r
10787 <TD width=15% BGCOLOR=#FFFF00>
\r
10790 <TD width=10% BGCOLOR=#FFFF00>
\r
10793 <TD width=10% BGCOLOR=#FFFF00>
\r
10796 <TD width=15% BGCOLOR=#FFFF00>
\r
10797 <B>Reset Value</B>
\r
10799 <TD width=35% BGCOLOR=#FFFF00>
\r
10800 <B>Description</B>
\r
10803 <TR valign="top">
\r
10804 <TD width=15% BGCOLOR=#FBF5EF>
\r
10805 <B>NAND_REF_CTRL</B>
\r
10807 <TD width=15% BGCOLOR=#FBF5EF>
\r
10808 <B>0XFF5E00B4</B>
\r
10810 <TD width=10% BGCOLOR=#FBF5EF>
\r
10813 <TD width=10% BGCOLOR=#FBF5EF>
\r
10816 <TD width=15% BGCOLOR=#FBF5EF>
\r
10817 <B>0x00000000</B>
\r
10819 <TD width=35% BGCOLOR=#FBF5EF>
\r
10825 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10826 <TR valign="top">
\r
10827 <TD width=15% BGCOLOR=#C0FFC0>
\r
10828 <B>Field Name</B>
\r
10830 <TD width=15% BGCOLOR=#C0FFC0>
\r
10833 <TD width=10% BGCOLOR=#C0FFC0>
\r
10836 <TD width=10% BGCOLOR=#C0FFC0>
\r
10839 <TD width=15% BGCOLOR=#C0FFC0>
\r
10840 <B>Shifted Value</B>
\r
10842 <TD width=35% BGCOLOR=#C0FFC0>
\r
10843 <B>Description</B>
\r
10846 <TR valign="top">
\r
10847 <TD width=15% BGCOLOR=#FBF5EF>
\r
10848 <B>PSU_CRL_APB_NAND_REF_CTRL_CLKACT</B>
\r
10850 <TD width=15% BGCOLOR=#FBF5EF>
\r
10853 <TD width=10% BGCOLOR=#FBF5EF>
\r
10856 <TD width=10% BGCOLOR=#FBF5EF>
\r
10859 <TD width=15% BGCOLOR=#FBF5EF>
\r
10862 <TD width=35% BGCOLOR=#FBF5EF>
\r
10863 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
10866 <TR valign="top">
\r
10867 <TD width=15% BGCOLOR=#FBF5EF>
\r
10868 <B>PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1</B>
\r
10870 <TD width=15% BGCOLOR=#FBF5EF>
\r
10873 <TD width=10% BGCOLOR=#FBF5EF>
\r
10876 <TD width=10% BGCOLOR=#FBF5EF>
\r
10879 <TD width=15% BGCOLOR=#FBF5EF>
\r
10882 <TD width=35% BGCOLOR=#FBF5EF>
\r
10883 <B>6 bit divider</B>
\r
10886 <TR valign="top">
\r
10887 <TD width=15% BGCOLOR=#FBF5EF>
\r
10888 <B>PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0</B>
\r
10890 <TD width=15% BGCOLOR=#FBF5EF>
\r
10893 <TD width=10% BGCOLOR=#FBF5EF>
\r
10896 <TD width=10% BGCOLOR=#FBF5EF>
\r
10899 <TD width=15% BGCOLOR=#FBF5EF>
\r
10902 <TD width=35% BGCOLOR=#FBF5EF>
\r
10903 <B>6 bit divider</B>
\r
10906 <TR valign="top">
\r
10907 <TD width=15% BGCOLOR=#FBF5EF>
\r
10908 <B>PSU_CRL_APB_NAND_REF_CTRL_SRCSEL</B>
\r
10910 <TD width=15% BGCOLOR=#FBF5EF>
\r
10913 <TD width=10% BGCOLOR=#FBF5EF>
\r
10916 <TD width=10% BGCOLOR=#FBF5EF>
\r
10919 <TD width=15% BGCOLOR=#FBF5EF>
\r
10922 <TD width=35% BGCOLOR=#FBF5EF>
\r
10923 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
10926 <TR valign="top">
\r
10927 <TD width=15% BGCOLOR=#C0C0C0>
\r
10928 <B>PSU_CRL_APB_NAND_REF_CTRL@0XFF5E00B4</B>
\r
10930 <TD width=15% BGCOLOR=#C0C0C0>
\r
10933 <TD width=10% BGCOLOR=#C0C0C0>
\r
10936 <TD width=10% BGCOLOR=#C0C0C0>
\r
10939 <TD width=15% BGCOLOR=#C0C0C0>
\r
10942 <TD width=35% BGCOLOR=#C0C0C0>
\r
10943 <B>This register controls this reference clock</B>
\r
10948 <H2><a name="ADMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)ADMA_REF_CTRL</a></H2>
\r
10949 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10950 <TR valign="top">
\r
10951 <TD width=15% BGCOLOR=#FFFF00>
\r
10952 <B>Register Name</B>
\r
10954 <TD width=15% BGCOLOR=#FFFF00>
\r
10957 <TD width=10% BGCOLOR=#FFFF00>
\r
10960 <TD width=10% BGCOLOR=#FFFF00>
\r
10963 <TD width=15% BGCOLOR=#FFFF00>
\r
10964 <B>Reset Value</B>
\r
10966 <TD width=35% BGCOLOR=#FFFF00>
\r
10967 <B>Description</B>
\r
10970 <TR valign="top">
\r
10971 <TD width=15% BGCOLOR=#FBF5EF>
\r
10972 <B>ADMA_REF_CTRL</B>
\r
10974 <TD width=15% BGCOLOR=#FBF5EF>
\r
10975 <B>0XFF5E00B8</B>
\r
10977 <TD width=10% BGCOLOR=#FBF5EF>
\r
10980 <TD width=10% BGCOLOR=#FBF5EF>
\r
10983 <TD width=15% BGCOLOR=#FBF5EF>
\r
10984 <B>0x00000000</B>
\r
10986 <TD width=35% BGCOLOR=#FBF5EF>
\r
10992 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
10993 <TR valign="top">
\r
10994 <TD width=15% BGCOLOR=#C0FFC0>
\r
10995 <B>Field Name</B>
\r
10997 <TD width=15% BGCOLOR=#C0FFC0>
\r
11000 <TD width=10% BGCOLOR=#C0FFC0>
\r
11003 <TD width=10% BGCOLOR=#C0FFC0>
\r
11006 <TD width=15% BGCOLOR=#C0FFC0>
\r
11007 <B>Shifted Value</B>
\r
11009 <TD width=35% BGCOLOR=#C0FFC0>
\r
11010 <B>Description</B>
\r
11013 <TR valign="top">
\r
11014 <TD width=15% BGCOLOR=#FBF5EF>
\r
11015 <B>PSU_CRL_APB_ADMA_REF_CTRL_CLKACT</B>
\r
11017 <TD width=15% BGCOLOR=#FBF5EF>
\r
11020 <TD width=10% BGCOLOR=#FBF5EF>
\r
11023 <TD width=10% BGCOLOR=#FBF5EF>
\r
11026 <TD width=15% BGCOLOR=#FBF5EF>
\r
11029 <TD width=35% BGCOLOR=#FBF5EF>
\r
11030 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11033 <TR valign="top">
\r
11034 <TD width=15% BGCOLOR=#FBF5EF>
\r
11035 <B>PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0</B>
\r
11037 <TD width=15% BGCOLOR=#FBF5EF>
\r
11040 <TD width=10% BGCOLOR=#FBF5EF>
\r
11043 <TD width=10% BGCOLOR=#FBF5EF>
\r
11046 <TD width=15% BGCOLOR=#FBF5EF>
\r
11049 <TD width=35% BGCOLOR=#FBF5EF>
\r
11050 <B>6 bit divider</B>
\r
11053 <TR valign="top">
\r
11054 <TD width=15% BGCOLOR=#FBF5EF>
\r
11055 <B>PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL</B>
\r
11057 <TD width=15% BGCOLOR=#FBF5EF>
\r
11060 <TD width=10% BGCOLOR=#FBF5EF>
\r
11063 <TD width=10% BGCOLOR=#FBF5EF>
\r
11066 <TD width=15% BGCOLOR=#FBF5EF>
\r
11069 <TD width=35% BGCOLOR=#FBF5EF>
\r
11070 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11073 <TR valign="top">
\r
11074 <TD width=15% BGCOLOR=#C0C0C0>
\r
11075 <B>PSU_CRL_APB_ADMA_REF_CTRL@0XFF5E00B8</B>
\r
11077 <TD width=15% BGCOLOR=#C0C0C0>
\r
11080 <TD width=10% BGCOLOR=#C0C0C0>
\r
11083 <TD width=10% BGCOLOR=#C0C0C0>
\r
11086 <TD width=15% BGCOLOR=#C0C0C0>
\r
11089 <TD width=35% BGCOLOR=#C0C0C0>
\r
11090 <B>This register controls this reference clock</B>
\r
11095 <H2><a name="AMS_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)AMS_REF_CTRL</a></H2>
\r
11096 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11097 <TR valign="top">
\r
11098 <TD width=15% BGCOLOR=#FFFF00>
\r
11099 <B>Register Name</B>
\r
11101 <TD width=15% BGCOLOR=#FFFF00>
\r
11104 <TD width=10% BGCOLOR=#FFFF00>
\r
11107 <TD width=10% BGCOLOR=#FFFF00>
\r
11110 <TD width=15% BGCOLOR=#FFFF00>
\r
11111 <B>Reset Value</B>
\r
11113 <TD width=35% BGCOLOR=#FFFF00>
\r
11114 <B>Description</B>
\r
11117 <TR valign="top">
\r
11118 <TD width=15% BGCOLOR=#FBF5EF>
\r
11119 <B>AMS_REF_CTRL</B>
\r
11121 <TD width=15% BGCOLOR=#FBF5EF>
\r
11122 <B>0XFF5E0108</B>
\r
11124 <TD width=10% BGCOLOR=#FBF5EF>
\r
11127 <TD width=10% BGCOLOR=#FBF5EF>
\r
11130 <TD width=15% BGCOLOR=#FBF5EF>
\r
11131 <B>0x00000000</B>
\r
11133 <TD width=35% BGCOLOR=#FBF5EF>
\r
11139 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11140 <TR valign="top">
\r
11141 <TD width=15% BGCOLOR=#C0FFC0>
\r
11142 <B>Field Name</B>
\r
11144 <TD width=15% BGCOLOR=#C0FFC0>
\r
11147 <TD width=10% BGCOLOR=#C0FFC0>
\r
11150 <TD width=10% BGCOLOR=#C0FFC0>
\r
11153 <TD width=15% BGCOLOR=#C0FFC0>
\r
11154 <B>Shifted Value</B>
\r
11156 <TD width=35% BGCOLOR=#C0FFC0>
\r
11157 <B>Description</B>
\r
11160 <TR valign="top">
\r
11161 <TD width=15% BGCOLOR=#FBF5EF>
\r
11162 <B>PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1</B>
\r
11164 <TD width=15% BGCOLOR=#FBF5EF>
\r
11167 <TD width=10% BGCOLOR=#FBF5EF>
\r
11170 <TD width=10% BGCOLOR=#FBF5EF>
\r
11173 <TD width=15% BGCOLOR=#FBF5EF>
\r
11176 <TD width=35% BGCOLOR=#FBF5EF>
\r
11177 <B>6 bit divider</B>
\r
11180 <TR valign="top">
\r
11181 <TD width=15% BGCOLOR=#FBF5EF>
\r
11182 <B>PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0</B>
\r
11184 <TD width=15% BGCOLOR=#FBF5EF>
\r
11187 <TD width=10% BGCOLOR=#FBF5EF>
\r
11190 <TD width=10% BGCOLOR=#FBF5EF>
\r
11193 <TD width=15% BGCOLOR=#FBF5EF>
\r
11196 <TD width=35% BGCOLOR=#FBF5EF>
\r
11197 <B>6 bit divider</B>
\r
11200 <TR valign="top">
\r
11201 <TD width=15% BGCOLOR=#FBF5EF>
\r
11202 <B>PSU_CRL_APB_AMS_REF_CTRL_SRCSEL</B>
\r
11204 <TD width=15% BGCOLOR=#FBF5EF>
\r
11207 <TD width=10% BGCOLOR=#FBF5EF>
\r
11210 <TD width=10% BGCOLOR=#FBF5EF>
\r
11213 <TD width=15% BGCOLOR=#FBF5EF>
\r
11216 <TD width=35% BGCOLOR=#FBF5EF>
\r
11217 <B>000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11220 <TR valign="top">
\r
11221 <TD width=15% BGCOLOR=#FBF5EF>
\r
11222 <B>PSU_CRL_APB_AMS_REF_CTRL_CLKACT</B>
\r
11224 <TD width=15% BGCOLOR=#FBF5EF>
\r
11227 <TD width=10% BGCOLOR=#FBF5EF>
\r
11230 <TD width=10% BGCOLOR=#FBF5EF>
\r
11233 <TD width=15% BGCOLOR=#FBF5EF>
\r
11236 <TD width=35% BGCOLOR=#FBF5EF>
\r
11237 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11240 <TR valign="top">
\r
11241 <TD width=15% BGCOLOR=#C0C0C0>
\r
11242 <B>PSU_CRL_APB_AMS_REF_CTRL@0XFF5E0108</B>
\r
11244 <TD width=15% BGCOLOR=#C0C0C0>
\r
11247 <TD width=10% BGCOLOR=#C0C0C0>
\r
11250 <TD width=10% BGCOLOR=#C0C0C0>
\r
11253 <TD width=15% BGCOLOR=#C0C0C0>
\r
11256 <TD width=35% BGCOLOR=#C0C0C0>
\r
11257 <B>This register controls this reference clock</B>
\r
11262 <H2><a name="DLL_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DLL_REF_CTRL</a></H2>
\r
11263 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11264 <TR valign="top">
\r
11265 <TD width=15% BGCOLOR=#FFFF00>
\r
11266 <B>Register Name</B>
\r
11268 <TD width=15% BGCOLOR=#FFFF00>
\r
11271 <TD width=10% BGCOLOR=#FFFF00>
\r
11274 <TD width=10% BGCOLOR=#FFFF00>
\r
11277 <TD width=15% BGCOLOR=#FFFF00>
\r
11278 <B>Reset Value</B>
\r
11280 <TD width=35% BGCOLOR=#FFFF00>
\r
11281 <B>Description</B>
\r
11284 <TR valign="top">
\r
11285 <TD width=15% BGCOLOR=#FBF5EF>
\r
11286 <B>DLL_REF_CTRL</B>
\r
11288 <TD width=15% BGCOLOR=#FBF5EF>
\r
11289 <B>0XFF5E0104</B>
\r
11291 <TD width=10% BGCOLOR=#FBF5EF>
\r
11294 <TD width=10% BGCOLOR=#FBF5EF>
\r
11297 <TD width=15% BGCOLOR=#FBF5EF>
\r
11298 <B>0x00000000</B>
\r
11300 <TD width=35% BGCOLOR=#FBF5EF>
\r
11306 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11307 <TR valign="top">
\r
11308 <TD width=15% BGCOLOR=#C0FFC0>
\r
11309 <B>Field Name</B>
\r
11311 <TD width=15% BGCOLOR=#C0FFC0>
\r
11314 <TD width=10% BGCOLOR=#C0FFC0>
\r
11317 <TD width=10% BGCOLOR=#C0FFC0>
\r
11320 <TD width=15% BGCOLOR=#C0FFC0>
\r
11321 <B>Shifted Value</B>
\r
11323 <TD width=35% BGCOLOR=#C0FFC0>
\r
11324 <B>Description</B>
\r
11327 <TR valign="top">
\r
11328 <TD width=15% BGCOLOR=#FBF5EF>
\r
11329 <B>PSU_CRL_APB_DLL_REF_CTRL_SRCSEL</B>
\r
11331 <TD width=15% BGCOLOR=#FBF5EF>
\r
11334 <TD width=10% BGCOLOR=#FBF5EF>
\r
11337 <TD width=10% BGCOLOR=#FBF5EF>
\r
11340 <TD width=15% BGCOLOR=#FBF5EF>
\r
11343 <TD width=35% BGCOLOR=#FBF5EF>
\r
11344 <B>000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11347 <TR valign="top">
\r
11348 <TD width=15% BGCOLOR=#C0C0C0>
\r
11349 <B>PSU_CRL_APB_DLL_REF_CTRL@0XFF5E0104</B>
\r
11351 <TD width=15% BGCOLOR=#C0C0C0>
\r
11354 <TD width=10% BGCOLOR=#C0C0C0>
\r
11357 <TD width=10% BGCOLOR=#C0C0C0>
\r
11360 <TD width=15% BGCOLOR=#C0C0C0>
\r
11363 <TD width=35% BGCOLOR=#C0C0C0>
\r
11364 <B>This register controls this reference clock</B>
\r
11369 <H2><a name="TIMESTAMP_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)TIMESTAMP_REF_CTRL</a></H2>
\r
11370 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11371 <TR valign="top">
\r
11372 <TD width=15% BGCOLOR=#FFFF00>
\r
11373 <B>Register Name</B>
\r
11375 <TD width=15% BGCOLOR=#FFFF00>
\r
11378 <TD width=10% BGCOLOR=#FFFF00>
\r
11381 <TD width=10% BGCOLOR=#FFFF00>
\r
11384 <TD width=15% BGCOLOR=#FFFF00>
\r
11385 <B>Reset Value</B>
\r
11387 <TD width=35% BGCOLOR=#FFFF00>
\r
11388 <B>Description</B>
\r
11391 <TR valign="top">
\r
11392 <TD width=15% BGCOLOR=#FBF5EF>
\r
11393 <B>TIMESTAMP_REF_CTRL</B>
\r
11395 <TD width=15% BGCOLOR=#FBF5EF>
\r
11396 <B>0XFF5E0128</B>
\r
11398 <TD width=10% BGCOLOR=#FBF5EF>
\r
11401 <TD width=10% BGCOLOR=#FBF5EF>
\r
11404 <TD width=15% BGCOLOR=#FBF5EF>
\r
11405 <B>0x00000000</B>
\r
11407 <TD width=35% BGCOLOR=#FBF5EF>
\r
11413 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11414 <TR valign="top">
\r
11415 <TD width=15% BGCOLOR=#C0FFC0>
\r
11416 <B>Field Name</B>
\r
11418 <TD width=15% BGCOLOR=#C0FFC0>
\r
11421 <TD width=10% BGCOLOR=#C0FFC0>
\r
11424 <TD width=10% BGCOLOR=#C0FFC0>
\r
11427 <TD width=15% BGCOLOR=#C0FFC0>
\r
11428 <B>Shifted Value</B>
\r
11430 <TD width=35% BGCOLOR=#C0FFC0>
\r
11431 <B>Description</B>
\r
11434 <TR valign="top">
\r
11435 <TD width=15% BGCOLOR=#FBF5EF>
\r
11436 <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0</B>
\r
11438 <TD width=15% BGCOLOR=#FBF5EF>
\r
11441 <TD width=10% BGCOLOR=#FBF5EF>
\r
11444 <TD width=10% BGCOLOR=#FBF5EF>
\r
11447 <TD width=15% BGCOLOR=#FBF5EF>
\r
11450 <TD width=35% BGCOLOR=#FBF5EF>
\r
11451 <B>6 bit divider</B>
\r
11454 <TR valign="top">
\r
11455 <TD width=15% BGCOLOR=#FBF5EF>
\r
11456 <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL</B>
\r
11458 <TD width=15% BGCOLOR=#FBF5EF>
\r
11461 <TD width=10% BGCOLOR=#FBF5EF>
\r
11464 <TD width=10% BGCOLOR=#FBF5EF>
\r
11467 <TD width=15% BGCOLOR=#FBF5EF>
\r
11470 <TD width=35% BGCOLOR=#FBF5EF>
\r
11471 <B>1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11474 <TR valign="top">
\r
11475 <TD width=15% BGCOLOR=#FBF5EF>
\r
11476 <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT</B>
\r
11478 <TD width=15% BGCOLOR=#FBF5EF>
\r
11481 <TD width=10% BGCOLOR=#FBF5EF>
\r
11484 <TD width=10% BGCOLOR=#FBF5EF>
\r
11487 <TD width=15% BGCOLOR=#FBF5EF>
\r
11490 <TD width=35% BGCOLOR=#FBF5EF>
\r
11491 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11494 <TR valign="top">
\r
11495 <TD width=15% BGCOLOR=#C0C0C0>
\r
11496 <B>PSU_CRL_APB_TIMESTAMP_REF_CTRL@0XFF5E0128</B>
\r
11498 <TD width=15% BGCOLOR=#C0C0C0>
\r
11501 <TD width=10% BGCOLOR=#C0C0C0>
\r
11504 <TD width=10% BGCOLOR=#C0C0C0>
\r
11507 <TD width=15% BGCOLOR=#C0C0C0>
\r
11510 <TD width=35% BGCOLOR=#C0C0C0>
\r
11511 <B>This register controls this reference clock</B>
\r
11516 <H2><a name="PCIE_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCIE_REF_CTRL</a></H2>
\r
11517 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11518 <TR valign="top">
\r
11519 <TD width=15% BGCOLOR=#FFFF00>
\r
11520 <B>Register Name</B>
\r
11522 <TD width=15% BGCOLOR=#FFFF00>
\r
11525 <TD width=10% BGCOLOR=#FFFF00>
\r
11528 <TD width=10% BGCOLOR=#FFFF00>
\r
11531 <TD width=15% BGCOLOR=#FFFF00>
\r
11532 <B>Reset Value</B>
\r
11534 <TD width=35% BGCOLOR=#FFFF00>
\r
11535 <B>Description</B>
\r
11538 <TR valign="top">
\r
11539 <TD width=15% BGCOLOR=#FBF5EF>
\r
11540 <B>PCIE_REF_CTRL</B>
\r
11542 <TD width=15% BGCOLOR=#FBF5EF>
\r
11543 <B>0XFD1A00B4</B>
\r
11545 <TD width=10% BGCOLOR=#FBF5EF>
\r
11548 <TD width=10% BGCOLOR=#FBF5EF>
\r
11551 <TD width=15% BGCOLOR=#FBF5EF>
\r
11552 <B>0x00000000</B>
\r
11554 <TD width=35% BGCOLOR=#FBF5EF>
\r
11560 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11561 <TR valign="top">
\r
11562 <TD width=15% BGCOLOR=#C0FFC0>
\r
11563 <B>Field Name</B>
\r
11565 <TD width=15% BGCOLOR=#C0FFC0>
\r
11568 <TD width=10% BGCOLOR=#C0FFC0>
\r
11571 <TD width=10% BGCOLOR=#C0FFC0>
\r
11574 <TD width=15% BGCOLOR=#C0FFC0>
\r
11575 <B>Shifted Value</B>
\r
11577 <TD width=35% BGCOLOR=#C0FFC0>
\r
11578 <B>Description</B>
\r
11581 <TR valign="top">
\r
11582 <TD width=15% BGCOLOR=#FBF5EF>
\r
11583 <B>PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL</B>
\r
11585 <TD width=15% BGCOLOR=#FBF5EF>
\r
11588 <TD width=10% BGCOLOR=#FBF5EF>
\r
11591 <TD width=10% BGCOLOR=#FBF5EF>
\r
11594 <TD width=15% BGCOLOR=#FBF5EF>
\r
11597 <TD width=35% BGCOLOR=#FBF5EF>
\r
11598 <B>000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11601 <TR valign="top">
\r
11602 <TD width=15% BGCOLOR=#FBF5EF>
\r
11603 <B>PSU_CRF_APB_PCIE_REF_CTRL_CLKACT</B>
\r
11605 <TD width=15% BGCOLOR=#FBF5EF>
\r
11608 <TD width=10% BGCOLOR=#FBF5EF>
\r
11611 <TD width=10% BGCOLOR=#FBF5EF>
\r
11614 <TD width=15% BGCOLOR=#FBF5EF>
\r
11617 <TD width=35% BGCOLOR=#FBF5EF>
\r
11618 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11621 <TR valign="top">
\r
11622 <TD width=15% BGCOLOR=#FBF5EF>
\r
11623 <B>PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0</B>
\r
11625 <TD width=15% BGCOLOR=#FBF5EF>
\r
11628 <TD width=10% BGCOLOR=#FBF5EF>
\r
11631 <TD width=10% BGCOLOR=#FBF5EF>
\r
11634 <TD width=15% BGCOLOR=#FBF5EF>
\r
11637 <TD width=35% BGCOLOR=#FBF5EF>
\r
11638 <B>6 bit divider</B>
\r
11641 <TR valign="top">
\r
11642 <TD width=15% BGCOLOR=#C0C0C0>
\r
11643 <B>PSU_CRF_APB_PCIE_REF_CTRL@0XFD1A00B4</B>
\r
11645 <TD width=15% BGCOLOR=#C0C0C0>
\r
11648 <TD width=10% BGCOLOR=#C0C0C0>
\r
11651 <TD width=10% BGCOLOR=#C0C0C0>
\r
11654 <TD width=15% BGCOLOR=#C0C0C0>
\r
11657 <TD width=35% BGCOLOR=#C0C0C0>
\r
11658 <B>This register controls this reference clock</B>
\r
11663 <H2><a name="DP_VIDEO_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_VIDEO_REF_CTRL</a></H2>
\r
11664 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11665 <TR valign="top">
\r
11666 <TD width=15% BGCOLOR=#FFFF00>
\r
11667 <B>Register Name</B>
\r
11669 <TD width=15% BGCOLOR=#FFFF00>
\r
11672 <TD width=10% BGCOLOR=#FFFF00>
\r
11675 <TD width=10% BGCOLOR=#FFFF00>
\r
11678 <TD width=15% BGCOLOR=#FFFF00>
\r
11679 <B>Reset Value</B>
\r
11681 <TD width=35% BGCOLOR=#FFFF00>
\r
11682 <B>Description</B>
\r
11685 <TR valign="top">
\r
11686 <TD width=15% BGCOLOR=#FBF5EF>
\r
11687 <B>DP_VIDEO_REF_CTRL</B>
\r
11689 <TD width=15% BGCOLOR=#FBF5EF>
\r
11690 <B>0XFD1A0070</B>
\r
11692 <TD width=10% BGCOLOR=#FBF5EF>
\r
11695 <TD width=10% BGCOLOR=#FBF5EF>
\r
11698 <TD width=15% BGCOLOR=#FBF5EF>
\r
11699 <B>0x00000000</B>
\r
11701 <TD width=35% BGCOLOR=#FBF5EF>
\r
11707 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11708 <TR valign="top">
\r
11709 <TD width=15% BGCOLOR=#C0FFC0>
\r
11710 <B>Field Name</B>
\r
11712 <TD width=15% BGCOLOR=#C0FFC0>
\r
11715 <TD width=10% BGCOLOR=#C0FFC0>
\r
11718 <TD width=10% BGCOLOR=#C0FFC0>
\r
11721 <TD width=15% BGCOLOR=#C0FFC0>
\r
11722 <B>Shifted Value</B>
\r
11724 <TD width=35% BGCOLOR=#C0FFC0>
\r
11725 <B>Description</B>
\r
11728 <TR valign="top">
\r
11729 <TD width=15% BGCOLOR=#FBF5EF>
\r
11730 <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1</B>
\r
11732 <TD width=15% BGCOLOR=#FBF5EF>
\r
11735 <TD width=10% BGCOLOR=#FBF5EF>
\r
11738 <TD width=10% BGCOLOR=#FBF5EF>
\r
11741 <TD width=15% BGCOLOR=#FBF5EF>
\r
11744 <TD width=35% BGCOLOR=#FBF5EF>
\r
11745 <B>6 bit divider</B>
\r
11748 <TR valign="top">
\r
11749 <TD width=15% BGCOLOR=#FBF5EF>
\r
11750 <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0</B>
\r
11752 <TD width=15% BGCOLOR=#FBF5EF>
\r
11755 <TD width=10% BGCOLOR=#FBF5EF>
\r
11758 <TD width=10% BGCOLOR=#FBF5EF>
\r
11761 <TD width=15% BGCOLOR=#FBF5EF>
\r
11764 <TD width=35% BGCOLOR=#FBF5EF>
\r
11765 <B>6 bit divider</B>
\r
11768 <TR valign="top">
\r
11769 <TD width=15% BGCOLOR=#FBF5EF>
\r
11770 <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL</B>
\r
11772 <TD width=15% BGCOLOR=#FBF5EF>
\r
11775 <TD width=10% BGCOLOR=#FBF5EF>
\r
11778 <TD width=10% BGCOLOR=#FBF5EF>
\r
11781 <TD width=15% BGCOLOR=#FBF5EF>
\r
11784 <TD width=35% BGCOLOR=#FBF5EF>
\r
11785 <B>000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11788 <TR valign="top">
\r
11789 <TD width=15% BGCOLOR=#FBF5EF>
\r
11790 <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT</B>
\r
11792 <TD width=15% BGCOLOR=#FBF5EF>
\r
11795 <TD width=10% BGCOLOR=#FBF5EF>
\r
11798 <TD width=10% BGCOLOR=#FBF5EF>
\r
11801 <TD width=15% BGCOLOR=#FBF5EF>
\r
11804 <TD width=35% BGCOLOR=#FBF5EF>
\r
11805 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11808 <TR valign="top">
\r
11809 <TD width=15% BGCOLOR=#C0C0C0>
\r
11810 <B>PSU_CRF_APB_DP_VIDEO_REF_CTRL@0XFD1A0070</B>
\r
11812 <TD width=15% BGCOLOR=#C0C0C0>
\r
11815 <TD width=10% BGCOLOR=#C0C0C0>
\r
11818 <TD width=10% BGCOLOR=#C0C0C0>
\r
11821 <TD width=15% BGCOLOR=#C0C0C0>
\r
11824 <TD width=35% BGCOLOR=#C0C0C0>
\r
11825 <B>This register controls this reference clock</B>
\r
11830 <H2><a name="DP_AUDIO_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_AUDIO_REF_CTRL</a></H2>
\r
11831 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11832 <TR valign="top">
\r
11833 <TD width=15% BGCOLOR=#FFFF00>
\r
11834 <B>Register Name</B>
\r
11836 <TD width=15% BGCOLOR=#FFFF00>
\r
11839 <TD width=10% BGCOLOR=#FFFF00>
\r
11842 <TD width=10% BGCOLOR=#FFFF00>
\r
11845 <TD width=15% BGCOLOR=#FFFF00>
\r
11846 <B>Reset Value</B>
\r
11848 <TD width=35% BGCOLOR=#FFFF00>
\r
11849 <B>Description</B>
\r
11852 <TR valign="top">
\r
11853 <TD width=15% BGCOLOR=#FBF5EF>
\r
11854 <B>DP_AUDIO_REF_CTRL</B>
\r
11856 <TD width=15% BGCOLOR=#FBF5EF>
\r
11857 <B>0XFD1A0074</B>
\r
11859 <TD width=10% BGCOLOR=#FBF5EF>
\r
11862 <TD width=10% BGCOLOR=#FBF5EF>
\r
11865 <TD width=15% BGCOLOR=#FBF5EF>
\r
11866 <B>0x00000000</B>
\r
11868 <TD width=35% BGCOLOR=#FBF5EF>
\r
11874 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11875 <TR valign="top">
\r
11876 <TD width=15% BGCOLOR=#C0FFC0>
\r
11877 <B>Field Name</B>
\r
11879 <TD width=15% BGCOLOR=#C0FFC0>
\r
11882 <TD width=10% BGCOLOR=#C0FFC0>
\r
11885 <TD width=10% BGCOLOR=#C0FFC0>
\r
11888 <TD width=15% BGCOLOR=#C0FFC0>
\r
11889 <B>Shifted Value</B>
\r
11891 <TD width=35% BGCOLOR=#C0FFC0>
\r
11892 <B>Description</B>
\r
11895 <TR valign="top">
\r
11896 <TD width=15% BGCOLOR=#FBF5EF>
\r
11897 <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1</B>
\r
11899 <TD width=15% BGCOLOR=#FBF5EF>
\r
11902 <TD width=10% BGCOLOR=#FBF5EF>
\r
11905 <TD width=10% BGCOLOR=#FBF5EF>
\r
11908 <TD width=15% BGCOLOR=#FBF5EF>
\r
11911 <TD width=35% BGCOLOR=#FBF5EF>
\r
11912 <B>6 bit divider</B>
\r
11915 <TR valign="top">
\r
11916 <TD width=15% BGCOLOR=#FBF5EF>
\r
11917 <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0</B>
\r
11919 <TD width=15% BGCOLOR=#FBF5EF>
\r
11922 <TD width=10% BGCOLOR=#FBF5EF>
\r
11925 <TD width=10% BGCOLOR=#FBF5EF>
\r
11928 <TD width=15% BGCOLOR=#FBF5EF>
\r
11931 <TD width=35% BGCOLOR=#FBF5EF>
\r
11932 <B>6 bit divider</B>
\r
11935 <TR valign="top">
\r
11936 <TD width=15% BGCOLOR=#FBF5EF>
\r
11937 <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL</B>
\r
11939 <TD width=15% BGCOLOR=#FBF5EF>
\r
11942 <TD width=10% BGCOLOR=#FBF5EF>
\r
11945 <TD width=10% BGCOLOR=#FBF5EF>
\r
11948 <TD width=15% BGCOLOR=#FBF5EF>
\r
11951 <TD width=35% BGCOLOR=#FBF5EF>
\r
11952 <B>000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
11955 <TR valign="top">
\r
11956 <TD width=15% BGCOLOR=#FBF5EF>
\r
11957 <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT</B>
\r
11959 <TD width=15% BGCOLOR=#FBF5EF>
\r
11962 <TD width=10% BGCOLOR=#FBF5EF>
\r
11965 <TD width=10% BGCOLOR=#FBF5EF>
\r
11968 <TD width=15% BGCOLOR=#FBF5EF>
\r
11971 <TD width=35% BGCOLOR=#FBF5EF>
\r
11972 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
11975 <TR valign="top">
\r
11976 <TD width=15% BGCOLOR=#C0C0C0>
\r
11977 <B>PSU_CRF_APB_DP_AUDIO_REF_CTRL@0XFD1A0074</B>
\r
11979 <TD width=15% BGCOLOR=#C0C0C0>
\r
11982 <TD width=10% BGCOLOR=#C0C0C0>
\r
11985 <TD width=10% BGCOLOR=#C0C0C0>
\r
11988 <TD width=15% BGCOLOR=#C0C0C0>
\r
11991 <TD width=35% BGCOLOR=#C0C0C0>
\r
11992 <B>This register controls this reference clock</B>
\r
11997 <H2><a name="DP_STC_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DP_STC_REF_CTRL</a></H2>
\r
11998 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
11999 <TR valign="top">
\r
12000 <TD width=15% BGCOLOR=#FFFF00>
\r
12001 <B>Register Name</B>
\r
12003 <TD width=15% BGCOLOR=#FFFF00>
\r
12006 <TD width=10% BGCOLOR=#FFFF00>
\r
12009 <TD width=10% BGCOLOR=#FFFF00>
\r
12012 <TD width=15% BGCOLOR=#FFFF00>
\r
12013 <B>Reset Value</B>
\r
12015 <TD width=35% BGCOLOR=#FFFF00>
\r
12016 <B>Description</B>
\r
12019 <TR valign="top">
\r
12020 <TD width=15% BGCOLOR=#FBF5EF>
\r
12021 <B>DP_STC_REF_CTRL</B>
\r
12023 <TD width=15% BGCOLOR=#FBF5EF>
\r
12024 <B>0XFD1A007C</B>
\r
12026 <TD width=10% BGCOLOR=#FBF5EF>
\r
12029 <TD width=10% BGCOLOR=#FBF5EF>
\r
12032 <TD width=15% BGCOLOR=#FBF5EF>
\r
12033 <B>0x00000000</B>
\r
12035 <TD width=35% BGCOLOR=#FBF5EF>
\r
12041 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12042 <TR valign="top">
\r
12043 <TD width=15% BGCOLOR=#C0FFC0>
\r
12044 <B>Field Name</B>
\r
12046 <TD width=15% BGCOLOR=#C0FFC0>
\r
12049 <TD width=10% BGCOLOR=#C0FFC0>
\r
12052 <TD width=10% BGCOLOR=#C0FFC0>
\r
12055 <TD width=15% BGCOLOR=#C0FFC0>
\r
12056 <B>Shifted Value</B>
\r
12058 <TD width=35% BGCOLOR=#C0FFC0>
\r
12059 <B>Description</B>
\r
12062 <TR valign="top">
\r
12063 <TD width=15% BGCOLOR=#FBF5EF>
\r
12064 <B>PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1</B>
\r
12066 <TD width=15% BGCOLOR=#FBF5EF>
\r
12069 <TD width=10% BGCOLOR=#FBF5EF>
\r
12072 <TD width=10% BGCOLOR=#FBF5EF>
\r
12075 <TD width=15% BGCOLOR=#FBF5EF>
\r
12078 <TD width=35% BGCOLOR=#FBF5EF>
\r
12079 <B>6 bit divider</B>
\r
12082 <TR valign="top">
\r
12083 <TD width=15% BGCOLOR=#FBF5EF>
\r
12084 <B>PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0</B>
\r
12086 <TD width=15% BGCOLOR=#FBF5EF>
\r
12089 <TD width=10% BGCOLOR=#FBF5EF>
\r
12092 <TD width=10% BGCOLOR=#FBF5EF>
\r
12095 <TD width=15% BGCOLOR=#FBF5EF>
\r
12098 <TD width=35% BGCOLOR=#FBF5EF>
\r
12099 <B>6 bit divider</B>
\r
12102 <TR valign="top">
\r
12103 <TD width=15% BGCOLOR=#FBF5EF>
\r
12104 <B>PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL</B>
\r
12106 <TD width=15% BGCOLOR=#FBF5EF>
\r
12109 <TD width=10% BGCOLOR=#FBF5EF>
\r
12112 <TD width=10% BGCOLOR=#FBF5EF>
\r
12115 <TD width=15% BGCOLOR=#FBF5EF>
\r
12118 <TD width=35% BGCOLOR=#FBF5EF>
\r
12119 <B>000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12122 <TR valign="top">
\r
12123 <TD width=15% BGCOLOR=#FBF5EF>
\r
12124 <B>PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT</B>
\r
12126 <TD width=15% BGCOLOR=#FBF5EF>
\r
12129 <TD width=10% BGCOLOR=#FBF5EF>
\r
12132 <TD width=10% BGCOLOR=#FBF5EF>
\r
12135 <TD width=15% BGCOLOR=#FBF5EF>
\r
12138 <TD width=35% BGCOLOR=#FBF5EF>
\r
12139 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
12142 <TR valign="top">
\r
12143 <TD width=15% BGCOLOR=#C0C0C0>
\r
12144 <B>PSU_CRF_APB_DP_STC_REF_CTRL@0XFD1A007C</B>
\r
12146 <TD width=15% BGCOLOR=#C0C0C0>
\r
12149 <TD width=10% BGCOLOR=#C0C0C0>
\r
12152 <TD width=10% BGCOLOR=#C0C0C0>
\r
12155 <TD width=15% BGCOLOR=#C0C0C0>
\r
12158 <TD width=35% BGCOLOR=#C0C0C0>
\r
12159 <B>This register controls this reference clock</B>
\r
12164 <H2><a name="ACPU_CTRL">Register (<A href=#mod___slcr> slcr </A>)ACPU_CTRL</a></H2>
\r
12165 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12166 <TR valign="top">
\r
12167 <TD width=15% BGCOLOR=#FFFF00>
\r
12168 <B>Register Name</B>
\r
12170 <TD width=15% BGCOLOR=#FFFF00>
\r
12173 <TD width=10% BGCOLOR=#FFFF00>
\r
12176 <TD width=10% BGCOLOR=#FFFF00>
\r
12179 <TD width=15% BGCOLOR=#FFFF00>
\r
12180 <B>Reset Value</B>
\r
12182 <TD width=35% BGCOLOR=#FFFF00>
\r
12183 <B>Description</B>
\r
12186 <TR valign="top">
\r
12187 <TD width=15% BGCOLOR=#FBF5EF>
\r
12190 <TD width=15% BGCOLOR=#FBF5EF>
\r
12191 <B>0XFD1A0060</B>
\r
12193 <TD width=10% BGCOLOR=#FBF5EF>
\r
12196 <TD width=10% BGCOLOR=#FBF5EF>
\r
12199 <TD width=15% BGCOLOR=#FBF5EF>
\r
12200 <B>0x00000000</B>
\r
12202 <TD width=35% BGCOLOR=#FBF5EF>
\r
12208 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12209 <TR valign="top">
\r
12210 <TD width=15% BGCOLOR=#C0FFC0>
\r
12211 <B>Field Name</B>
\r
12213 <TD width=15% BGCOLOR=#C0FFC0>
\r
12216 <TD width=10% BGCOLOR=#C0FFC0>
\r
12219 <TD width=10% BGCOLOR=#C0FFC0>
\r
12222 <TD width=15% BGCOLOR=#C0FFC0>
\r
12223 <B>Shifted Value</B>
\r
12225 <TD width=35% BGCOLOR=#C0FFC0>
\r
12226 <B>Description</B>
\r
12229 <TR valign="top">
\r
12230 <TD width=15% BGCOLOR=#FBF5EF>
\r
12231 <B>PSU_CRF_APB_ACPU_CTRL_DIVISOR0</B>
\r
12233 <TD width=15% BGCOLOR=#FBF5EF>
\r
12236 <TD width=10% BGCOLOR=#FBF5EF>
\r
12239 <TD width=10% BGCOLOR=#FBF5EF>
\r
12242 <TD width=15% BGCOLOR=#FBF5EF>
\r
12245 <TD width=35% BGCOLOR=#FBF5EF>
\r
12246 <B>6 bit divider</B>
\r
12249 <TR valign="top">
\r
12250 <TD width=15% BGCOLOR=#FBF5EF>
\r
12251 <B>PSU_CRF_APB_ACPU_CTRL_SRCSEL</B>
\r
12253 <TD width=15% BGCOLOR=#FBF5EF>
\r
12256 <TD width=10% BGCOLOR=#FBF5EF>
\r
12259 <TD width=10% BGCOLOR=#FBF5EF>
\r
12262 <TD width=15% BGCOLOR=#FBF5EF>
\r
12265 <TD width=35% BGCOLOR=#FBF5EF>
\r
12266 <B>000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12269 <TR valign="top">
\r
12270 <TD width=15% BGCOLOR=#FBF5EF>
\r
12271 <B>PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF</B>
\r
12273 <TD width=15% BGCOLOR=#FBF5EF>
\r
12276 <TD width=10% BGCOLOR=#FBF5EF>
\r
12279 <TD width=10% BGCOLOR=#FBF5EF>
\r
12282 <TD width=15% BGCOLOR=#FBF5EF>
\r
12285 <TD width=35% BGCOLOR=#FBF5EF>
\r
12286 <B>Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock</B>
\r
12289 <TR valign="top">
\r
12290 <TD width=15% BGCOLOR=#FBF5EF>
\r
12291 <B>PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL</B>
\r
12293 <TD width=15% BGCOLOR=#FBF5EF>
\r
12296 <TD width=10% BGCOLOR=#FBF5EF>
\r
12299 <TD width=10% BGCOLOR=#FBF5EF>
\r
12302 <TD width=15% BGCOLOR=#FBF5EF>
\r
12305 <TD width=35% BGCOLOR=#FBF5EF>
\r
12306 <B>Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed clock to the entire APU</B>
\r
12309 <TR valign="top">
\r
12310 <TD width=15% BGCOLOR=#C0C0C0>
\r
12311 <B>PSU_CRF_APB_ACPU_CTRL@0XFD1A0060</B>
\r
12313 <TD width=15% BGCOLOR=#C0C0C0>
\r
12316 <TD width=10% BGCOLOR=#C0C0C0>
\r
12319 <TD width=10% BGCOLOR=#C0C0C0>
\r
12322 <TD width=15% BGCOLOR=#C0C0C0>
\r
12325 <TD width=35% BGCOLOR=#C0C0C0>
\r
12326 <B>This register controls this reference clock</B>
\r
12331 <H2><a name="DBG_TRACE_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_TRACE_CTRL</a></H2>
\r
12332 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12333 <TR valign="top">
\r
12334 <TD width=15% BGCOLOR=#FFFF00>
\r
12335 <B>Register Name</B>
\r
12337 <TD width=15% BGCOLOR=#FFFF00>
\r
12340 <TD width=10% BGCOLOR=#FFFF00>
\r
12343 <TD width=10% BGCOLOR=#FFFF00>
\r
12346 <TD width=15% BGCOLOR=#FFFF00>
\r
12347 <B>Reset Value</B>
\r
12349 <TD width=35% BGCOLOR=#FFFF00>
\r
12350 <B>Description</B>
\r
12353 <TR valign="top">
\r
12354 <TD width=15% BGCOLOR=#FBF5EF>
\r
12355 <B>DBG_TRACE_CTRL</B>
\r
12357 <TD width=15% BGCOLOR=#FBF5EF>
\r
12358 <B>0XFD1A0064</B>
\r
12360 <TD width=10% BGCOLOR=#FBF5EF>
\r
12363 <TD width=10% BGCOLOR=#FBF5EF>
\r
12366 <TD width=15% BGCOLOR=#FBF5EF>
\r
12367 <B>0x00000000</B>
\r
12369 <TD width=35% BGCOLOR=#FBF5EF>
\r
12375 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12376 <TR valign="top">
\r
12377 <TD width=15% BGCOLOR=#C0FFC0>
\r
12378 <B>Field Name</B>
\r
12380 <TD width=15% BGCOLOR=#C0FFC0>
\r
12383 <TD width=10% BGCOLOR=#C0FFC0>
\r
12386 <TD width=10% BGCOLOR=#C0FFC0>
\r
12389 <TD width=15% BGCOLOR=#C0FFC0>
\r
12390 <B>Shifted Value</B>
\r
12392 <TD width=35% BGCOLOR=#C0FFC0>
\r
12393 <B>Description</B>
\r
12396 <TR valign="top">
\r
12397 <TD width=15% BGCOLOR=#FBF5EF>
\r
12398 <B>PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0</B>
\r
12400 <TD width=15% BGCOLOR=#FBF5EF>
\r
12403 <TD width=10% BGCOLOR=#FBF5EF>
\r
12406 <TD width=10% BGCOLOR=#FBF5EF>
\r
12409 <TD width=15% BGCOLOR=#FBF5EF>
\r
12412 <TD width=35% BGCOLOR=#FBF5EF>
\r
12413 <B>6 bit divider</B>
\r
12416 <TR valign="top">
\r
12417 <TD width=15% BGCOLOR=#FBF5EF>
\r
12418 <B>PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL</B>
\r
12420 <TD width=15% BGCOLOR=#FBF5EF>
\r
12423 <TD width=10% BGCOLOR=#FBF5EF>
\r
12426 <TD width=10% BGCOLOR=#FBF5EF>
\r
12429 <TD width=15% BGCOLOR=#FBF5EF>
\r
12432 <TD width=35% BGCOLOR=#FBF5EF>
\r
12433 <B>000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12436 <TR valign="top">
\r
12437 <TD width=15% BGCOLOR=#FBF5EF>
\r
12438 <B>PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT</B>
\r
12440 <TD width=15% BGCOLOR=#FBF5EF>
\r
12443 <TD width=10% BGCOLOR=#FBF5EF>
\r
12446 <TD width=10% BGCOLOR=#FBF5EF>
\r
12449 <TD width=15% BGCOLOR=#FBF5EF>
\r
12452 <TD width=35% BGCOLOR=#FBF5EF>
\r
12453 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
12456 <TR valign="top">
\r
12457 <TD width=15% BGCOLOR=#C0C0C0>
\r
12458 <B>PSU_CRF_APB_DBG_TRACE_CTRL@0XFD1A0064</B>
\r
12460 <TD width=15% BGCOLOR=#C0C0C0>
\r
12463 <TD width=10% BGCOLOR=#C0C0C0>
\r
12466 <TD width=10% BGCOLOR=#C0C0C0>
\r
12469 <TD width=15% BGCOLOR=#C0C0C0>
\r
12472 <TD width=35% BGCOLOR=#C0C0C0>
\r
12473 <B>This register controls this reference clock</B>
\r
12478 <H2><a name="DBG_FPD_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_FPD_CTRL</a></H2>
\r
12479 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12480 <TR valign="top">
\r
12481 <TD width=15% BGCOLOR=#FFFF00>
\r
12482 <B>Register Name</B>
\r
12484 <TD width=15% BGCOLOR=#FFFF00>
\r
12487 <TD width=10% BGCOLOR=#FFFF00>
\r
12490 <TD width=10% BGCOLOR=#FFFF00>
\r
12493 <TD width=15% BGCOLOR=#FFFF00>
\r
12494 <B>Reset Value</B>
\r
12496 <TD width=35% BGCOLOR=#FFFF00>
\r
12497 <B>Description</B>
\r
12500 <TR valign="top">
\r
12501 <TD width=15% BGCOLOR=#FBF5EF>
\r
12502 <B>DBG_FPD_CTRL</B>
\r
12504 <TD width=15% BGCOLOR=#FBF5EF>
\r
12505 <B>0XFD1A0068</B>
\r
12507 <TD width=10% BGCOLOR=#FBF5EF>
\r
12510 <TD width=10% BGCOLOR=#FBF5EF>
\r
12513 <TD width=15% BGCOLOR=#FBF5EF>
\r
12514 <B>0x00000000</B>
\r
12516 <TD width=35% BGCOLOR=#FBF5EF>
\r
12522 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12523 <TR valign="top">
\r
12524 <TD width=15% BGCOLOR=#C0FFC0>
\r
12525 <B>Field Name</B>
\r
12527 <TD width=15% BGCOLOR=#C0FFC0>
\r
12530 <TD width=10% BGCOLOR=#C0FFC0>
\r
12533 <TD width=10% BGCOLOR=#C0FFC0>
\r
12536 <TD width=15% BGCOLOR=#C0FFC0>
\r
12537 <B>Shifted Value</B>
\r
12539 <TD width=35% BGCOLOR=#C0FFC0>
\r
12540 <B>Description</B>
\r
12543 <TR valign="top">
\r
12544 <TD width=15% BGCOLOR=#FBF5EF>
\r
12545 <B>PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0</B>
\r
12547 <TD width=15% BGCOLOR=#FBF5EF>
\r
12550 <TD width=10% BGCOLOR=#FBF5EF>
\r
12553 <TD width=10% BGCOLOR=#FBF5EF>
\r
12556 <TD width=15% BGCOLOR=#FBF5EF>
\r
12559 <TD width=35% BGCOLOR=#FBF5EF>
\r
12560 <B>6 bit divider</B>
\r
12563 <TR valign="top">
\r
12564 <TD width=15% BGCOLOR=#FBF5EF>
\r
12565 <B>PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL</B>
\r
12567 <TD width=15% BGCOLOR=#FBF5EF>
\r
12570 <TD width=10% BGCOLOR=#FBF5EF>
\r
12573 <TD width=10% BGCOLOR=#FBF5EF>
\r
12576 <TD width=15% BGCOLOR=#FBF5EF>
\r
12579 <TD width=35% BGCOLOR=#FBF5EF>
\r
12580 <B>000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12583 <TR valign="top">
\r
12584 <TD width=15% BGCOLOR=#FBF5EF>
\r
12585 <B>PSU_CRF_APB_DBG_FPD_CTRL_CLKACT</B>
\r
12587 <TD width=15% BGCOLOR=#FBF5EF>
\r
12590 <TD width=10% BGCOLOR=#FBF5EF>
\r
12593 <TD width=10% BGCOLOR=#FBF5EF>
\r
12596 <TD width=15% BGCOLOR=#FBF5EF>
\r
12599 <TD width=35% BGCOLOR=#FBF5EF>
\r
12600 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
12603 <TR valign="top">
\r
12604 <TD width=15% BGCOLOR=#C0C0C0>
\r
12605 <B>PSU_CRF_APB_DBG_FPD_CTRL@0XFD1A0068</B>
\r
12607 <TD width=15% BGCOLOR=#C0C0C0>
\r
12610 <TD width=10% BGCOLOR=#C0C0C0>
\r
12613 <TD width=10% BGCOLOR=#C0C0C0>
\r
12616 <TD width=15% BGCOLOR=#C0C0C0>
\r
12619 <TD width=35% BGCOLOR=#C0C0C0>
\r
12620 <B>This register controls this reference clock</B>
\r
12625 <H2><a name="DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CTRL</a></H2>
\r
12626 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12627 <TR valign="top">
\r
12628 <TD width=15% BGCOLOR=#FFFF00>
\r
12629 <B>Register Name</B>
\r
12631 <TD width=15% BGCOLOR=#FFFF00>
\r
12634 <TD width=10% BGCOLOR=#FFFF00>
\r
12637 <TD width=10% BGCOLOR=#FFFF00>
\r
12640 <TD width=15% BGCOLOR=#FFFF00>
\r
12641 <B>Reset Value</B>
\r
12643 <TD width=35% BGCOLOR=#FFFF00>
\r
12644 <B>Description</B>
\r
12647 <TR valign="top">
\r
12648 <TD width=15% BGCOLOR=#FBF5EF>
\r
12651 <TD width=15% BGCOLOR=#FBF5EF>
\r
12652 <B>0XFD1A0080</B>
\r
12654 <TD width=10% BGCOLOR=#FBF5EF>
\r
12657 <TD width=10% BGCOLOR=#FBF5EF>
\r
12660 <TD width=15% BGCOLOR=#FBF5EF>
\r
12661 <B>0x00000000</B>
\r
12663 <TD width=35% BGCOLOR=#FBF5EF>
\r
12669 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12670 <TR valign="top">
\r
12671 <TD width=15% BGCOLOR=#C0FFC0>
\r
12672 <B>Field Name</B>
\r
12674 <TD width=15% BGCOLOR=#C0FFC0>
\r
12677 <TD width=10% BGCOLOR=#C0FFC0>
\r
12680 <TD width=10% BGCOLOR=#C0FFC0>
\r
12683 <TD width=15% BGCOLOR=#C0FFC0>
\r
12684 <B>Shifted Value</B>
\r
12686 <TD width=35% BGCOLOR=#C0FFC0>
\r
12687 <B>Description</B>
\r
12690 <TR valign="top">
\r
12691 <TD width=15% BGCOLOR=#FBF5EF>
\r
12692 <B>PSU_CRF_APB_DDR_CTRL_DIVISOR0</B>
\r
12694 <TD width=15% BGCOLOR=#FBF5EF>
\r
12697 <TD width=10% BGCOLOR=#FBF5EF>
\r
12700 <TD width=10% BGCOLOR=#FBF5EF>
\r
12703 <TD width=15% BGCOLOR=#FBF5EF>
\r
12706 <TD width=35% BGCOLOR=#FBF5EF>
\r
12707 <B>6 bit divider</B>
\r
12710 <TR valign="top">
\r
12711 <TD width=15% BGCOLOR=#FBF5EF>
\r
12712 <B>PSU_CRF_APB_DDR_CTRL_SRCSEL</B>
\r
12714 <TD width=15% BGCOLOR=#FBF5EF>
\r
12717 <TD width=10% BGCOLOR=#FBF5EF>
\r
12720 <TD width=10% BGCOLOR=#FBF5EF>
\r
12723 <TD width=15% BGCOLOR=#FBF5EF>
\r
12726 <TD width=35% BGCOLOR=#FBF5EF>
\r
12727 <B>000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12730 <TR valign="top">
\r
12731 <TD width=15% BGCOLOR=#C0C0C0>
\r
12732 <B>PSU_CRF_APB_DDR_CTRL@0XFD1A0080</B>
\r
12734 <TD width=15% BGCOLOR=#C0C0C0>
\r
12737 <TD width=10% BGCOLOR=#C0C0C0>
\r
12740 <TD width=10% BGCOLOR=#C0C0C0>
\r
12743 <TD width=15% BGCOLOR=#C0C0C0>
\r
12746 <TD width=35% BGCOLOR=#C0C0C0>
\r
12747 <B>This register controls this reference clock</B>
\r
12752 <H2><a name="GPU_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GPU_REF_CTRL</a></H2>
\r
12753 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12754 <TR valign="top">
\r
12755 <TD width=15% BGCOLOR=#FFFF00>
\r
12756 <B>Register Name</B>
\r
12758 <TD width=15% BGCOLOR=#FFFF00>
\r
12761 <TD width=10% BGCOLOR=#FFFF00>
\r
12764 <TD width=10% BGCOLOR=#FFFF00>
\r
12767 <TD width=15% BGCOLOR=#FFFF00>
\r
12768 <B>Reset Value</B>
\r
12770 <TD width=35% BGCOLOR=#FFFF00>
\r
12771 <B>Description</B>
\r
12774 <TR valign="top">
\r
12775 <TD width=15% BGCOLOR=#FBF5EF>
\r
12776 <B>GPU_REF_CTRL</B>
\r
12778 <TD width=15% BGCOLOR=#FBF5EF>
\r
12779 <B>0XFD1A0084</B>
\r
12781 <TD width=10% BGCOLOR=#FBF5EF>
\r
12784 <TD width=10% BGCOLOR=#FBF5EF>
\r
12787 <TD width=15% BGCOLOR=#FBF5EF>
\r
12788 <B>0x00000000</B>
\r
12790 <TD width=35% BGCOLOR=#FBF5EF>
\r
12796 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12797 <TR valign="top">
\r
12798 <TD width=15% BGCOLOR=#C0FFC0>
\r
12799 <B>Field Name</B>
\r
12801 <TD width=15% BGCOLOR=#C0FFC0>
\r
12804 <TD width=10% BGCOLOR=#C0FFC0>
\r
12807 <TD width=10% BGCOLOR=#C0FFC0>
\r
12810 <TD width=15% BGCOLOR=#C0FFC0>
\r
12811 <B>Shifted Value</B>
\r
12813 <TD width=35% BGCOLOR=#C0FFC0>
\r
12814 <B>Description</B>
\r
12817 <TR valign="top">
\r
12818 <TD width=15% BGCOLOR=#FBF5EF>
\r
12819 <B>PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0</B>
\r
12821 <TD width=15% BGCOLOR=#FBF5EF>
\r
12824 <TD width=10% BGCOLOR=#FBF5EF>
\r
12827 <TD width=10% BGCOLOR=#FBF5EF>
\r
12830 <TD width=15% BGCOLOR=#FBF5EF>
\r
12833 <TD width=35% BGCOLOR=#FBF5EF>
\r
12834 <B>6 bit divider</B>
\r
12837 <TR valign="top">
\r
12838 <TD width=15% BGCOLOR=#FBF5EF>
\r
12839 <B>PSU_CRF_APB_GPU_REF_CTRL_SRCSEL</B>
\r
12841 <TD width=15% BGCOLOR=#FBF5EF>
\r
12844 <TD width=10% BGCOLOR=#FBF5EF>
\r
12847 <TD width=10% BGCOLOR=#FBF5EF>
\r
12850 <TD width=15% BGCOLOR=#FBF5EF>
\r
12853 <TD width=35% BGCOLOR=#FBF5EF>
\r
12854 <B>000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
12857 <TR valign="top">
\r
12858 <TD width=15% BGCOLOR=#FBF5EF>
\r
12859 <B>PSU_CRF_APB_GPU_REF_CTRL_CLKACT</B>
\r
12861 <TD width=15% BGCOLOR=#FBF5EF>
\r
12864 <TD width=10% BGCOLOR=#FBF5EF>
\r
12867 <TD width=10% BGCOLOR=#FBF5EF>
\r
12870 <TD width=15% BGCOLOR=#FBF5EF>
\r
12873 <TD width=35% BGCOLOR=#FBF5EF>
\r
12874 <B>Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below</B>
\r
12877 <TR valign="top">
\r
12878 <TD width=15% BGCOLOR=#FBF5EF>
\r
12879 <B>PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT</B>
\r
12881 <TD width=15% BGCOLOR=#FBF5EF>
\r
12884 <TD width=10% BGCOLOR=#FBF5EF>
\r
12887 <TD width=10% BGCOLOR=#FBF5EF>
\r
12890 <TD width=15% BGCOLOR=#FBF5EF>
\r
12893 <TD width=35% BGCOLOR=#FBF5EF>
\r
12894 <B>Clock active signal for Pixel Processor. Switch to 0 to disable the clock</B>
\r
12897 <TR valign="top">
\r
12898 <TD width=15% BGCOLOR=#FBF5EF>
\r
12899 <B>PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT</B>
\r
12901 <TD width=15% BGCOLOR=#FBF5EF>
\r
12904 <TD width=10% BGCOLOR=#FBF5EF>
\r
12907 <TD width=10% BGCOLOR=#FBF5EF>
\r
12910 <TD width=15% BGCOLOR=#FBF5EF>
\r
12913 <TD width=35% BGCOLOR=#FBF5EF>
\r
12914 <B>Clock active signal for Pixel Processor. Switch to 0 to disable the clock</B>
\r
12917 <TR valign="top">
\r
12918 <TD width=15% BGCOLOR=#C0C0C0>
\r
12919 <B>PSU_CRF_APB_GPU_REF_CTRL@0XFD1A0084</B>
\r
12921 <TD width=15% BGCOLOR=#C0C0C0>
\r
12924 <TD width=10% BGCOLOR=#C0C0C0>
\r
12927 <TD width=10% BGCOLOR=#C0C0C0>
\r
12930 <TD width=15% BGCOLOR=#C0C0C0>
\r
12933 <TD width=35% BGCOLOR=#C0C0C0>
\r
12934 <B>This register controls this reference clock</B>
\r
12939 <H2><a name="GDMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GDMA_REF_CTRL</a></H2>
\r
12940 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12941 <TR valign="top">
\r
12942 <TD width=15% BGCOLOR=#FFFF00>
\r
12943 <B>Register Name</B>
\r
12945 <TD width=15% BGCOLOR=#FFFF00>
\r
12948 <TD width=10% BGCOLOR=#FFFF00>
\r
12951 <TD width=10% BGCOLOR=#FFFF00>
\r
12954 <TD width=15% BGCOLOR=#FFFF00>
\r
12955 <B>Reset Value</B>
\r
12957 <TD width=35% BGCOLOR=#FFFF00>
\r
12958 <B>Description</B>
\r
12961 <TR valign="top">
\r
12962 <TD width=15% BGCOLOR=#FBF5EF>
\r
12963 <B>GDMA_REF_CTRL</B>
\r
12965 <TD width=15% BGCOLOR=#FBF5EF>
\r
12966 <B>0XFD1A00B8</B>
\r
12968 <TD width=10% BGCOLOR=#FBF5EF>
\r
12971 <TD width=10% BGCOLOR=#FBF5EF>
\r
12974 <TD width=15% BGCOLOR=#FBF5EF>
\r
12975 <B>0x00000000</B>
\r
12977 <TD width=35% BGCOLOR=#FBF5EF>
\r
12983 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
12984 <TR valign="top">
\r
12985 <TD width=15% BGCOLOR=#C0FFC0>
\r
12986 <B>Field Name</B>
\r
12988 <TD width=15% BGCOLOR=#C0FFC0>
\r
12991 <TD width=10% BGCOLOR=#C0FFC0>
\r
12994 <TD width=10% BGCOLOR=#C0FFC0>
\r
12997 <TD width=15% BGCOLOR=#C0FFC0>
\r
12998 <B>Shifted Value</B>
\r
13000 <TD width=35% BGCOLOR=#C0FFC0>
\r
13001 <B>Description</B>
\r
13004 <TR valign="top">
\r
13005 <TD width=15% BGCOLOR=#FBF5EF>
\r
13006 <B>PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0</B>
\r
13008 <TD width=15% BGCOLOR=#FBF5EF>
\r
13011 <TD width=10% BGCOLOR=#FBF5EF>
\r
13014 <TD width=10% BGCOLOR=#FBF5EF>
\r
13017 <TD width=15% BGCOLOR=#FBF5EF>
\r
13020 <TD width=35% BGCOLOR=#FBF5EF>
\r
13021 <B>6 bit divider</B>
\r
13024 <TR valign="top">
\r
13025 <TD width=15% BGCOLOR=#FBF5EF>
\r
13026 <B>PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL</B>
\r
13028 <TD width=15% BGCOLOR=#FBF5EF>
\r
13031 <TD width=10% BGCOLOR=#FBF5EF>
\r
13034 <TD width=10% BGCOLOR=#FBF5EF>
\r
13037 <TD width=15% BGCOLOR=#FBF5EF>
\r
13040 <TD width=35% BGCOLOR=#FBF5EF>
\r
13041 <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13044 <TR valign="top">
\r
13045 <TD width=15% BGCOLOR=#FBF5EF>
\r
13046 <B>PSU_CRF_APB_GDMA_REF_CTRL_CLKACT</B>
\r
13048 <TD width=15% BGCOLOR=#FBF5EF>
\r
13051 <TD width=10% BGCOLOR=#FBF5EF>
\r
13054 <TD width=10% BGCOLOR=#FBF5EF>
\r
13057 <TD width=15% BGCOLOR=#FBF5EF>
\r
13060 <TD width=35% BGCOLOR=#FBF5EF>
\r
13061 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
13064 <TR valign="top">
\r
13065 <TD width=15% BGCOLOR=#C0C0C0>
\r
13066 <B>PSU_CRF_APB_GDMA_REF_CTRL@0XFD1A00B8</B>
\r
13068 <TD width=15% BGCOLOR=#C0C0C0>
\r
13071 <TD width=10% BGCOLOR=#C0C0C0>
\r
13074 <TD width=10% BGCOLOR=#C0C0C0>
\r
13077 <TD width=15% BGCOLOR=#C0C0C0>
\r
13080 <TD width=35% BGCOLOR=#C0C0C0>
\r
13081 <B>This register controls this reference clock</B>
\r
13086 <H2><a name="DPDMA_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)DPDMA_REF_CTRL</a></H2>
\r
13087 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13088 <TR valign="top">
\r
13089 <TD width=15% BGCOLOR=#FFFF00>
\r
13090 <B>Register Name</B>
\r
13092 <TD width=15% BGCOLOR=#FFFF00>
\r
13095 <TD width=10% BGCOLOR=#FFFF00>
\r
13098 <TD width=10% BGCOLOR=#FFFF00>
\r
13101 <TD width=15% BGCOLOR=#FFFF00>
\r
13102 <B>Reset Value</B>
\r
13104 <TD width=35% BGCOLOR=#FFFF00>
\r
13105 <B>Description</B>
\r
13108 <TR valign="top">
\r
13109 <TD width=15% BGCOLOR=#FBF5EF>
\r
13110 <B>DPDMA_REF_CTRL</B>
\r
13112 <TD width=15% BGCOLOR=#FBF5EF>
\r
13113 <B>0XFD1A00BC</B>
\r
13115 <TD width=10% BGCOLOR=#FBF5EF>
\r
13118 <TD width=10% BGCOLOR=#FBF5EF>
\r
13121 <TD width=15% BGCOLOR=#FBF5EF>
\r
13122 <B>0x00000000</B>
\r
13124 <TD width=35% BGCOLOR=#FBF5EF>
\r
13130 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13131 <TR valign="top">
\r
13132 <TD width=15% BGCOLOR=#C0FFC0>
\r
13133 <B>Field Name</B>
\r
13135 <TD width=15% BGCOLOR=#C0FFC0>
\r
13138 <TD width=10% BGCOLOR=#C0FFC0>
\r
13141 <TD width=10% BGCOLOR=#C0FFC0>
\r
13144 <TD width=15% BGCOLOR=#C0FFC0>
\r
13145 <B>Shifted Value</B>
\r
13147 <TD width=35% BGCOLOR=#C0FFC0>
\r
13148 <B>Description</B>
\r
13151 <TR valign="top">
\r
13152 <TD width=15% BGCOLOR=#FBF5EF>
\r
13153 <B>PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0</B>
\r
13155 <TD width=15% BGCOLOR=#FBF5EF>
\r
13158 <TD width=10% BGCOLOR=#FBF5EF>
\r
13161 <TD width=10% BGCOLOR=#FBF5EF>
\r
13164 <TD width=15% BGCOLOR=#FBF5EF>
\r
13167 <TD width=35% BGCOLOR=#FBF5EF>
\r
13168 <B>6 bit divider</B>
\r
13171 <TR valign="top">
\r
13172 <TD width=15% BGCOLOR=#FBF5EF>
\r
13173 <B>PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL</B>
\r
13175 <TD width=15% BGCOLOR=#FBF5EF>
\r
13178 <TD width=10% BGCOLOR=#FBF5EF>
\r
13181 <TD width=10% BGCOLOR=#FBF5EF>
\r
13184 <TD width=15% BGCOLOR=#FBF5EF>
\r
13187 <TD width=35% BGCOLOR=#FBF5EF>
\r
13188 <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13191 <TR valign="top">
\r
13192 <TD width=15% BGCOLOR=#FBF5EF>
\r
13193 <B>PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT</B>
\r
13195 <TD width=15% BGCOLOR=#FBF5EF>
\r
13198 <TD width=10% BGCOLOR=#FBF5EF>
\r
13201 <TD width=10% BGCOLOR=#FBF5EF>
\r
13204 <TD width=15% BGCOLOR=#FBF5EF>
\r
13207 <TD width=35% BGCOLOR=#FBF5EF>
\r
13208 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
13211 <TR valign="top">
\r
13212 <TD width=15% BGCOLOR=#C0C0C0>
\r
13213 <B>PSU_CRF_APB_DPDMA_REF_CTRL@0XFD1A00BC</B>
\r
13215 <TD width=15% BGCOLOR=#C0C0C0>
\r
13218 <TD width=10% BGCOLOR=#C0C0C0>
\r
13221 <TD width=10% BGCOLOR=#C0C0C0>
\r
13224 <TD width=15% BGCOLOR=#C0C0C0>
\r
13227 <TD width=35% BGCOLOR=#C0C0C0>
\r
13228 <B>This register controls this reference clock</B>
\r
13233 <H2><a name="TOPSW_MAIN_CTRL">Register (<A href=#mod___slcr> slcr </A>)TOPSW_MAIN_CTRL</a></H2>
\r
13234 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13235 <TR valign="top">
\r
13236 <TD width=15% BGCOLOR=#FFFF00>
\r
13237 <B>Register Name</B>
\r
13239 <TD width=15% BGCOLOR=#FFFF00>
\r
13242 <TD width=10% BGCOLOR=#FFFF00>
\r
13245 <TD width=10% BGCOLOR=#FFFF00>
\r
13248 <TD width=15% BGCOLOR=#FFFF00>
\r
13249 <B>Reset Value</B>
\r
13251 <TD width=35% BGCOLOR=#FFFF00>
\r
13252 <B>Description</B>
\r
13255 <TR valign="top">
\r
13256 <TD width=15% BGCOLOR=#FBF5EF>
\r
13257 <B>TOPSW_MAIN_CTRL</B>
\r
13259 <TD width=15% BGCOLOR=#FBF5EF>
\r
13260 <B>0XFD1A00C0</B>
\r
13262 <TD width=10% BGCOLOR=#FBF5EF>
\r
13265 <TD width=10% BGCOLOR=#FBF5EF>
\r
13268 <TD width=15% BGCOLOR=#FBF5EF>
\r
13269 <B>0x00000000</B>
\r
13271 <TD width=35% BGCOLOR=#FBF5EF>
\r
13277 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13278 <TR valign="top">
\r
13279 <TD width=15% BGCOLOR=#C0FFC0>
\r
13280 <B>Field Name</B>
\r
13282 <TD width=15% BGCOLOR=#C0FFC0>
\r
13285 <TD width=10% BGCOLOR=#C0FFC0>
\r
13288 <TD width=10% BGCOLOR=#C0FFC0>
\r
13291 <TD width=15% BGCOLOR=#C0FFC0>
\r
13292 <B>Shifted Value</B>
\r
13294 <TD width=35% BGCOLOR=#C0FFC0>
\r
13295 <B>Description</B>
\r
13298 <TR valign="top">
\r
13299 <TD width=15% BGCOLOR=#FBF5EF>
\r
13300 <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0</B>
\r
13302 <TD width=15% BGCOLOR=#FBF5EF>
\r
13305 <TD width=10% BGCOLOR=#FBF5EF>
\r
13308 <TD width=10% BGCOLOR=#FBF5EF>
\r
13311 <TD width=15% BGCOLOR=#FBF5EF>
\r
13314 <TD width=35% BGCOLOR=#FBF5EF>
\r
13315 <B>6 bit divider</B>
\r
13318 <TR valign="top">
\r
13319 <TD width=15% BGCOLOR=#FBF5EF>
\r
13320 <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL</B>
\r
13322 <TD width=15% BGCOLOR=#FBF5EF>
\r
13325 <TD width=10% BGCOLOR=#FBF5EF>
\r
13328 <TD width=10% BGCOLOR=#FBF5EF>
\r
13331 <TD width=15% BGCOLOR=#FBF5EF>
\r
13334 <TD width=35% BGCOLOR=#FBF5EF>
\r
13335 <B>000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13338 <TR valign="top">
\r
13339 <TD width=15% BGCOLOR=#FBF5EF>
\r
13340 <B>PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT</B>
\r
13342 <TD width=15% BGCOLOR=#FBF5EF>
\r
13345 <TD width=10% BGCOLOR=#FBF5EF>
\r
13348 <TD width=10% BGCOLOR=#FBF5EF>
\r
13351 <TD width=15% BGCOLOR=#FBF5EF>
\r
13354 <TD width=35% BGCOLOR=#FBF5EF>
\r
13355 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
13358 <TR valign="top">
\r
13359 <TD width=15% BGCOLOR=#C0C0C0>
\r
13360 <B>PSU_CRF_APB_TOPSW_MAIN_CTRL@0XFD1A00C0</B>
\r
13362 <TD width=15% BGCOLOR=#C0C0C0>
\r
13365 <TD width=10% BGCOLOR=#C0C0C0>
\r
13368 <TD width=10% BGCOLOR=#C0C0C0>
\r
13371 <TD width=15% BGCOLOR=#C0C0C0>
\r
13374 <TD width=35% BGCOLOR=#C0C0C0>
\r
13375 <B>This register controls this reference clock</B>
\r
13380 <H2><a name="TOPSW_LSBUS_CTRL">Register (<A href=#mod___slcr> slcr </A>)TOPSW_LSBUS_CTRL</a></H2>
\r
13381 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13382 <TR valign="top">
\r
13383 <TD width=15% BGCOLOR=#FFFF00>
\r
13384 <B>Register Name</B>
\r
13386 <TD width=15% BGCOLOR=#FFFF00>
\r
13389 <TD width=10% BGCOLOR=#FFFF00>
\r
13392 <TD width=10% BGCOLOR=#FFFF00>
\r
13395 <TD width=15% BGCOLOR=#FFFF00>
\r
13396 <B>Reset Value</B>
\r
13398 <TD width=35% BGCOLOR=#FFFF00>
\r
13399 <B>Description</B>
\r
13402 <TR valign="top">
\r
13403 <TD width=15% BGCOLOR=#FBF5EF>
\r
13404 <B>TOPSW_LSBUS_CTRL</B>
\r
13406 <TD width=15% BGCOLOR=#FBF5EF>
\r
13407 <B>0XFD1A00C4</B>
\r
13409 <TD width=10% BGCOLOR=#FBF5EF>
\r
13412 <TD width=10% BGCOLOR=#FBF5EF>
\r
13415 <TD width=15% BGCOLOR=#FBF5EF>
\r
13416 <B>0x00000000</B>
\r
13418 <TD width=35% BGCOLOR=#FBF5EF>
\r
13424 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13425 <TR valign="top">
\r
13426 <TD width=15% BGCOLOR=#C0FFC0>
\r
13427 <B>Field Name</B>
\r
13429 <TD width=15% BGCOLOR=#C0FFC0>
\r
13432 <TD width=10% BGCOLOR=#C0FFC0>
\r
13435 <TD width=10% BGCOLOR=#C0FFC0>
\r
13438 <TD width=15% BGCOLOR=#C0FFC0>
\r
13439 <B>Shifted Value</B>
\r
13441 <TD width=35% BGCOLOR=#C0FFC0>
\r
13442 <B>Description</B>
\r
13445 <TR valign="top">
\r
13446 <TD width=15% BGCOLOR=#FBF5EF>
\r
13447 <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0</B>
\r
13449 <TD width=15% BGCOLOR=#FBF5EF>
\r
13452 <TD width=10% BGCOLOR=#FBF5EF>
\r
13455 <TD width=10% BGCOLOR=#FBF5EF>
\r
13458 <TD width=15% BGCOLOR=#FBF5EF>
\r
13461 <TD width=35% BGCOLOR=#FBF5EF>
\r
13462 <B>6 bit divider</B>
\r
13465 <TR valign="top">
\r
13466 <TD width=15% BGCOLOR=#FBF5EF>
\r
13467 <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL</B>
\r
13469 <TD width=15% BGCOLOR=#FBF5EF>
\r
13472 <TD width=10% BGCOLOR=#FBF5EF>
\r
13475 <TD width=10% BGCOLOR=#FBF5EF>
\r
13478 <TD width=15% BGCOLOR=#FBF5EF>
\r
13481 <TD width=35% BGCOLOR=#FBF5EF>
\r
13482 <B>000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13485 <TR valign="top">
\r
13486 <TD width=15% BGCOLOR=#FBF5EF>
\r
13487 <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT</B>
\r
13489 <TD width=15% BGCOLOR=#FBF5EF>
\r
13492 <TD width=10% BGCOLOR=#FBF5EF>
\r
13495 <TD width=10% BGCOLOR=#FBF5EF>
\r
13498 <TD width=15% BGCOLOR=#FBF5EF>
\r
13501 <TD width=35% BGCOLOR=#FBF5EF>
\r
13502 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
13505 <TR valign="top">
\r
13506 <TD width=15% BGCOLOR=#C0C0C0>
\r
13507 <B>PSU_CRF_APB_TOPSW_LSBUS_CTRL@0XFD1A00C4</B>
\r
13509 <TD width=15% BGCOLOR=#C0C0C0>
\r
13512 <TD width=10% BGCOLOR=#C0C0C0>
\r
13515 <TD width=10% BGCOLOR=#C0C0C0>
\r
13518 <TD width=15% BGCOLOR=#C0C0C0>
\r
13521 <TD width=35% BGCOLOR=#C0C0C0>
\r
13522 <B>This register controls this reference clock</B>
\r
13527 <H2><a name="GTGREF0_REF_CTRL">Register (<A href=#mod___slcr> slcr </A>)GTGREF0_REF_CTRL</a></H2>
\r
13528 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13529 <TR valign="top">
\r
13530 <TD width=15% BGCOLOR=#FFFF00>
\r
13531 <B>Register Name</B>
\r
13533 <TD width=15% BGCOLOR=#FFFF00>
\r
13536 <TD width=10% BGCOLOR=#FFFF00>
\r
13539 <TD width=10% BGCOLOR=#FFFF00>
\r
13542 <TD width=15% BGCOLOR=#FFFF00>
\r
13543 <B>Reset Value</B>
\r
13545 <TD width=35% BGCOLOR=#FFFF00>
\r
13546 <B>Description</B>
\r
13549 <TR valign="top">
\r
13550 <TD width=15% BGCOLOR=#FBF5EF>
\r
13551 <B>GTGREF0_REF_CTRL</B>
\r
13553 <TD width=15% BGCOLOR=#FBF5EF>
\r
13554 <B>0XFD1A00C8</B>
\r
13556 <TD width=10% BGCOLOR=#FBF5EF>
\r
13559 <TD width=10% BGCOLOR=#FBF5EF>
\r
13562 <TD width=15% BGCOLOR=#FBF5EF>
\r
13563 <B>0x00000000</B>
\r
13565 <TD width=35% BGCOLOR=#FBF5EF>
\r
13571 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13572 <TR valign="top">
\r
13573 <TD width=15% BGCOLOR=#C0FFC0>
\r
13574 <B>Field Name</B>
\r
13576 <TD width=15% BGCOLOR=#C0FFC0>
\r
13579 <TD width=10% BGCOLOR=#C0FFC0>
\r
13582 <TD width=10% BGCOLOR=#C0FFC0>
\r
13585 <TD width=15% BGCOLOR=#C0FFC0>
\r
13586 <B>Shifted Value</B>
\r
13588 <TD width=35% BGCOLOR=#C0FFC0>
\r
13589 <B>Description</B>
\r
13592 <TR valign="top">
\r
13593 <TD width=15% BGCOLOR=#FBF5EF>
\r
13594 <B>PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0</B>
\r
13596 <TD width=15% BGCOLOR=#FBF5EF>
\r
13599 <TD width=10% BGCOLOR=#FBF5EF>
\r
13602 <TD width=10% BGCOLOR=#FBF5EF>
\r
13605 <TD width=15% BGCOLOR=#FBF5EF>
\r
13608 <TD width=35% BGCOLOR=#FBF5EF>
\r
13609 <B>6 bit divider</B>
\r
13612 <TR valign="top">
\r
13613 <TD width=15% BGCOLOR=#FBF5EF>
\r
13614 <B>PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL</B>
\r
13616 <TD width=15% BGCOLOR=#FBF5EF>
\r
13619 <TD width=10% BGCOLOR=#FBF5EF>
\r
13622 <TD width=10% BGCOLOR=#FBF5EF>
\r
13625 <TD width=15% BGCOLOR=#FBF5EF>
\r
13628 <TD width=35% BGCOLOR=#FBF5EF>
\r
13629 <B>000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13632 <TR valign="top">
\r
13633 <TD width=15% BGCOLOR=#FBF5EF>
\r
13634 <B>PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT</B>
\r
13636 <TD width=15% BGCOLOR=#FBF5EF>
\r
13639 <TD width=10% BGCOLOR=#FBF5EF>
\r
13642 <TD width=10% BGCOLOR=#FBF5EF>
\r
13645 <TD width=15% BGCOLOR=#FBF5EF>
\r
13648 <TD width=35% BGCOLOR=#FBF5EF>
\r
13649 <B>Clock active signal. Switch to 0 to disable the clock</B>
\r
13652 <TR valign="top">
\r
13653 <TD width=15% BGCOLOR=#C0C0C0>
\r
13654 <B>PSU_CRF_APB_GTGREF0_REF_CTRL@0XFD1A00C8</B>
\r
13656 <TD width=15% BGCOLOR=#C0C0C0>
\r
13659 <TD width=10% BGCOLOR=#C0C0C0>
\r
13662 <TD width=10% BGCOLOR=#C0C0C0>
\r
13665 <TD width=15% BGCOLOR=#C0C0C0>
\r
13668 <TD width=35% BGCOLOR=#C0C0C0>
\r
13669 <B>This register controls this reference clock</B>
\r
13674 <H2><a name="DBG_TSTMP_CTRL">Register (<A href=#mod___slcr> slcr </A>)DBG_TSTMP_CTRL</a></H2>
\r
13675 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13676 <TR valign="top">
\r
13677 <TD width=15% BGCOLOR=#FFFF00>
\r
13678 <B>Register Name</B>
\r
13680 <TD width=15% BGCOLOR=#FFFF00>
\r
13683 <TD width=10% BGCOLOR=#FFFF00>
\r
13686 <TD width=10% BGCOLOR=#FFFF00>
\r
13689 <TD width=15% BGCOLOR=#FFFF00>
\r
13690 <B>Reset Value</B>
\r
13692 <TD width=35% BGCOLOR=#FFFF00>
\r
13693 <B>Description</B>
\r
13696 <TR valign="top">
\r
13697 <TD width=15% BGCOLOR=#FBF5EF>
\r
13698 <B>DBG_TSTMP_CTRL</B>
\r
13700 <TD width=15% BGCOLOR=#FBF5EF>
\r
13701 <B>0XFD1A00F8</B>
\r
13703 <TD width=10% BGCOLOR=#FBF5EF>
\r
13706 <TD width=10% BGCOLOR=#FBF5EF>
\r
13709 <TD width=15% BGCOLOR=#FBF5EF>
\r
13710 <B>0x00000000</B>
\r
13712 <TD width=35% BGCOLOR=#FBF5EF>
\r
13718 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13719 <TR valign="top">
\r
13720 <TD width=15% BGCOLOR=#C0FFC0>
\r
13721 <B>Field Name</B>
\r
13723 <TD width=15% BGCOLOR=#C0FFC0>
\r
13726 <TD width=10% BGCOLOR=#C0FFC0>
\r
13729 <TD width=10% BGCOLOR=#C0FFC0>
\r
13732 <TD width=15% BGCOLOR=#C0FFC0>
\r
13733 <B>Shifted Value</B>
\r
13735 <TD width=35% BGCOLOR=#C0FFC0>
\r
13736 <B>Description</B>
\r
13739 <TR valign="top">
\r
13740 <TD width=15% BGCOLOR=#FBF5EF>
\r
13741 <B>PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0</B>
\r
13743 <TD width=15% BGCOLOR=#FBF5EF>
\r
13746 <TD width=10% BGCOLOR=#FBF5EF>
\r
13749 <TD width=10% BGCOLOR=#FBF5EF>
\r
13752 <TD width=15% BGCOLOR=#FBF5EF>
\r
13755 <TD width=35% BGCOLOR=#FBF5EF>
\r
13756 <B>6 bit divider</B>
\r
13759 <TR valign="top">
\r
13760 <TD width=15% BGCOLOR=#FBF5EF>
\r
13761 <B>PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL</B>
\r
13763 <TD width=15% BGCOLOR=#FBF5EF>
\r
13766 <TD width=10% BGCOLOR=#FBF5EF>
\r
13769 <TD width=10% BGCOLOR=#FBF5EF>
\r
13772 <TD width=15% BGCOLOR=#FBF5EF>
\r
13775 <TD width=35% BGCOLOR=#FBF5EF>
\r
13776 <B>000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)</B>
\r
13779 <TR valign="top">
\r
13780 <TD width=15% BGCOLOR=#C0C0C0>
\r
13781 <B>PSU_CRF_APB_DBG_TSTMP_CTRL@0XFD1A00F8</B>
\r
13783 <TD width=15% BGCOLOR=#C0C0C0>
\r
13786 <TD width=10% BGCOLOR=#C0C0C0>
\r
13789 <TD width=10% BGCOLOR=#C0C0C0>
\r
13792 <TD width=15% BGCOLOR=#C0C0C0>
\r
13795 <TD width=35% BGCOLOR=#C0C0C0>
\r
13796 <B>This register controls this reference clock</B>
\r
13803 <H2><a name="psu_ddr_init_data_3_0">psu_ddr_init_data_3_0</a></H2>
\r
13804 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13805 <TR valign="top">
\r
13806 <TD width=15% BGCOLOR=#FFC0FF>
\r
13807 <B>Register Name</B>
\r
13809 <TD width=15% BGCOLOR=#FFC0FF>
\r
13812 <TD width=10% BGCOLOR=#FFC0FF>
\r
13815 <TD width=10% BGCOLOR=#FFC0FF>
\r
13818 <TD width=15% BGCOLOR=#FFC0FF>
\r
13819 <B>Reset Value</B>
\r
13821 <TD width=35% BGCOLOR=#FFC0FF>
\r
13822 <B>Description</B>
\r
13827 <H2><a name="psu_ddr_init_data_3_0">psu_ddr_init_data_3_0</a></H2>
\r
13828 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13829 <TR valign="top">
\r
13830 <TD width=15% BGCOLOR=#FFC0FF>
\r
13831 <B>Register Name</B>
\r
13833 <TD width=15% BGCOLOR=#FFC0FF>
\r
13836 <TD width=10% BGCOLOR=#FFC0FF>
\r
13839 <TD width=10% BGCOLOR=#FFC0FF>
\r
13842 <TD width=15% BGCOLOR=#FFC0FF>
\r
13843 <B>Reset Value</B>
\r
13845 <TD width=35% BGCOLOR=#FFC0FF>
\r
13846 <B>Description</B>
\r
13851 <H2><a name="psu_mio_init_data">psu_mio_init_data</a></H2>
\r
13852 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
13853 <TR valign="top">
\r
13854 <TD width=15% BGCOLOR=#FFC0FF>
\r
13855 <B>Register Name</B>
\r
13857 <TD width=15% BGCOLOR=#FFC0FF>
\r
13860 <TD width=10% BGCOLOR=#FFC0FF>
\r
13863 <TD width=10% BGCOLOR=#FFC0FF>
\r
13866 <TD width=15% BGCOLOR=#FFC0FF>
\r
13867 <B>Reset Value</B>
\r
13869 <TD width=35% BGCOLOR=#FFC0FF>
\r
13870 <B>Description</B>
\r
13873 <TR valign="top">
\r
13874 <TD width=15% BGCOLOR=#FBF5EF>
\r
13875 <A href="#PSU_IOU_SLCR_MIO_PIN_0">
\r
13876 PSU_IOU_SLCR_MIO_PIN_0
\r
13879 <TD width=15% BGCOLOR=#FBF5EF>
\r
13880 <B>0XFF180000</B>
\r
13882 <TD width=10% BGCOLOR=#FBF5EF>
\r
13885 <TD width=10% BGCOLOR=#FBF5EF>
\r
13888 <TD width=15% BGCOLOR=#FBF5EF>
\r
13891 <TD width=35% BGCOLOR=#FBF5EF>
\r
13892 <B>Configures MIO Pin 0 peripheral interface mapping. S</B>
\r
13895 <TR valign="top">
\r
13896 <TD width=15% BGCOLOR=#FBF5EF>
\r
13897 <A href="#PSU_IOU_SLCR_MIO_PIN_1">
\r
13898 PSU_IOU_SLCR_MIO_PIN_1
\r
13901 <TD width=15% BGCOLOR=#FBF5EF>
\r
13902 <B>0XFF180004</B>
\r
13904 <TD width=10% BGCOLOR=#FBF5EF>
\r
13907 <TD width=10% BGCOLOR=#FBF5EF>
\r
13910 <TD width=15% BGCOLOR=#FBF5EF>
\r
13913 <TD width=35% BGCOLOR=#FBF5EF>
\r
13914 <B>Configures MIO Pin 1 peripheral interface mapping</B>
\r
13917 <TR valign="top">
\r
13918 <TD width=15% BGCOLOR=#FBF5EF>
\r
13919 <A href="#PSU_IOU_SLCR_MIO_PIN_2">
\r
13920 PSU_IOU_SLCR_MIO_PIN_2
\r
13923 <TD width=15% BGCOLOR=#FBF5EF>
\r
13924 <B>0XFF180008</B>
\r
13926 <TD width=10% BGCOLOR=#FBF5EF>
\r
13929 <TD width=10% BGCOLOR=#FBF5EF>
\r
13932 <TD width=15% BGCOLOR=#FBF5EF>
\r
13935 <TD width=35% BGCOLOR=#FBF5EF>
\r
13936 <B>Configures MIO Pin 2 peripheral interface mapping</B>
\r
13939 <TR valign="top">
\r
13940 <TD width=15% BGCOLOR=#FBF5EF>
\r
13941 <A href="#PSU_IOU_SLCR_MIO_PIN_3">
\r
13942 PSU_IOU_SLCR_MIO_PIN_3
\r
13945 <TD width=15% BGCOLOR=#FBF5EF>
\r
13946 <B>0XFF18000C</B>
\r
13948 <TD width=10% BGCOLOR=#FBF5EF>
\r
13951 <TD width=10% BGCOLOR=#FBF5EF>
\r
13954 <TD width=15% BGCOLOR=#FBF5EF>
\r
13957 <TD width=35% BGCOLOR=#FBF5EF>
\r
13958 <B>Configures MIO Pin 3 peripheral interface mapping</B>
\r
13961 <TR valign="top">
\r
13962 <TD width=15% BGCOLOR=#FBF5EF>
\r
13963 <A href="#PSU_IOU_SLCR_MIO_PIN_4">
\r
13964 PSU_IOU_SLCR_MIO_PIN_4
\r
13967 <TD width=15% BGCOLOR=#FBF5EF>
\r
13968 <B>0XFF180010</B>
\r
13970 <TD width=10% BGCOLOR=#FBF5EF>
\r
13973 <TD width=10% BGCOLOR=#FBF5EF>
\r
13976 <TD width=15% BGCOLOR=#FBF5EF>
\r
13979 <TD width=35% BGCOLOR=#FBF5EF>
\r
13980 <B>Configures MIO Pin 4 peripheral interface mapping</B>
\r
13983 <TR valign="top">
\r
13984 <TD width=15% BGCOLOR=#FBF5EF>
\r
13985 <A href="#PSU_IOU_SLCR_MIO_PIN_5">
\r
13986 PSU_IOU_SLCR_MIO_PIN_5
\r
13989 <TD width=15% BGCOLOR=#FBF5EF>
\r
13990 <B>0XFF180014</B>
\r
13992 <TD width=10% BGCOLOR=#FBF5EF>
\r
13995 <TD width=10% BGCOLOR=#FBF5EF>
\r
13998 <TD width=15% BGCOLOR=#FBF5EF>
\r
14001 <TD width=35% BGCOLOR=#FBF5EF>
\r
14002 <B>Configures MIO Pin 5 peripheral interface mapping</B>
\r
14005 <TR valign="top">
\r
14006 <TD width=15% BGCOLOR=#FBF5EF>
\r
14007 <A href="#PSU_IOU_SLCR_MIO_PIN_6">
\r
14008 PSU_IOU_SLCR_MIO_PIN_6
\r
14011 <TD width=15% BGCOLOR=#FBF5EF>
\r
14012 <B>0XFF180018</B>
\r
14014 <TD width=10% BGCOLOR=#FBF5EF>
\r
14017 <TD width=10% BGCOLOR=#FBF5EF>
\r
14020 <TD width=15% BGCOLOR=#FBF5EF>
\r
14023 <TD width=35% BGCOLOR=#FBF5EF>
\r
14024 <B>Configures MIO Pin 6 peripheral interface mapping</B>
\r
14027 <TR valign="top">
\r
14028 <TD width=15% BGCOLOR=#FBF5EF>
\r
14029 <A href="#PSU_IOU_SLCR_MIO_PIN_7">
\r
14030 PSU_IOU_SLCR_MIO_PIN_7
\r
14033 <TD width=15% BGCOLOR=#FBF5EF>
\r
14034 <B>0XFF18001C</B>
\r
14036 <TD width=10% BGCOLOR=#FBF5EF>
\r
14039 <TD width=10% BGCOLOR=#FBF5EF>
\r
14042 <TD width=15% BGCOLOR=#FBF5EF>
\r
14045 <TD width=35% BGCOLOR=#FBF5EF>
\r
14046 <B>Configures MIO Pin 7 peripheral interface mapping</B>
\r
14049 <TR valign="top">
\r
14050 <TD width=15% BGCOLOR=#FBF5EF>
\r
14051 <A href="#PSU_IOU_SLCR_MIO_PIN_8">
\r
14052 PSU_IOU_SLCR_MIO_PIN_8
\r
14055 <TD width=15% BGCOLOR=#FBF5EF>
\r
14056 <B>0XFF180020</B>
\r
14058 <TD width=10% BGCOLOR=#FBF5EF>
\r
14061 <TD width=10% BGCOLOR=#FBF5EF>
\r
14064 <TD width=15% BGCOLOR=#FBF5EF>
\r
14067 <TD width=35% BGCOLOR=#FBF5EF>
\r
14068 <B>Configures MIO Pin 8 peripheral interface mapping</B>
\r
14071 <TR valign="top">
\r
14072 <TD width=15% BGCOLOR=#FBF5EF>
\r
14073 <A href="#PSU_IOU_SLCR_MIO_PIN_9">
\r
14074 PSU_IOU_SLCR_MIO_PIN_9
\r
14077 <TD width=15% BGCOLOR=#FBF5EF>
\r
14078 <B>0XFF180024</B>
\r
14080 <TD width=10% BGCOLOR=#FBF5EF>
\r
14083 <TD width=10% BGCOLOR=#FBF5EF>
\r
14086 <TD width=15% BGCOLOR=#FBF5EF>
\r
14089 <TD width=35% BGCOLOR=#FBF5EF>
\r
14090 <B>Configures MIO Pin 9 peripheral interface mapping</B>
\r
14093 <TR valign="top">
\r
14094 <TD width=15% BGCOLOR=#FBF5EF>
\r
14095 <A href="#PSU_IOU_SLCR_MIO_PIN_10">
\r
14096 PSU_IOU_SLCR_MIO_PIN_10
\r
14099 <TD width=15% BGCOLOR=#FBF5EF>
\r
14100 <B>0XFF180028</B>
\r
14102 <TD width=10% BGCOLOR=#FBF5EF>
\r
14105 <TD width=10% BGCOLOR=#FBF5EF>
\r
14108 <TD width=15% BGCOLOR=#FBF5EF>
\r
14111 <TD width=35% BGCOLOR=#FBF5EF>
\r
14112 <B>Configures MIO Pin 10 peripheral interface mapping</B>
\r
14115 <TR valign="top">
\r
14116 <TD width=15% BGCOLOR=#FBF5EF>
\r
14117 <A href="#PSU_IOU_SLCR_MIO_PIN_11">
\r
14118 PSU_IOU_SLCR_MIO_PIN_11
\r
14121 <TD width=15% BGCOLOR=#FBF5EF>
\r
14122 <B>0XFF18002C</B>
\r
14124 <TD width=10% BGCOLOR=#FBF5EF>
\r
14127 <TD width=10% BGCOLOR=#FBF5EF>
\r
14130 <TD width=15% BGCOLOR=#FBF5EF>
\r
14133 <TD width=35% BGCOLOR=#FBF5EF>
\r
14134 <B>Configures MIO Pin 11 peripheral interface mapping</B>
\r
14137 <TR valign="top">
\r
14138 <TD width=15% BGCOLOR=#FBF5EF>
\r
14139 <A href="#PSU_IOU_SLCR_MIO_PIN_12">
\r
14140 PSU_IOU_SLCR_MIO_PIN_12
\r
14143 <TD width=15% BGCOLOR=#FBF5EF>
\r
14144 <B>0XFF180030</B>
\r
14146 <TD width=10% BGCOLOR=#FBF5EF>
\r
14149 <TD width=10% BGCOLOR=#FBF5EF>
\r
14152 <TD width=15% BGCOLOR=#FBF5EF>
\r
14155 <TD width=35% BGCOLOR=#FBF5EF>
\r
14156 <B>Configures MIO Pin 12 peripheral interface mapping</B>
\r
14159 <TR valign="top">
\r
14160 <TD width=15% BGCOLOR=#FBF5EF>
\r
14161 <A href="#PSU_IOU_SLCR_MIO_PIN_13">
\r
14162 PSU_IOU_SLCR_MIO_PIN_13
\r
14165 <TD width=15% BGCOLOR=#FBF5EF>
\r
14166 <B>0XFF180034</B>
\r
14168 <TD width=10% BGCOLOR=#FBF5EF>
\r
14171 <TD width=10% BGCOLOR=#FBF5EF>
\r
14174 <TD width=15% BGCOLOR=#FBF5EF>
\r
14177 <TD width=35% BGCOLOR=#FBF5EF>
\r
14178 <B>Configures MIO Pin 13 peripheral interface mapping</B>
\r
14181 <TR valign="top">
\r
14182 <TD width=15% BGCOLOR=#FBF5EF>
\r
14183 <A href="#PSU_IOU_SLCR_MIO_PIN_14">
\r
14184 PSU_IOU_SLCR_MIO_PIN_14
\r
14187 <TD width=15% BGCOLOR=#FBF5EF>
\r
14188 <B>0XFF180038</B>
\r
14190 <TD width=10% BGCOLOR=#FBF5EF>
\r
14193 <TD width=10% BGCOLOR=#FBF5EF>
\r
14196 <TD width=15% BGCOLOR=#FBF5EF>
\r
14199 <TD width=35% BGCOLOR=#FBF5EF>
\r
14200 <B>Configures MIO Pin 14 peripheral interface mapping</B>
\r
14203 <TR valign="top">
\r
14204 <TD width=15% BGCOLOR=#FBF5EF>
\r
14205 <A href="#PSU_IOU_SLCR_MIO_PIN_15">
\r
14206 PSU_IOU_SLCR_MIO_PIN_15
\r
14209 <TD width=15% BGCOLOR=#FBF5EF>
\r
14210 <B>0XFF18003C</B>
\r
14212 <TD width=10% BGCOLOR=#FBF5EF>
\r
14215 <TD width=10% BGCOLOR=#FBF5EF>
\r
14218 <TD width=15% BGCOLOR=#FBF5EF>
\r
14221 <TD width=35% BGCOLOR=#FBF5EF>
\r
14222 <B>Configures MIO Pin 15 peripheral interface mapping</B>
\r
14225 <TR valign="top">
\r
14226 <TD width=15% BGCOLOR=#FBF5EF>
\r
14227 <A href="#PSU_IOU_SLCR_MIO_PIN_16">
\r
14228 PSU_IOU_SLCR_MIO_PIN_16
\r
14231 <TD width=15% BGCOLOR=#FBF5EF>
\r
14232 <B>0XFF180040</B>
\r
14234 <TD width=10% BGCOLOR=#FBF5EF>
\r
14237 <TD width=10% BGCOLOR=#FBF5EF>
\r
14240 <TD width=15% BGCOLOR=#FBF5EF>
\r
14243 <TD width=35% BGCOLOR=#FBF5EF>
\r
14244 <B>Configures MIO Pin 16 peripheral interface mapping</B>
\r
14247 <TR valign="top">
\r
14248 <TD width=15% BGCOLOR=#FBF5EF>
\r
14249 <A href="#PSU_IOU_SLCR_MIO_PIN_17">
\r
14250 PSU_IOU_SLCR_MIO_PIN_17
\r
14253 <TD width=15% BGCOLOR=#FBF5EF>
\r
14254 <B>0XFF180044</B>
\r
14256 <TD width=10% BGCOLOR=#FBF5EF>
\r
14259 <TD width=10% BGCOLOR=#FBF5EF>
\r
14262 <TD width=15% BGCOLOR=#FBF5EF>
\r
14265 <TD width=35% BGCOLOR=#FBF5EF>
\r
14266 <B>Configures MIO Pin 17 peripheral interface mapping</B>
\r
14269 <TR valign="top">
\r
14270 <TD width=15% BGCOLOR=#FBF5EF>
\r
14271 <A href="#PSU_IOU_SLCR_MIO_PIN_18">
\r
14272 PSU_IOU_SLCR_MIO_PIN_18
\r
14275 <TD width=15% BGCOLOR=#FBF5EF>
\r
14276 <B>0XFF180048</B>
\r
14278 <TD width=10% BGCOLOR=#FBF5EF>
\r
14281 <TD width=10% BGCOLOR=#FBF5EF>
\r
14284 <TD width=15% BGCOLOR=#FBF5EF>
\r
14287 <TD width=35% BGCOLOR=#FBF5EF>
\r
14288 <B>Configures MIO Pin 18 peripheral interface mapping</B>
\r
14291 <TR valign="top">
\r
14292 <TD width=15% BGCOLOR=#FBF5EF>
\r
14293 <A href="#PSU_IOU_SLCR_MIO_PIN_19">
\r
14294 PSU_IOU_SLCR_MIO_PIN_19
\r
14297 <TD width=15% BGCOLOR=#FBF5EF>
\r
14298 <B>0XFF18004C</B>
\r
14300 <TD width=10% BGCOLOR=#FBF5EF>
\r
14303 <TD width=10% BGCOLOR=#FBF5EF>
\r
14306 <TD width=15% BGCOLOR=#FBF5EF>
\r
14309 <TD width=35% BGCOLOR=#FBF5EF>
\r
14310 <B>Configures MIO Pin 19 peripheral interface mapping</B>
\r
14313 <TR valign="top">
\r
14314 <TD width=15% BGCOLOR=#FBF5EF>
\r
14315 <A href="#PSU_IOU_SLCR_MIO_PIN_20">
\r
14316 PSU_IOU_SLCR_MIO_PIN_20
\r
14319 <TD width=15% BGCOLOR=#FBF5EF>
\r
14320 <B>0XFF180050</B>
\r
14322 <TD width=10% BGCOLOR=#FBF5EF>
\r
14325 <TD width=10% BGCOLOR=#FBF5EF>
\r
14328 <TD width=15% BGCOLOR=#FBF5EF>
\r
14331 <TD width=35% BGCOLOR=#FBF5EF>
\r
14332 <B>Configures MIO Pin 20 peripheral interface mapping</B>
\r
14335 <TR valign="top">
\r
14336 <TD width=15% BGCOLOR=#FBF5EF>
\r
14337 <A href="#PSU_IOU_SLCR_MIO_PIN_21">
\r
14338 PSU_IOU_SLCR_MIO_PIN_21
\r
14341 <TD width=15% BGCOLOR=#FBF5EF>
\r
14342 <B>0XFF180054</B>
\r
14344 <TD width=10% BGCOLOR=#FBF5EF>
\r
14347 <TD width=10% BGCOLOR=#FBF5EF>
\r
14350 <TD width=15% BGCOLOR=#FBF5EF>
\r
14353 <TD width=35% BGCOLOR=#FBF5EF>
\r
14354 <B>Configures MIO Pin 21 peripheral interface mapping</B>
\r
14357 <TR valign="top">
\r
14358 <TD width=15% BGCOLOR=#FBF5EF>
\r
14359 <A href="#PSU_IOU_SLCR_MIO_PIN_22">
\r
14360 PSU_IOU_SLCR_MIO_PIN_22
\r
14363 <TD width=15% BGCOLOR=#FBF5EF>
\r
14364 <B>0XFF180058</B>
\r
14366 <TD width=10% BGCOLOR=#FBF5EF>
\r
14369 <TD width=10% BGCOLOR=#FBF5EF>
\r
14372 <TD width=15% BGCOLOR=#FBF5EF>
\r
14375 <TD width=35% BGCOLOR=#FBF5EF>
\r
14376 <B>Configures MIO Pin 22 peripheral interface mapping</B>
\r
14379 <TR valign="top">
\r
14380 <TD width=15% BGCOLOR=#FBF5EF>
\r
14381 <A href="#PSU_IOU_SLCR_MIO_PIN_23">
\r
14382 PSU_IOU_SLCR_MIO_PIN_23
\r
14385 <TD width=15% BGCOLOR=#FBF5EF>
\r
14386 <B>0XFF18005C</B>
\r
14388 <TD width=10% BGCOLOR=#FBF5EF>
\r
14391 <TD width=10% BGCOLOR=#FBF5EF>
\r
14394 <TD width=15% BGCOLOR=#FBF5EF>
\r
14397 <TD width=35% BGCOLOR=#FBF5EF>
\r
14398 <B>Configures MIO Pin 23 peripheral interface mapping</B>
\r
14401 <TR valign="top">
\r
14402 <TD width=15% BGCOLOR=#FBF5EF>
\r
14403 <A href="#PSU_IOU_SLCR_MIO_PIN_24">
\r
14404 PSU_IOU_SLCR_MIO_PIN_24
\r
14407 <TD width=15% BGCOLOR=#FBF5EF>
\r
14408 <B>0XFF180060</B>
\r
14410 <TD width=10% BGCOLOR=#FBF5EF>
\r
14413 <TD width=10% BGCOLOR=#FBF5EF>
\r
14416 <TD width=15% BGCOLOR=#FBF5EF>
\r
14419 <TD width=35% BGCOLOR=#FBF5EF>
\r
14420 <B>Configures MIO Pin 24 peripheral interface mapping</B>
\r
14423 <TR valign="top">
\r
14424 <TD width=15% BGCOLOR=#FBF5EF>
\r
14425 <A href="#PSU_IOU_SLCR_MIO_PIN_25">
\r
14426 PSU_IOU_SLCR_MIO_PIN_25
\r
14429 <TD width=15% BGCOLOR=#FBF5EF>
\r
14430 <B>0XFF180064</B>
\r
14432 <TD width=10% BGCOLOR=#FBF5EF>
\r
14435 <TD width=10% BGCOLOR=#FBF5EF>
\r
14438 <TD width=15% BGCOLOR=#FBF5EF>
\r
14441 <TD width=35% BGCOLOR=#FBF5EF>
\r
14442 <B>Configures MIO Pin 25 peripheral interface mapping</B>
\r
14445 <TR valign="top">
\r
14446 <TD width=15% BGCOLOR=#FBF5EF>
\r
14447 <A href="#PSU_IOU_SLCR_MIO_PIN_26">
\r
14448 PSU_IOU_SLCR_MIO_PIN_26
\r
14451 <TD width=15% BGCOLOR=#FBF5EF>
\r
14452 <B>0XFF180068</B>
\r
14454 <TD width=10% BGCOLOR=#FBF5EF>
\r
14457 <TD width=10% BGCOLOR=#FBF5EF>
\r
14460 <TD width=15% BGCOLOR=#FBF5EF>
\r
14463 <TD width=35% BGCOLOR=#FBF5EF>
\r
14464 <B>Configures MIO Pin 26 peripheral interface mapping</B>
\r
14467 <TR valign="top">
\r
14468 <TD width=15% BGCOLOR=#FBF5EF>
\r
14469 <A href="#PSU_IOU_SLCR_MIO_PIN_27">
\r
14470 PSU_IOU_SLCR_MIO_PIN_27
\r
14473 <TD width=15% BGCOLOR=#FBF5EF>
\r
14474 <B>0XFF18006C</B>
\r
14476 <TD width=10% BGCOLOR=#FBF5EF>
\r
14479 <TD width=10% BGCOLOR=#FBF5EF>
\r
14482 <TD width=15% BGCOLOR=#FBF5EF>
\r
14485 <TD width=35% BGCOLOR=#FBF5EF>
\r
14486 <B>Configures MIO Pin 27 peripheral interface mapping</B>
\r
14489 <TR valign="top">
\r
14490 <TD width=15% BGCOLOR=#FBF5EF>
\r
14491 <A href="#PSU_IOU_SLCR_MIO_PIN_28">
\r
14492 PSU_IOU_SLCR_MIO_PIN_28
\r
14495 <TD width=15% BGCOLOR=#FBF5EF>
\r
14496 <B>0XFF180070</B>
\r
14498 <TD width=10% BGCOLOR=#FBF5EF>
\r
14501 <TD width=10% BGCOLOR=#FBF5EF>
\r
14504 <TD width=15% BGCOLOR=#FBF5EF>
\r
14507 <TD width=35% BGCOLOR=#FBF5EF>
\r
14508 <B>Configures MIO Pin 28 peripheral interface mapping</B>
\r
14511 <TR valign="top">
\r
14512 <TD width=15% BGCOLOR=#FBF5EF>
\r
14513 <A href="#PSU_IOU_SLCR_MIO_PIN_29">
\r
14514 PSU_IOU_SLCR_MIO_PIN_29
\r
14517 <TD width=15% BGCOLOR=#FBF5EF>
\r
14518 <B>0XFF180074</B>
\r
14520 <TD width=10% BGCOLOR=#FBF5EF>
\r
14523 <TD width=10% BGCOLOR=#FBF5EF>
\r
14526 <TD width=15% BGCOLOR=#FBF5EF>
\r
14529 <TD width=35% BGCOLOR=#FBF5EF>
\r
14530 <B>Configures MIO Pin 29 peripheral interface mapping</B>
\r
14533 <TR valign="top">
\r
14534 <TD width=15% BGCOLOR=#FBF5EF>
\r
14535 <A href="#PSU_IOU_SLCR_MIO_PIN_30">
\r
14536 PSU_IOU_SLCR_MIO_PIN_30
\r
14539 <TD width=15% BGCOLOR=#FBF5EF>
\r
14540 <B>0XFF180078</B>
\r
14542 <TD width=10% BGCOLOR=#FBF5EF>
\r
14545 <TD width=10% BGCOLOR=#FBF5EF>
\r
14548 <TD width=15% BGCOLOR=#FBF5EF>
\r
14551 <TD width=35% BGCOLOR=#FBF5EF>
\r
14552 <B>Configures MIO Pin 30 peripheral interface mapping</B>
\r
14555 <TR valign="top">
\r
14556 <TD width=15% BGCOLOR=#FBF5EF>
\r
14557 <A href="#PSU_IOU_SLCR_MIO_PIN_31">
\r
14558 PSU_IOU_SLCR_MIO_PIN_31
\r
14561 <TD width=15% BGCOLOR=#FBF5EF>
\r
14562 <B>0XFF18007C</B>
\r
14564 <TD width=10% BGCOLOR=#FBF5EF>
\r
14567 <TD width=10% BGCOLOR=#FBF5EF>
\r
14570 <TD width=15% BGCOLOR=#FBF5EF>
\r
14573 <TD width=35% BGCOLOR=#FBF5EF>
\r
14574 <B>Configures MIO Pin 31 peripheral interface mapping</B>
\r
14577 <TR valign="top">
\r
14578 <TD width=15% BGCOLOR=#FBF5EF>
\r
14579 <A href="#PSU_IOU_SLCR_MIO_PIN_32">
\r
14580 PSU_IOU_SLCR_MIO_PIN_32
\r
14583 <TD width=15% BGCOLOR=#FBF5EF>
\r
14584 <B>0XFF180080</B>
\r
14586 <TD width=10% BGCOLOR=#FBF5EF>
\r
14589 <TD width=10% BGCOLOR=#FBF5EF>
\r
14592 <TD width=15% BGCOLOR=#FBF5EF>
\r
14595 <TD width=35% BGCOLOR=#FBF5EF>
\r
14596 <B>Configures MIO Pin 32 peripheral interface mapping</B>
\r
14599 <TR valign="top">
\r
14600 <TD width=15% BGCOLOR=#FBF5EF>
\r
14601 <A href="#PSU_IOU_SLCR_MIO_PIN_33">
\r
14602 PSU_IOU_SLCR_MIO_PIN_33
\r
14605 <TD width=15% BGCOLOR=#FBF5EF>
\r
14606 <B>0XFF180084</B>
\r
14608 <TD width=10% BGCOLOR=#FBF5EF>
\r
14611 <TD width=10% BGCOLOR=#FBF5EF>
\r
14614 <TD width=15% BGCOLOR=#FBF5EF>
\r
14617 <TD width=35% BGCOLOR=#FBF5EF>
\r
14618 <B>Configures MIO Pin 33 peripheral interface mapping</B>
\r
14621 <TR valign="top">
\r
14622 <TD width=15% BGCOLOR=#FBF5EF>
\r
14623 <A href="#PSU_IOU_SLCR_MIO_PIN_34">
\r
14624 PSU_IOU_SLCR_MIO_PIN_34
\r
14627 <TD width=15% BGCOLOR=#FBF5EF>
\r
14628 <B>0XFF180088</B>
\r
14630 <TD width=10% BGCOLOR=#FBF5EF>
\r
14633 <TD width=10% BGCOLOR=#FBF5EF>
\r
14636 <TD width=15% BGCOLOR=#FBF5EF>
\r
14639 <TD width=35% BGCOLOR=#FBF5EF>
\r
14640 <B>Configures MIO Pin 34 peripheral interface mapping</B>
\r
14643 <TR valign="top">
\r
14644 <TD width=15% BGCOLOR=#FBF5EF>
\r
14645 <A href="#PSU_IOU_SLCR_MIO_PIN_35">
\r
14646 PSU_IOU_SLCR_MIO_PIN_35
\r
14649 <TD width=15% BGCOLOR=#FBF5EF>
\r
14650 <B>0XFF18008C</B>
\r
14652 <TD width=10% BGCOLOR=#FBF5EF>
\r
14655 <TD width=10% BGCOLOR=#FBF5EF>
\r
14658 <TD width=15% BGCOLOR=#FBF5EF>
\r
14661 <TD width=35% BGCOLOR=#FBF5EF>
\r
14662 <B>Configures MIO Pin 35 peripheral interface mapping</B>
\r
14665 <TR valign="top">
\r
14666 <TD width=15% BGCOLOR=#FBF5EF>
\r
14667 <A href="#PSU_IOU_SLCR_MIO_PIN_36">
\r
14668 PSU_IOU_SLCR_MIO_PIN_36
\r
14671 <TD width=15% BGCOLOR=#FBF5EF>
\r
14672 <B>0XFF180090</B>
\r
14674 <TD width=10% BGCOLOR=#FBF5EF>
\r
14677 <TD width=10% BGCOLOR=#FBF5EF>
\r
14680 <TD width=15% BGCOLOR=#FBF5EF>
\r
14683 <TD width=35% BGCOLOR=#FBF5EF>
\r
14684 <B>Configures MIO Pin 36 peripheral interface mapping</B>
\r
14687 <TR valign="top">
\r
14688 <TD width=15% BGCOLOR=#FBF5EF>
\r
14689 <A href="#PSU_IOU_SLCR_MIO_PIN_37">
\r
14690 PSU_IOU_SLCR_MIO_PIN_37
\r
14693 <TD width=15% BGCOLOR=#FBF5EF>
\r
14694 <B>0XFF180094</B>
\r
14696 <TD width=10% BGCOLOR=#FBF5EF>
\r
14699 <TD width=10% BGCOLOR=#FBF5EF>
\r
14702 <TD width=15% BGCOLOR=#FBF5EF>
\r
14705 <TD width=35% BGCOLOR=#FBF5EF>
\r
14706 <B>Configures MIO Pin 37 peripheral interface mapping</B>
\r
14709 <TR valign="top">
\r
14710 <TD width=15% BGCOLOR=#FBF5EF>
\r
14711 <A href="#PSU_IOU_SLCR_MIO_PIN_38">
\r
14712 PSU_IOU_SLCR_MIO_PIN_38
\r
14715 <TD width=15% BGCOLOR=#FBF5EF>
\r
14716 <B>0XFF180098</B>
\r
14718 <TD width=10% BGCOLOR=#FBF5EF>
\r
14721 <TD width=10% BGCOLOR=#FBF5EF>
\r
14724 <TD width=15% BGCOLOR=#FBF5EF>
\r
14727 <TD width=35% BGCOLOR=#FBF5EF>
\r
14728 <B>Configures MIO Pin 38 peripheral interface mapping</B>
\r
14731 <TR valign="top">
\r
14732 <TD width=15% BGCOLOR=#FBF5EF>
\r
14733 <A href="#PSU_IOU_SLCR_MIO_PIN_39">
\r
14734 PSU_IOU_SLCR_MIO_PIN_39
\r
14737 <TD width=15% BGCOLOR=#FBF5EF>
\r
14738 <B>0XFF18009C</B>
\r
14740 <TD width=10% BGCOLOR=#FBF5EF>
\r
14743 <TD width=10% BGCOLOR=#FBF5EF>
\r
14746 <TD width=15% BGCOLOR=#FBF5EF>
\r
14749 <TD width=35% BGCOLOR=#FBF5EF>
\r
14750 <B>Configures MIO Pin 39 peripheral interface mapping</B>
\r
14753 <TR valign="top">
\r
14754 <TD width=15% BGCOLOR=#FBF5EF>
\r
14755 <A href="#PSU_IOU_SLCR_MIO_PIN_40">
\r
14756 PSU_IOU_SLCR_MIO_PIN_40
\r
14759 <TD width=15% BGCOLOR=#FBF5EF>
\r
14760 <B>0XFF1800A0</B>
\r
14762 <TD width=10% BGCOLOR=#FBF5EF>
\r
14765 <TD width=10% BGCOLOR=#FBF5EF>
\r
14768 <TD width=15% BGCOLOR=#FBF5EF>
\r
14771 <TD width=35% BGCOLOR=#FBF5EF>
\r
14772 <B>Configures MIO Pin 40 peripheral interface mapping</B>
\r
14775 <TR valign="top">
\r
14776 <TD width=15% BGCOLOR=#FBF5EF>
\r
14777 <A href="#PSU_IOU_SLCR_MIO_PIN_41">
\r
14778 PSU_IOU_SLCR_MIO_PIN_41
\r
14781 <TD width=15% BGCOLOR=#FBF5EF>
\r
14782 <B>0XFF1800A4</B>
\r
14784 <TD width=10% BGCOLOR=#FBF5EF>
\r
14787 <TD width=10% BGCOLOR=#FBF5EF>
\r
14790 <TD width=15% BGCOLOR=#FBF5EF>
\r
14793 <TD width=35% BGCOLOR=#FBF5EF>
\r
14794 <B>Configures MIO Pin 41 peripheral interface mapping</B>
\r
14797 <TR valign="top">
\r
14798 <TD width=15% BGCOLOR=#FBF5EF>
\r
14799 <A href="#PSU_IOU_SLCR_MIO_PIN_42">
\r
14800 PSU_IOU_SLCR_MIO_PIN_42
\r
14803 <TD width=15% BGCOLOR=#FBF5EF>
\r
14804 <B>0XFF1800A8</B>
\r
14806 <TD width=10% BGCOLOR=#FBF5EF>
\r
14809 <TD width=10% BGCOLOR=#FBF5EF>
\r
14812 <TD width=15% BGCOLOR=#FBF5EF>
\r
14815 <TD width=35% BGCOLOR=#FBF5EF>
\r
14816 <B>Configures MIO Pin 42 peripheral interface mapping</B>
\r
14819 <TR valign="top">
\r
14820 <TD width=15% BGCOLOR=#FBF5EF>
\r
14821 <A href="#PSU_IOU_SLCR_MIO_PIN_43">
\r
14822 PSU_IOU_SLCR_MIO_PIN_43
\r
14825 <TD width=15% BGCOLOR=#FBF5EF>
\r
14826 <B>0XFF1800AC</B>
\r
14828 <TD width=10% BGCOLOR=#FBF5EF>
\r
14831 <TD width=10% BGCOLOR=#FBF5EF>
\r
14834 <TD width=15% BGCOLOR=#FBF5EF>
\r
14837 <TD width=35% BGCOLOR=#FBF5EF>
\r
14838 <B>Configures MIO Pin 43 peripheral interface mapping</B>
\r
14841 <TR valign="top">
\r
14842 <TD width=15% BGCOLOR=#FBF5EF>
\r
14843 <A href="#PSU_IOU_SLCR_MIO_PIN_44">
\r
14844 PSU_IOU_SLCR_MIO_PIN_44
\r
14847 <TD width=15% BGCOLOR=#FBF5EF>
\r
14848 <B>0XFF1800B0</B>
\r
14850 <TD width=10% BGCOLOR=#FBF5EF>
\r
14853 <TD width=10% BGCOLOR=#FBF5EF>
\r
14856 <TD width=15% BGCOLOR=#FBF5EF>
\r
14859 <TD width=35% BGCOLOR=#FBF5EF>
\r
14860 <B>Configures MIO Pin 44 peripheral interface mapping</B>
\r
14863 <TR valign="top">
\r
14864 <TD width=15% BGCOLOR=#FBF5EF>
\r
14865 <A href="#PSU_IOU_SLCR_MIO_PIN_45">
\r
14866 PSU_IOU_SLCR_MIO_PIN_45
\r
14869 <TD width=15% BGCOLOR=#FBF5EF>
\r
14870 <B>0XFF1800B4</B>
\r
14872 <TD width=10% BGCOLOR=#FBF5EF>
\r
14875 <TD width=10% BGCOLOR=#FBF5EF>
\r
14878 <TD width=15% BGCOLOR=#FBF5EF>
\r
14881 <TD width=35% BGCOLOR=#FBF5EF>
\r
14882 <B>Configures MIO Pin 45 peripheral interface mapping</B>
\r
14885 <TR valign="top">
\r
14886 <TD width=15% BGCOLOR=#FBF5EF>
\r
14887 <A href="#PSU_IOU_SLCR_MIO_PIN_46">
\r
14888 PSU_IOU_SLCR_MIO_PIN_46
\r
14891 <TD width=15% BGCOLOR=#FBF5EF>
\r
14892 <B>0XFF1800B8</B>
\r
14894 <TD width=10% BGCOLOR=#FBF5EF>
\r
14897 <TD width=10% BGCOLOR=#FBF5EF>
\r
14900 <TD width=15% BGCOLOR=#FBF5EF>
\r
14903 <TD width=35% BGCOLOR=#FBF5EF>
\r
14904 <B>Configures MIO Pin 46 peripheral interface mapping</B>
\r
14907 <TR valign="top">
\r
14908 <TD width=15% BGCOLOR=#FBF5EF>
\r
14909 <A href="#PSU_IOU_SLCR_MIO_PIN_47">
\r
14910 PSU_IOU_SLCR_MIO_PIN_47
\r
14913 <TD width=15% BGCOLOR=#FBF5EF>
\r
14914 <B>0XFF1800BC</B>
\r
14916 <TD width=10% BGCOLOR=#FBF5EF>
\r
14919 <TD width=10% BGCOLOR=#FBF5EF>
\r
14922 <TD width=15% BGCOLOR=#FBF5EF>
\r
14925 <TD width=35% BGCOLOR=#FBF5EF>
\r
14926 <B>Configures MIO Pin 47 peripheral interface mapping</B>
\r
14929 <TR valign="top">
\r
14930 <TD width=15% BGCOLOR=#FBF5EF>
\r
14931 <A href="#PSU_IOU_SLCR_MIO_PIN_48">
\r
14932 PSU_IOU_SLCR_MIO_PIN_48
\r
14935 <TD width=15% BGCOLOR=#FBF5EF>
\r
14936 <B>0XFF1800C0</B>
\r
14938 <TD width=10% BGCOLOR=#FBF5EF>
\r
14941 <TD width=10% BGCOLOR=#FBF5EF>
\r
14944 <TD width=15% BGCOLOR=#FBF5EF>
\r
14947 <TD width=35% BGCOLOR=#FBF5EF>
\r
14948 <B>Configures MIO Pin 48 peripheral interface mapping</B>
\r
14951 <TR valign="top">
\r
14952 <TD width=15% BGCOLOR=#FBF5EF>
\r
14953 <A href="#PSU_IOU_SLCR_MIO_PIN_49">
\r
14954 PSU_IOU_SLCR_MIO_PIN_49
\r
14957 <TD width=15% BGCOLOR=#FBF5EF>
\r
14958 <B>0XFF1800C4</B>
\r
14960 <TD width=10% BGCOLOR=#FBF5EF>
\r
14963 <TD width=10% BGCOLOR=#FBF5EF>
\r
14966 <TD width=15% BGCOLOR=#FBF5EF>
\r
14969 <TD width=35% BGCOLOR=#FBF5EF>
\r
14970 <B>Configures MIO Pin 49 peripheral interface mapping</B>
\r
14973 <TR valign="top">
\r
14974 <TD width=15% BGCOLOR=#FBF5EF>
\r
14975 <A href="#PSU_IOU_SLCR_MIO_PIN_50">
\r
14976 PSU_IOU_SLCR_MIO_PIN_50
\r
14979 <TD width=15% BGCOLOR=#FBF5EF>
\r
14980 <B>0XFF1800C8</B>
\r
14982 <TD width=10% BGCOLOR=#FBF5EF>
\r
14985 <TD width=10% BGCOLOR=#FBF5EF>
\r
14988 <TD width=15% BGCOLOR=#FBF5EF>
\r
14991 <TD width=35% BGCOLOR=#FBF5EF>
\r
14992 <B>Configures MIO Pin 50 peripheral interface mapping</B>
\r
14995 <TR valign="top">
\r
14996 <TD width=15% BGCOLOR=#FBF5EF>
\r
14997 <A href="#PSU_IOU_SLCR_MIO_PIN_51">
\r
14998 PSU_IOU_SLCR_MIO_PIN_51
\r
15001 <TD width=15% BGCOLOR=#FBF5EF>
\r
15002 <B>0XFF1800CC</B>
\r
15004 <TD width=10% BGCOLOR=#FBF5EF>
\r
15007 <TD width=10% BGCOLOR=#FBF5EF>
\r
15010 <TD width=15% BGCOLOR=#FBF5EF>
\r
15013 <TD width=35% BGCOLOR=#FBF5EF>
\r
15014 <B>Configures MIO Pin 51 peripheral interface mapping</B>
\r
15017 <TR valign="top">
\r
15018 <TD width=15% BGCOLOR=#FBF5EF>
\r
15019 <A href="#PSU_IOU_SLCR_MIO_PIN_52">
\r
15020 PSU_IOU_SLCR_MIO_PIN_52
\r
15023 <TD width=15% BGCOLOR=#FBF5EF>
\r
15024 <B>0XFF1800D0</B>
\r
15026 <TD width=10% BGCOLOR=#FBF5EF>
\r
15029 <TD width=10% BGCOLOR=#FBF5EF>
\r
15032 <TD width=15% BGCOLOR=#FBF5EF>
\r
15035 <TD width=35% BGCOLOR=#FBF5EF>
\r
15036 <B>Configures MIO Pin 52 peripheral interface mapping</B>
\r
15039 <TR valign="top">
\r
15040 <TD width=15% BGCOLOR=#FBF5EF>
\r
15041 <A href="#PSU_IOU_SLCR_MIO_PIN_53">
\r
15042 PSU_IOU_SLCR_MIO_PIN_53
\r
15045 <TD width=15% BGCOLOR=#FBF5EF>
\r
15046 <B>0XFF1800D4</B>
\r
15048 <TD width=10% BGCOLOR=#FBF5EF>
\r
15051 <TD width=10% BGCOLOR=#FBF5EF>
\r
15054 <TD width=15% BGCOLOR=#FBF5EF>
\r
15057 <TD width=35% BGCOLOR=#FBF5EF>
\r
15058 <B>Configures MIO Pin 53 peripheral interface mapping</B>
\r
15061 <TR valign="top">
\r
15062 <TD width=15% BGCOLOR=#FBF5EF>
\r
15063 <A href="#PSU_IOU_SLCR_MIO_PIN_54">
\r
15064 PSU_IOU_SLCR_MIO_PIN_54
\r
15067 <TD width=15% BGCOLOR=#FBF5EF>
\r
15068 <B>0XFF1800D8</B>
\r
15070 <TD width=10% BGCOLOR=#FBF5EF>
\r
15073 <TD width=10% BGCOLOR=#FBF5EF>
\r
15076 <TD width=15% BGCOLOR=#FBF5EF>
\r
15079 <TD width=35% BGCOLOR=#FBF5EF>
\r
15080 <B>Configures MIO Pin 54 peripheral interface mapping</B>
\r
15083 <TR valign="top">
\r
15084 <TD width=15% BGCOLOR=#FBF5EF>
\r
15085 <A href="#PSU_IOU_SLCR_MIO_PIN_55">
\r
15086 PSU_IOU_SLCR_MIO_PIN_55
\r
15089 <TD width=15% BGCOLOR=#FBF5EF>
\r
15090 <B>0XFF1800DC</B>
\r
15092 <TD width=10% BGCOLOR=#FBF5EF>
\r
15095 <TD width=10% BGCOLOR=#FBF5EF>
\r
15098 <TD width=15% BGCOLOR=#FBF5EF>
\r
15101 <TD width=35% BGCOLOR=#FBF5EF>
\r
15102 <B>Configures MIO Pin 55 peripheral interface mapping</B>
\r
15105 <TR valign="top">
\r
15106 <TD width=15% BGCOLOR=#FBF5EF>
\r
15107 <A href="#PSU_IOU_SLCR_MIO_PIN_56">
\r
15108 PSU_IOU_SLCR_MIO_PIN_56
\r
15111 <TD width=15% BGCOLOR=#FBF5EF>
\r
15112 <B>0XFF1800E0</B>
\r
15114 <TD width=10% BGCOLOR=#FBF5EF>
\r
15117 <TD width=10% BGCOLOR=#FBF5EF>
\r
15120 <TD width=15% BGCOLOR=#FBF5EF>
\r
15123 <TD width=35% BGCOLOR=#FBF5EF>
\r
15124 <B>Configures MIO Pin 56 peripheral interface mapping</B>
\r
15127 <TR valign="top">
\r
15128 <TD width=15% BGCOLOR=#FBF5EF>
\r
15129 <A href="#PSU_IOU_SLCR_MIO_PIN_57">
\r
15130 PSU_IOU_SLCR_MIO_PIN_57
\r
15133 <TD width=15% BGCOLOR=#FBF5EF>
\r
15134 <B>0XFF1800E4</B>
\r
15136 <TD width=10% BGCOLOR=#FBF5EF>
\r
15139 <TD width=10% BGCOLOR=#FBF5EF>
\r
15142 <TD width=15% BGCOLOR=#FBF5EF>
\r
15145 <TD width=35% BGCOLOR=#FBF5EF>
\r
15146 <B>Configures MIO Pin 57 peripheral interface mapping</B>
\r
15149 <TR valign="top">
\r
15150 <TD width=15% BGCOLOR=#FBF5EF>
\r
15151 <A href="#PSU_IOU_SLCR_MIO_PIN_58">
\r
15152 PSU_IOU_SLCR_MIO_PIN_58
\r
15155 <TD width=15% BGCOLOR=#FBF5EF>
\r
15156 <B>0XFF1800E8</B>
\r
15158 <TD width=10% BGCOLOR=#FBF5EF>
\r
15161 <TD width=10% BGCOLOR=#FBF5EF>
\r
15164 <TD width=15% BGCOLOR=#FBF5EF>
\r
15167 <TD width=35% BGCOLOR=#FBF5EF>
\r
15168 <B>Configures MIO Pin 58 peripheral interface mapping</B>
\r
15171 <TR valign="top">
\r
15172 <TD width=15% BGCOLOR=#FBF5EF>
\r
15173 <A href="#PSU_IOU_SLCR_MIO_PIN_59">
\r
15174 PSU_IOU_SLCR_MIO_PIN_59
\r
15177 <TD width=15% BGCOLOR=#FBF5EF>
\r
15178 <B>0XFF1800EC</B>
\r
15180 <TD width=10% BGCOLOR=#FBF5EF>
\r
15183 <TD width=10% BGCOLOR=#FBF5EF>
\r
15186 <TD width=15% BGCOLOR=#FBF5EF>
\r
15189 <TD width=35% BGCOLOR=#FBF5EF>
\r
15190 <B>Configures MIO Pin 59 peripheral interface mapping</B>
\r
15193 <TR valign="top">
\r
15194 <TD width=15% BGCOLOR=#FBF5EF>
\r
15195 <A href="#PSU_IOU_SLCR_MIO_PIN_60">
\r
15196 PSU_IOU_SLCR_MIO_PIN_60
\r
15199 <TD width=15% BGCOLOR=#FBF5EF>
\r
15200 <B>0XFF1800F0</B>
\r
15202 <TD width=10% BGCOLOR=#FBF5EF>
\r
15205 <TD width=10% BGCOLOR=#FBF5EF>
\r
15208 <TD width=15% BGCOLOR=#FBF5EF>
\r
15211 <TD width=35% BGCOLOR=#FBF5EF>
\r
15212 <B>Configures MIO Pin 60 peripheral interface mapping</B>
\r
15215 <TR valign="top">
\r
15216 <TD width=15% BGCOLOR=#FBF5EF>
\r
15217 <A href="#PSU_IOU_SLCR_MIO_PIN_61">
\r
15218 PSU_IOU_SLCR_MIO_PIN_61
\r
15221 <TD width=15% BGCOLOR=#FBF5EF>
\r
15222 <B>0XFF1800F4</B>
\r
15224 <TD width=10% BGCOLOR=#FBF5EF>
\r
15227 <TD width=10% BGCOLOR=#FBF5EF>
\r
15230 <TD width=15% BGCOLOR=#FBF5EF>
\r
15233 <TD width=35% BGCOLOR=#FBF5EF>
\r
15234 <B>Configures MIO Pin 61 peripheral interface mapping</B>
\r
15237 <TR valign="top">
\r
15238 <TD width=15% BGCOLOR=#FBF5EF>
\r
15239 <A href="#PSU_IOU_SLCR_MIO_PIN_62">
\r
15240 PSU_IOU_SLCR_MIO_PIN_62
\r
15243 <TD width=15% BGCOLOR=#FBF5EF>
\r
15244 <B>0XFF1800F8</B>
\r
15246 <TD width=10% BGCOLOR=#FBF5EF>
\r
15249 <TD width=10% BGCOLOR=#FBF5EF>
\r
15252 <TD width=15% BGCOLOR=#FBF5EF>
\r
15255 <TD width=35% BGCOLOR=#FBF5EF>
\r
15256 <B>Configures MIO Pin 62 peripheral interface mapping</B>
\r
15259 <TR valign="top">
\r
15260 <TD width=15% BGCOLOR=#FBF5EF>
\r
15261 <A href="#PSU_IOU_SLCR_MIO_PIN_63">
\r
15262 PSU_IOU_SLCR_MIO_PIN_63
\r
15265 <TD width=15% BGCOLOR=#FBF5EF>
\r
15266 <B>0XFF1800FC</B>
\r
15268 <TD width=10% BGCOLOR=#FBF5EF>
\r
15271 <TD width=10% BGCOLOR=#FBF5EF>
\r
15274 <TD width=15% BGCOLOR=#FBF5EF>
\r
15277 <TD width=35% BGCOLOR=#FBF5EF>
\r
15278 <B>Configures MIO Pin 63 peripheral interface mapping</B>
\r
15281 <TR valign="top">
\r
15282 <TD width=15% BGCOLOR=#FBF5EF>
\r
15283 <A href="#PSU_IOU_SLCR_MIO_PIN_64">
\r
15284 PSU_IOU_SLCR_MIO_PIN_64
\r
15287 <TD width=15% BGCOLOR=#FBF5EF>
\r
15288 <B>0XFF180100</B>
\r
15290 <TD width=10% BGCOLOR=#FBF5EF>
\r
15293 <TD width=10% BGCOLOR=#FBF5EF>
\r
15296 <TD width=15% BGCOLOR=#FBF5EF>
\r
15299 <TD width=35% BGCOLOR=#FBF5EF>
\r
15300 <B>Configures MIO Pin 64 peripheral interface mapping</B>
\r
15303 <TR valign="top">
\r
15304 <TD width=15% BGCOLOR=#FBF5EF>
\r
15305 <A href="#PSU_IOU_SLCR_MIO_PIN_65">
\r
15306 PSU_IOU_SLCR_MIO_PIN_65
\r
15309 <TD width=15% BGCOLOR=#FBF5EF>
\r
15310 <B>0XFF180104</B>
\r
15312 <TD width=10% BGCOLOR=#FBF5EF>
\r
15315 <TD width=10% BGCOLOR=#FBF5EF>
\r
15318 <TD width=15% BGCOLOR=#FBF5EF>
\r
15321 <TD width=35% BGCOLOR=#FBF5EF>
\r
15322 <B>Configures MIO Pin 65 peripheral interface mapping</B>
\r
15325 <TR valign="top">
\r
15326 <TD width=15% BGCOLOR=#FBF5EF>
\r
15327 <A href="#PSU_IOU_SLCR_MIO_PIN_66">
\r
15328 PSU_IOU_SLCR_MIO_PIN_66
\r
15331 <TD width=15% BGCOLOR=#FBF5EF>
\r
15332 <B>0XFF180108</B>
\r
15334 <TD width=10% BGCOLOR=#FBF5EF>
\r
15337 <TD width=10% BGCOLOR=#FBF5EF>
\r
15340 <TD width=15% BGCOLOR=#FBF5EF>
\r
15343 <TD width=35% BGCOLOR=#FBF5EF>
\r
15344 <B>Configures MIO Pin 66 peripheral interface mapping</B>
\r
15347 <TR valign="top">
\r
15348 <TD width=15% BGCOLOR=#FBF5EF>
\r
15349 <A href="#PSU_IOU_SLCR_MIO_PIN_67">
\r
15350 PSU_IOU_SLCR_MIO_PIN_67
\r
15353 <TD width=15% BGCOLOR=#FBF5EF>
\r
15354 <B>0XFF18010C</B>
\r
15356 <TD width=10% BGCOLOR=#FBF5EF>
\r
15359 <TD width=10% BGCOLOR=#FBF5EF>
\r
15362 <TD width=15% BGCOLOR=#FBF5EF>
\r
15365 <TD width=35% BGCOLOR=#FBF5EF>
\r
15366 <B>Configures MIO Pin 67 peripheral interface mapping</B>
\r
15369 <TR valign="top">
\r
15370 <TD width=15% BGCOLOR=#FBF5EF>
\r
15371 <A href="#PSU_IOU_SLCR_MIO_PIN_68">
\r
15372 PSU_IOU_SLCR_MIO_PIN_68
\r
15375 <TD width=15% BGCOLOR=#FBF5EF>
\r
15376 <B>0XFF180110</B>
\r
15378 <TD width=10% BGCOLOR=#FBF5EF>
\r
15381 <TD width=10% BGCOLOR=#FBF5EF>
\r
15384 <TD width=15% BGCOLOR=#FBF5EF>
\r
15387 <TD width=35% BGCOLOR=#FBF5EF>
\r
15388 <B>Configures MIO Pin 68 peripheral interface mapping</B>
\r
15391 <TR valign="top">
\r
15392 <TD width=15% BGCOLOR=#FBF5EF>
\r
15393 <A href="#PSU_IOU_SLCR_MIO_PIN_69">
\r
15394 PSU_IOU_SLCR_MIO_PIN_69
\r
15397 <TD width=15% BGCOLOR=#FBF5EF>
\r
15398 <B>0XFF180114</B>
\r
15400 <TD width=10% BGCOLOR=#FBF5EF>
\r
15403 <TD width=10% BGCOLOR=#FBF5EF>
\r
15406 <TD width=15% BGCOLOR=#FBF5EF>
\r
15409 <TD width=35% BGCOLOR=#FBF5EF>
\r
15410 <B>Configures MIO Pin 69 peripheral interface mapping</B>
\r
15413 <TR valign="top">
\r
15414 <TD width=15% BGCOLOR=#FBF5EF>
\r
15415 <A href="#PSU_IOU_SLCR_MIO_PIN_70">
\r
15416 PSU_IOU_SLCR_MIO_PIN_70
\r
15419 <TD width=15% BGCOLOR=#FBF5EF>
\r
15420 <B>0XFF180118</B>
\r
15422 <TD width=10% BGCOLOR=#FBF5EF>
\r
15425 <TD width=10% BGCOLOR=#FBF5EF>
\r
15428 <TD width=15% BGCOLOR=#FBF5EF>
\r
15431 <TD width=35% BGCOLOR=#FBF5EF>
\r
15432 <B>Configures MIO Pin 70 peripheral interface mapping</B>
\r
15435 <TR valign="top">
\r
15436 <TD width=15% BGCOLOR=#FBF5EF>
\r
15437 <A href="#PSU_IOU_SLCR_MIO_PIN_71">
\r
15438 PSU_IOU_SLCR_MIO_PIN_71
\r
15441 <TD width=15% BGCOLOR=#FBF5EF>
\r
15442 <B>0XFF18011C</B>
\r
15444 <TD width=10% BGCOLOR=#FBF5EF>
\r
15447 <TD width=10% BGCOLOR=#FBF5EF>
\r
15450 <TD width=15% BGCOLOR=#FBF5EF>
\r
15453 <TD width=35% BGCOLOR=#FBF5EF>
\r
15454 <B>Configures MIO Pin 71 peripheral interface mapping</B>
\r
15457 <TR valign="top">
\r
15458 <TD width=15% BGCOLOR=#FBF5EF>
\r
15459 <A href="#PSU_IOU_SLCR_MIO_PIN_72">
\r
15460 PSU_IOU_SLCR_MIO_PIN_72
\r
15463 <TD width=15% BGCOLOR=#FBF5EF>
\r
15464 <B>0XFF180120</B>
\r
15466 <TD width=10% BGCOLOR=#FBF5EF>
\r
15469 <TD width=10% BGCOLOR=#FBF5EF>
\r
15472 <TD width=15% BGCOLOR=#FBF5EF>
\r
15475 <TD width=35% BGCOLOR=#FBF5EF>
\r
15476 <B>Configures MIO Pin 72 peripheral interface mapping</B>
\r
15479 <TR valign="top">
\r
15480 <TD width=15% BGCOLOR=#FBF5EF>
\r
15481 <A href="#PSU_IOU_SLCR_MIO_PIN_73">
\r
15482 PSU_IOU_SLCR_MIO_PIN_73
\r
15485 <TD width=15% BGCOLOR=#FBF5EF>
\r
15486 <B>0XFF180124</B>
\r
15488 <TD width=10% BGCOLOR=#FBF5EF>
\r
15491 <TD width=10% BGCOLOR=#FBF5EF>
\r
15494 <TD width=15% BGCOLOR=#FBF5EF>
\r
15497 <TD width=35% BGCOLOR=#FBF5EF>
\r
15498 <B>Configures MIO Pin 73 peripheral interface mapping</B>
\r
15501 <TR valign="top">
\r
15502 <TD width=15% BGCOLOR=#FBF5EF>
\r
15503 <A href="#PSU_IOU_SLCR_MIO_PIN_74">
\r
15504 PSU_IOU_SLCR_MIO_PIN_74
\r
15507 <TD width=15% BGCOLOR=#FBF5EF>
\r
15508 <B>0XFF180128</B>
\r
15510 <TD width=10% BGCOLOR=#FBF5EF>
\r
15513 <TD width=10% BGCOLOR=#FBF5EF>
\r
15516 <TD width=15% BGCOLOR=#FBF5EF>
\r
15519 <TD width=35% BGCOLOR=#FBF5EF>
\r
15520 <B>Configures MIO Pin 74 peripheral interface mapping</B>
\r
15523 <TR valign="top">
\r
15524 <TD width=15% BGCOLOR=#FBF5EF>
\r
15525 <A href="#PSU_IOU_SLCR_MIO_PIN_75">
\r
15526 PSU_IOU_SLCR_MIO_PIN_75
\r
15529 <TD width=15% BGCOLOR=#FBF5EF>
\r
15530 <B>0XFF18012C</B>
\r
15532 <TD width=10% BGCOLOR=#FBF5EF>
\r
15535 <TD width=10% BGCOLOR=#FBF5EF>
\r
15538 <TD width=15% BGCOLOR=#FBF5EF>
\r
15541 <TD width=35% BGCOLOR=#FBF5EF>
\r
15542 <B>Configures MIO Pin 75 peripheral interface mapping</B>
\r
15545 <TR valign="top">
\r
15546 <TD width=15% BGCOLOR=#FBF5EF>
\r
15547 <A href="#PSU_IOU_SLCR_MIO_PIN_76">
\r
15548 PSU_IOU_SLCR_MIO_PIN_76
\r
15551 <TD width=15% BGCOLOR=#FBF5EF>
\r
15552 <B>0XFF180130</B>
\r
15554 <TD width=10% BGCOLOR=#FBF5EF>
\r
15557 <TD width=10% BGCOLOR=#FBF5EF>
\r
15560 <TD width=15% BGCOLOR=#FBF5EF>
\r
15563 <TD width=35% BGCOLOR=#FBF5EF>
\r
15564 <B>Configures MIO Pin 76 peripheral interface mapping</B>
\r
15567 <TR valign="top">
\r
15568 <TD width=15% BGCOLOR=#FBF5EF>
\r
15569 <A href="#PSU_IOU_SLCR_MIO_PIN_77">
\r
15570 PSU_IOU_SLCR_MIO_PIN_77
\r
15573 <TD width=15% BGCOLOR=#FBF5EF>
\r
15574 <B>0XFF180134</B>
\r
15576 <TD width=10% BGCOLOR=#FBF5EF>
\r
15579 <TD width=10% BGCOLOR=#FBF5EF>
\r
15582 <TD width=15% BGCOLOR=#FBF5EF>
\r
15585 <TD width=35% BGCOLOR=#FBF5EF>
\r
15586 <B>Configures MIO Pin 77 peripheral interface mapping</B>
\r
15589 <TR valign="top">
\r
15590 <TD width=15% BGCOLOR=#FBF5EF>
\r
15591 <A href="#PSU_IOU_SLCR_MIO_MST_TRI0">
\r
15592 PSU_IOU_SLCR_MIO_MST_TRI0
\r
15595 <TD width=15% BGCOLOR=#FBF5EF>
\r
15596 <B>0XFF180204</B>
\r
15598 <TD width=10% BGCOLOR=#FBF5EF>
\r
15601 <TD width=10% BGCOLOR=#FBF5EF>
\r
15604 <TD width=15% BGCOLOR=#FBF5EF>
\r
15607 <TD width=35% BGCOLOR=#FBF5EF>
\r
15608 <B>MIO pin Tri-state Enables, 31:0</B>
\r
15611 <TR valign="top">
\r
15612 <TD width=15% BGCOLOR=#FBF5EF>
\r
15613 <A href="#PSU_IOU_SLCR_MIO_MST_TRI1">
\r
15614 PSU_IOU_SLCR_MIO_MST_TRI1
\r
15617 <TD width=15% BGCOLOR=#FBF5EF>
\r
15618 <B>0XFF180208</B>
\r
15620 <TD width=10% BGCOLOR=#FBF5EF>
\r
15623 <TD width=10% BGCOLOR=#FBF5EF>
\r
15626 <TD width=15% BGCOLOR=#FBF5EF>
\r
15629 <TD width=35% BGCOLOR=#FBF5EF>
\r
15630 <B>MIO pin Tri-state Enables, 63:32</B>
\r
15633 <TR valign="top">
\r
15634 <TD width=15% BGCOLOR=#FBF5EF>
\r
15635 <A href="#PSU_IOU_SLCR_MIO_MST_TRI2">
\r
15636 PSU_IOU_SLCR_MIO_MST_TRI2
\r
15639 <TD width=15% BGCOLOR=#FBF5EF>
\r
15640 <B>0XFF18020C</B>
\r
15642 <TD width=10% BGCOLOR=#FBF5EF>
\r
15645 <TD width=10% BGCOLOR=#FBF5EF>
\r
15648 <TD width=15% BGCOLOR=#FBF5EF>
\r
15651 <TD width=35% BGCOLOR=#FBF5EF>
\r
15652 <B>MIO pin Tri-state Enables, 77:64</B>
\r
15655 <TR valign="top">
\r
15656 <TD width=15% BGCOLOR=#FBF5EF>
\r
15657 <A href="#PSU_IOU_SLCR_MIO_LOOPBACK">
\r
15658 PSU_IOU_SLCR_MIO_LOOPBACK
\r
15661 <TD width=15% BGCOLOR=#FBF5EF>
\r
15662 <B>0XFF180200</B>
\r
15664 <TD width=10% BGCOLOR=#FBF5EF>
\r
15667 <TD width=10% BGCOLOR=#FBF5EF>
\r
15670 <TD width=15% BGCOLOR=#FBF5EF>
\r
15673 <TD width=35% BGCOLOR=#FBF5EF>
\r
15674 <B>Loopback function within MIO</B>
\r
15679 <H2><a name="psu_mio_init_data">psu_mio_init_data</a></H2>
\r
15680 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
15681 <TR valign="top">
\r
15682 <TD width=15% BGCOLOR=#FFC0FF>
\r
15683 <B>Register Name</B>
\r
15685 <TD width=15% BGCOLOR=#FFC0FF>
\r
15688 <TD width=10% BGCOLOR=#FFC0FF>
\r
15691 <TD width=10% BGCOLOR=#FFC0FF>
\r
15694 <TD width=15% BGCOLOR=#FFC0FF>
\r
15695 <B>Reset Value</B>
\r
15697 <TD width=35% BGCOLOR=#FFC0FF>
\r
15698 <B>Description</B>
\r
15701 <H1>MIO PROGRAMMING</H1>
\r
15702 <H2><a name="MIO_PIN_0">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_0</a></H2>
\r
15703 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
15704 <TR valign="top">
\r
15705 <TD width=15% BGCOLOR=#FFFF00>
\r
15706 <B>Register Name</B>
\r
15708 <TD width=15% BGCOLOR=#FFFF00>
\r
15711 <TD width=10% BGCOLOR=#FFFF00>
\r
15714 <TD width=10% BGCOLOR=#FFFF00>
\r
15717 <TD width=15% BGCOLOR=#FFFF00>
\r
15718 <B>Reset Value</B>
\r
15720 <TD width=35% BGCOLOR=#FFFF00>
\r
15721 <B>Description</B>
\r
15724 <TR valign="top">
\r
15725 <TD width=15% BGCOLOR=#FBF5EF>
\r
15728 <TD width=15% BGCOLOR=#FBF5EF>
\r
15729 <B>0XFF180000</B>
\r
15731 <TD width=10% BGCOLOR=#FBF5EF>
\r
15734 <TD width=10% BGCOLOR=#FBF5EF>
\r
15737 <TD width=15% BGCOLOR=#FBF5EF>
\r
15738 <B>0x00000000</B>
\r
15740 <TD width=35% BGCOLOR=#FBF5EF>
\r
15746 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
15747 <TR valign="top">
\r
15748 <TD width=15% BGCOLOR=#C0FFC0>
\r
15749 <B>Field Name</B>
\r
15751 <TD width=15% BGCOLOR=#C0FFC0>
\r
15754 <TD width=10% BGCOLOR=#C0FFC0>
\r
15757 <TD width=10% BGCOLOR=#C0FFC0>
\r
15760 <TD width=15% BGCOLOR=#C0FFC0>
\r
15761 <B>Shifted Value</B>
\r
15763 <TD width=35% BGCOLOR=#C0FFC0>
\r
15764 <B>Description</B>
\r
15767 <TR valign="top">
\r
15768 <TD width=15% BGCOLOR=#FBF5EF>
\r
15769 <B>PSU_IOU_SLCR_MIO_PIN_0_L0_SEL</B>
\r
15771 <TD width=15% BGCOLOR=#FBF5EF>
\r
15774 <TD width=10% BGCOLOR=#FBF5EF>
\r
15777 <TD width=10% BGCOLOR=#FBF5EF>
\r
15780 <TD width=15% BGCOLOR=#FBF5EF>
\r
15783 <TD width=35% BGCOLOR=#FBF5EF>
\r
15784 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)</B>
\r
15787 <TR valign="top">
\r
15788 <TD width=15% BGCOLOR=#FBF5EF>
\r
15789 <B>PSU_IOU_SLCR_MIO_PIN_0_L1_SEL</B>
\r
15791 <TD width=15% BGCOLOR=#FBF5EF>
\r
15794 <TD width=10% BGCOLOR=#FBF5EF>
\r
15797 <TD width=10% BGCOLOR=#FBF5EF>
\r
15800 <TD width=15% BGCOLOR=#FBF5EF>
\r
15803 <TD width=35% BGCOLOR=#FBF5EF>
\r
15804 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
15807 <TR valign="top">
\r
15808 <TD width=15% BGCOLOR=#FBF5EF>
\r
15809 <B>PSU_IOU_SLCR_MIO_PIN_0_L2_SEL</B>
\r
15811 <TD width=15% BGCOLOR=#FBF5EF>
\r
15814 <TD width=10% BGCOLOR=#FBF5EF>
\r
15817 <TD width=10% BGCOLOR=#FBF5EF>
\r
15820 <TD width=15% BGCOLOR=#FBF5EF>
\r
15823 <TD width=35% BGCOLOR=#FBF5EF>
\r
15824 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0]- (Test Scan Port) 3= Not Used</B>
\r
15827 <TR valign="top">
\r
15828 <TD width=15% BGCOLOR=#FBF5EF>
\r
15829 <B>PSU_IOU_SLCR_MIO_PIN_0_L3_SEL</B>
\r
15831 <TD width=15% BGCOLOR=#FBF5EF>
\r
15834 <TD width=10% BGCOLOR=#FBF5EF>
\r
15837 <TD width=10% BGCOLOR=#FBF5EF>
\r
15840 <TD width=15% BGCOLOR=#FBF5EF>
\r
15843 <TD width=35% BGCOLOR=#FBF5EF>
\r
15844 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)</B>
\r
15847 <TR valign="top">
\r
15848 <TD width=15% BGCOLOR=#C0C0C0>
\r
15849 <B>PSU_IOU_SLCR_MIO_PIN_0@0XFF180000</B>
\r
15851 <TD width=15% BGCOLOR=#C0C0C0>
\r
15854 <TD width=10% BGCOLOR=#C0C0C0>
\r
15857 <TD width=10% BGCOLOR=#C0C0C0>
\r
15860 <TD width=15% BGCOLOR=#C0C0C0>
\r
15863 <TD width=35% BGCOLOR=#C0C0C0>
\r
15864 <B>Configures MIO Pin 0 peripheral interface mapping. S</B>
\r
15869 <H2><a name="MIO_PIN_1">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_1</a></H2>
\r
15870 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
15871 <TR valign="top">
\r
15872 <TD width=15% BGCOLOR=#FFFF00>
\r
15873 <B>Register Name</B>
\r
15875 <TD width=15% BGCOLOR=#FFFF00>
\r
15878 <TD width=10% BGCOLOR=#FFFF00>
\r
15881 <TD width=10% BGCOLOR=#FFFF00>
\r
15884 <TD width=15% BGCOLOR=#FFFF00>
\r
15885 <B>Reset Value</B>
\r
15887 <TD width=35% BGCOLOR=#FFFF00>
\r
15888 <B>Description</B>
\r
15891 <TR valign="top">
\r
15892 <TD width=15% BGCOLOR=#FBF5EF>
\r
15895 <TD width=15% BGCOLOR=#FBF5EF>
\r
15896 <B>0XFF180004</B>
\r
15898 <TD width=10% BGCOLOR=#FBF5EF>
\r
15901 <TD width=10% BGCOLOR=#FBF5EF>
\r
15904 <TD width=15% BGCOLOR=#FBF5EF>
\r
15905 <B>0x00000000</B>
\r
15907 <TD width=35% BGCOLOR=#FBF5EF>
\r
15913 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
15914 <TR valign="top">
\r
15915 <TD width=15% BGCOLOR=#C0FFC0>
\r
15916 <B>Field Name</B>
\r
15918 <TD width=15% BGCOLOR=#C0FFC0>
\r
15921 <TD width=10% BGCOLOR=#C0FFC0>
\r
15924 <TD width=10% BGCOLOR=#C0FFC0>
\r
15927 <TD width=15% BGCOLOR=#C0FFC0>
\r
15928 <B>Shifted Value</B>
\r
15930 <TD width=35% BGCOLOR=#C0FFC0>
\r
15931 <B>Description</B>
\r
15934 <TR valign="top">
\r
15935 <TD width=15% BGCOLOR=#FBF5EF>
\r
15936 <B>PSU_IOU_SLCR_MIO_PIN_1_L0_SEL</B>
\r
15938 <TD width=15% BGCOLOR=#FBF5EF>
\r
15941 <TD width=10% BGCOLOR=#FBF5EF>
\r
15944 <TD width=10% BGCOLOR=#FBF5EF>
\r
15947 <TD width=15% BGCOLOR=#FBF5EF>
\r
15950 <TD width=35% BGCOLOR=#FBF5EF>
\r
15951 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)</B>
\r
15954 <TR valign="top">
\r
15955 <TD width=15% BGCOLOR=#FBF5EF>
\r
15956 <B>PSU_IOU_SLCR_MIO_PIN_1_L1_SEL</B>
\r
15958 <TD width=15% BGCOLOR=#FBF5EF>
\r
15961 <TD width=10% BGCOLOR=#FBF5EF>
\r
15964 <TD width=10% BGCOLOR=#FBF5EF>
\r
15967 <TD width=15% BGCOLOR=#FBF5EF>
\r
15970 <TD width=35% BGCOLOR=#FBF5EF>
\r
15971 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
15974 <TR valign="top">
\r
15975 <TD width=15% BGCOLOR=#FBF5EF>
\r
15976 <B>PSU_IOU_SLCR_MIO_PIN_1_L2_SEL</B>
\r
15978 <TD width=15% BGCOLOR=#FBF5EF>
\r
15981 <TD width=10% BGCOLOR=#FBF5EF>
\r
15984 <TD width=10% BGCOLOR=#FBF5EF>
\r
15987 <TD width=15% BGCOLOR=#FBF5EF>
\r
15990 <TD width=35% BGCOLOR=#FBF5EF>
\r
15991 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1]- (Test Scan Port) 3= Not Used</B>
\r
15994 <TR valign="top">
\r
15995 <TD width=15% BGCOLOR=#FBF5EF>
\r
15996 <B>PSU_IOU_SLCR_MIO_PIN_1_L3_SEL</B>
\r
15998 <TD width=15% BGCOLOR=#FBF5EF>
\r
16001 <TD width=10% BGCOLOR=#FBF5EF>
\r
16004 <TD width=10% BGCOLOR=#FBF5EF>
\r
16007 <TD width=15% BGCOLOR=#FBF5EF>
\r
16010 <TD width=35% BGCOLOR=#FBF5EF>
\r
16011 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B>
\r
16014 <TR valign="top">
\r
16015 <TD width=15% BGCOLOR=#C0C0C0>
\r
16016 <B>PSU_IOU_SLCR_MIO_PIN_1@0XFF180004</B>
\r
16018 <TD width=15% BGCOLOR=#C0C0C0>
\r
16021 <TD width=10% BGCOLOR=#C0C0C0>
\r
16024 <TD width=10% BGCOLOR=#C0C0C0>
\r
16027 <TD width=15% BGCOLOR=#C0C0C0>
\r
16030 <TD width=35% BGCOLOR=#C0C0C0>
\r
16031 <B>Configures MIO Pin 1 peripheral interface mapping</B>
\r
16036 <H2><a name="MIO_PIN_2">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_2</a></H2>
\r
16037 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16038 <TR valign="top">
\r
16039 <TD width=15% BGCOLOR=#FFFF00>
\r
16040 <B>Register Name</B>
\r
16042 <TD width=15% BGCOLOR=#FFFF00>
\r
16045 <TD width=10% BGCOLOR=#FFFF00>
\r
16048 <TD width=10% BGCOLOR=#FFFF00>
\r
16051 <TD width=15% BGCOLOR=#FFFF00>
\r
16052 <B>Reset Value</B>
\r
16054 <TD width=35% BGCOLOR=#FFFF00>
\r
16055 <B>Description</B>
\r
16058 <TR valign="top">
\r
16059 <TD width=15% BGCOLOR=#FBF5EF>
\r
16062 <TD width=15% BGCOLOR=#FBF5EF>
\r
16063 <B>0XFF180008</B>
\r
16065 <TD width=10% BGCOLOR=#FBF5EF>
\r
16068 <TD width=10% BGCOLOR=#FBF5EF>
\r
16071 <TD width=15% BGCOLOR=#FBF5EF>
\r
16072 <B>0x00000000</B>
\r
16074 <TD width=35% BGCOLOR=#FBF5EF>
\r
16080 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16081 <TR valign="top">
\r
16082 <TD width=15% BGCOLOR=#C0FFC0>
\r
16083 <B>Field Name</B>
\r
16085 <TD width=15% BGCOLOR=#C0FFC0>
\r
16088 <TD width=10% BGCOLOR=#C0FFC0>
\r
16091 <TD width=10% BGCOLOR=#C0FFC0>
\r
16094 <TD width=15% BGCOLOR=#C0FFC0>
\r
16095 <B>Shifted Value</B>
\r
16097 <TD width=35% BGCOLOR=#C0FFC0>
\r
16098 <B>Description</B>
\r
16101 <TR valign="top">
\r
16102 <TD width=15% BGCOLOR=#FBF5EF>
\r
16103 <B>PSU_IOU_SLCR_MIO_PIN_2_L0_SEL</B>
\r
16105 <TD width=15% BGCOLOR=#FBF5EF>
\r
16108 <TD width=10% BGCOLOR=#FBF5EF>
\r
16111 <TD width=10% BGCOLOR=#FBF5EF>
\r
16114 <TD width=15% BGCOLOR=#FBF5EF>
\r
16117 <TD width=35% BGCOLOR=#FBF5EF>
\r
16118 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)</B>
\r
16121 <TR valign="top">
\r
16122 <TD width=15% BGCOLOR=#FBF5EF>
\r
16123 <B>PSU_IOU_SLCR_MIO_PIN_2_L1_SEL</B>
\r
16125 <TD width=15% BGCOLOR=#FBF5EF>
\r
16128 <TD width=10% BGCOLOR=#FBF5EF>
\r
16131 <TD width=10% BGCOLOR=#FBF5EF>
\r
16134 <TD width=15% BGCOLOR=#FBF5EF>
\r
16137 <TD width=35% BGCOLOR=#FBF5EF>
\r
16138 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16141 <TR valign="top">
\r
16142 <TD width=15% BGCOLOR=#FBF5EF>
\r
16143 <B>PSU_IOU_SLCR_MIO_PIN_2_L2_SEL</B>
\r
16145 <TD width=15% BGCOLOR=#FBF5EF>
\r
16148 <TD width=10% BGCOLOR=#FBF5EF>
\r
16151 <TD width=10% BGCOLOR=#FBF5EF>
\r
16154 <TD width=15% BGCOLOR=#FBF5EF>
\r
16157 <TD width=35% BGCOLOR=#FBF5EF>
\r
16158 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2]- (Test Scan Port) 3= Not Used</B>
\r
16161 <TR valign="top">
\r
16162 <TD width=15% BGCOLOR=#FBF5EF>
\r
16163 <B>PSU_IOU_SLCR_MIO_PIN_2_L3_SEL</B>
\r
16165 <TD width=15% BGCOLOR=#FBF5EF>
\r
16168 <TD width=10% BGCOLOR=#FBF5EF>
\r
16171 <TD width=10% BGCOLOR=#FBF5EF>
\r
16174 <TD width=15% BGCOLOR=#FBF5EF>
\r
16177 <TD width=35% BGCOLOR=#FBF5EF>
\r
16178 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B>
\r
16181 <TR valign="top">
\r
16182 <TD width=15% BGCOLOR=#C0C0C0>
\r
16183 <B>PSU_IOU_SLCR_MIO_PIN_2@0XFF180008</B>
\r
16185 <TD width=15% BGCOLOR=#C0C0C0>
\r
16188 <TD width=10% BGCOLOR=#C0C0C0>
\r
16191 <TD width=10% BGCOLOR=#C0C0C0>
\r
16194 <TD width=15% BGCOLOR=#C0C0C0>
\r
16197 <TD width=35% BGCOLOR=#C0C0C0>
\r
16198 <B>Configures MIO Pin 2 peripheral interface mapping</B>
\r
16203 <H2><a name="MIO_PIN_3">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_3</a></H2>
\r
16204 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16205 <TR valign="top">
\r
16206 <TD width=15% BGCOLOR=#FFFF00>
\r
16207 <B>Register Name</B>
\r
16209 <TD width=15% BGCOLOR=#FFFF00>
\r
16212 <TD width=10% BGCOLOR=#FFFF00>
\r
16215 <TD width=10% BGCOLOR=#FFFF00>
\r
16218 <TD width=15% BGCOLOR=#FFFF00>
\r
16219 <B>Reset Value</B>
\r
16221 <TD width=35% BGCOLOR=#FFFF00>
\r
16222 <B>Description</B>
\r
16225 <TR valign="top">
\r
16226 <TD width=15% BGCOLOR=#FBF5EF>
\r
16229 <TD width=15% BGCOLOR=#FBF5EF>
\r
16230 <B>0XFF18000C</B>
\r
16232 <TD width=10% BGCOLOR=#FBF5EF>
\r
16235 <TD width=10% BGCOLOR=#FBF5EF>
\r
16238 <TD width=15% BGCOLOR=#FBF5EF>
\r
16239 <B>0x00000000</B>
\r
16241 <TD width=35% BGCOLOR=#FBF5EF>
\r
16247 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16248 <TR valign="top">
\r
16249 <TD width=15% BGCOLOR=#C0FFC0>
\r
16250 <B>Field Name</B>
\r
16252 <TD width=15% BGCOLOR=#C0FFC0>
\r
16255 <TD width=10% BGCOLOR=#C0FFC0>
\r
16258 <TD width=10% BGCOLOR=#C0FFC0>
\r
16261 <TD width=15% BGCOLOR=#C0FFC0>
\r
16262 <B>Shifted Value</B>
\r
16264 <TD width=35% BGCOLOR=#C0FFC0>
\r
16265 <B>Description</B>
\r
16268 <TR valign="top">
\r
16269 <TD width=15% BGCOLOR=#FBF5EF>
\r
16270 <B>PSU_IOU_SLCR_MIO_PIN_3_L0_SEL</B>
\r
16272 <TD width=15% BGCOLOR=#FBF5EF>
\r
16275 <TD width=10% BGCOLOR=#FBF5EF>
\r
16278 <TD width=10% BGCOLOR=#FBF5EF>
\r
16281 <TD width=15% BGCOLOR=#FBF5EF>
\r
16284 <TD width=35% BGCOLOR=#FBF5EF>
\r
16285 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)</B>
\r
16288 <TR valign="top">
\r
16289 <TD width=15% BGCOLOR=#FBF5EF>
\r
16290 <B>PSU_IOU_SLCR_MIO_PIN_3_L1_SEL</B>
\r
16292 <TD width=15% BGCOLOR=#FBF5EF>
\r
16295 <TD width=10% BGCOLOR=#FBF5EF>
\r
16298 <TD width=10% BGCOLOR=#FBF5EF>
\r
16301 <TD width=15% BGCOLOR=#FBF5EF>
\r
16304 <TD width=35% BGCOLOR=#FBF5EF>
\r
16305 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16308 <TR valign="top">
\r
16309 <TD width=15% BGCOLOR=#FBF5EF>
\r
16310 <B>PSU_IOU_SLCR_MIO_PIN_3_L2_SEL</B>
\r
16312 <TD width=15% BGCOLOR=#FBF5EF>
\r
16315 <TD width=10% BGCOLOR=#FBF5EF>
\r
16318 <TD width=10% BGCOLOR=#FBF5EF>
\r
16321 <TD width=15% BGCOLOR=#FBF5EF>
\r
16324 <TD width=35% BGCOLOR=#FBF5EF>
\r
16325 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3]- (Test Scan Port) 3= Not Used</B>
\r
16328 <TR valign="top">
\r
16329 <TD width=15% BGCOLOR=#FBF5EF>
\r
16330 <B>PSU_IOU_SLCR_MIO_PIN_3_L3_SEL</B>
\r
16332 <TD width=15% BGCOLOR=#FBF5EF>
\r
16335 <TD width=10% BGCOLOR=#FBF5EF>
\r
16338 <TD width=10% BGCOLOR=#FBF5EF>
\r
16341 <TD width=15% BGCOLOR=#FBF5EF>
\r
16344 <TD width=35% BGCOLOR=#FBF5EF>
\r
16345 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B>
\r
16348 <TR valign="top">
\r
16349 <TD width=15% BGCOLOR=#C0C0C0>
\r
16350 <B>PSU_IOU_SLCR_MIO_PIN_3@0XFF18000C</B>
\r
16352 <TD width=15% BGCOLOR=#C0C0C0>
\r
16355 <TD width=10% BGCOLOR=#C0C0C0>
\r
16358 <TD width=10% BGCOLOR=#C0C0C0>
\r
16361 <TD width=15% BGCOLOR=#C0C0C0>
\r
16364 <TD width=35% BGCOLOR=#C0C0C0>
\r
16365 <B>Configures MIO Pin 3 peripheral interface mapping</B>
\r
16370 <H2><a name="MIO_PIN_4">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_4</a></H2>
\r
16371 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16372 <TR valign="top">
\r
16373 <TD width=15% BGCOLOR=#FFFF00>
\r
16374 <B>Register Name</B>
\r
16376 <TD width=15% BGCOLOR=#FFFF00>
\r
16379 <TD width=10% BGCOLOR=#FFFF00>
\r
16382 <TD width=10% BGCOLOR=#FFFF00>
\r
16385 <TD width=15% BGCOLOR=#FFFF00>
\r
16386 <B>Reset Value</B>
\r
16388 <TD width=35% BGCOLOR=#FFFF00>
\r
16389 <B>Description</B>
\r
16392 <TR valign="top">
\r
16393 <TD width=15% BGCOLOR=#FBF5EF>
\r
16396 <TD width=15% BGCOLOR=#FBF5EF>
\r
16397 <B>0XFF180010</B>
\r
16399 <TD width=10% BGCOLOR=#FBF5EF>
\r
16402 <TD width=10% BGCOLOR=#FBF5EF>
\r
16405 <TD width=15% BGCOLOR=#FBF5EF>
\r
16406 <B>0x00000000</B>
\r
16408 <TD width=35% BGCOLOR=#FBF5EF>
\r
16414 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16415 <TR valign="top">
\r
16416 <TD width=15% BGCOLOR=#C0FFC0>
\r
16417 <B>Field Name</B>
\r
16419 <TD width=15% BGCOLOR=#C0FFC0>
\r
16422 <TD width=10% BGCOLOR=#C0FFC0>
\r
16425 <TD width=10% BGCOLOR=#C0FFC0>
\r
16428 <TD width=15% BGCOLOR=#C0FFC0>
\r
16429 <B>Shifted Value</B>
\r
16431 <TD width=35% BGCOLOR=#C0FFC0>
\r
16432 <B>Description</B>
\r
16435 <TR valign="top">
\r
16436 <TD width=15% BGCOLOR=#FBF5EF>
\r
16437 <B>PSU_IOU_SLCR_MIO_PIN_4_L0_SEL</B>
\r
16439 <TD width=15% BGCOLOR=#FBF5EF>
\r
16442 <TD width=10% BGCOLOR=#FBF5EF>
\r
16445 <TD width=10% BGCOLOR=#FBF5EF>
\r
16448 <TD width=15% BGCOLOR=#FBF5EF>
\r
16451 <TD width=35% BGCOLOR=#FBF5EF>
\r
16452 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)</B>
\r
16455 <TR valign="top">
\r
16456 <TD width=15% BGCOLOR=#FBF5EF>
\r
16457 <B>PSU_IOU_SLCR_MIO_PIN_4_L1_SEL</B>
\r
16459 <TD width=15% BGCOLOR=#FBF5EF>
\r
16462 <TD width=10% BGCOLOR=#FBF5EF>
\r
16465 <TD width=10% BGCOLOR=#FBF5EF>
\r
16468 <TD width=15% BGCOLOR=#FBF5EF>
\r
16471 <TD width=35% BGCOLOR=#FBF5EF>
\r
16472 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16475 <TR valign="top">
\r
16476 <TD width=15% BGCOLOR=#FBF5EF>
\r
16477 <B>PSU_IOU_SLCR_MIO_PIN_4_L2_SEL</B>
\r
16479 <TD width=15% BGCOLOR=#FBF5EF>
\r
16482 <TD width=10% BGCOLOR=#FBF5EF>
\r
16485 <TD width=10% BGCOLOR=#FBF5EF>
\r
16488 <TD width=15% BGCOLOR=#FBF5EF>
\r
16491 <TD width=35% BGCOLOR=#FBF5EF>
\r
16492 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4]- (Test Scan Port) 3= Not Used</B>
\r
16495 <TR valign="top">
\r
16496 <TD width=15% BGCOLOR=#FBF5EF>
\r
16497 <B>PSU_IOU_SLCR_MIO_PIN_4_L3_SEL</B>
\r
16499 <TD width=15% BGCOLOR=#FBF5EF>
\r
16502 <TD width=10% BGCOLOR=#FBF5EF>
\r
16505 <TD width=10% BGCOLOR=#FBF5EF>
\r
16508 <TD width=15% BGCOLOR=#FBF5EF>
\r
16511 <TD width=35% BGCOLOR=#FBF5EF>
\r
16512 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B>
\r
16515 <TR valign="top">
\r
16516 <TD width=15% BGCOLOR=#C0C0C0>
\r
16517 <B>PSU_IOU_SLCR_MIO_PIN_4@0XFF180010</B>
\r
16519 <TD width=15% BGCOLOR=#C0C0C0>
\r
16522 <TD width=10% BGCOLOR=#C0C0C0>
\r
16525 <TD width=10% BGCOLOR=#C0C0C0>
\r
16528 <TD width=15% BGCOLOR=#C0C0C0>
\r
16531 <TD width=35% BGCOLOR=#C0C0C0>
\r
16532 <B>Configures MIO Pin 4 peripheral interface mapping</B>
\r
16537 <H2><a name="MIO_PIN_5">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_5</a></H2>
\r
16538 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16539 <TR valign="top">
\r
16540 <TD width=15% BGCOLOR=#FFFF00>
\r
16541 <B>Register Name</B>
\r
16543 <TD width=15% BGCOLOR=#FFFF00>
\r
16546 <TD width=10% BGCOLOR=#FFFF00>
\r
16549 <TD width=10% BGCOLOR=#FFFF00>
\r
16552 <TD width=15% BGCOLOR=#FFFF00>
\r
16553 <B>Reset Value</B>
\r
16555 <TD width=35% BGCOLOR=#FFFF00>
\r
16556 <B>Description</B>
\r
16559 <TR valign="top">
\r
16560 <TD width=15% BGCOLOR=#FBF5EF>
\r
16563 <TD width=15% BGCOLOR=#FBF5EF>
\r
16564 <B>0XFF180014</B>
\r
16566 <TD width=10% BGCOLOR=#FBF5EF>
\r
16569 <TD width=10% BGCOLOR=#FBF5EF>
\r
16572 <TD width=15% BGCOLOR=#FBF5EF>
\r
16573 <B>0x00000000</B>
\r
16575 <TD width=35% BGCOLOR=#FBF5EF>
\r
16581 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16582 <TR valign="top">
\r
16583 <TD width=15% BGCOLOR=#C0FFC0>
\r
16584 <B>Field Name</B>
\r
16586 <TD width=15% BGCOLOR=#C0FFC0>
\r
16589 <TD width=10% BGCOLOR=#C0FFC0>
\r
16592 <TD width=10% BGCOLOR=#C0FFC0>
\r
16595 <TD width=15% BGCOLOR=#C0FFC0>
\r
16596 <B>Shifted Value</B>
\r
16598 <TD width=35% BGCOLOR=#C0FFC0>
\r
16599 <B>Description</B>
\r
16602 <TR valign="top">
\r
16603 <TD width=15% BGCOLOR=#FBF5EF>
\r
16604 <B>PSU_IOU_SLCR_MIO_PIN_5_L0_SEL</B>
\r
16606 <TD width=15% BGCOLOR=#FBF5EF>
\r
16609 <TD width=10% BGCOLOR=#FBF5EF>
\r
16612 <TD width=10% BGCOLOR=#FBF5EF>
\r
16615 <TD width=15% BGCOLOR=#FBF5EF>
\r
16618 <TD width=35% BGCOLOR=#FBF5EF>
\r
16619 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)</B>
\r
16622 <TR valign="top">
\r
16623 <TD width=15% BGCOLOR=#FBF5EF>
\r
16624 <B>PSU_IOU_SLCR_MIO_PIN_5_L1_SEL</B>
\r
16626 <TD width=15% BGCOLOR=#FBF5EF>
\r
16629 <TD width=10% BGCOLOR=#FBF5EF>
\r
16632 <TD width=10% BGCOLOR=#FBF5EF>
\r
16635 <TD width=15% BGCOLOR=#FBF5EF>
\r
16638 <TD width=35% BGCOLOR=#FBF5EF>
\r
16639 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16642 <TR valign="top">
\r
16643 <TD width=15% BGCOLOR=#FBF5EF>
\r
16644 <B>PSU_IOU_SLCR_MIO_PIN_5_L2_SEL</B>
\r
16646 <TD width=15% BGCOLOR=#FBF5EF>
\r
16649 <TD width=10% BGCOLOR=#FBF5EF>
\r
16652 <TD width=10% BGCOLOR=#FBF5EF>
\r
16655 <TD width=15% BGCOLOR=#FBF5EF>
\r
16658 <TD width=35% BGCOLOR=#FBF5EF>
\r
16659 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5]- (Test Scan Port) 3= Not Used</B>
\r
16662 <TR valign="top">
\r
16663 <TD width=15% BGCOLOR=#FBF5EF>
\r
16664 <B>PSU_IOU_SLCR_MIO_PIN_5_L3_SEL</B>
\r
16666 <TD width=15% BGCOLOR=#FBF5EF>
\r
16669 <TD width=10% BGCOLOR=#FBF5EF>
\r
16672 <TD width=10% BGCOLOR=#FBF5EF>
\r
16675 <TD width=15% BGCOLOR=#FBF5EF>
\r
16678 <TD width=35% BGCOLOR=#FBF5EF>
\r
16679 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B>
\r
16682 <TR valign="top">
\r
16683 <TD width=15% BGCOLOR=#C0C0C0>
\r
16684 <B>PSU_IOU_SLCR_MIO_PIN_5@0XFF180014</B>
\r
16686 <TD width=15% BGCOLOR=#C0C0C0>
\r
16689 <TD width=10% BGCOLOR=#C0C0C0>
\r
16692 <TD width=10% BGCOLOR=#C0C0C0>
\r
16695 <TD width=15% BGCOLOR=#C0C0C0>
\r
16698 <TD width=35% BGCOLOR=#C0C0C0>
\r
16699 <B>Configures MIO Pin 5 peripheral interface mapping</B>
\r
16704 <H2><a name="MIO_PIN_6">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_6</a></H2>
\r
16705 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16706 <TR valign="top">
\r
16707 <TD width=15% BGCOLOR=#FFFF00>
\r
16708 <B>Register Name</B>
\r
16710 <TD width=15% BGCOLOR=#FFFF00>
\r
16713 <TD width=10% BGCOLOR=#FFFF00>
\r
16716 <TD width=10% BGCOLOR=#FFFF00>
\r
16719 <TD width=15% BGCOLOR=#FFFF00>
\r
16720 <B>Reset Value</B>
\r
16722 <TD width=35% BGCOLOR=#FFFF00>
\r
16723 <B>Description</B>
\r
16726 <TR valign="top">
\r
16727 <TD width=15% BGCOLOR=#FBF5EF>
\r
16730 <TD width=15% BGCOLOR=#FBF5EF>
\r
16731 <B>0XFF180018</B>
\r
16733 <TD width=10% BGCOLOR=#FBF5EF>
\r
16736 <TD width=10% BGCOLOR=#FBF5EF>
\r
16739 <TD width=15% BGCOLOR=#FBF5EF>
\r
16740 <B>0x00000000</B>
\r
16742 <TD width=35% BGCOLOR=#FBF5EF>
\r
16748 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16749 <TR valign="top">
\r
16750 <TD width=15% BGCOLOR=#C0FFC0>
\r
16751 <B>Field Name</B>
\r
16753 <TD width=15% BGCOLOR=#C0FFC0>
\r
16756 <TD width=10% BGCOLOR=#C0FFC0>
\r
16759 <TD width=10% BGCOLOR=#C0FFC0>
\r
16762 <TD width=15% BGCOLOR=#C0FFC0>
\r
16763 <B>Shifted Value</B>
\r
16765 <TD width=35% BGCOLOR=#C0FFC0>
\r
16766 <B>Description</B>
\r
16769 <TR valign="top">
\r
16770 <TD width=15% BGCOLOR=#FBF5EF>
\r
16771 <B>PSU_IOU_SLCR_MIO_PIN_6_L0_SEL</B>
\r
16773 <TD width=15% BGCOLOR=#FBF5EF>
\r
16776 <TD width=10% BGCOLOR=#FBF5EF>
\r
16779 <TD width=10% BGCOLOR=#FBF5EF>
\r
16782 <TD width=15% BGCOLOR=#FBF5EF>
\r
16785 <TD width=35% BGCOLOR=#FBF5EF>
\r
16786 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</B>
\r
16789 <TR valign="top">
\r
16790 <TD width=15% BGCOLOR=#FBF5EF>
\r
16791 <B>PSU_IOU_SLCR_MIO_PIN_6_L1_SEL</B>
\r
16793 <TD width=15% BGCOLOR=#FBF5EF>
\r
16796 <TD width=10% BGCOLOR=#FBF5EF>
\r
16799 <TD width=10% BGCOLOR=#FBF5EF>
\r
16802 <TD width=15% BGCOLOR=#FBF5EF>
\r
16805 <TD width=35% BGCOLOR=#FBF5EF>
\r
16806 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16809 <TR valign="top">
\r
16810 <TD width=15% BGCOLOR=#FBF5EF>
\r
16811 <B>PSU_IOU_SLCR_MIO_PIN_6_L2_SEL</B>
\r
16813 <TD width=15% BGCOLOR=#FBF5EF>
\r
16816 <TD width=10% BGCOLOR=#FBF5EF>
\r
16819 <TD width=10% BGCOLOR=#FBF5EF>
\r
16822 <TD width=15% BGCOLOR=#FBF5EF>
\r
16825 <TD width=35% BGCOLOR=#FBF5EF>
\r
16826 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6]- (Test Scan Port) 3= Not Used</B>
\r
16829 <TR valign="top">
\r
16830 <TD width=15% BGCOLOR=#FBF5EF>
\r
16831 <B>PSU_IOU_SLCR_MIO_PIN_6_L3_SEL</B>
\r
16833 <TD width=15% BGCOLOR=#FBF5EF>
\r
16836 <TD width=10% BGCOLOR=#FBF5EF>
\r
16839 <TD width=10% BGCOLOR=#FBF5EF>
\r
16842 <TD width=15% BGCOLOR=#FBF5EF>
\r
16845 <TD width=35% BGCOLOR=#FBF5EF>
\r
16846 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B>
\r
16849 <TR valign="top">
\r
16850 <TD width=15% BGCOLOR=#C0C0C0>
\r
16851 <B>PSU_IOU_SLCR_MIO_PIN_6@0XFF180018</B>
\r
16853 <TD width=15% BGCOLOR=#C0C0C0>
\r
16856 <TD width=10% BGCOLOR=#C0C0C0>
\r
16859 <TD width=10% BGCOLOR=#C0C0C0>
\r
16862 <TD width=15% BGCOLOR=#C0C0C0>
\r
16865 <TD width=35% BGCOLOR=#C0C0C0>
\r
16866 <B>Configures MIO Pin 6 peripheral interface mapping</B>
\r
16871 <H2><a name="MIO_PIN_7">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_7</a></H2>
\r
16872 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16873 <TR valign="top">
\r
16874 <TD width=15% BGCOLOR=#FFFF00>
\r
16875 <B>Register Name</B>
\r
16877 <TD width=15% BGCOLOR=#FFFF00>
\r
16880 <TD width=10% BGCOLOR=#FFFF00>
\r
16883 <TD width=10% BGCOLOR=#FFFF00>
\r
16886 <TD width=15% BGCOLOR=#FFFF00>
\r
16887 <B>Reset Value</B>
\r
16889 <TD width=35% BGCOLOR=#FFFF00>
\r
16890 <B>Description</B>
\r
16893 <TR valign="top">
\r
16894 <TD width=15% BGCOLOR=#FBF5EF>
\r
16897 <TD width=15% BGCOLOR=#FBF5EF>
\r
16898 <B>0XFF18001C</B>
\r
16900 <TD width=10% BGCOLOR=#FBF5EF>
\r
16903 <TD width=10% BGCOLOR=#FBF5EF>
\r
16906 <TD width=15% BGCOLOR=#FBF5EF>
\r
16907 <B>0x00000000</B>
\r
16909 <TD width=35% BGCOLOR=#FBF5EF>
\r
16915 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
16916 <TR valign="top">
\r
16917 <TD width=15% BGCOLOR=#C0FFC0>
\r
16918 <B>Field Name</B>
\r
16920 <TD width=15% BGCOLOR=#C0FFC0>
\r
16923 <TD width=10% BGCOLOR=#C0FFC0>
\r
16926 <TD width=10% BGCOLOR=#C0FFC0>
\r
16929 <TD width=15% BGCOLOR=#C0FFC0>
\r
16930 <B>Shifted Value</B>
\r
16932 <TD width=35% BGCOLOR=#C0FFC0>
\r
16933 <B>Description</B>
\r
16936 <TR valign="top">
\r
16937 <TD width=15% BGCOLOR=#FBF5EF>
\r
16938 <B>PSU_IOU_SLCR_MIO_PIN_7_L0_SEL</B>
\r
16940 <TD width=15% BGCOLOR=#FBF5EF>
\r
16943 <TD width=10% BGCOLOR=#FBF5EF>
\r
16946 <TD width=10% BGCOLOR=#FBF5EF>
\r
16949 <TD width=15% BGCOLOR=#FBF5EF>
\r
16952 <TD width=35% BGCOLOR=#FBF5EF>
\r
16953 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)</B>
\r
16956 <TR valign="top">
\r
16957 <TD width=15% BGCOLOR=#FBF5EF>
\r
16958 <B>PSU_IOU_SLCR_MIO_PIN_7_L1_SEL</B>
\r
16960 <TD width=15% BGCOLOR=#FBF5EF>
\r
16963 <TD width=10% BGCOLOR=#FBF5EF>
\r
16966 <TD width=10% BGCOLOR=#FBF5EF>
\r
16969 <TD width=15% BGCOLOR=#FBF5EF>
\r
16972 <TD width=35% BGCOLOR=#FBF5EF>
\r
16973 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
16976 <TR valign="top">
\r
16977 <TD width=15% BGCOLOR=#FBF5EF>
\r
16978 <B>PSU_IOU_SLCR_MIO_PIN_7_L2_SEL</B>
\r
16980 <TD width=15% BGCOLOR=#FBF5EF>
\r
16983 <TD width=10% BGCOLOR=#FBF5EF>
\r
16986 <TD width=10% BGCOLOR=#FBF5EF>
\r
16989 <TD width=15% BGCOLOR=#FBF5EF>
\r
16992 <TD width=35% BGCOLOR=#FBF5EF>
\r
16993 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7]- (Test Scan Port) 3= Not Used</B>
\r
16996 <TR valign="top">
\r
16997 <TD width=15% BGCOLOR=#FBF5EF>
\r
16998 <B>PSU_IOU_SLCR_MIO_PIN_7_L3_SEL</B>
\r
17000 <TD width=15% BGCOLOR=#FBF5EF>
\r
17003 <TD width=10% BGCOLOR=#FBF5EF>
\r
17006 <TD width=10% BGCOLOR=#FBF5EF>
\r
17009 <TD width=15% BGCOLOR=#FBF5EF>
\r
17012 <TD width=35% BGCOLOR=#FBF5EF>
\r
17013 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B>
\r
17016 <TR valign="top">
\r
17017 <TD width=15% BGCOLOR=#C0C0C0>
\r
17018 <B>PSU_IOU_SLCR_MIO_PIN_7@0XFF18001C</B>
\r
17020 <TD width=15% BGCOLOR=#C0C0C0>
\r
17023 <TD width=10% BGCOLOR=#C0C0C0>
\r
17026 <TD width=10% BGCOLOR=#C0C0C0>
\r
17029 <TD width=15% BGCOLOR=#C0C0C0>
\r
17032 <TD width=35% BGCOLOR=#C0C0C0>
\r
17033 <B>Configures MIO Pin 7 peripheral interface mapping</B>
\r
17038 <H2><a name="MIO_PIN_8">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_8</a></H2>
\r
17039 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17040 <TR valign="top">
\r
17041 <TD width=15% BGCOLOR=#FFFF00>
\r
17042 <B>Register Name</B>
\r
17044 <TD width=15% BGCOLOR=#FFFF00>
\r
17047 <TD width=10% BGCOLOR=#FFFF00>
\r
17050 <TD width=10% BGCOLOR=#FFFF00>
\r
17053 <TD width=15% BGCOLOR=#FFFF00>
\r
17054 <B>Reset Value</B>
\r
17056 <TD width=35% BGCOLOR=#FFFF00>
\r
17057 <B>Description</B>
\r
17060 <TR valign="top">
\r
17061 <TD width=15% BGCOLOR=#FBF5EF>
\r
17064 <TD width=15% BGCOLOR=#FBF5EF>
\r
17065 <B>0XFF180020</B>
\r
17067 <TD width=10% BGCOLOR=#FBF5EF>
\r
17070 <TD width=10% BGCOLOR=#FBF5EF>
\r
17073 <TD width=15% BGCOLOR=#FBF5EF>
\r
17074 <B>0x00000000</B>
\r
17076 <TD width=35% BGCOLOR=#FBF5EF>
\r
17082 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17083 <TR valign="top">
\r
17084 <TD width=15% BGCOLOR=#C0FFC0>
\r
17085 <B>Field Name</B>
\r
17087 <TD width=15% BGCOLOR=#C0FFC0>
\r
17090 <TD width=10% BGCOLOR=#C0FFC0>
\r
17093 <TD width=10% BGCOLOR=#C0FFC0>
\r
17096 <TD width=15% BGCOLOR=#C0FFC0>
\r
17097 <B>Shifted Value</B>
\r
17099 <TD width=35% BGCOLOR=#C0FFC0>
\r
17100 <B>Description</B>
\r
17103 <TR valign="top">
\r
17104 <TD width=15% BGCOLOR=#FBF5EF>
\r
17105 <B>PSU_IOU_SLCR_MIO_PIN_8_L0_SEL</B>
\r
17107 <TD width=15% BGCOLOR=#FBF5EF>
\r
17110 <TD width=10% BGCOLOR=#FBF5EF>
\r
17113 <TD width=10% BGCOLOR=#FBF5EF>
\r
17116 <TD width=15% BGCOLOR=#FBF5EF>
\r
17119 <TD width=35% BGCOLOR=#FBF5EF>
\r
17120 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</B>
\r
17123 <TR valign="top">
\r
17124 <TD width=15% BGCOLOR=#FBF5EF>
\r
17125 <B>PSU_IOU_SLCR_MIO_PIN_8_L1_SEL</B>
\r
17127 <TD width=15% BGCOLOR=#FBF5EF>
\r
17130 <TD width=10% BGCOLOR=#FBF5EF>
\r
17133 <TD width=10% BGCOLOR=#FBF5EF>
\r
17136 <TD width=15% BGCOLOR=#FBF5EF>
\r
17139 <TD width=35% BGCOLOR=#FBF5EF>
\r
17140 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
17143 <TR valign="top">
\r
17144 <TD width=15% BGCOLOR=#FBF5EF>
\r
17145 <B>PSU_IOU_SLCR_MIO_PIN_8_L2_SEL</B>
\r
17147 <TD width=15% BGCOLOR=#FBF5EF>
\r
17150 <TD width=10% BGCOLOR=#FBF5EF>
\r
17153 <TD width=10% BGCOLOR=#FBF5EF>
\r
17156 <TD width=15% BGCOLOR=#FBF5EF>
\r
17159 <TD width=35% BGCOLOR=#FBF5EF>
\r
17160 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8]- (Test Scan Port) 3= Not Used</B>
\r
17163 <TR valign="top">
\r
17164 <TD width=15% BGCOLOR=#FBF5EF>
\r
17165 <B>PSU_IOU_SLCR_MIO_PIN_8_L3_SEL</B>
\r
17167 <TD width=15% BGCOLOR=#FBF5EF>
\r
17170 <TD width=10% BGCOLOR=#FBF5EF>
\r
17173 <TD width=10% BGCOLOR=#FBF5EF>
\r
17176 <TD width=15% BGCOLOR=#FBF5EF>
\r
17179 <TD width=35% BGCOLOR=#FBF5EF>
\r
17180 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B>
\r
17183 <TR valign="top">
\r
17184 <TD width=15% BGCOLOR=#C0C0C0>
\r
17185 <B>PSU_IOU_SLCR_MIO_PIN_8@0XFF180020</B>
\r
17187 <TD width=15% BGCOLOR=#C0C0C0>
\r
17190 <TD width=10% BGCOLOR=#C0C0C0>
\r
17193 <TD width=10% BGCOLOR=#C0C0C0>
\r
17196 <TD width=15% BGCOLOR=#C0C0C0>
\r
17199 <TD width=35% BGCOLOR=#C0C0C0>
\r
17200 <B>Configures MIO Pin 8 peripheral interface mapping</B>
\r
17205 <H2><a name="MIO_PIN_9">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_9</a></H2>
\r
17206 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17207 <TR valign="top">
\r
17208 <TD width=15% BGCOLOR=#FFFF00>
\r
17209 <B>Register Name</B>
\r
17211 <TD width=15% BGCOLOR=#FFFF00>
\r
17214 <TD width=10% BGCOLOR=#FFFF00>
\r
17217 <TD width=10% BGCOLOR=#FFFF00>
\r
17220 <TD width=15% BGCOLOR=#FFFF00>
\r
17221 <B>Reset Value</B>
\r
17223 <TD width=35% BGCOLOR=#FFFF00>
\r
17224 <B>Description</B>
\r
17227 <TR valign="top">
\r
17228 <TD width=15% BGCOLOR=#FBF5EF>
\r
17231 <TD width=15% BGCOLOR=#FBF5EF>
\r
17232 <B>0XFF180024</B>
\r
17234 <TD width=10% BGCOLOR=#FBF5EF>
\r
17237 <TD width=10% BGCOLOR=#FBF5EF>
\r
17240 <TD width=15% BGCOLOR=#FBF5EF>
\r
17241 <B>0x00000000</B>
\r
17243 <TD width=35% BGCOLOR=#FBF5EF>
\r
17249 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17250 <TR valign="top">
\r
17251 <TD width=15% BGCOLOR=#C0FFC0>
\r
17252 <B>Field Name</B>
\r
17254 <TD width=15% BGCOLOR=#C0FFC0>
\r
17257 <TD width=10% BGCOLOR=#C0FFC0>
\r
17260 <TD width=10% BGCOLOR=#C0FFC0>
\r
17263 <TD width=15% BGCOLOR=#C0FFC0>
\r
17264 <B>Shifted Value</B>
\r
17266 <TD width=35% BGCOLOR=#C0FFC0>
\r
17267 <B>Description</B>
\r
17270 <TR valign="top">
\r
17271 <TD width=15% BGCOLOR=#FBF5EF>
\r
17272 <B>PSU_IOU_SLCR_MIO_PIN_9_L0_SEL</B>
\r
17274 <TD width=15% BGCOLOR=#FBF5EF>
\r
17277 <TD width=10% BGCOLOR=#FBF5EF>
\r
17280 <TD width=10% BGCOLOR=#FBF5EF>
\r
17283 <TD width=15% BGCOLOR=#FBF5EF>
\r
17286 <TD width=35% BGCOLOR=#FBF5EF>
\r
17287 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</B>
\r
17290 <TR valign="top">
\r
17291 <TD width=15% BGCOLOR=#FBF5EF>
\r
17292 <B>PSU_IOU_SLCR_MIO_PIN_9_L1_SEL</B>
\r
17294 <TD width=15% BGCOLOR=#FBF5EF>
\r
17297 <TD width=10% BGCOLOR=#FBF5EF>
\r
17300 <TD width=10% BGCOLOR=#FBF5EF>
\r
17303 <TD width=15% BGCOLOR=#FBF5EF>
\r
17306 <TD width=35% BGCOLOR=#FBF5EF>
\r
17307 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)</B>
\r
17310 <TR valign="top">
\r
17311 <TD width=15% BGCOLOR=#FBF5EF>
\r
17312 <B>PSU_IOU_SLCR_MIO_PIN_9_L2_SEL</B>
\r
17314 <TD width=15% BGCOLOR=#FBF5EF>
\r
17317 <TD width=10% BGCOLOR=#FBF5EF>
\r
17320 <TD width=10% BGCOLOR=#FBF5EF>
\r
17323 <TD width=15% BGCOLOR=#FBF5EF>
\r
17326 <TD width=35% BGCOLOR=#FBF5EF>
\r
17327 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9]- (Test Scan Port) 3= Not Used</B>
\r
17330 <TR valign="top">
\r
17331 <TD width=15% BGCOLOR=#FBF5EF>
\r
17332 <B>PSU_IOU_SLCR_MIO_PIN_9_L3_SEL</B>
\r
17334 <TD width=15% BGCOLOR=#FBF5EF>
\r
17337 <TD width=10% BGCOLOR=#FBF5EF>
\r
17340 <TD width=10% BGCOLOR=#FBF5EF>
\r
17343 <TD width=15% BGCOLOR=#FBF5EF>
\r
17346 <TD width=35% BGCOLOR=#FBF5EF>
\r
17347 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B>
\r
17350 <TR valign="top">
\r
17351 <TD width=15% BGCOLOR=#C0C0C0>
\r
17352 <B>PSU_IOU_SLCR_MIO_PIN_9@0XFF180024</B>
\r
17354 <TD width=15% BGCOLOR=#C0C0C0>
\r
17357 <TD width=10% BGCOLOR=#C0C0C0>
\r
17360 <TD width=10% BGCOLOR=#C0C0C0>
\r
17363 <TD width=15% BGCOLOR=#C0C0C0>
\r
17366 <TD width=35% BGCOLOR=#C0C0C0>
\r
17367 <B>Configures MIO Pin 9 peripheral interface mapping</B>
\r
17372 <H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
\r
17373 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17374 <TR valign="top">
\r
17375 <TD width=15% BGCOLOR=#FFFF00>
\r
17376 <B>Register Name</B>
\r
17378 <TD width=15% BGCOLOR=#FFFF00>
\r
17381 <TD width=10% BGCOLOR=#FFFF00>
\r
17384 <TD width=10% BGCOLOR=#FFFF00>
\r
17387 <TD width=15% BGCOLOR=#FFFF00>
\r
17388 <B>Reset Value</B>
\r
17390 <TD width=35% BGCOLOR=#FFFF00>
\r
17391 <B>Description</B>
\r
17394 <TR valign="top">
\r
17395 <TD width=15% BGCOLOR=#FBF5EF>
\r
17396 <B>MIO_PIN_10</B>
\r
17398 <TD width=15% BGCOLOR=#FBF5EF>
\r
17399 <B>0XFF180028</B>
\r
17401 <TD width=10% BGCOLOR=#FBF5EF>
\r
17404 <TD width=10% BGCOLOR=#FBF5EF>
\r
17407 <TD width=15% BGCOLOR=#FBF5EF>
\r
17408 <B>0x00000000</B>
\r
17410 <TD width=35% BGCOLOR=#FBF5EF>
\r
17416 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17417 <TR valign="top">
\r
17418 <TD width=15% BGCOLOR=#C0FFC0>
\r
17419 <B>Field Name</B>
\r
17421 <TD width=15% BGCOLOR=#C0FFC0>
\r
17424 <TD width=10% BGCOLOR=#C0FFC0>
\r
17427 <TD width=10% BGCOLOR=#C0FFC0>
\r
17430 <TD width=15% BGCOLOR=#C0FFC0>
\r
17431 <B>Shifted Value</B>
\r
17433 <TD width=35% BGCOLOR=#C0FFC0>
\r
17434 <B>Description</B>
\r
17437 <TR valign="top">
\r
17438 <TD width=15% BGCOLOR=#FBF5EF>
\r
17439 <B>PSU_IOU_SLCR_MIO_PIN_10_L0_SEL</B>
\r
17441 <TD width=15% BGCOLOR=#FBF5EF>
\r
17444 <TD width=10% BGCOLOR=#FBF5EF>
\r
17447 <TD width=10% BGCOLOR=#FBF5EF>
\r
17450 <TD width=15% BGCOLOR=#FBF5EF>
\r
17453 <TD width=35% BGCOLOR=#FBF5EF>
\r
17454 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</B>
\r
17457 <TR valign="top">
\r
17458 <TD width=15% BGCOLOR=#FBF5EF>
\r
17459 <B>PSU_IOU_SLCR_MIO_PIN_10_L1_SEL</B>
\r
17461 <TD width=15% BGCOLOR=#FBF5EF>
\r
17464 <TD width=10% BGCOLOR=#FBF5EF>
\r
17467 <TD width=10% BGCOLOR=#FBF5EF>
\r
17470 <TD width=15% BGCOLOR=#FBF5EF>
\r
17473 <TD width=35% BGCOLOR=#FBF5EF>
\r
17474 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)</B>
\r
17477 <TR valign="top">
\r
17478 <TD width=15% BGCOLOR=#FBF5EF>
\r
17479 <B>PSU_IOU_SLCR_MIO_PIN_10_L2_SEL</B>
\r
17481 <TD width=15% BGCOLOR=#FBF5EF>
\r
17484 <TD width=10% BGCOLOR=#FBF5EF>
\r
17487 <TD width=10% BGCOLOR=#FBF5EF>
\r
17490 <TD width=15% BGCOLOR=#FBF5EF>
\r
17493 <TD width=35% BGCOLOR=#FBF5EF>
\r
17494 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[10]- (Test Scan Port) 3= Not Used</B>
\r
17497 <TR valign="top">
\r
17498 <TD width=15% BGCOLOR=#FBF5EF>
\r
17499 <B>PSU_IOU_SLCR_MIO_PIN_10_L3_SEL</B>
\r
17501 <TD width=15% BGCOLOR=#FBF5EF>
\r
17504 <TD width=10% BGCOLOR=#FBF5EF>
\r
17507 <TD width=10% BGCOLOR=#FBF5EF>
\r
17510 <TD width=15% BGCOLOR=#FBF5EF>
\r
17513 <TD width=35% BGCOLOR=#FBF5EF>
\r
17514 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B>
\r
17517 <TR valign="top">
\r
17518 <TD width=15% BGCOLOR=#C0C0C0>
\r
17519 <B>PSU_IOU_SLCR_MIO_PIN_10@0XFF180028</B>
\r
17521 <TD width=15% BGCOLOR=#C0C0C0>
\r
17524 <TD width=10% BGCOLOR=#C0C0C0>
\r
17527 <TD width=10% BGCOLOR=#C0C0C0>
\r
17530 <TD width=15% BGCOLOR=#C0C0C0>
\r
17533 <TD width=35% BGCOLOR=#C0C0C0>
\r
17534 <B>Configures MIO Pin 10 peripheral interface mapping</B>
\r
17539 <H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
\r
17540 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17541 <TR valign="top">
\r
17542 <TD width=15% BGCOLOR=#FFFF00>
\r
17543 <B>Register Name</B>
\r
17545 <TD width=15% BGCOLOR=#FFFF00>
\r
17548 <TD width=10% BGCOLOR=#FFFF00>
\r
17551 <TD width=10% BGCOLOR=#FFFF00>
\r
17554 <TD width=15% BGCOLOR=#FFFF00>
\r
17555 <B>Reset Value</B>
\r
17557 <TD width=35% BGCOLOR=#FFFF00>
\r
17558 <B>Description</B>
\r
17561 <TR valign="top">
\r
17562 <TD width=15% BGCOLOR=#FBF5EF>
\r
17563 <B>MIO_PIN_11</B>
\r
17565 <TD width=15% BGCOLOR=#FBF5EF>
\r
17566 <B>0XFF18002C</B>
\r
17568 <TD width=10% BGCOLOR=#FBF5EF>
\r
17571 <TD width=10% BGCOLOR=#FBF5EF>
\r
17574 <TD width=15% BGCOLOR=#FBF5EF>
\r
17575 <B>0x00000000</B>
\r
17577 <TD width=35% BGCOLOR=#FBF5EF>
\r
17583 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17584 <TR valign="top">
\r
17585 <TD width=15% BGCOLOR=#C0FFC0>
\r
17586 <B>Field Name</B>
\r
17588 <TD width=15% BGCOLOR=#C0FFC0>
\r
17591 <TD width=10% BGCOLOR=#C0FFC0>
\r
17594 <TD width=10% BGCOLOR=#C0FFC0>
\r
17597 <TD width=15% BGCOLOR=#C0FFC0>
\r
17598 <B>Shifted Value</B>
\r
17600 <TD width=35% BGCOLOR=#C0FFC0>
\r
17601 <B>Description</B>
\r
17604 <TR valign="top">
\r
17605 <TD width=15% BGCOLOR=#FBF5EF>
\r
17606 <B>PSU_IOU_SLCR_MIO_PIN_11_L0_SEL</B>
\r
17608 <TD width=15% BGCOLOR=#FBF5EF>
\r
17611 <TD width=10% BGCOLOR=#FBF5EF>
\r
17614 <TD width=10% BGCOLOR=#FBF5EF>
\r
17617 <TD width=15% BGCOLOR=#FBF5EF>
\r
17620 <TD width=35% BGCOLOR=#FBF5EF>
\r
17621 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</B>
\r
17624 <TR valign="top">
\r
17625 <TD width=15% BGCOLOR=#FBF5EF>
\r
17626 <B>PSU_IOU_SLCR_MIO_PIN_11_L1_SEL</B>
\r
17628 <TD width=15% BGCOLOR=#FBF5EF>
\r
17631 <TD width=10% BGCOLOR=#FBF5EF>
\r
17634 <TD width=10% BGCOLOR=#FBF5EF>
\r
17637 <TD width=15% BGCOLOR=#FBF5EF>
\r
17640 <TD width=35% BGCOLOR=#FBF5EF>
\r
17641 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)</B>
\r
17644 <TR valign="top">
\r
17645 <TD width=15% BGCOLOR=#FBF5EF>
\r
17646 <B>PSU_IOU_SLCR_MIO_PIN_11_L2_SEL</B>
\r
17648 <TD width=15% BGCOLOR=#FBF5EF>
\r
17651 <TD width=10% BGCOLOR=#FBF5EF>
\r
17654 <TD width=10% BGCOLOR=#FBF5EF>
\r
17657 <TD width=15% BGCOLOR=#FBF5EF>
\r
17660 <TD width=35% BGCOLOR=#FBF5EF>
\r
17661 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[11]- (Test Scan Port) 3= Not Used</B>
\r
17664 <TR valign="top">
\r
17665 <TD width=15% BGCOLOR=#FBF5EF>
\r
17666 <B>PSU_IOU_SLCR_MIO_PIN_11_L3_SEL</B>
\r
17668 <TD width=15% BGCOLOR=#FBF5EF>
\r
17671 <TD width=10% BGCOLOR=#FBF5EF>
\r
17674 <TD width=10% BGCOLOR=#FBF5EF>
\r
17677 <TD width=15% BGCOLOR=#FBF5EF>
\r
17680 <TD width=35% BGCOLOR=#FBF5EF>
\r
17681 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B>
\r
17684 <TR valign="top">
\r
17685 <TD width=15% BGCOLOR=#C0C0C0>
\r
17686 <B>PSU_IOU_SLCR_MIO_PIN_11@0XFF18002C</B>
\r
17688 <TD width=15% BGCOLOR=#C0C0C0>
\r
17691 <TD width=10% BGCOLOR=#C0C0C0>
\r
17694 <TD width=10% BGCOLOR=#C0C0C0>
\r
17697 <TD width=15% BGCOLOR=#C0C0C0>
\r
17700 <TD width=35% BGCOLOR=#C0C0C0>
\r
17701 <B>Configures MIO Pin 11 peripheral interface mapping</B>
\r
17706 <H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
\r
17707 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17708 <TR valign="top">
\r
17709 <TD width=15% BGCOLOR=#FFFF00>
\r
17710 <B>Register Name</B>
\r
17712 <TD width=15% BGCOLOR=#FFFF00>
\r
17715 <TD width=10% BGCOLOR=#FFFF00>
\r
17718 <TD width=10% BGCOLOR=#FFFF00>
\r
17721 <TD width=15% BGCOLOR=#FFFF00>
\r
17722 <B>Reset Value</B>
\r
17724 <TD width=35% BGCOLOR=#FFFF00>
\r
17725 <B>Description</B>
\r
17728 <TR valign="top">
\r
17729 <TD width=15% BGCOLOR=#FBF5EF>
\r
17730 <B>MIO_PIN_12</B>
\r
17732 <TD width=15% BGCOLOR=#FBF5EF>
\r
17733 <B>0XFF180030</B>
\r
17735 <TD width=10% BGCOLOR=#FBF5EF>
\r
17738 <TD width=10% BGCOLOR=#FBF5EF>
\r
17741 <TD width=15% BGCOLOR=#FBF5EF>
\r
17742 <B>0x00000000</B>
\r
17744 <TD width=35% BGCOLOR=#FBF5EF>
\r
17750 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17751 <TR valign="top">
\r
17752 <TD width=15% BGCOLOR=#C0FFC0>
\r
17753 <B>Field Name</B>
\r
17755 <TD width=15% BGCOLOR=#C0FFC0>
\r
17758 <TD width=10% BGCOLOR=#C0FFC0>
\r
17761 <TD width=10% BGCOLOR=#C0FFC0>
\r
17764 <TD width=15% BGCOLOR=#C0FFC0>
\r
17765 <B>Shifted Value</B>
\r
17767 <TD width=35% BGCOLOR=#C0FFC0>
\r
17768 <B>Description</B>
\r
17771 <TR valign="top">
\r
17772 <TD width=15% BGCOLOR=#FBF5EF>
\r
17773 <B>PSU_IOU_SLCR_MIO_PIN_12_L0_SEL</B>
\r
17775 <TD width=15% BGCOLOR=#FBF5EF>
\r
17778 <TD width=10% BGCOLOR=#FBF5EF>
\r
17781 <TD width=10% BGCOLOR=#FBF5EF>
\r
17784 <TD width=15% BGCOLOR=#FBF5EF>
\r
17787 <TD width=35% BGCOLOR=#FBF5EF>
\r
17788 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</B>
\r
17791 <TR valign="top">
\r
17792 <TD width=15% BGCOLOR=#FBF5EF>
\r
17793 <B>PSU_IOU_SLCR_MIO_PIN_12_L1_SEL</B>
\r
17795 <TD width=15% BGCOLOR=#FBF5EF>
\r
17798 <TD width=10% BGCOLOR=#FBF5EF>
\r
17801 <TD width=10% BGCOLOR=#FBF5EF>
\r
17804 <TD width=15% BGCOLOR=#FBF5EF>
\r
17807 <TD width=35% BGCOLOR=#FBF5EF>
\r
17808 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)</B>
\r
17811 <TR valign="top">
\r
17812 <TD width=15% BGCOLOR=#FBF5EF>
\r
17813 <B>PSU_IOU_SLCR_MIO_PIN_12_L2_SEL</B>
\r
17815 <TD width=15% BGCOLOR=#FBF5EF>
\r
17818 <TD width=10% BGCOLOR=#FBF5EF>
\r
17821 <TD width=10% BGCOLOR=#FBF5EF>
\r
17824 <TD width=15% BGCOLOR=#FBF5EF>
\r
17827 <TD width=35% BGCOLOR=#FBF5EF>
\r
17828 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[12]- (Test Scan Port) 3= Not Used</B>
\r
17831 <TR valign="top">
\r
17832 <TD width=15% BGCOLOR=#FBF5EF>
\r
17833 <B>PSU_IOU_SLCR_MIO_PIN_12_L3_SEL</B>
\r
17835 <TD width=15% BGCOLOR=#FBF5EF>
\r
17838 <TD width=10% BGCOLOR=#FBF5EF>
\r
17841 <TD width=10% BGCOLOR=#FBF5EF>
\r
17844 <TD width=15% BGCOLOR=#FBF5EF>
\r
17847 <TD width=35% BGCOLOR=#FBF5EF>
\r
17848 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B>
\r
17851 <TR valign="top">
\r
17852 <TD width=15% BGCOLOR=#C0C0C0>
\r
17853 <B>PSU_IOU_SLCR_MIO_PIN_12@0XFF180030</B>
\r
17855 <TD width=15% BGCOLOR=#C0C0C0>
\r
17858 <TD width=10% BGCOLOR=#C0C0C0>
\r
17861 <TD width=10% BGCOLOR=#C0C0C0>
\r
17864 <TD width=15% BGCOLOR=#C0C0C0>
\r
17867 <TD width=35% BGCOLOR=#C0C0C0>
\r
17868 <B>Configures MIO Pin 12 peripheral interface mapping</B>
\r
17873 <H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
\r
17874 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17875 <TR valign="top">
\r
17876 <TD width=15% BGCOLOR=#FFFF00>
\r
17877 <B>Register Name</B>
\r
17879 <TD width=15% BGCOLOR=#FFFF00>
\r
17882 <TD width=10% BGCOLOR=#FFFF00>
\r
17885 <TD width=10% BGCOLOR=#FFFF00>
\r
17888 <TD width=15% BGCOLOR=#FFFF00>
\r
17889 <B>Reset Value</B>
\r
17891 <TD width=35% BGCOLOR=#FFFF00>
\r
17892 <B>Description</B>
\r
17895 <TR valign="top">
\r
17896 <TD width=15% BGCOLOR=#FBF5EF>
\r
17897 <B>MIO_PIN_13</B>
\r
17899 <TD width=15% BGCOLOR=#FBF5EF>
\r
17900 <B>0XFF180034</B>
\r
17902 <TD width=10% BGCOLOR=#FBF5EF>
\r
17905 <TD width=10% BGCOLOR=#FBF5EF>
\r
17908 <TD width=15% BGCOLOR=#FBF5EF>
\r
17909 <B>0x00000000</B>
\r
17911 <TD width=35% BGCOLOR=#FBF5EF>
\r
17917 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
17918 <TR valign="top">
\r
17919 <TD width=15% BGCOLOR=#C0FFC0>
\r
17920 <B>Field Name</B>
\r
17922 <TD width=15% BGCOLOR=#C0FFC0>
\r
17925 <TD width=10% BGCOLOR=#C0FFC0>
\r
17928 <TD width=10% BGCOLOR=#C0FFC0>
\r
17931 <TD width=15% BGCOLOR=#C0FFC0>
\r
17932 <B>Shifted Value</B>
\r
17934 <TD width=35% BGCOLOR=#C0FFC0>
\r
17935 <B>Description</B>
\r
17938 <TR valign="top">
\r
17939 <TD width=15% BGCOLOR=#FBF5EF>
\r
17940 <B>PSU_IOU_SLCR_MIO_PIN_13_L0_SEL</B>
\r
17942 <TD width=15% BGCOLOR=#FBF5EF>
\r
17945 <TD width=10% BGCOLOR=#FBF5EF>
\r
17948 <TD width=10% BGCOLOR=#FBF5EF>
\r
17951 <TD width=15% BGCOLOR=#FBF5EF>
\r
17954 <TD width=35% BGCOLOR=#FBF5EF>
\r
17955 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
17958 <TR valign="top">
\r
17959 <TD width=15% BGCOLOR=#FBF5EF>
\r
17960 <B>PSU_IOU_SLCR_MIO_PIN_13_L1_SEL</B>
\r
17962 <TD width=15% BGCOLOR=#FBF5EF>
\r
17965 <TD width=10% BGCOLOR=#FBF5EF>
\r
17968 <TD width=10% BGCOLOR=#FBF5EF>
\r
17971 <TD width=15% BGCOLOR=#FBF5EF>
\r
17974 <TD width=35% BGCOLOR=#FBF5EF>
\r
17975 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)</B>
\r
17978 <TR valign="top">
\r
17979 <TD width=15% BGCOLOR=#FBF5EF>
\r
17980 <B>PSU_IOU_SLCR_MIO_PIN_13_L2_SEL</B>
\r
17982 <TD width=15% BGCOLOR=#FBF5EF>
\r
17985 <TD width=10% BGCOLOR=#FBF5EF>
\r
17988 <TD width=10% BGCOLOR=#FBF5EF>
\r
17991 <TD width=15% BGCOLOR=#FBF5EF>
\r
17994 <TD width=35% BGCOLOR=#FBF5EF>
\r
17995 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port) 3= Not Used</B>
\r
17998 <TR valign="top">
\r
17999 <TD width=15% BGCOLOR=#FBF5EF>
\r
18000 <B>PSU_IOU_SLCR_MIO_PIN_13_L3_SEL</B>
\r
18002 <TD width=15% BGCOLOR=#FBF5EF>
\r
18005 <TD width=10% BGCOLOR=#FBF5EF>
\r
18008 <TD width=10% BGCOLOR=#FBF5EF>
\r
18011 <TD width=15% BGCOLOR=#FBF5EF>
\r
18014 <TD width=35% BGCOLOR=#FBF5EF>
\r
18015 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B>
\r
18018 <TR valign="top">
\r
18019 <TD width=15% BGCOLOR=#C0C0C0>
\r
18020 <B>PSU_IOU_SLCR_MIO_PIN_13@0XFF180034</B>
\r
18022 <TD width=15% BGCOLOR=#C0C0C0>
\r
18025 <TD width=10% BGCOLOR=#C0C0C0>
\r
18028 <TD width=10% BGCOLOR=#C0C0C0>
\r
18031 <TD width=15% BGCOLOR=#C0C0C0>
\r
18034 <TD width=35% BGCOLOR=#C0C0C0>
\r
18035 <B>Configures MIO Pin 13 peripheral interface mapping</B>
\r
18040 <H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
\r
18041 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18042 <TR valign="top">
\r
18043 <TD width=15% BGCOLOR=#FFFF00>
\r
18044 <B>Register Name</B>
\r
18046 <TD width=15% BGCOLOR=#FFFF00>
\r
18049 <TD width=10% BGCOLOR=#FFFF00>
\r
18052 <TD width=10% BGCOLOR=#FFFF00>
\r
18055 <TD width=15% BGCOLOR=#FFFF00>
\r
18056 <B>Reset Value</B>
\r
18058 <TD width=35% BGCOLOR=#FFFF00>
\r
18059 <B>Description</B>
\r
18062 <TR valign="top">
\r
18063 <TD width=15% BGCOLOR=#FBF5EF>
\r
18064 <B>MIO_PIN_14</B>
\r
18066 <TD width=15% BGCOLOR=#FBF5EF>
\r
18067 <B>0XFF180038</B>
\r
18069 <TD width=10% BGCOLOR=#FBF5EF>
\r
18072 <TD width=10% BGCOLOR=#FBF5EF>
\r
18075 <TD width=15% BGCOLOR=#FBF5EF>
\r
18076 <B>0x00000000</B>
\r
18078 <TD width=35% BGCOLOR=#FBF5EF>
\r
18084 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18085 <TR valign="top">
\r
18086 <TD width=15% BGCOLOR=#C0FFC0>
\r
18087 <B>Field Name</B>
\r
18089 <TD width=15% BGCOLOR=#C0FFC0>
\r
18092 <TD width=10% BGCOLOR=#C0FFC0>
\r
18095 <TD width=10% BGCOLOR=#C0FFC0>
\r
18098 <TD width=15% BGCOLOR=#C0FFC0>
\r
18099 <B>Shifted Value</B>
\r
18101 <TD width=35% BGCOLOR=#C0FFC0>
\r
18102 <B>Description</B>
\r
18105 <TR valign="top">
\r
18106 <TD width=15% BGCOLOR=#FBF5EF>
\r
18107 <B>PSU_IOU_SLCR_MIO_PIN_14_L0_SEL</B>
\r
18109 <TD width=15% BGCOLOR=#FBF5EF>
\r
18112 <TD width=10% BGCOLOR=#FBF5EF>
\r
18115 <TD width=10% BGCOLOR=#FBF5EF>
\r
18118 <TD width=15% BGCOLOR=#FBF5EF>
\r
18121 <TD width=35% BGCOLOR=#FBF5EF>
\r
18122 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18125 <TR valign="top">
\r
18126 <TD width=15% BGCOLOR=#FBF5EF>
\r
18127 <B>PSU_IOU_SLCR_MIO_PIN_14_L1_SEL</B>
\r
18129 <TD width=15% BGCOLOR=#FBF5EF>
\r
18132 <TD width=10% BGCOLOR=#FBF5EF>
\r
18135 <TD width=10% BGCOLOR=#FBF5EF>
\r
18138 <TD width=15% BGCOLOR=#FBF5EF>
\r
18141 <TD width=35% BGCOLOR=#FBF5EF>
\r
18142 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)</B>
\r
18145 <TR valign="top">
\r
18146 <TD width=15% BGCOLOR=#FBF5EF>
\r
18147 <B>PSU_IOU_SLCR_MIO_PIN_14_L2_SEL</B>
\r
18149 <TD width=15% BGCOLOR=#FBF5EF>
\r
18152 <TD width=10% BGCOLOR=#FBF5EF>
\r
18155 <TD width=10% BGCOLOR=#FBF5EF>
\r
18158 <TD width=15% BGCOLOR=#FBF5EF>
\r
18161 <TD width=35% BGCOLOR=#FBF5EF>
\r
18162 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port) 3= Not Used</B>
\r
18165 <TR valign="top">
\r
18166 <TD width=15% BGCOLOR=#FBF5EF>
\r
18167 <B>PSU_IOU_SLCR_MIO_PIN_14_L3_SEL</B>
\r
18169 <TD width=15% BGCOLOR=#FBF5EF>
\r
18172 <TD width=10% BGCOLOR=#FBF5EF>
\r
18175 <TD width=10% BGCOLOR=#FBF5EF>
\r
18178 <TD width=15% BGCOLOR=#FBF5EF>
\r
18181 <TD width=35% BGCOLOR=#FBF5EF>
\r
18182 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B>
\r
18185 <TR valign="top">
\r
18186 <TD width=15% BGCOLOR=#C0C0C0>
\r
18187 <B>PSU_IOU_SLCR_MIO_PIN_14@0XFF180038</B>
\r
18189 <TD width=15% BGCOLOR=#C0C0C0>
\r
18192 <TD width=10% BGCOLOR=#C0C0C0>
\r
18195 <TD width=10% BGCOLOR=#C0C0C0>
\r
18198 <TD width=15% BGCOLOR=#C0C0C0>
\r
18201 <TD width=35% BGCOLOR=#C0C0C0>
\r
18202 <B>Configures MIO Pin 14 peripheral interface mapping</B>
\r
18207 <H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
\r
18208 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18209 <TR valign="top">
\r
18210 <TD width=15% BGCOLOR=#FFFF00>
\r
18211 <B>Register Name</B>
\r
18213 <TD width=15% BGCOLOR=#FFFF00>
\r
18216 <TD width=10% BGCOLOR=#FFFF00>
\r
18219 <TD width=10% BGCOLOR=#FFFF00>
\r
18222 <TD width=15% BGCOLOR=#FFFF00>
\r
18223 <B>Reset Value</B>
\r
18225 <TD width=35% BGCOLOR=#FFFF00>
\r
18226 <B>Description</B>
\r
18229 <TR valign="top">
\r
18230 <TD width=15% BGCOLOR=#FBF5EF>
\r
18231 <B>MIO_PIN_15</B>
\r
18233 <TD width=15% BGCOLOR=#FBF5EF>
\r
18234 <B>0XFF18003C</B>
\r
18236 <TD width=10% BGCOLOR=#FBF5EF>
\r
18239 <TD width=10% BGCOLOR=#FBF5EF>
\r
18242 <TD width=15% BGCOLOR=#FBF5EF>
\r
18243 <B>0x00000000</B>
\r
18245 <TD width=35% BGCOLOR=#FBF5EF>
\r
18251 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18252 <TR valign="top">
\r
18253 <TD width=15% BGCOLOR=#C0FFC0>
\r
18254 <B>Field Name</B>
\r
18256 <TD width=15% BGCOLOR=#C0FFC0>
\r
18259 <TD width=10% BGCOLOR=#C0FFC0>
\r
18262 <TD width=10% BGCOLOR=#C0FFC0>
\r
18265 <TD width=15% BGCOLOR=#C0FFC0>
\r
18266 <B>Shifted Value</B>
\r
18268 <TD width=35% BGCOLOR=#C0FFC0>
\r
18269 <B>Description</B>
\r
18272 <TR valign="top">
\r
18273 <TD width=15% BGCOLOR=#FBF5EF>
\r
18274 <B>PSU_IOU_SLCR_MIO_PIN_15_L0_SEL</B>
\r
18276 <TD width=15% BGCOLOR=#FBF5EF>
\r
18279 <TD width=10% BGCOLOR=#FBF5EF>
\r
18282 <TD width=10% BGCOLOR=#FBF5EF>
\r
18285 <TD width=15% BGCOLOR=#FBF5EF>
\r
18288 <TD width=35% BGCOLOR=#FBF5EF>
\r
18289 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18292 <TR valign="top">
\r
18293 <TD width=15% BGCOLOR=#FBF5EF>
\r
18294 <B>PSU_IOU_SLCR_MIO_PIN_15_L1_SEL</B>
\r
18296 <TD width=15% BGCOLOR=#FBF5EF>
\r
18299 <TD width=10% BGCOLOR=#FBF5EF>
\r
18302 <TD width=10% BGCOLOR=#FBF5EF>
\r
18305 <TD width=15% BGCOLOR=#FBF5EF>
\r
18308 <TD width=35% BGCOLOR=#FBF5EF>
\r
18309 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)</B>
\r
18312 <TR valign="top">
\r
18313 <TD width=15% BGCOLOR=#FBF5EF>
\r
18314 <B>PSU_IOU_SLCR_MIO_PIN_15_L2_SEL</B>
\r
18316 <TD width=15% BGCOLOR=#FBF5EF>
\r
18319 <TD width=10% BGCOLOR=#FBF5EF>
\r
18322 <TD width=10% BGCOLOR=#FBF5EF>
\r
18325 <TD width=15% BGCOLOR=#FBF5EF>
\r
18328 <TD width=35% BGCOLOR=#FBF5EF>
\r
18329 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port) 3= Not Used</B>
\r
18332 <TR valign="top">
\r
18333 <TD width=15% BGCOLOR=#FBF5EF>
\r
18334 <B>PSU_IOU_SLCR_MIO_PIN_15_L3_SEL</B>
\r
18336 <TD width=15% BGCOLOR=#FBF5EF>
\r
18339 <TD width=10% BGCOLOR=#FBF5EF>
\r
18342 <TD width=10% BGCOLOR=#FBF5EF>
\r
18345 <TD width=15% BGCOLOR=#FBF5EF>
\r
18348 <TD width=35% BGCOLOR=#FBF5EF>
\r
18349 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B>
\r
18352 <TR valign="top">
\r
18353 <TD width=15% BGCOLOR=#C0C0C0>
\r
18354 <B>PSU_IOU_SLCR_MIO_PIN_15@0XFF18003C</B>
\r
18356 <TD width=15% BGCOLOR=#C0C0C0>
\r
18359 <TD width=10% BGCOLOR=#C0C0C0>
\r
18362 <TD width=10% BGCOLOR=#C0C0C0>
\r
18365 <TD width=15% BGCOLOR=#C0C0C0>
\r
18368 <TD width=35% BGCOLOR=#C0C0C0>
\r
18369 <B>Configures MIO Pin 15 peripheral interface mapping</B>
\r
18374 <H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
\r
18375 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18376 <TR valign="top">
\r
18377 <TD width=15% BGCOLOR=#FFFF00>
\r
18378 <B>Register Name</B>
\r
18380 <TD width=15% BGCOLOR=#FFFF00>
\r
18383 <TD width=10% BGCOLOR=#FFFF00>
\r
18386 <TD width=10% BGCOLOR=#FFFF00>
\r
18389 <TD width=15% BGCOLOR=#FFFF00>
\r
18390 <B>Reset Value</B>
\r
18392 <TD width=35% BGCOLOR=#FFFF00>
\r
18393 <B>Description</B>
\r
18396 <TR valign="top">
\r
18397 <TD width=15% BGCOLOR=#FBF5EF>
\r
18398 <B>MIO_PIN_16</B>
\r
18400 <TD width=15% BGCOLOR=#FBF5EF>
\r
18401 <B>0XFF180040</B>
\r
18403 <TD width=10% BGCOLOR=#FBF5EF>
\r
18406 <TD width=10% BGCOLOR=#FBF5EF>
\r
18409 <TD width=15% BGCOLOR=#FBF5EF>
\r
18410 <B>0x00000000</B>
\r
18412 <TD width=35% BGCOLOR=#FBF5EF>
\r
18418 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18419 <TR valign="top">
\r
18420 <TD width=15% BGCOLOR=#C0FFC0>
\r
18421 <B>Field Name</B>
\r
18423 <TD width=15% BGCOLOR=#C0FFC0>
\r
18426 <TD width=10% BGCOLOR=#C0FFC0>
\r
18429 <TD width=10% BGCOLOR=#C0FFC0>
\r
18432 <TD width=15% BGCOLOR=#C0FFC0>
\r
18433 <B>Shifted Value</B>
\r
18435 <TD width=35% BGCOLOR=#C0FFC0>
\r
18436 <B>Description</B>
\r
18439 <TR valign="top">
\r
18440 <TD width=15% BGCOLOR=#FBF5EF>
\r
18441 <B>PSU_IOU_SLCR_MIO_PIN_16_L0_SEL</B>
\r
18443 <TD width=15% BGCOLOR=#FBF5EF>
\r
18446 <TD width=10% BGCOLOR=#FBF5EF>
\r
18449 <TD width=10% BGCOLOR=#FBF5EF>
\r
18452 <TD width=15% BGCOLOR=#FBF5EF>
\r
18455 <TD width=35% BGCOLOR=#FBF5EF>
\r
18456 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18459 <TR valign="top">
\r
18460 <TD width=15% BGCOLOR=#FBF5EF>
\r
18461 <B>PSU_IOU_SLCR_MIO_PIN_16_L1_SEL</B>
\r
18463 <TD width=15% BGCOLOR=#FBF5EF>
\r
18466 <TD width=10% BGCOLOR=#FBF5EF>
\r
18469 <TD width=10% BGCOLOR=#FBF5EF>
\r
18472 <TD width=15% BGCOLOR=#FBF5EF>
\r
18475 <TD width=35% BGCOLOR=#FBF5EF>
\r
18476 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)</B>
\r
18479 <TR valign="top">
\r
18480 <TD width=15% BGCOLOR=#FBF5EF>
\r
18481 <B>PSU_IOU_SLCR_MIO_PIN_16_L2_SEL</B>
\r
18483 <TD width=15% BGCOLOR=#FBF5EF>
\r
18486 <TD width=10% BGCOLOR=#FBF5EF>
\r
18489 <TD width=10% BGCOLOR=#FBF5EF>
\r
18492 <TD width=15% BGCOLOR=#FBF5EF>
\r
18495 <TD width=35% BGCOLOR=#FBF5EF>
\r
18496 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port) 3= Not Used</B>
\r
18499 <TR valign="top">
\r
18500 <TD width=15% BGCOLOR=#FBF5EF>
\r
18501 <B>PSU_IOU_SLCR_MIO_PIN_16_L3_SEL</B>
\r
18503 <TD width=15% BGCOLOR=#FBF5EF>
\r
18506 <TD width=10% BGCOLOR=#FBF5EF>
\r
18509 <TD width=10% BGCOLOR=#FBF5EF>
\r
18512 <TD width=15% BGCOLOR=#FBF5EF>
\r
18515 <TD width=35% BGCOLOR=#FBF5EF>
\r
18516 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B>
\r
18519 <TR valign="top">
\r
18520 <TD width=15% BGCOLOR=#C0C0C0>
\r
18521 <B>PSU_IOU_SLCR_MIO_PIN_16@0XFF180040</B>
\r
18523 <TD width=15% BGCOLOR=#C0C0C0>
\r
18526 <TD width=10% BGCOLOR=#C0C0C0>
\r
18529 <TD width=10% BGCOLOR=#C0C0C0>
\r
18532 <TD width=15% BGCOLOR=#C0C0C0>
\r
18535 <TD width=35% BGCOLOR=#C0C0C0>
\r
18536 <B>Configures MIO Pin 16 peripheral interface mapping</B>
\r
18541 <H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
\r
18542 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18543 <TR valign="top">
\r
18544 <TD width=15% BGCOLOR=#FFFF00>
\r
18545 <B>Register Name</B>
\r
18547 <TD width=15% BGCOLOR=#FFFF00>
\r
18550 <TD width=10% BGCOLOR=#FFFF00>
\r
18553 <TD width=10% BGCOLOR=#FFFF00>
\r
18556 <TD width=15% BGCOLOR=#FFFF00>
\r
18557 <B>Reset Value</B>
\r
18559 <TD width=35% BGCOLOR=#FFFF00>
\r
18560 <B>Description</B>
\r
18563 <TR valign="top">
\r
18564 <TD width=15% BGCOLOR=#FBF5EF>
\r
18565 <B>MIO_PIN_17</B>
\r
18567 <TD width=15% BGCOLOR=#FBF5EF>
\r
18568 <B>0XFF180044</B>
\r
18570 <TD width=10% BGCOLOR=#FBF5EF>
\r
18573 <TD width=10% BGCOLOR=#FBF5EF>
\r
18576 <TD width=15% BGCOLOR=#FBF5EF>
\r
18577 <B>0x00000000</B>
\r
18579 <TD width=35% BGCOLOR=#FBF5EF>
\r
18585 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18586 <TR valign="top">
\r
18587 <TD width=15% BGCOLOR=#C0FFC0>
\r
18588 <B>Field Name</B>
\r
18590 <TD width=15% BGCOLOR=#C0FFC0>
\r
18593 <TD width=10% BGCOLOR=#C0FFC0>
\r
18596 <TD width=10% BGCOLOR=#C0FFC0>
\r
18599 <TD width=15% BGCOLOR=#C0FFC0>
\r
18600 <B>Shifted Value</B>
\r
18602 <TD width=35% BGCOLOR=#C0FFC0>
\r
18603 <B>Description</B>
\r
18606 <TR valign="top">
\r
18607 <TD width=15% BGCOLOR=#FBF5EF>
\r
18608 <B>PSU_IOU_SLCR_MIO_PIN_17_L0_SEL</B>
\r
18610 <TD width=15% BGCOLOR=#FBF5EF>
\r
18613 <TD width=10% BGCOLOR=#FBF5EF>
\r
18616 <TD width=10% BGCOLOR=#FBF5EF>
\r
18619 <TD width=15% BGCOLOR=#FBF5EF>
\r
18622 <TD width=35% BGCOLOR=#FBF5EF>
\r
18623 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18626 <TR valign="top">
\r
18627 <TD width=15% BGCOLOR=#FBF5EF>
\r
18628 <B>PSU_IOU_SLCR_MIO_PIN_17_L1_SEL</B>
\r
18630 <TD width=15% BGCOLOR=#FBF5EF>
\r
18633 <TD width=10% BGCOLOR=#FBF5EF>
\r
18636 <TD width=10% BGCOLOR=#FBF5EF>
\r
18639 <TD width=15% BGCOLOR=#FBF5EF>
\r
18642 <TD width=35% BGCOLOR=#FBF5EF>
\r
18643 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)</B>
\r
18646 <TR valign="top">
\r
18647 <TD width=15% BGCOLOR=#FBF5EF>
\r
18648 <B>PSU_IOU_SLCR_MIO_PIN_17_L2_SEL</B>
\r
18650 <TD width=15% BGCOLOR=#FBF5EF>
\r
18653 <TD width=10% BGCOLOR=#FBF5EF>
\r
18656 <TD width=10% BGCOLOR=#FBF5EF>
\r
18659 <TD width=15% BGCOLOR=#FBF5EF>
\r
18662 <TD width=35% BGCOLOR=#FBF5EF>
\r
18663 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port) 3= Not Used</B>
\r
18666 <TR valign="top">
\r
18667 <TD width=15% BGCOLOR=#FBF5EF>
\r
18668 <B>PSU_IOU_SLCR_MIO_PIN_17_L3_SEL</B>
\r
18670 <TD width=15% BGCOLOR=#FBF5EF>
\r
18673 <TD width=10% BGCOLOR=#FBF5EF>
\r
18676 <TD width=10% BGCOLOR=#FBF5EF>
\r
18679 <TD width=15% BGCOLOR=#FBF5EF>
\r
18682 <TD width=35% BGCOLOR=#FBF5EF>
\r
18683 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B>
\r
18686 <TR valign="top">
\r
18687 <TD width=15% BGCOLOR=#C0C0C0>
\r
18688 <B>PSU_IOU_SLCR_MIO_PIN_17@0XFF180044</B>
\r
18690 <TD width=15% BGCOLOR=#C0C0C0>
\r
18693 <TD width=10% BGCOLOR=#C0C0C0>
\r
18696 <TD width=10% BGCOLOR=#C0C0C0>
\r
18699 <TD width=15% BGCOLOR=#C0C0C0>
\r
18702 <TD width=35% BGCOLOR=#C0C0C0>
\r
18703 <B>Configures MIO Pin 17 peripheral interface mapping</B>
\r
18708 <H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
\r
18709 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18710 <TR valign="top">
\r
18711 <TD width=15% BGCOLOR=#FFFF00>
\r
18712 <B>Register Name</B>
\r
18714 <TD width=15% BGCOLOR=#FFFF00>
\r
18717 <TD width=10% BGCOLOR=#FFFF00>
\r
18720 <TD width=10% BGCOLOR=#FFFF00>
\r
18723 <TD width=15% BGCOLOR=#FFFF00>
\r
18724 <B>Reset Value</B>
\r
18726 <TD width=35% BGCOLOR=#FFFF00>
\r
18727 <B>Description</B>
\r
18730 <TR valign="top">
\r
18731 <TD width=15% BGCOLOR=#FBF5EF>
\r
18732 <B>MIO_PIN_18</B>
\r
18734 <TD width=15% BGCOLOR=#FBF5EF>
\r
18735 <B>0XFF180048</B>
\r
18737 <TD width=10% BGCOLOR=#FBF5EF>
\r
18740 <TD width=10% BGCOLOR=#FBF5EF>
\r
18743 <TD width=15% BGCOLOR=#FBF5EF>
\r
18744 <B>0x00000000</B>
\r
18746 <TD width=35% BGCOLOR=#FBF5EF>
\r
18752 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18753 <TR valign="top">
\r
18754 <TD width=15% BGCOLOR=#C0FFC0>
\r
18755 <B>Field Name</B>
\r
18757 <TD width=15% BGCOLOR=#C0FFC0>
\r
18760 <TD width=10% BGCOLOR=#C0FFC0>
\r
18763 <TD width=10% BGCOLOR=#C0FFC0>
\r
18766 <TD width=15% BGCOLOR=#C0FFC0>
\r
18767 <B>Shifted Value</B>
\r
18769 <TD width=35% BGCOLOR=#C0FFC0>
\r
18770 <B>Description</B>
\r
18773 <TR valign="top">
\r
18774 <TD width=15% BGCOLOR=#FBF5EF>
\r
18775 <B>PSU_IOU_SLCR_MIO_PIN_18_L0_SEL</B>
\r
18777 <TD width=15% BGCOLOR=#FBF5EF>
\r
18780 <TD width=10% BGCOLOR=#FBF5EF>
\r
18783 <TD width=10% BGCOLOR=#FBF5EF>
\r
18786 <TD width=15% BGCOLOR=#FBF5EF>
\r
18789 <TD width=35% BGCOLOR=#FBF5EF>
\r
18790 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18793 <TR valign="top">
\r
18794 <TD width=15% BGCOLOR=#FBF5EF>
\r
18795 <B>PSU_IOU_SLCR_MIO_PIN_18_L1_SEL</B>
\r
18797 <TD width=15% BGCOLOR=#FBF5EF>
\r
18800 <TD width=10% BGCOLOR=#FBF5EF>
\r
18803 <TD width=10% BGCOLOR=#FBF5EF>
\r
18806 <TD width=15% BGCOLOR=#FBF5EF>
\r
18809 <TD width=35% BGCOLOR=#FBF5EF>
\r
18810 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)</B>
\r
18813 <TR valign="top">
\r
18814 <TD width=15% BGCOLOR=#FBF5EF>
\r
18815 <B>PSU_IOU_SLCR_MIO_PIN_18_L2_SEL</B>
\r
18817 <TD width=15% BGCOLOR=#FBF5EF>
\r
18820 <TD width=10% BGCOLOR=#FBF5EF>
\r
18823 <TD width=10% BGCOLOR=#FBF5EF>
\r
18826 <TD width=15% BGCOLOR=#FBF5EF>
\r
18829 <TD width=35% BGCOLOR=#FBF5EF>
\r
18830 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
18833 <TR valign="top">
\r
18834 <TD width=15% BGCOLOR=#FBF5EF>
\r
18835 <B>PSU_IOU_SLCR_MIO_PIN_18_L3_SEL</B>
\r
18837 <TD width=15% BGCOLOR=#FBF5EF>
\r
18840 <TD width=10% BGCOLOR=#FBF5EF>
\r
18843 <TD width=10% BGCOLOR=#FBF5EF>
\r
18846 <TD width=15% BGCOLOR=#FBF5EF>
\r
18849 <TD width=35% BGCOLOR=#FBF5EF>
\r
18850 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
18853 <TR valign="top">
\r
18854 <TD width=15% BGCOLOR=#C0C0C0>
\r
18855 <B>PSU_IOU_SLCR_MIO_PIN_18@0XFF180048</B>
\r
18857 <TD width=15% BGCOLOR=#C0C0C0>
\r
18860 <TD width=10% BGCOLOR=#C0C0C0>
\r
18863 <TD width=10% BGCOLOR=#C0C0C0>
\r
18866 <TD width=15% BGCOLOR=#C0C0C0>
\r
18869 <TD width=35% BGCOLOR=#C0C0C0>
\r
18870 <B>Configures MIO Pin 18 peripheral interface mapping</B>
\r
18875 <H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
\r
18876 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18877 <TR valign="top">
\r
18878 <TD width=15% BGCOLOR=#FFFF00>
\r
18879 <B>Register Name</B>
\r
18881 <TD width=15% BGCOLOR=#FFFF00>
\r
18884 <TD width=10% BGCOLOR=#FFFF00>
\r
18887 <TD width=10% BGCOLOR=#FFFF00>
\r
18890 <TD width=15% BGCOLOR=#FFFF00>
\r
18891 <B>Reset Value</B>
\r
18893 <TD width=35% BGCOLOR=#FFFF00>
\r
18894 <B>Description</B>
\r
18897 <TR valign="top">
\r
18898 <TD width=15% BGCOLOR=#FBF5EF>
\r
18899 <B>MIO_PIN_19</B>
\r
18901 <TD width=15% BGCOLOR=#FBF5EF>
\r
18902 <B>0XFF18004C</B>
\r
18904 <TD width=10% BGCOLOR=#FBF5EF>
\r
18907 <TD width=10% BGCOLOR=#FBF5EF>
\r
18910 <TD width=15% BGCOLOR=#FBF5EF>
\r
18911 <B>0x00000000</B>
\r
18913 <TD width=35% BGCOLOR=#FBF5EF>
\r
18919 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
18920 <TR valign="top">
\r
18921 <TD width=15% BGCOLOR=#C0FFC0>
\r
18922 <B>Field Name</B>
\r
18924 <TD width=15% BGCOLOR=#C0FFC0>
\r
18927 <TD width=10% BGCOLOR=#C0FFC0>
\r
18930 <TD width=10% BGCOLOR=#C0FFC0>
\r
18933 <TD width=15% BGCOLOR=#C0FFC0>
\r
18934 <B>Shifted Value</B>
\r
18936 <TD width=35% BGCOLOR=#C0FFC0>
\r
18937 <B>Description</B>
\r
18940 <TR valign="top">
\r
18941 <TD width=15% BGCOLOR=#FBF5EF>
\r
18942 <B>PSU_IOU_SLCR_MIO_PIN_19_L0_SEL</B>
\r
18944 <TD width=15% BGCOLOR=#FBF5EF>
\r
18947 <TD width=10% BGCOLOR=#FBF5EF>
\r
18950 <TD width=10% BGCOLOR=#FBF5EF>
\r
18953 <TD width=15% BGCOLOR=#FBF5EF>
\r
18956 <TD width=35% BGCOLOR=#FBF5EF>
\r
18957 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
18960 <TR valign="top">
\r
18961 <TD width=15% BGCOLOR=#FBF5EF>
\r
18962 <B>PSU_IOU_SLCR_MIO_PIN_19_L1_SEL</B>
\r
18964 <TD width=15% BGCOLOR=#FBF5EF>
\r
18967 <TD width=10% BGCOLOR=#FBF5EF>
\r
18970 <TD width=10% BGCOLOR=#FBF5EF>
\r
18973 <TD width=15% BGCOLOR=#FBF5EF>
\r
18976 <TD width=35% BGCOLOR=#FBF5EF>
\r
18977 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)</B>
\r
18980 <TR valign="top">
\r
18981 <TD width=15% BGCOLOR=#FBF5EF>
\r
18982 <B>PSU_IOU_SLCR_MIO_PIN_19_L2_SEL</B>
\r
18984 <TD width=15% BGCOLOR=#FBF5EF>
\r
18987 <TD width=10% BGCOLOR=#FBF5EF>
\r
18990 <TD width=10% BGCOLOR=#FBF5EF>
\r
18993 <TD width=15% BGCOLOR=#FBF5EF>
\r
18996 <TD width=35% BGCOLOR=#FBF5EF>
\r
18997 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19000 <TR valign="top">
\r
19001 <TD width=15% BGCOLOR=#FBF5EF>
\r
19002 <B>PSU_IOU_SLCR_MIO_PIN_19_L3_SEL</B>
\r
19004 <TD width=15% BGCOLOR=#FBF5EF>
\r
19007 <TD width=10% BGCOLOR=#FBF5EF>
\r
19010 <TD width=10% BGCOLOR=#FBF5EF>
\r
19013 <TD width=15% BGCOLOR=#FBF5EF>
\r
19016 <TD width=35% BGCOLOR=#FBF5EF>
\r
19017 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
19020 <TR valign="top">
\r
19021 <TD width=15% BGCOLOR=#C0C0C0>
\r
19022 <B>PSU_IOU_SLCR_MIO_PIN_19@0XFF18004C</B>
\r
19024 <TD width=15% BGCOLOR=#C0C0C0>
\r
19027 <TD width=10% BGCOLOR=#C0C0C0>
\r
19030 <TD width=10% BGCOLOR=#C0C0C0>
\r
19033 <TD width=15% BGCOLOR=#C0C0C0>
\r
19036 <TD width=35% BGCOLOR=#C0C0C0>
\r
19037 <B>Configures MIO Pin 19 peripheral interface mapping</B>
\r
19042 <H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
\r
19043 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19044 <TR valign="top">
\r
19045 <TD width=15% BGCOLOR=#FFFF00>
\r
19046 <B>Register Name</B>
\r
19048 <TD width=15% BGCOLOR=#FFFF00>
\r
19051 <TD width=10% BGCOLOR=#FFFF00>
\r
19054 <TD width=10% BGCOLOR=#FFFF00>
\r
19057 <TD width=15% BGCOLOR=#FFFF00>
\r
19058 <B>Reset Value</B>
\r
19060 <TD width=35% BGCOLOR=#FFFF00>
\r
19061 <B>Description</B>
\r
19064 <TR valign="top">
\r
19065 <TD width=15% BGCOLOR=#FBF5EF>
\r
19066 <B>MIO_PIN_20</B>
\r
19068 <TD width=15% BGCOLOR=#FBF5EF>
\r
19069 <B>0XFF180050</B>
\r
19071 <TD width=10% BGCOLOR=#FBF5EF>
\r
19074 <TD width=10% BGCOLOR=#FBF5EF>
\r
19077 <TD width=15% BGCOLOR=#FBF5EF>
\r
19078 <B>0x00000000</B>
\r
19080 <TD width=35% BGCOLOR=#FBF5EF>
\r
19086 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19087 <TR valign="top">
\r
19088 <TD width=15% BGCOLOR=#C0FFC0>
\r
19089 <B>Field Name</B>
\r
19091 <TD width=15% BGCOLOR=#C0FFC0>
\r
19094 <TD width=10% BGCOLOR=#C0FFC0>
\r
19097 <TD width=10% BGCOLOR=#C0FFC0>
\r
19100 <TD width=15% BGCOLOR=#C0FFC0>
\r
19101 <B>Shifted Value</B>
\r
19103 <TD width=35% BGCOLOR=#C0FFC0>
\r
19104 <B>Description</B>
\r
19107 <TR valign="top">
\r
19108 <TD width=15% BGCOLOR=#FBF5EF>
\r
19109 <B>PSU_IOU_SLCR_MIO_PIN_20_L0_SEL</B>
\r
19111 <TD width=15% BGCOLOR=#FBF5EF>
\r
19114 <TD width=10% BGCOLOR=#FBF5EF>
\r
19117 <TD width=10% BGCOLOR=#FBF5EF>
\r
19120 <TD width=15% BGCOLOR=#FBF5EF>
\r
19123 <TD width=35% BGCOLOR=#FBF5EF>
\r
19124 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19127 <TR valign="top">
\r
19128 <TD width=15% BGCOLOR=#FBF5EF>
\r
19129 <B>PSU_IOU_SLCR_MIO_PIN_20_L1_SEL</B>
\r
19131 <TD width=15% BGCOLOR=#FBF5EF>
\r
19134 <TD width=10% BGCOLOR=#FBF5EF>
\r
19137 <TD width=10% BGCOLOR=#FBF5EF>
\r
19140 <TD width=15% BGCOLOR=#FBF5EF>
\r
19143 <TD width=35% BGCOLOR=#FBF5EF>
\r
19144 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)</B>
\r
19147 <TR valign="top">
\r
19148 <TD width=15% BGCOLOR=#FBF5EF>
\r
19149 <B>PSU_IOU_SLCR_MIO_PIN_20_L2_SEL</B>
\r
19151 <TD width=15% BGCOLOR=#FBF5EF>
\r
19154 <TD width=10% BGCOLOR=#FBF5EF>
\r
19157 <TD width=10% BGCOLOR=#FBF5EF>
\r
19160 <TD width=15% BGCOLOR=#FBF5EF>
\r
19163 <TD width=35% BGCOLOR=#FBF5EF>
\r
19164 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19167 <TR valign="top">
\r
19168 <TD width=15% BGCOLOR=#FBF5EF>
\r
19169 <B>PSU_IOU_SLCR_MIO_PIN_20_L3_SEL</B>
\r
19171 <TD width=15% BGCOLOR=#FBF5EF>
\r
19174 <TD width=10% BGCOLOR=#FBF5EF>
\r
19177 <TD width=10% BGCOLOR=#FBF5EF>
\r
19180 <TD width=15% BGCOLOR=#FBF5EF>
\r
19183 <TD width=35% BGCOLOR=#FBF5EF>
\r
19184 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B>
\r
19187 <TR valign="top">
\r
19188 <TD width=15% BGCOLOR=#C0C0C0>
\r
19189 <B>PSU_IOU_SLCR_MIO_PIN_20@0XFF180050</B>
\r
19191 <TD width=15% BGCOLOR=#C0C0C0>
\r
19194 <TD width=10% BGCOLOR=#C0C0C0>
\r
19197 <TD width=10% BGCOLOR=#C0C0C0>
\r
19200 <TD width=15% BGCOLOR=#C0C0C0>
\r
19203 <TD width=35% BGCOLOR=#C0C0C0>
\r
19204 <B>Configures MIO Pin 20 peripheral interface mapping</B>
\r
19209 <H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
\r
19210 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19211 <TR valign="top">
\r
19212 <TD width=15% BGCOLOR=#FFFF00>
\r
19213 <B>Register Name</B>
\r
19215 <TD width=15% BGCOLOR=#FFFF00>
\r
19218 <TD width=10% BGCOLOR=#FFFF00>
\r
19221 <TD width=10% BGCOLOR=#FFFF00>
\r
19224 <TD width=15% BGCOLOR=#FFFF00>
\r
19225 <B>Reset Value</B>
\r
19227 <TD width=35% BGCOLOR=#FFFF00>
\r
19228 <B>Description</B>
\r
19231 <TR valign="top">
\r
19232 <TD width=15% BGCOLOR=#FBF5EF>
\r
19233 <B>MIO_PIN_21</B>
\r
19235 <TD width=15% BGCOLOR=#FBF5EF>
\r
19236 <B>0XFF180054</B>
\r
19238 <TD width=10% BGCOLOR=#FBF5EF>
\r
19241 <TD width=10% BGCOLOR=#FBF5EF>
\r
19244 <TD width=15% BGCOLOR=#FBF5EF>
\r
19245 <B>0x00000000</B>
\r
19247 <TD width=35% BGCOLOR=#FBF5EF>
\r
19253 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19254 <TR valign="top">
\r
19255 <TD width=15% BGCOLOR=#C0FFC0>
\r
19256 <B>Field Name</B>
\r
19258 <TD width=15% BGCOLOR=#C0FFC0>
\r
19261 <TD width=10% BGCOLOR=#C0FFC0>
\r
19264 <TD width=10% BGCOLOR=#C0FFC0>
\r
19267 <TD width=15% BGCOLOR=#C0FFC0>
\r
19268 <B>Shifted Value</B>
\r
19270 <TD width=35% BGCOLOR=#C0FFC0>
\r
19271 <B>Description</B>
\r
19274 <TR valign="top">
\r
19275 <TD width=15% BGCOLOR=#FBF5EF>
\r
19276 <B>PSU_IOU_SLCR_MIO_PIN_21_L0_SEL</B>
\r
19278 <TD width=15% BGCOLOR=#FBF5EF>
\r
19281 <TD width=10% BGCOLOR=#FBF5EF>
\r
19284 <TD width=10% BGCOLOR=#FBF5EF>
\r
19287 <TD width=15% BGCOLOR=#FBF5EF>
\r
19290 <TD width=35% BGCOLOR=#FBF5EF>
\r
19291 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19294 <TR valign="top">
\r
19295 <TD width=15% BGCOLOR=#FBF5EF>
\r
19296 <B>PSU_IOU_SLCR_MIO_PIN_21_L1_SEL</B>
\r
19298 <TD width=15% BGCOLOR=#FBF5EF>
\r
19301 <TD width=10% BGCOLOR=#FBF5EF>
\r
19304 <TD width=10% BGCOLOR=#FBF5EF>
\r
19307 <TD width=15% BGCOLOR=#FBF5EF>
\r
19310 <TD width=35% BGCOLOR=#FBF5EF>
\r
19311 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)</B>
\r
19314 <TR valign="top">
\r
19315 <TD width=15% BGCOLOR=#FBF5EF>
\r
19316 <B>PSU_IOU_SLCR_MIO_PIN_21_L2_SEL</B>
\r
19318 <TD width=15% BGCOLOR=#FBF5EF>
\r
19321 <TD width=10% BGCOLOR=#FBF5EF>
\r
19324 <TD width=10% BGCOLOR=#FBF5EF>
\r
19327 <TD width=15% BGCOLOR=#FBF5EF>
\r
19330 <TD width=35% BGCOLOR=#FBF5EF>
\r
19331 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19334 <TR valign="top">
\r
19335 <TD width=15% BGCOLOR=#FBF5EF>
\r
19336 <B>PSU_IOU_SLCR_MIO_PIN_21_L3_SEL</B>
\r
19338 <TD width=15% BGCOLOR=#FBF5EF>
\r
19341 <TD width=10% BGCOLOR=#FBF5EF>
\r
19344 <TD width=10% BGCOLOR=#FBF5EF>
\r
19347 <TD width=15% BGCOLOR=#FBF5EF>
\r
19350 <TD width=35% BGCOLOR=#FBF5EF>
\r
19351 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B>
\r
19354 <TR valign="top">
\r
19355 <TD width=15% BGCOLOR=#C0C0C0>
\r
19356 <B>PSU_IOU_SLCR_MIO_PIN_21@0XFF180054</B>
\r
19358 <TD width=15% BGCOLOR=#C0C0C0>
\r
19361 <TD width=10% BGCOLOR=#C0C0C0>
\r
19364 <TD width=10% BGCOLOR=#C0C0C0>
\r
19367 <TD width=15% BGCOLOR=#C0C0C0>
\r
19370 <TD width=35% BGCOLOR=#C0C0C0>
\r
19371 <B>Configures MIO Pin 21 peripheral interface mapping</B>
\r
19376 <H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
\r
19377 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19378 <TR valign="top">
\r
19379 <TD width=15% BGCOLOR=#FFFF00>
\r
19380 <B>Register Name</B>
\r
19382 <TD width=15% BGCOLOR=#FFFF00>
\r
19385 <TD width=10% BGCOLOR=#FFFF00>
\r
19388 <TD width=10% BGCOLOR=#FFFF00>
\r
19391 <TD width=15% BGCOLOR=#FFFF00>
\r
19392 <B>Reset Value</B>
\r
19394 <TD width=35% BGCOLOR=#FFFF00>
\r
19395 <B>Description</B>
\r
19398 <TR valign="top">
\r
19399 <TD width=15% BGCOLOR=#FBF5EF>
\r
19400 <B>MIO_PIN_22</B>
\r
19402 <TD width=15% BGCOLOR=#FBF5EF>
\r
19403 <B>0XFF180058</B>
\r
19405 <TD width=10% BGCOLOR=#FBF5EF>
\r
19408 <TD width=10% BGCOLOR=#FBF5EF>
\r
19411 <TD width=15% BGCOLOR=#FBF5EF>
\r
19412 <B>0x00000000</B>
\r
19414 <TD width=35% BGCOLOR=#FBF5EF>
\r
19420 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19421 <TR valign="top">
\r
19422 <TD width=15% BGCOLOR=#C0FFC0>
\r
19423 <B>Field Name</B>
\r
19425 <TD width=15% BGCOLOR=#C0FFC0>
\r
19428 <TD width=10% BGCOLOR=#C0FFC0>
\r
19431 <TD width=10% BGCOLOR=#C0FFC0>
\r
19434 <TD width=15% BGCOLOR=#C0FFC0>
\r
19435 <B>Shifted Value</B>
\r
19437 <TD width=35% BGCOLOR=#C0FFC0>
\r
19438 <B>Description</B>
\r
19441 <TR valign="top">
\r
19442 <TD width=15% BGCOLOR=#FBF5EF>
\r
19443 <B>PSU_IOU_SLCR_MIO_PIN_22_L0_SEL</B>
\r
19445 <TD width=15% BGCOLOR=#FBF5EF>
\r
19448 <TD width=10% BGCOLOR=#FBF5EF>
\r
19451 <TD width=10% BGCOLOR=#FBF5EF>
\r
19454 <TD width=15% BGCOLOR=#FBF5EF>
\r
19457 <TD width=35% BGCOLOR=#FBF5EF>
\r
19458 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19461 <TR valign="top">
\r
19462 <TD width=15% BGCOLOR=#FBF5EF>
\r
19463 <B>PSU_IOU_SLCR_MIO_PIN_22_L1_SEL</B>
\r
19465 <TD width=15% BGCOLOR=#FBF5EF>
\r
19468 <TD width=10% BGCOLOR=#FBF5EF>
\r
19471 <TD width=10% BGCOLOR=#FBF5EF>
\r
19474 <TD width=15% BGCOLOR=#FBF5EF>
\r
19477 <TD width=35% BGCOLOR=#FBF5EF>
\r
19478 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)</B>
\r
19481 <TR valign="top">
\r
19482 <TD width=15% BGCOLOR=#FBF5EF>
\r
19483 <B>PSU_IOU_SLCR_MIO_PIN_22_L2_SEL</B>
\r
19485 <TD width=15% BGCOLOR=#FBF5EF>
\r
19488 <TD width=10% BGCOLOR=#FBF5EF>
\r
19491 <TD width=10% BGCOLOR=#FBF5EF>
\r
19494 <TD width=15% BGCOLOR=#FBF5EF>
\r
19497 <TD width=35% BGCOLOR=#FBF5EF>
\r
19498 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19501 <TR valign="top">
\r
19502 <TD width=15% BGCOLOR=#FBF5EF>
\r
19503 <B>PSU_IOU_SLCR_MIO_PIN_22_L3_SEL</B>
\r
19505 <TD width=15% BGCOLOR=#FBF5EF>
\r
19508 <TD width=10% BGCOLOR=#FBF5EF>
\r
19511 <TD width=10% BGCOLOR=#FBF5EF>
\r
19514 <TD width=15% BGCOLOR=#FBF5EF>
\r
19517 <TD width=35% BGCOLOR=#FBF5EF>
\r
19518 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
19521 <TR valign="top">
\r
19522 <TD width=15% BGCOLOR=#C0C0C0>
\r
19523 <B>PSU_IOU_SLCR_MIO_PIN_22@0XFF180058</B>
\r
19525 <TD width=15% BGCOLOR=#C0C0C0>
\r
19528 <TD width=10% BGCOLOR=#C0C0C0>
\r
19531 <TD width=10% BGCOLOR=#C0C0C0>
\r
19534 <TD width=15% BGCOLOR=#C0C0C0>
\r
19537 <TD width=35% BGCOLOR=#C0C0C0>
\r
19538 <B>Configures MIO Pin 22 peripheral interface mapping</B>
\r
19543 <H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
\r
19544 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19545 <TR valign="top">
\r
19546 <TD width=15% BGCOLOR=#FFFF00>
\r
19547 <B>Register Name</B>
\r
19549 <TD width=15% BGCOLOR=#FFFF00>
\r
19552 <TD width=10% BGCOLOR=#FFFF00>
\r
19555 <TD width=10% BGCOLOR=#FFFF00>
\r
19558 <TD width=15% BGCOLOR=#FFFF00>
\r
19559 <B>Reset Value</B>
\r
19561 <TD width=35% BGCOLOR=#FFFF00>
\r
19562 <B>Description</B>
\r
19565 <TR valign="top">
\r
19566 <TD width=15% BGCOLOR=#FBF5EF>
\r
19567 <B>MIO_PIN_23</B>
\r
19569 <TD width=15% BGCOLOR=#FBF5EF>
\r
19570 <B>0XFF18005C</B>
\r
19572 <TD width=10% BGCOLOR=#FBF5EF>
\r
19575 <TD width=10% BGCOLOR=#FBF5EF>
\r
19578 <TD width=15% BGCOLOR=#FBF5EF>
\r
19579 <B>0x00000000</B>
\r
19581 <TD width=35% BGCOLOR=#FBF5EF>
\r
19587 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19588 <TR valign="top">
\r
19589 <TD width=15% BGCOLOR=#C0FFC0>
\r
19590 <B>Field Name</B>
\r
19592 <TD width=15% BGCOLOR=#C0FFC0>
\r
19595 <TD width=10% BGCOLOR=#C0FFC0>
\r
19598 <TD width=10% BGCOLOR=#C0FFC0>
\r
19601 <TD width=15% BGCOLOR=#C0FFC0>
\r
19602 <B>Shifted Value</B>
\r
19604 <TD width=35% BGCOLOR=#C0FFC0>
\r
19605 <B>Description</B>
\r
19608 <TR valign="top">
\r
19609 <TD width=15% BGCOLOR=#FBF5EF>
\r
19610 <B>PSU_IOU_SLCR_MIO_PIN_23_L0_SEL</B>
\r
19612 <TD width=15% BGCOLOR=#FBF5EF>
\r
19615 <TD width=10% BGCOLOR=#FBF5EF>
\r
19618 <TD width=10% BGCOLOR=#FBF5EF>
\r
19621 <TD width=15% BGCOLOR=#FBF5EF>
\r
19624 <TD width=35% BGCOLOR=#FBF5EF>
\r
19625 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19628 <TR valign="top">
\r
19629 <TD width=15% BGCOLOR=#FBF5EF>
\r
19630 <B>PSU_IOU_SLCR_MIO_PIN_23_L1_SEL</B>
\r
19632 <TD width=15% BGCOLOR=#FBF5EF>
\r
19635 <TD width=10% BGCOLOR=#FBF5EF>
\r
19638 <TD width=10% BGCOLOR=#FBF5EF>
\r
19641 <TD width=15% BGCOLOR=#FBF5EF>
\r
19644 <TD width=35% BGCOLOR=#FBF5EF>
\r
19645 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)</B>
\r
19648 <TR valign="top">
\r
19649 <TD width=15% BGCOLOR=#FBF5EF>
\r
19650 <B>PSU_IOU_SLCR_MIO_PIN_23_L2_SEL</B>
\r
19652 <TD width=15% BGCOLOR=#FBF5EF>
\r
19655 <TD width=10% BGCOLOR=#FBF5EF>
\r
19658 <TD width=10% BGCOLOR=#FBF5EF>
\r
19661 <TD width=15% BGCOLOR=#FBF5EF>
\r
19664 <TD width=35% BGCOLOR=#FBF5EF>
\r
19665 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19668 <TR valign="top">
\r
19669 <TD width=15% BGCOLOR=#FBF5EF>
\r
19670 <B>PSU_IOU_SLCR_MIO_PIN_23_L3_SEL</B>
\r
19672 <TD width=15% BGCOLOR=#FBF5EF>
\r
19675 <TD width=10% BGCOLOR=#FBF5EF>
\r
19678 <TD width=10% BGCOLOR=#FBF5EF>
\r
19681 <TD width=15% BGCOLOR=#FBF5EF>
\r
19684 <TD width=35% BGCOLOR=#FBF5EF>
\r
19685 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
19688 <TR valign="top">
\r
19689 <TD width=15% BGCOLOR=#C0C0C0>
\r
19690 <B>PSU_IOU_SLCR_MIO_PIN_23@0XFF18005C</B>
\r
19692 <TD width=15% BGCOLOR=#C0C0C0>
\r
19695 <TD width=10% BGCOLOR=#C0C0C0>
\r
19698 <TD width=10% BGCOLOR=#C0C0C0>
\r
19701 <TD width=15% BGCOLOR=#C0C0C0>
\r
19704 <TD width=35% BGCOLOR=#C0C0C0>
\r
19705 <B>Configures MIO Pin 23 peripheral interface mapping</B>
\r
19710 <H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
\r
19711 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19712 <TR valign="top">
\r
19713 <TD width=15% BGCOLOR=#FFFF00>
\r
19714 <B>Register Name</B>
\r
19716 <TD width=15% BGCOLOR=#FFFF00>
\r
19719 <TD width=10% BGCOLOR=#FFFF00>
\r
19722 <TD width=10% BGCOLOR=#FFFF00>
\r
19725 <TD width=15% BGCOLOR=#FFFF00>
\r
19726 <B>Reset Value</B>
\r
19728 <TD width=35% BGCOLOR=#FFFF00>
\r
19729 <B>Description</B>
\r
19732 <TR valign="top">
\r
19733 <TD width=15% BGCOLOR=#FBF5EF>
\r
19734 <B>MIO_PIN_24</B>
\r
19736 <TD width=15% BGCOLOR=#FBF5EF>
\r
19737 <B>0XFF180060</B>
\r
19739 <TD width=10% BGCOLOR=#FBF5EF>
\r
19742 <TD width=10% BGCOLOR=#FBF5EF>
\r
19745 <TD width=15% BGCOLOR=#FBF5EF>
\r
19746 <B>0x00000000</B>
\r
19748 <TD width=35% BGCOLOR=#FBF5EF>
\r
19754 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19755 <TR valign="top">
\r
19756 <TD width=15% BGCOLOR=#C0FFC0>
\r
19757 <B>Field Name</B>
\r
19759 <TD width=15% BGCOLOR=#C0FFC0>
\r
19762 <TD width=10% BGCOLOR=#C0FFC0>
\r
19765 <TD width=10% BGCOLOR=#C0FFC0>
\r
19768 <TD width=15% BGCOLOR=#C0FFC0>
\r
19769 <B>Shifted Value</B>
\r
19771 <TD width=35% BGCOLOR=#C0FFC0>
\r
19772 <B>Description</B>
\r
19775 <TR valign="top">
\r
19776 <TD width=15% BGCOLOR=#FBF5EF>
\r
19777 <B>PSU_IOU_SLCR_MIO_PIN_24_L0_SEL</B>
\r
19779 <TD width=15% BGCOLOR=#FBF5EF>
\r
19782 <TD width=10% BGCOLOR=#FBF5EF>
\r
19785 <TD width=10% BGCOLOR=#FBF5EF>
\r
19788 <TD width=15% BGCOLOR=#FBF5EF>
\r
19791 <TD width=35% BGCOLOR=#FBF5EF>
\r
19792 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19795 <TR valign="top">
\r
19796 <TD width=15% BGCOLOR=#FBF5EF>
\r
19797 <B>PSU_IOU_SLCR_MIO_PIN_24_L1_SEL</B>
\r
19799 <TD width=15% BGCOLOR=#FBF5EF>
\r
19802 <TD width=10% BGCOLOR=#FBF5EF>
\r
19805 <TD width=10% BGCOLOR=#FBF5EF>
\r
19808 <TD width=15% BGCOLOR=#FBF5EF>
\r
19811 <TD width=35% BGCOLOR=#FBF5EF>
\r
19812 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)</B>
\r
19815 <TR valign="top">
\r
19816 <TD width=15% BGCOLOR=#FBF5EF>
\r
19817 <B>PSU_IOU_SLCR_MIO_PIN_24_L2_SEL</B>
\r
19819 <TD width=15% BGCOLOR=#FBF5EF>
\r
19822 <TD width=10% BGCOLOR=#FBF5EF>
\r
19825 <TD width=10% BGCOLOR=#FBF5EF>
\r
19828 <TD width=15% BGCOLOR=#FBF5EF>
\r
19831 <TD width=35% BGCOLOR=#FBF5EF>
\r
19832 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
19835 <TR valign="top">
\r
19836 <TD width=15% BGCOLOR=#FBF5EF>
\r
19837 <B>PSU_IOU_SLCR_MIO_PIN_24_L3_SEL</B>
\r
19839 <TD width=15% BGCOLOR=#FBF5EF>
\r
19842 <TD width=10% BGCOLOR=#FBF5EF>
\r
19845 <TD width=10% BGCOLOR=#FBF5EF>
\r
19848 <TD width=15% BGCOLOR=#FBF5EF>
\r
19851 <TD width=35% BGCOLOR=#FBF5EF>
\r
19852 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B>
\r
19855 <TR valign="top">
\r
19856 <TD width=15% BGCOLOR=#C0C0C0>
\r
19857 <B>PSU_IOU_SLCR_MIO_PIN_24@0XFF180060</B>
\r
19859 <TD width=15% BGCOLOR=#C0C0C0>
\r
19862 <TD width=10% BGCOLOR=#C0C0C0>
\r
19865 <TD width=10% BGCOLOR=#C0C0C0>
\r
19868 <TD width=15% BGCOLOR=#C0C0C0>
\r
19871 <TD width=35% BGCOLOR=#C0C0C0>
\r
19872 <B>Configures MIO Pin 24 peripheral interface mapping</B>
\r
19877 <H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
\r
19878 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19879 <TR valign="top">
\r
19880 <TD width=15% BGCOLOR=#FFFF00>
\r
19881 <B>Register Name</B>
\r
19883 <TD width=15% BGCOLOR=#FFFF00>
\r
19886 <TD width=10% BGCOLOR=#FFFF00>
\r
19889 <TD width=10% BGCOLOR=#FFFF00>
\r
19892 <TD width=15% BGCOLOR=#FFFF00>
\r
19893 <B>Reset Value</B>
\r
19895 <TD width=35% BGCOLOR=#FFFF00>
\r
19896 <B>Description</B>
\r
19899 <TR valign="top">
\r
19900 <TD width=15% BGCOLOR=#FBF5EF>
\r
19901 <B>MIO_PIN_25</B>
\r
19903 <TD width=15% BGCOLOR=#FBF5EF>
\r
19904 <B>0XFF180064</B>
\r
19906 <TD width=10% BGCOLOR=#FBF5EF>
\r
19909 <TD width=10% BGCOLOR=#FBF5EF>
\r
19912 <TD width=15% BGCOLOR=#FBF5EF>
\r
19913 <B>0x00000000</B>
\r
19915 <TD width=35% BGCOLOR=#FBF5EF>
\r
19921 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
19922 <TR valign="top">
\r
19923 <TD width=15% BGCOLOR=#C0FFC0>
\r
19924 <B>Field Name</B>
\r
19926 <TD width=15% BGCOLOR=#C0FFC0>
\r
19929 <TD width=10% BGCOLOR=#C0FFC0>
\r
19932 <TD width=10% BGCOLOR=#C0FFC0>
\r
19935 <TD width=15% BGCOLOR=#C0FFC0>
\r
19936 <B>Shifted Value</B>
\r
19938 <TD width=35% BGCOLOR=#C0FFC0>
\r
19939 <B>Description</B>
\r
19942 <TR valign="top">
\r
19943 <TD width=15% BGCOLOR=#FBF5EF>
\r
19944 <B>PSU_IOU_SLCR_MIO_PIN_25_L0_SEL</B>
\r
19946 <TD width=15% BGCOLOR=#FBF5EF>
\r
19949 <TD width=10% BGCOLOR=#FBF5EF>
\r
19952 <TD width=10% BGCOLOR=#FBF5EF>
\r
19955 <TD width=15% BGCOLOR=#FBF5EF>
\r
19958 <TD width=35% BGCOLOR=#FBF5EF>
\r
19959 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
19962 <TR valign="top">
\r
19963 <TD width=15% BGCOLOR=#FBF5EF>
\r
19964 <B>PSU_IOU_SLCR_MIO_PIN_25_L1_SEL</B>
\r
19966 <TD width=15% BGCOLOR=#FBF5EF>
\r
19969 <TD width=10% BGCOLOR=#FBF5EF>
\r
19972 <TD width=10% BGCOLOR=#FBF5EF>
\r
19975 <TD width=15% BGCOLOR=#FBF5EF>
\r
19978 <TD width=35% BGCOLOR=#FBF5EF>
\r
19979 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)</B>
\r
19982 <TR valign="top">
\r
19983 <TD width=15% BGCOLOR=#FBF5EF>
\r
19984 <B>PSU_IOU_SLCR_MIO_PIN_25_L2_SEL</B>
\r
19986 <TD width=15% BGCOLOR=#FBF5EF>
\r
19989 <TD width=10% BGCOLOR=#FBF5EF>
\r
19992 <TD width=10% BGCOLOR=#FBF5EF>
\r
19995 <TD width=15% BGCOLOR=#FBF5EF>
\r
19998 <TD width=35% BGCOLOR=#FBF5EF>
\r
19999 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
20002 <TR valign="top">
\r
20003 <TD width=15% BGCOLOR=#FBF5EF>
\r
20004 <B>PSU_IOU_SLCR_MIO_PIN_25_L3_SEL</B>
\r
20006 <TD width=15% BGCOLOR=#FBF5EF>
\r
20009 <TD width=10% BGCOLOR=#FBF5EF>
\r
20012 <TD width=10% BGCOLOR=#FBF5EF>
\r
20015 <TD width=15% BGCOLOR=#FBF5EF>
\r
20018 <TD width=35% BGCOLOR=#FBF5EF>
\r
20019 <B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B>
\r
20022 <TR valign="top">
\r
20023 <TD width=15% BGCOLOR=#C0C0C0>
\r
20024 <B>PSU_IOU_SLCR_MIO_PIN_25@0XFF180064</B>
\r
20026 <TD width=15% BGCOLOR=#C0C0C0>
\r
20029 <TD width=10% BGCOLOR=#C0C0C0>
\r
20032 <TD width=10% BGCOLOR=#C0C0C0>
\r
20035 <TD width=15% BGCOLOR=#C0C0C0>
\r
20038 <TD width=35% BGCOLOR=#C0C0C0>
\r
20039 <B>Configures MIO Pin 25 peripheral interface mapping</B>
\r
20044 <H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
\r
20045 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20046 <TR valign="top">
\r
20047 <TD width=15% BGCOLOR=#FFFF00>
\r
20048 <B>Register Name</B>
\r
20050 <TD width=15% BGCOLOR=#FFFF00>
\r
20053 <TD width=10% BGCOLOR=#FFFF00>
\r
20056 <TD width=10% BGCOLOR=#FFFF00>
\r
20059 <TD width=15% BGCOLOR=#FFFF00>
\r
20060 <B>Reset Value</B>
\r
20062 <TD width=35% BGCOLOR=#FFFF00>
\r
20063 <B>Description</B>
\r
20066 <TR valign="top">
\r
20067 <TD width=15% BGCOLOR=#FBF5EF>
\r
20068 <B>MIO_PIN_26</B>
\r
20070 <TD width=15% BGCOLOR=#FBF5EF>
\r
20071 <B>0XFF180068</B>
\r
20073 <TD width=10% BGCOLOR=#FBF5EF>
\r
20076 <TD width=10% BGCOLOR=#FBF5EF>
\r
20079 <TD width=15% BGCOLOR=#FBF5EF>
\r
20080 <B>0x00000000</B>
\r
20082 <TD width=35% BGCOLOR=#FBF5EF>
\r
20088 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20089 <TR valign="top">
\r
20090 <TD width=15% BGCOLOR=#C0FFC0>
\r
20091 <B>Field Name</B>
\r
20093 <TD width=15% BGCOLOR=#C0FFC0>
\r
20096 <TD width=10% BGCOLOR=#C0FFC0>
\r
20099 <TD width=10% BGCOLOR=#C0FFC0>
\r
20102 <TD width=15% BGCOLOR=#C0FFC0>
\r
20103 <B>Shifted Value</B>
\r
20105 <TD width=35% BGCOLOR=#C0FFC0>
\r
20106 <B>Description</B>
\r
20109 <TR valign="top">
\r
20110 <TD width=15% BGCOLOR=#FBF5EF>
\r
20111 <B>PSU_IOU_SLCR_MIO_PIN_26_L0_SEL</B>
\r
20113 <TD width=15% BGCOLOR=#FBF5EF>
\r
20116 <TD width=10% BGCOLOR=#FBF5EF>
\r
20119 <TD width=10% BGCOLOR=#FBF5EF>
\r
20122 <TD width=15% BGCOLOR=#FBF5EF>
\r
20125 <TD width=35% BGCOLOR=#FBF5EF>
\r
20126 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</B>
\r
20129 <TR valign="top">
\r
20130 <TD width=15% BGCOLOR=#FBF5EF>
\r
20131 <B>PSU_IOU_SLCR_MIO_PIN_26_L1_SEL</B>
\r
20133 <TD width=15% BGCOLOR=#FBF5EF>
\r
20136 <TD width=10% BGCOLOR=#FBF5EF>
\r
20139 <TD width=10% BGCOLOR=#FBF5EF>
\r
20142 <TD width=15% BGCOLOR=#FBF5EF>
\r
20145 <TD width=35% BGCOLOR=#FBF5EF>
\r
20146 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)</B>
\r
20149 <TR valign="top">
\r
20150 <TD width=15% BGCOLOR=#FBF5EF>
\r
20151 <B>PSU_IOU_SLCR_MIO_PIN_26_L2_SEL</B>
\r
20153 <TD width=15% BGCOLOR=#FBF5EF>
\r
20156 <TD width=10% BGCOLOR=#FBF5EF>
\r
20159 <TD width=10% BGCOLOR=#FBF5EF>
\r
20162 <TD width=15% BGCOLOR=#FBF5EF>
\r
20165 <TD width=35% BGCOLOR=#FBF5EF>
\r
20166 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
20169 <TR valign="top">
\r
20170 <TD width=15% BGCOLOR=#FBF5EF>
\r
20171 <B>PSU_IOU_SLCR_MIO_PIN_26_L3_SEL</B>
\r
20173 <TD width=15% BGCOLOR=#FBF5EF>
\r
20176 <TD width=10% BGCOLOR=#FBF5EF>
\r
20179 <TD width=10% BGCOLOR=#FBF5EF>
\r
20182 <TD width=15% BGCOLOR=#FBF5EF>
\r
20185 <TD width=35% BGCOLOR=#FBF5EF>
\r
20186 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B>
\r
20189 <TR valign="top">
\r
20190 <TD width=15% BGCOLOR=#C0C0C0>
\r
20191 <B>PSU_IOU_SLCR_MIO_PIN_26@0XFF180068</B>
\r
20193 <TD width=15% BGCOLOR=#C0C0C0>
\r
20196 <TD width=10% BGCOLOR=#C0C0C0>
\r
20199 <TD width=10% BGCOLOR=#C0C0C0>
\r
20202 <TD width=15% BGCOLOR=#C0C0C0>
\r
20205 <TD width=35% BGCOLOR=#C0C0C0>
\r
20206 <B>Configures MIO Pin 26 peripheral interface mapping</B>
\r
20211 <H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
\r
20212 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20213 <TR valign="top">
\r
20214 <TD width=15% BGCOLOR=#FFFF00>
\r
20215 <B>Register Name</B>
\r
20217 <TD width=15% BGCOLOR=#FFFF00>
\r
20220 <TD width=10% BGCOLOR=#FFFF00>
\r
20223 <TD width=10% BGCOLOR=#FFFF00>
\r
20226 <TD width=15% BGCOLOR=#FFFF00>
\r
20227 <B>Reset Value</B>
\r
20229 <TD width=35% BGCOLOR=#FFFF00>
\r
20230 <B>Description</B>
\r
20233 <TR valign="top">
\r
20234 <TD width=15% BGCOLOR=#FBF5EF>
\r
20235 <B>MIO_PIN_27</B>
\r
20237 <TD width=15% BGCOLOR=#FBF5EF>
\r
20238 <B>0XFF18006C</B>
\r
20240 <TD width=10% BGCOLOR=#FBF5EF>
\r
20243 <TD width=10% BGCOLOR=#FBF5EF>
\r
20246 <TD width=15% BGCOLOR=#FBF5EF>
\r
20247 <B>0x00000000</B>
\r
20249 <TD width=35% BGCOLOR=#FBF5EF>
\r
20255 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20256 <TR valign="top">
\r
20257 <TD width=15% BGCOLOR=#C0FFC0>
\r
20258 <B>Field Name</B>
\r
20260 <TD width=15% BGCOLOR=#C0FFC0>
\r
20263 <TD width=10% BGCOLOR=#C0FFC0>
\r
20266 <TD width=10% BGCOLOR=#C0FFC0>
\r
20269 <TD width=15% BGCOLOR=#C0FFC0>
\r
20270 <B>Shifted Value</B>
\r
20272 <TD width=35% BGCOLOR=#C0FFC0>
\r
20273 <B>Description</B>
\r
20276 <TR valign="top">
\r
20277 <TD width=15% BGCOLOR=#FBF5EF>
\r
20278 <B>PSU_IOU_SLCR_MIO_PIN_27_L0_SEL</B>
\r
20280 <TD width=15% BGCOLOR=#FBF5EF>
\r
20283 <TD width=10% BGCOLOR=#FBF5EF>
\r
20286 <TD width=10% BGCOLOR=#FBF5EF>
\r
20289 <TD width=15% BGCOLOR=#FBF5EF>
\r
20292 <TD width=35% BGCOLOR=#FBF5EF>
\r
20293 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</B>
\r
20296 <TR valign="top">
\r
20297 <TD width=15% BGCOLOR=#FBF5EF>
\r
20298 <B>PSU_IOU_SLCR_MIO_PIN_27_L1_SEL</B>
\r
20300 <TD width=15% BGCOLOR=#FBF5EF>
\r
20303 <TD width=10% BGCOLOR=#FBF5EF>
\r
20306 <TD width=10% BGCOLOR=#FBF5EF>
\r
20309 <TD width=15% BGCOLOR=#FBF5EF>
\r
20312 <TD width=35% BGCOLOR=#FBF5EF>
\r
20313 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)</B>
\r
20316 <TR valign="top">
\r
20317 <TD width=15% BGCOLOR=#FBF5EF>
\r
20318 <B>PSU_IOU_SLCR_MIO_PIN_27_L2_SEL</B>
\r
20320 <TD width=15% BGCOLOR=#FBF5EF>
\r
20323 <TD width=10% BGCOLOR=#FBF5EF>
\r
20326 <TD width=10% BGCOLOR=#FBF5EF>
\r
20329 <TD width=15% BGCOLOR=#FBF5EF>
\r
20332 <TD width=35% BGCOLOR=#FBF5EF>
\r
20333 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B>
\r
20336 <TR valign="top">
\r
20337 <TD width=15% BGCOLOR=#FBF5EF>
\r
20338 <B>PSU_IOU_SLCR_MIO_PIN_27_L3_SEL</B>
\r
20340 <TD width=15% BGCOLOR=#FBF5EF>
\r
20343 <TD width=10% BGCOLOR=#FBF5EF>
\r
20346 <TD width=10% BGCOLOR=#FBF5EF>
\r
20349 <TD width=15% BGCOLOR=#FBF5EF>
\r
20352 <TD width=35% BGCOLOR=#FBF5EF>
\r
20353 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B>
\r
20356 <TR valign="top">
\r
20357 <TD width=15% BGCOLOR=#C0C0C0>
\r
20358 <B>PSU_IOU_SLCR_MIO_PIN_27@0XFF18006C</B>
\r
20360 <TD width=15% BGCOLOR=#C0C0C0>
\r
20363 <TD width=10% BGCOLOR=#C0C0C0>
\r
20366 <TD width=10% BGCOLOR=#C0C0C0>
\r
20369 <TD width=15% BGCOLOR=#C0C0C0>
\r
20372 <TD width=35% BGCOLOR=#C0C0C0>
\r
20373 <B>Configures MIO Pin 27 peripheral interface mapping</B>
\r
20378 <H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
\r
20379 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20380 <TR valign="top">
\r
20381 <TD width=15% BGCOLOR=#FFFF00>
\r
20382 <B>Register Name</B>
\r
20384 <TD width=15% BGCOLOR=#FFFF00>
\r
20387 <TD width=10% BGCOLOR=#FFFF00>
\r
20390 <TD width=10% BGCOLOR=#FFFF00>
\r
20393 <TD width=15% BGCOLOR=#FFFF00>
\r
20394 <B>Reset Value</B>
\r
20396 <TD width=35% BGCOLOR=#FFFF00>
\r
20397 <B>Description</B>
\r
20400 <TR valign="top">
\r
20401 <TD width=15% BGCOLOR=#FBF5EF>
\r
20402 <B>MIO_PIN_28</B>
\r
20404 <TD width=15% BGCOLOR=#FBF5EF>
\r
20405 <B>0XFF180070</B>
\r
20407 <TD width=10% BGCOLOR=#FBF5EF>
\r
20410 <TD width=10% BGCOLOR=#FBF5EF>
\r
20413 <TD width=15% BGCOLOR=#FBF5EF>
\r
20414 <B>0x00000000</B>
\r
20416 <TD width=35% BGCOLOR=#FBF5EF>
\r
20422 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20423 <TR valign="top">
\r
20424 <TD width=15% BGCOLOR=#C0FFC0>
\r
20425 <B>Field Name</B>
\r
20427 <TD width=15% BGCOLOR=#C0FFC0>
\r
20430 <TD width=10% BGCOLOR=#C0FFC0>
\r
20433 <TD width=10% BGCOLOR=#C0FFC0>
\r
20436 <TD width=15% BGCOLOR=#C0FFC0>
\r
20437 <B>Shifted Value</B>
\r
20439 <TD width=35% BGCOLOR=#C0FFC0>
\r
20440 <B>Description</B>
\r
20443 <TR valign="top">
\r
20444 <TD width=15% BGCOLOR=#FBF5EF>
\r
20445 <B>PSU_IOU_SLCR_MIO_PIN_28_L0_SEL</B>
\r
20447 <TD width=15% BGCOLOR=#FBF5EF>
\r
20450 <TD width=10% BGCOLOR=#FBF5EF>
\r
20453 <TD width=10% BGCOLOR=#FBF5EF>
\r
20456 <TD width=15% BGCOLOR=#FBF5EF>
\r
20459 <TD width=35% BGCOLOR=#FBF5EF>
\r
20460 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</B>
\r
20463 <TR valign="top">
\r
20464 <TD width=15% BGCOLOR=#FBF5EF>
\r
20465 <B>PSU_IOU_SLCR_MIO_PIN_28_L1_SEL</B>
\r
20467 <TD width=15% BGCOLOR=#FBF5EF>
\r
20470 <TD width=10% BGCOLOR=#FBF5EF>
\r
20473 <TD width=10% BGCOLOR=#FBF5EF>
\r
20476 <TD width=15% BGCOLOR=#FBF5EF>
\r
20479 <TD width=35% BGCOLOR=#FBF5EF>
\r
20480 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)</B>
\r
20483 <TR valign="top">
\r
20484 <TD width=15% BGCOLOR=#FBF5EF>
\r
20485 <B>PSU_IOU_SLCR_MIO_PIN_28_L2_SEL</B>
\r
20487 <TD width=15% BGCOLOR=#FBF5EF>
\r
20490 <TD width=10% BGCOLOR=#FBF5EF>
\r
20493 <TD width=10% BGCOLOR=#FBF5EF>
\r
20496 <TD width=15% BGCOLOR=#FBF5EF>
\r
20499 <TD width=35% BGCOLOR=#FBF5EF>
\r
20500 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B>
\r
20503 <TR valign="top">
\r
20504 <TD width=15% BGCOLOR=#FBF5EF>
\r
20505 <B>PSU_IOU_SLCR_MIO_PIN_28_L3_SEL</B>
\r
20507 <TD width=15% BGCOLOR=#FBF5EF>
\r
20510 <TD width=10% BGCOLOR=#FBF5EF>
\r
20513 <TD width=10% BGCOLOR=#FBF5EF>
\r
20516 <TD width=15% BGCOLOR=#FBF5EF>
\r
20519 <TD width=35% BGCOLOR=#FBF5EF>
\r
20520 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B>
\r
20523 <TR valign="top">
\r
20524 <TD width=15% BGCOLOR=#C0C0C0>
\r
20525 <B>PSU_IOU_SLCR_MIO_PIN_28@0XFF180070</B>
\r
20527 <TD width=15% BGCOLOR=#C0C0C0>
\r
20530 <TD width=10% BGCOLOR=#C0C0C0>
\r
20533 <TD width=10% BGCOLOR=#C0C0C0>
\r
20536 <TD width=15% BGCOLOR=#C0C0C0>
\r
20539 <TD width=35% BGCOLOR=#C0C0C0>
\r
20540 <B>Configures MIO Pin 28 peripheral interface mapping</B>
\r
20545 <H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
\r
20546 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20547 <TR valign="top">
\r
20548 <TD width=15% BGCOLOR=#FFFF00>
\r
20549 <B>Register Name</B>
\r
20551 <TD width=15% BGCOLOR=#FFFF00>
\r
20554 <TD width=10% BGCOLOR=#FFFF00>
\r
20557 <TD width=10% BGCOLOR=#FFFF00>
\r
20560 <TD width=15% BGCOLOR=#FFFF00>
\r
20561 <B>Reset Value</B>
\r
20563 <TD width=35% BGCOLOR=#FFFF00>
\r
20564 <B>Description</B>
\r
20567 <TR valign="top">
\r
20568 <TD width=15% BGCOLOR=#FBF5EF>
\r
20569 <B>MIO_PIN_29</B>
\r
20571 <TD width=15% BGCOLOR=#FBF5EF>
\r
20572 <B>0XFF180074</B>
\r
20574 <TD width=10% BGCOLOR=#FBF5EF>
\r
20577 <TD width=10% BGCOLOR=#FBF5EF>
\r
20580 <TD width=15% BGCOLOR=#FBF5EF>
\r
20581 <B>0x00000000</B>
\r
20583 <TD width=35% BGCOLOR=#FBF5EF>
\r
20589 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20590 <TR valign="top">
\r
20591 <TD width=15% BGCOLOR=#C0FFC0>
\r
20592 <B>Field Name</B>
\r
20594 <TD width=15% BGCOLOR=#C0FFC0>
\r
20597 <TD width=10% BGCOLOR=#C0FFC0>
\r
20600 <TD width=10% BGCOLOR=#C0FFC0>
\r
20603 <TD width=15% BGCOLOR=#C0FFC0>
\r
20604 <B>Shifted Value</B>
\r
20606 <TD width=35% BGCOLOR=#C0FFC0>
\r
20607 <B>Description</B>
\r
20610 <TR valign="top">
\r
20611 <TD width=15% BGCOLOR=#FBF5EF>
\r
20612 <B>PSU_IOU_SLCR_MIO_PIN_29_L0_SEL</B>
\r
20614 <TD width=15% BGCOLOR=#FBF5EF>
\r
20617 <TD width=10% BGCOLOR=#FBF5EF>
\r
20620 <TD width=10% BGCOLOR=#FBF5EF>
\r
20623 <TD width=15% BGCOLOR=#FBF5EF>
\r
20626 <TD width=35% BGCOLOR=#FBF5EF>
\r
20627 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</B>
\r
20630 <TR valign="top">
\r
20631 <TD width=15% BGCOLOR=#FBF5EF>
\r
20632 <B>PSU_IOU_SLCR_MIO_PIN_29_L1_SEL</B>
\r
20634 <TD width=15% BGCOLOR=#FBF5EF>
\r
20637 <TD width=10% BGCOLOR=#FBF5EF>
\r
20640 <TD width=10% BGCOLOR=#FBF5EF>
\r
20643 <TD width=15% BGCOLOR=#FBF5EF>
\r
20646 <TD width=35% BGCOLOR=#FBF5EF>
\r
20647 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
20650 <TR valign="top">
\r
20651 <TD width=15% BGCOLOR=#FBF5EF>
\r
20652 <B>PSU_IOU_SLCR_MIO_PIN_29_L2_SEL</B>
\r
20654 <TD width=15% BGCOLOR=#FBF5EF>
\r
20657 <TD width=10% BGCOLOR=#FBF5EF>
\r
20660 <TD width=10% BGCOLOR=#FBF5EF>
\r
20663 <TD width=15% BGCOLOR=#FBF5EF>
\r
20666 <TD width=35% BGCOLOR=#FBF5EF>
\r
20667 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B>
\r
20670 <TR valign="top">
\r
20671 <TD width=15% BGCOLOR=#FBF5EF>
\r
20672 <B>PSU_IOU_SLCR_MIO_PIN_29_L3_SEL</B>
\r
20674 <TD width=15% BGCOLOR=#FBF5EF>
\r
20677 <TD width=10% BGCOLOR=#FBF5EF>
\r
20680 <TD width=10% BGCOLOR=#FBF5EF>
\r
20683 <TD width=15% BGCOLOR=#FBF5EF>
\r
20686 <TD width=35% BGCOLOR=#FBF5EF>
\r
20687 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B>
\r
20690 <TR valign="top">
\r
20691 <TD width=15% BGCOLOR=#C0C0C0>
\r
20692 <B>PSU_IOU_SLCR_MIO_PIN_29@0XFF180074</B>
\r
20694 <TD width=15% BGCOLOR=#C0C0C0>
\r
20697 <TD width=10% BGCOLOR=#C0C0C0>
\r
20700 <TD width=10% BGCOLOR=#C0C0C0>
\r
20703 <TD width=15% BGCOLOR=#C0C0C0>
\r
20706 <TD width=35% BGCOLOR=#C0C0C0>
\r
20707 <B>Configures MIO Pin 29 peripheral interface mapping</B>
\r
20712 <H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
\r
20713 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20714 <TR valign="top">
\r
20715 <TD width=15% BGCOLOR=#FFFF00>
\r
20716 <B>Register Name</B>
\r
20718 <TD width=15% BGCOLOR=#FFFF00>
\r
20721 <TD width=10% BGCOLOR=#FFFF00>
\r
20724 <TD width=10% BGCOLOR=#FFFF00>
\r
20727 <TD width=15% BGCOLOR=#FFFF00>
\r
20728 <B>Reset Value</B>
\r
20730 <TD width=35% BGCOLOR=#FFFF00>
\r
20731 <B>Description</B>
\r
20734 <TR valign="top">
\r
20735 <TD width=15% BGCOLOR=#FBF5EF>
\r
20736 <B>MIO_PIN_30</B>
\r
20738 <TD width=15% BGCOLOR=#FBF5EF>
\r
20739 <B>0XFF180078</B>
\r
20741 <TD width=10% BGCOLOR=#FBF5EF>
\r
20744 <TD width=10% BGCOLOR=#FBF5EF>
\r
20747 <TD width=15% BGCOLOR=#FBF5EF>
\r
20748 <B>0x00000000</B>
\r
20750 <TD width=35% BGCOLOR=#FBF5EF>
\r
20756 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20757 <TR valign="top">
\r
20758 <TD width=15% BGCOLOR=#C0FFC0>
\r
20759 <B>Field Name</B>
\r
20761 <TD width=15% BGCOLOR=#C0FFC0>
\r
20764 <TD width=10% BGCOLOR=#C0FFC0>
\r
20767 <TD width=10% BGCOLOR=#C0FFC0>
\r
20770 <TD width=15% BGCOLOR=#C0FFC0>
\r
20771 <B>Shifted Value</B>
\r
20773 <TD width=35% BGCOLOR=#C0FFC0>
\r
20774 <B>Description</B>
\r
20777 <TR valign="top">
\r
20778 <TD width=15% BGCOLOR=#FBF5EF>
\r
20779 <B>PSU_IOU_SLCR_MIO_PIN_30_L0_SEL</B>
\r
20781 <TD width=15% BGCOLOR=#FBF5EF>
\r
20784 <TD width=10% BGCOLOR=#FBF5EF>
\r
20787 <TD width=10% BGCOLOR=#FBF5EF>
\r
20790 <TD width=15% BGCOLOR=#FBF5EF>
\r
20793 <TD width=35% BGCOLOR=#FBF5EF>
\r
20794 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</B>
\r
20797 <TR valign="top">
\r
20798 <TD width=15% BGCOLOR=#FBF5EF>
\r
20799 <B>PSU_IOU_SLCR_MIO_PIN_30_L1_SEL</B>
\r
20801 <TD width=15% BGCOLOR=#FBF5EF>
\r
20804 <TD width=10% BGCOLOR=#FBF5EF>
\r
20807 <TD width=10% BGCOLOR=#FBF5EF>
\r
20810 <TD width=15% BGCOLOR=#FBF5EF>
\r
20813 <TD width=35% BGCOLOR=#FBF5EF>
\r
20814 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
20817 <TR valign="top">
\r
20818 <TD width=15% BGCOLOR=#FBF5EF>
\r
20819 <B>PSU_IOU_SLCR_MIO_PIN_30_L2_SEL</B>
\r
20821 <TD width=15% BGCOLOR=#FBF5EF>
\r
20824 <TD width=10% BGCOLOR=#FBF5EF>
\r
20827 <TD width=10% BGCOLOR=#FBF5EF>
\r
20830 <TD width=15% BGCOLOR=#FBF5EF>
\r
20833 <TD width=35% BGCOLOR=#FBF5EF>
\r
20834 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B>
\r
20837 <TR valign="top">
\r
20838 <TD width=15% BGCOLOR=#FBF5EF>
\r
20839 <B>PSU_IOU_SLCR_MIO_PIN_30_L3_SEL</B>
\r
20841 <TD width=15% BGCOLOR=#FBF5EF>
\r
20844 <TD width=10% BGCOLOR=#FBF5EF>
\r
20847 <TD width=10% BGCOLOR=#FBF5EF>
\r
20850 <TD width=15% BGCOLOR=#FBF5EF>
\r
20853 <TD width=35% BGCOLOR=#FBF5EF>
\r
20854 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B>
\r
20857 <TR valign="top">
\r
20858 <TD width=15% BGCOLOR=#C0C0C0>
\r
20859 <B>PSU_IOU_SLCR_MIO_PIN_30@0XFF180078</B>
\r
20861 <TD width=15% BGCOLOR=#C0C0C0>
\r
20864 <TD width=10% BGCOLOR=#C0C0C0>
\r
20867 <TD width=10% BGCOLOR=#C0C0C0>
\r
20870 <TD width=15% BGCOLOR=#C0C0C0>
\r
20873 <TD width=35% BGCOLOR=#C0C0C0>
\r
20874 <B>Configures MIO Pin 30 peripheral interface mapping</B>
\r
20879 <H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
\r
20880 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20881 <TR valign="top">
\r
20882 <TD width=15% BGCOLOR=#FFFF00>
\r
20883 <B>Register Name</B>
\r
20885 <TD width=15% BGCOLOR=#FFFF00>
\r
20888 <TD width=10% BGCOLOR=#FFFF00>
\r
20891 <TD width=10% BGCOLOR=#FFFF00>
\r
20894 <TD width=15% BGCOLOR=#FFFF00>
\r
20895 <B>Reset Value</B>
\r
20897 <TD width=35% BGCOLOR=#FFFF00>
\r
20898 <B>Description</B>
\r
20901 <TR valign="top">
\r
20902 <TD width=15% BGCOLOR=#FBF5EF>
\r
20903 <B>MIO_PIN_31</B>
\r
20905 <TD width=15% BGCOLOR=#FBF5EF>
\r
20906 <B>0XFF18007C</B>
\r
20908 <TD width=10% BGCOLOR=#FBF5EF>
\r
20911 <TD width=10% BGCOLOR=#FBF5EF>
\r
20914 <TD width=15% BGCOLOR=#FBF5EF>
\r
20915 <B>0x00000000</B>
\r
20917 <TD width=35% BGCOLOR=#FBF5EF>
\r
20923 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
20924 <TR valign="top">
\r
20925 <TD width=15% BGCOLOR=#C0FFC0>
\r
20926 <B>Field Name</B>
\r
20928 <TD width=15% BGCOLOR=#C0FFC0>
\r
20931 <TD width=10% BGCOLOR=#C0FFC0>
\r
20934 <TD width=10% BGCOLOR=#C0FFC0>
\r
20937 <TD width=15% BGCOLOR=#C0FFC0>
\r
20938 <B>Shifted Value</B>
\r
20940 <TD width=35% BGCOLOR=#C0FFC0>
\r
20941 <B>Description</B>
\r
20944 <TR valign="top">
\r
20945 <TD width=15% BGCOLOR=#FBF5EF>
\r
20946 <B>PSU_IOU_SLCR_MIO_PIN_31_L0_SEL</B>
\r
20948 <TD width=15% BGCOLOR=#FBF5EF>
\r
20951 <TD width=10% BGCOLOR=#FBF5EF>
\r
20954 <TD width=10% BGCOLOR=#FBF5EF>
\r
20957 <TD width=15% BGCOLOR=#FBF5EF>
\r
20960 <TD width=35% BGCOLOR=#FBF5EF>
\r
20961 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</B>
\r
20964 <TR valign="top">
\r
20965 <TD width=15% BGCOLOR=#FBF5EF>
\r
20966 <B>PSU_IOU_SLCR_MIO_PIN_31_L1_SEL</B>
\r
20968 <TD width=15% BGCOLOR=#FBF5EF>
\r
20971 <TD width=10% BGCOLOR=#FBF5EF>
\r
20974 <TD width=10% BGCOLOR=#FBF5EF>
\r
20977 <TD width=15% BGCOLOR=#FBF5EF>
\r
20980 <TD width=35% BGCOLOR=#FBF5EF>
\r
20981 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
20984 <TR valign="top">
\r
20985 <TD width=15% BGCOLOR=#FBF5EF>
\r
20986 <B>PSU_IOU_SLCR_MIO_PIN_31_L2_SEL</B>
\r
20988 <TD width=15% BGCOLOR=#FBF5EF>
\r
20991 <TD width=10% BGCOLOR=#FBF5EF>
\r
20994 <TD width=10% BGCOLOR=#FBF5EF>
\r
20997 <TD width=15% BGCOLOR=#FBF5EF>
\r
21000 <TD width=35% BGCOLOR=#FBF5EF>
\r
21001 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
21004 <TR valign="top">
\r
21005 <TD width=15% BGCOLOR=#FBF5EF>
\r
21006 <B>PSU_IOU_SLCR_MIO_PIN_31_L3_SEL</B>
\r
21008 <TD width=15% BGCOLOR=#FBF5EF>
\r
21011 <TD width=10% BGCOLOR=#FBF5EF>
\r
21014 <TD width=10% BGCOLOR=#FBF5EF>
\r
21017 <TD width=15% BGCOLOR=#FBF5EF>
\r
21020 <TD width=35% BGCOLOR=#FBF5EF>
\r
21021 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B>
\r
21024 <TR valign="top">
\r
21025 <TD width=15% BGCOLOR=#C0C0C0>
\r
21026 <B>PSU_IOU_SLCR_MIO_PIN_31@0XFF18007C</B>
\r
21028 <TD width=15% BGCOLOR=#C0C0C0>
\r
21031 <TD width=10% BGCOLOR=#C0C0C0>
\r
21034 <TD width=10% BGCOLOR=#C0C0C0>
\r
21037 <TD width=15% BGCOLOR=#C0C0C0>
\r
21040 <TD width=35% BGCOLOR=#C0C0C0>
\r
21041 <B>Configures MIO Pin 31 peripheral interface mapping</B>
\r
21046 <H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
\r
21047 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21048 <TR valign="top">
\r
21049 <TD width=15% BGCOLOR=#FFFF00>
\r
21050 <B>Register Name</B>
\r
21052 <TD width=15% BGCOLOR=#FFFF00>
\r
21055 <TD width=10% BGCOLOR=#FFFF00>
\r
21058 <TD width=10% BGCOLOR=#FFFF00>
\r
21061 <TD width=15% BGCOLOR=#FFFF00>
\r
21062 <B>Reset Value</B>
\r
21064 <TD width=35% BGCOLOR=#FFFF00>
\r
21065 <B>Description</B>
\r
21068 <TR valign="top">
\r
21069 <TD width=15% BGCOLOR=#FBF5EF>
\r
21070 <B>MIO_PIN_32</B>
\r
21072 <TD width=15% BGCOLOR=#FBF5EF>
\r
21073 <B>0XFF180080</B>
\r
21075 <TD width=10% BGCOLOR=#FBF5EF>
\r
21078 <TD width=10% BGCOLOR=#FBF5EF>
\r
21081 <TD width=15% BGCOLOR=#FBF5EF>
\r
21082 <B>0x00000000</B>
\r
21084 <TD width=35% BGCOLOR=#FBF5EF>
\r
21090 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21091 <TR valign="top">
\r
21092 <TD width=15% BGCOLOR=#C0FFC0>
\r
21093 <B>Field Name</B>
\r
21095 <TD width=15% BGCOLOR=#C0FFC0>
\r
21098 <TD width=10% BGCOLOR=#C0FFC0>
\r
21101 <TD width=10% BGCOLOR=#C0FFC0>
\r
21104 <TD width=15% BGCOLOR=#C0FFC0>
\r
21105 <B>Shifted Value</B>
\r
21107 <TD width=35% BGCOLOR=#C0FFC0>
\r
21108 <B>Description</B>
\r
21111 <TR valign="top">
\r
21112 <TD width=15% BGCOLOR=#FBF5EF>
\r
21113 <B>PSU_IOU_SLCR_MIO_PIN_32_L0_SEL</B>
\r
21115 <TD width=15% BGCOLOR=#FBF5EF>
\r
21118 <TD width=10% BGCOLOR=#FBF5EF>
\r
21121 <TD width=10% BGCOLOR=#FBF5EF>
\r
21124 <TD width=15% BGCOLOR=#FBF5EF>
\r
21127 <TD width=35% BGCOLOR=#FBF5EF>
\r
21128 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</B>
\r
21131 <TR valign="top">
\r
21132 <TD width=15% BGCOLOR=#FBF5EF>
\r
21133 <B>PSU_IOU_SLCR_MIO_PIN_32_L1_SEL</B>
\r
21135 <TD width=15% BGCOLOR=#FBF5EF>
\r
21138 <TD width=10% BGCOLOR=#FBF5EF>
\r
21141 <TD width=10% BGCOLOR=#FBF5EF>
\r
21144 <TD width=15% BGCOLOR=#FBF5EF>
\r
21147 <TD width=35% BGCOLOR=#FBF5EF>
\r
21148 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)</B>
\r
21151 <TR valign="top">
\r
21152 <TD width=15% BGCOLOR=#FBF5EF>
\r
21153 <B>PSU_IOU_SLCR_MIO_PIN_32_L2_SEL</B>
\r
21155 <TD width=15% BGCOLOR=#FBF5EF>
\r
21158 <TD width=10% BGCOLOR=#FBF5EF>
\r
21161 <TD width=10% BGCOLOR=#FBF5EF>
\r
21164 <TD width=15% BGCOLOR=#FBF5EF>
\r
21167 <TD width=35% BGCOLOR=#FBF5EF>
\r
21168 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
21171 <TR valign="top">
\r
21172 <TD width=15% BGCOLOR=#FBF5EF>
\r
21173 <B>PSU_IOU_SLCR_MIO_PIN_32_L3_SEL</B>
\r
21175 <TD width=15% BGCOLOR=#FBF5EF>
\r
21178 <TD width=10% BGCOLOR=#FBF5EF>
\r
21181 <TD width=10% BGCOLOR=#FBF5EF>
\r
21184 <TD width=15% BGCOLOR=#FBF5EF>
\r
21187 <TD width=35% BGCOLOR=#FBF5EF>
\r
21188 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B>
\r
21191 <TR valign="top">
\r
21192 <TD width=15% BGCOLOR=#C0C0C0>
\r
21193 <B>PSU_IOU_SLCR_MIO_PIN_32@0XFF180080</B>
\r
21195 <TD width=15% BGCOLOR=#C0C0C0>
\r
21198 <TD width=10% BGCOLOR=#C0C0C0>
\r
21201 <TD width=10% BGCOLOR=#C0C0C0>
\r
21204 <TD width=15% BGCOLOR=#C0C0C0>
\r
21207 <TD width=35% BGCOLOR=#C0C0C0>
\r
21208 <B>Configures MIO Pin 32 peripheral interface mapping</B>
\r
21213 <H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
\r
21214 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21215 <TR valign="top">
\r
21216 <TD width=15% BGCOLOR=#FFFF00>
\r
21217 <B>Register Name</B>
\r
21219 <TD width=15% BGCOLOR=#FFFF00>
\r
21222 <TD width=10% BGCOLOR=#FFFF00>
\r
21225 <TD width=10% BGCOLOR=#FFFF00>
\r
21228 <TD width=15% BGCOLOR=#FFFF00>
\r
21229 <B>Reset Value</B>
\r
21231 <TD width=35% BGCOLOR=#FFFF00>
\r
21232 <B>Description</B>
\r
21235 <TR valign="top">
\r
21236 <TD width=15% BGCOLOR=#FBF5EF>
\r
21237 <B>MIO_PIN_33</B>
\r
21239 <TD width=15% BGCOLOR=#FBF5EF>
\r
21240 <B>0XFF180084</B>
\r
21242 <TD width=10% BGCOLOR=#FBF5EF>
\r
21245 <TD width=10% BGCOLOR=#FBF5EF>
\r
21248 <TD width=15% BGCOLOR=#FBF5EF>
\r
21249 <B>0x00000000</B>
\r
21251 <TD width=35% BGCOLOR=#FBF5EF>
\r
21257 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21258 <TR valign="top">
\r
21259 <TD width=15% BGCOLOR=#C0FFC0>
\r
21260 <B>Field Name</B>
\r
21262 <TD width=15% BGCOLOR=#C0FFC0>
\r
21265 <TD width=10% BGCOLOR=#C0FFC0>
\r
21268 <TD width=10% BGCOLOR=#C0FFC0>
\r
21271 <TD width=15% BGCOLOR=#C0FFC0>
\r
21272 <B>Shifted Value</B>
\r
21274 <TD width=35% BGCOLOR=#C0FFC0>
\r
21275 <B>Description</B>
\r
21278 <TR valign="top">
\r
21279 <TD width=15% BGCOLOR=#FBF5EF>
\r
21280 <B>PSU_IOU_SLCR_MIO_PIN_33_L0_SEL</B>
\r
21282 <TD width=15% BGCOLOR=#FBF5EF>
\r
21285 <TD width=10% BGCOLOR=#FBF5EF>
\r
21288 <TD width=10% BGCOLOR=#FBF5EF>
\r
21291 <TD width=15% BGCOLOR=#FBF5EF>
\r
21294 <TD width=35% BGCOLOR=#FBF5EF>
\r
21295 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</B>
\r
21298 <TR valign="top">
\r
21299 <TD width=15% BGCOLOR=#FBF5EF>
\r
21300 <B>PSU_IOU_SLCR_MIO_PIN_33_L1_SEL</B>
\r
21302 <TD width=15% BGCOLOR=#FBF5EF>
\r
21305 <TD width=10% BGCOLOR=#FBF5EF>
\r
21308 <TD width=10% BGCOLOR=#FBF5EF>
\r
21311 <TD width=15% BGCOLOR=#FBF5EF>
\r
21314 <TD width=35% BGCOLOR=#FBF5EF>
\r
21315 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
21318 <TR valign="top">
\r
21319 <TD width=15% BGCOLOR=#FBF5EF>
\r
21320 <B>PSU_IOU_SLCR_MIO_PIN_33_L2_SEL</B>
\r
21322 <TD width=15% BGCOLOR=#FBF5EF>
\r
21325 <TD width=10% BGCOLOR=#FBF5EF>
\r
21328 <TD width=10% BGCOLOR=#FBF5EF>
\r
21331 <TD width=15% BGCOLOR=#FBF5EF>
\r
21334 <TD width=35% BGCOLOR=#FBF5EF>
\r
21335 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)</B>
\r
21338 <TR valign="top">
\r
21339 <TD width=15% BGCOLOR=#FBF5EF>
\r
21340 <B>PSU_IOU_SLCR_MIO_PIN_33_L3_SEL</B>
\r
21342 <TD width=15% BGCOLOR=#FBF5EF>
\r
21345 <TD width=10% BGCOLOR=#FBF5EF>
\r
21348 <TD width=10% BGCOLOR=#FBF5EF>
\r
21351 <TD width=15% BGCOLOR=#FBF5EF>
\r
21354 <TD width=35% BGCOLOR=#FBF5EF>
\r
21355 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B>
\r
21358 <TR valign="top">
\r
21359 <TD width=15% BGCOLOR=#C0C0C0>
\r
21360 <B>PSU_IOU_SLCR_MIO_PIN_33@0XFF180084</B>
\r
21362 <TD width=15% BGCOLOR=#C0C0C0>
\r
21365 <TD width=10% BGCOLOR=#C0C0C0>
\r
21368 <TD width=10% BGCOLOR=#C0C0C0>
\r
21371 <TD width=15% BGCOLOR=#C0C0C0>
\r
21374 <TD width=35% BGCOLOR=#C0C0C0>
\r
21375 <B>Configures MIO Pin 33 peripheral interface mapping</B>
\r
21380 <H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
\r
21381 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21382 <TR valign="top">
\r
21383 <TD width=15% BGCOLOR=#FFFF00>
\r
21384 <B>Register Name</B>
\r
21386 <TD width=15% BGCOLOR=#FFFF00>
\r
21389 <TD width=10% BGCOLOR=#FFFF00>
\r
21392 <TD width=10% BGCOLOR=#FFFF00>
\r
21395 <TD width=15% BGCOLOR=#FFFF00>
\r
21396 <B>Reset Value</B>
\r
21398 <TD width=35% BGCOLOR=#FFFF00>
\r
21399 <B>Description</B>
\r
21402 <TR valign="top">
\r
21403 <TD width=15% BGCOLOR=#FBF5EF>
\r
21404 <B>MIO_PIN_34</B>
\r
21406 <TD width=15% BGCOLOR=#FBF5EF>
\r
21407 <B>0XFF180088</B>
\r
21409 <TD width=10% BGCOLOR=#FBF5EF>
\r
21412 <TD width=10% BGCOLOR=#FBF5EF>
\r
21415 <TD width=15% BGCOLOR=#FBF5EF>
\r
21416 <B>0x00000000</B>
\r
21418 <TD width=35% BGCOLOR=#FBF5EF>
\r
21424 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21425 <TR valign="top">
\r
21426 <TD width=15% BGCOLOR=#C0FFC0>
\r
21427 <B>Field Name</B>
\r
21429 <TD width=15% BGCOLOR=#C0FFC0>
\r
21432 <TD width=10% BGCOLOR=#C0FFC0>
\r
21435 <TD width=10% BGCOLOR=#C0FFC0>
\r
21438 <TD width=15% BGCOLOR=#C0FFC0>
\r
21439 <B>Shifted Value</B>
\r
21441 <TD width=35% BGCOLOR=#C0FFC0>
\r
21442 <B>Description</B>
\r
21445 <TR valign="top">
\r
21446 <TD width=15% BGCOLOR=#FBF5EF>
\r
21447 <B>PSU_IOU_SLCR_MIO_PIN_34_L0_SEL</B>
\r
21449 <TD width=15% BGCOLOR=#FBF5EF>
\r
21452 <TD width=10% BGCOLOR=#FBF5EF>
\r
21455 <TD width=10% BGCOLOR=#FBF5EF>
\r
21458 <TD width=15% BGCOLOR=#FBF5EF>
\r
21461 <TD width=35% BGCOLOR=#FBF5EF>
\r
21462 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</B>
\r
21465 <TR valign="top">
\r
21466 <TD width=15% BGCOLOR=#FBF5EF>
\r
21467 <B>PSU_IOU_SLCR_MIO_PIN_34_L1_SEL</B>
\r
21469 <TD width=15% BGCOLOR=#FBF5EF>
\r
21472 <TD width=10% BGCOLOR=#FBF5EF>
\r
21475 <TD width=10% BGCOLOR=#FBF5EF>
\r
21478 <TD width=15% BGCOLOR=#FBF5EF>
\r
21481 <TD width=35% BGCOLOR=#FBF5EF>
\r
21482 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
21485 <TR valign="top">
\r
21486 <TD width=15% BGCOLOR=#FBF5EF>
\r
21487 <B>PSU_IOU_SLCR_MIO_PIN_34_L2_SEL</B>
\r
21489 <TD width=15% BGCOLOR=#FBF5EF>
\r
21492 <TD width=10% BGCOLOR=#FBF5EF>
\r
21495 <TD width=10% BGCOLOR=#FBF5EF>
\r
21498 <TD width=15% BGCOLOR=#FBF5EF>
\r
21501 <TD width=35% BGCOLOR=#FBF5EF>
\r
21502 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B>
\r
21505 <TR valign="top">
\r
21506 <TD width=15% BGCOLOR=#FBF5EF>
\r
21507 <B>PSU_IOU_SLCR_MIO_PIN_34_L3_SEL</B>
\r
21509 <TD width=15% BGCOLOR=#FBF5EF>
\r
21512 <TD width=10% BGCOLOR=#FBF5EF>
\r
21515 <TD width=10% BGCOLOR=#FBF5EF>
\r
21518 <TD width=15% BGCOLOR=#FBF5EF>
\r
21521 <TD width=35% BGCOLOR=#FBF5EF>
\r
21522 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B>
\r
21525 <TR valign="top">
\r
21526 <TD width=15% BGCOLOR=#C0C0C0>
\r
21527 <B>PSU_IOU_SLCR_MIO_PIN_34@0XFF180088</B>
\r
21529 <TD width=15% BGCOLOR=#C0C0C0>
\r
21532 <TD width=10% BGCOLOR=#C0C0C0>
\r
21535 <TD width=10% BGCOLOR=#C0C0C0>
\r
21538 <TD width=15% BGCOLOR=#C0C0C0>
\r
21541 <TD width=35% BGCOLOR=#C0C0C0>
\r
21542 <B>Configures MIO Pin 34 peripheral interface mapping</B>
\r
21547 <H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
\r
21548 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21549 <TR valign="top">
\r
21550 <TD width=15% BGCOLOR=#FFFF00>
\r
21551 <B>Register Name</B>
\r
21553 <TD width=15% BGCOLOR=#FFFF00>
\r
21556 <TD width=10% BGCOLOR=#FFFF00>
\r
21559 <TD width=10% BGCOLOR=#FFFF00>
\r
21562 <TD width=15% BGCOLOR=#FFFF00>
\r
21563 <B>Reset Value</B>
\r
21565 <TD width=35% BGCOLOR=#FFFF00>
\r
21566 <B>Description</B>
\r
21569 <TR valign="top">
\r
21570 <TD width=15% BGCOLOR=#FBF5EF>
\r
21571 <B>MIO_PIN_35</B>
\r
21573 <TD width=15% BGCOLOR=#FBF5EF>
\r
21574 <B>0XFF18008C</B>
\r
21576 <TD width=10% BGCOLOR=#FBF5EF>
\r
21579 <TD width=10% BGCOLOR=#FBF5EF>
\r
21582 <TD width=15% BGCOLOR=#FBF5EF>
\r
21583 <B>0x00000000</B>
\r
21585 <TD width=35% BGCOLOR=#FBF5EF>
\r
21591 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21592 <TR valign="top">
\r
21593 <TD width=15% BGCOLOR=#C0FFC0>
\r
21594 <B>Field Name</B>
\r
21596 <TD width=15% BGCOLOR=#C0FFC0>
\r
21599 <TD width=10% BGCOLOR=#C0FFC0>
\r
21602 <TD width=10% BGCOLOR=#C0FFC0>
\r
21605 <TD width=15% BGCOLOR=#C0FFC0>
\r
21606 <B>Shifted Value</B>
\r
21608 <TD width=35% BGCOLOR=#C0FFC0>
\r
21609 <B>Description</B>
\r
21612 <TR valign="top">
\r
21613 <TD width=15% BGCOLOR=#FBF5EF>
\r
21614 <B>PSU_IOU_SLCR_MIO_PIN_35_L0_SEL</B>
\r
21616 <TD width=15% BGCOLOR=#FBF5EF>
\r
21619 <TD width=10% BGCOLOR=#FBF5EF>
\r
21622 <TD width=10% BGCOLOR=#FBF5EF>
\r
21625 <TD width=15% BGCOLOR=#FBF5EF>
\r
21628 <TD width=35% BGCOLOR=#FBF5EF>
\r
21629 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</B>
\r
21632 <TR valign="top">
\r
21633 <TD width=15% BGCOLOR=#FBF5EF>
\r
21634 <B>PSU_IOU_SLCR_MIO_PIN_35_L1_SEL</B>
\r
21636 <TD width=15% BGCOLOR=#FBF5EF>
\r
21639 <TD width=10% BGCOLOR=#FBF5EF>
\r
21642 <TD width=10% BGCOLOR=#FBF5EF>
\r
21645 <TD width=15% BGCOLOR=#FBF5EF>
\r
21648 <TD width=35% BGCOLOR=#FBF5EF>
\r
21649 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
21652 <TR valign="top">
\r
21653 <TD width=15% BGCOLOR=#FBF5EF>
\r
21654 <B>PSU_IOU_SLCR_MIO_PIN_35_L2_SEL</B>
\r
21656 <TD width=15% BGCOLOR=#FBF5EF>
\r
21659 <TD width=10% BGCOLOR=#FBF5EF>
\r
21662 <TD width=10% BGCOLOR=#FBF5EF>
\r
21665 <TD width=15% BGCOLOR=#FBF5EF>
\r
21668 <TD width=35% BGCOLOR=#FBF5EF>
\r
21669 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B>
\r
21672 <TR valign="top">
\r
21673 <TD width=15% BGCOLOR=#FBF5EF>
\r
21674 <B>PSU_IOU_SLCR_MIO_PIN_35_L3_SEL</B>
\r
21676 <TD width=15% BGCOLOR=#FBF5EF>
\r
21679 <TD width=10% BGCOLOR=#FBF5EF>
\r
21682 <TD width=10% BGCOLOR=#FBF5EF>
\r
21685 <TD width=15% BGCOLOR=#FBF5EF>
\r
21688 <TD width=35% BGCOLOR=#FBF5EF>
\r
21689 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B>
\r
21692 <TR valign="top">
\r
21693 <TD width=15% BGCOLOR=#C0C0C0>
\r
21694 <B>PSU_IOU_SLCR_MIO_PIN_35@0XFF18008C</B>
\r
21696 <TD width=15% BGCOLOR=#C0C0C0>
\r
21699 <TD width=10% BGCOLOR=#C0C0C0>
\r
21702 <TD width=10% BGCOLOR=#C0C0C0>
\r
21705 <TD width=15% BGCOLOR=#C0C0C0>
\r
21708 <TD width=35% BGCOLOR=#C0C0C0>
\r
21709 <B>Configures MIO Pin 35 peripheral interface mapping</B>
\r
21714 <H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
\r
21715 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21716 <TR valign="top">
\r
21717 <TD width=15% BGCOLOR=#FFFF00>
\r
21718 <B>Register Name</B>
\r
21720 <TD width=15% BGCOLOR=#FFFF00>
\r
21723 <TD width=10% BGCOLOR=#FFFF00>
\r
21726 <TD width=10% BGCOLOR=#FFFF00>
\r
21729 <TD width=15% BGCOLOR=#FFFF00>
\r
21730 <B>Reset Value</B>
\r
21732 <TD width=35% BGCOLOR=#FFFF00>
\r
21733 <B>Description</B>
\r
21736 <TR valign="top">
\r
21737 <TD width=15% BGCOLOR=#FBF5EF>
\r
21738 <B>MIO_PIN_36</B>
\r
21740 <TD width=15% BGCOLOR=#FBF5EF>
\r
21741 <B>0XFF180090</B>
\r
21743 <TD width=10% BGCOLOR=#FBF5EF>
\r
21746 <TD width=10% BGCOLOR=#FBF5EF>
\r
21749 <TD width=15% BGCOLOR=#FBF5EF>
\r
21750 <B>0x00000000</B>
\r
21752 <TD width=35% BGCOLOR=#FBF5EF>
\r
21758 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21759 <TR valign="top">
\r
21760 <TD width=15% BGCOLOR=#C0FFC0>
\r
21761 <B>Field Name</B>
\r
21763 <TD width=15% BGCOLOR=#C0FFC0>
\r
21766 <TD width=10% BGCOLOR=#C0FFC0>
\r
21769 <TD width=10% BGCOLOR=#C0FFC0>
\r
21772 <TD width=15% BGCOLOR=#C0FFC0>
\r
21773 <B>Shifted Value</B>
\r
21775 <TD width=35% BGCOLOR=#C0FFC0>
\r
21776 <B>Description</B>
\r
21779 <TR valign="top">
\r
21780 <TD width=15% BGCOLOR=#FBF5EF>
\r
21781 <B>PSU_IOU_SLCR_MIO_PIN_36_L0_SEL</B>
\r
21783 <TD width=15% BGCOLOR=#FBF5EF>
\r
21786 <TD width=10% BGCOLOR=#FBF5EF>
\r
21789 <TD width=10% BGCOLOR=#FBF5EF>
\r
21792 <TD width=15% BGCOLOR=#FBF5EF>
\r
21795 <TD width=35% BGCOLOR=#FBF5EF>
\r
21796 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</B>
\r
21799 <TR valign="top">
\r
21800 <TD width=15% BGCOLOR=#FBF5EF>
\r
21801 <B>PSU_IOU_SLCR_MIO_PIN_36_L1_SEL</B>
\r
21803 <TD width=15% BGCOLOR=#FBF5EF>
\r
21806 <TD width=10% BGCOLOR=#FBF5EF>
\r
21809 <TD width=10% BGCOLOR=#FBF5EF>
\r
21812 <TD width=15% BGCOLOR=#FBF5EF>
\r
21815 <TD width=35% BGCOLOR=#FBF5EF>
\r
21816 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
21819 <TR valign="top">
\r
21820 <TD width=15% BGCOLOR=#FBF5EF>
\r
21821 <B>PSU_IOU_SLCR_MIO_PIN_36_L2_SEL</B>
\r
21823 <TD width=15% BGCOLOR=#FBF5EF>
\r
21826 <TD width=10% BGCOLOR=#FBF5EF>
\r
21829 <TD width=10% BGCOLOR=#FBF5EF>
\r
21832 <TD width=15% BGCOLOR=#FBF5EF>
\r
21835 <TD width=35% BGCOLOR=#FBF5EF>
\r
21836 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)</B>
\r
21839 <TR valign="top">
\r
21840 <TD width=15% BGCOLOR=#FBF5EF>
\r
21841 <B>PSU_IOU_SLCR_MIO_PIN_36_L3_SEL</B>
\r
21843 <TD width=15% BGCOLOR=#FBF5EF>
\r
21846 <TD width=10% BGCOLOR=#FBF5EF>
\r
21849 <TD width=10% BGCOLOR=#FBF5EF>
\r
21852 <TD width=15% BGCOLOR=#FBF5EF>
\r
21855 <TD width=35% BGCOLOR=#FBF5EF>
\r
21856 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B>
\r
21859 <TR valign="top">
\r
21860 <TD width=15% BGCOLOR=#C0C0C0>
\r
21861 <B>PSU_IOU_SLCR_MIO_PIN_36@0XFF180090</B>
\r
21863 <TD width=15% BGCOLOR=#C0C0C0>
\r
21866 <TD width=10% BGCOLOR=#C0C0C0>
\r
21869 <TD width=10% BGCOLOR=#C0C0C0>
\r
21872 <TD width=15% BGCOLOR=#C0C0C0>
\r
21875 <TD width=35% BGCOLOR=#C0C0C0>
\r
21876 <B>Configures MIO Pin 36 peripheral interface mapping</B>
\r
21881 <H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
\r
21882 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21883 <TR valign="top">
\r
21884 <TD width=15% BGCOLOR=#FFFF00>
\r
21885 <B>Register Name</B>
\r
21887 <TD width=15% BGCOLOR=#FFFF00>
\r
21890 <TD width=10% BGCOLOR=#FFFF00>
\r
21893 <TD width=10% BGCOLOR=#FFFF00>
\r
21896 <TD width=15% BGCOLOR=#FFFF00>
\r
21897 <B>Reset Value</B>
\r
21899 <TD width=35% BGCOLOR=#FFFF00>
\r
21900 <B>Description</B>
\r
21903 <TR valign="top">
\r
21904 <TD width=15% BGCOLOR=#FBF5EF>
\r
21905 <B>MIO_PIN_37</B>
\r
21907 <TD width=15% BGCOLOR=#FBF5EF>
\r
21908 <B>0XFF180094</B>
\r
21910 <TD width=10% BGCOLOR=#FBF5EF>
\r
21913 <TD width=10% BGCOLOR=#FBF5EF>
\r
21916 <TD width=15% BGCOLOR=#FBF5EF>
\r
21917 <B>0x00000000</B>
\r
21919 <TD width=35% BGCOLOR=#FBF5EF>
\r
21925 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
21926 <TR valign="top">
\r
21927 <TD width=15% BGCOLOR=#C0FFC0>
\r
21928 <B>Field Name</B>
\r
21930 <TD width=15% BGCOLOR=#C0FFC0>
\r
21933 <TD width=10% BGCOLOR=#C0FFC0>
\r
21936 <TD width=10% BGCOLOR=#C0FFC0>
\r
21939 <TD width=15% BGCOLOR=#C0FFC0>
\r
21940 <B>Shifted Value</B>
\r
21942 <TD width=35% BGCOLOR=#C0FFC0>
\r
21943 <B>Description</B>
\r
21946 <TR valign="top">
\r
21947 <TD width=15% BGCOLOR=#FBF5EF>
\r
21948 <B>PSU_IOU_SLCR_MIO_PIN_37_L0_SEL</B>
\r
21950 <TD width=15% BGCOLOR=#FBF5EF>
\r
21953 <TD width=10% BGCOLOR=#FBF5EF>
\r
21956 <TD width=10% BGCOLOR=#FBF5EF>
\r
21959 <TD width=15% BGCOLOR=#FBF5EF>
\r
21962 <TD width=35% BGCOLOR=#FBF5EF>
\r
21963 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</B>
\r
21966 <TR valign="top">
\r
21967 <TD width=15% BGCOLOR=#FBF5EF>
\r
21968 <B>PSU_IOU_SLCR_MIO_PIN_37_L1_SEL</B>
\r
21970 <TD width=15% BGCOLOR=#FBF5EF>
\r
21973 <TD width=10% BGCOLOR=#FBF5EF>
\r
21976 <TD width=10% BGCOLOR=#FBF5EF>
\r
21979 <TD width=15% BGCOLOR=#FBF5EF>
\r
21982 <TD width=35% BGCOLOR=#FBF5EF>
\r
21983 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)</B>
\r
21986 <TR valign="top">
\r
21987 <TD width=15% BGCOLOR=#FBF5EF>
\r
21988 <B>PSU_IOU_SLCR_MIO_PIN_37_L2_SEL</B>
\r
21990 <TD width=15% BGCOLOR=#FBF5EF>
\r
21993 <TD width=10% BGCOLOR=#FBF5EF>
\r
21996 <TD width=10% BGCOLOR=#FBF5EF>
\r
21999 <TD width=15% BGCOLOR=#FBF5EF>
\r
22002 <TD width=35% BGCOLOR=#FBF5EF>
\r
22003 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)</B>
\r
22006 <TR valign="top">
\r
22007 <TD width=15% BGCOLOR=#FBF5EF>
\r
22008 <B>PSU_IOU_SLCR_MIO_PIN_37_L3_SEL</B>
\r
22010 <TD width=15% BGCOLOR=#FBF5EF>
\r
22013 <TD width=10% BGCOLOR=#FBF5EF>
\r
22016 <TD width=10% BGCOLOR=#FBF5EF>
\r
22019 <TD width=15% BGCOLOR=#FBF5EF>
\r
22022 <TD width=35% BGCOLOR=#FBF5EF>
\r
22023 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B>
\r
22026 <TR valign="top">
\r
22027 <TD width=15% BGCOLOR=#C0C0C0>
\r
22028 <B>PSU_IOU_SLCR_MIO_PIN_37@0XFF180094</B>
\r
22030 <TD width=15% BGCOLOR=#C0C0C0>
\r
22033 <TD width=10% BGCOLOR=#C0C0C0>
\r
22036 <TD width=10% BGCOLOR=#C0C0C0>
\r
22039 <TD width=15% BGCOLOR=#C0C0C0>
\r
22042 <TD width=35% BGCOLOR=#C0C0C0>
\r
22043 <B>Configures MIO Pin 37 peripheral interface mapping</B>
\r
22048 <H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
\r
22049 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22050 <TR valign="top">
\r
22051 <TD width=15% BGCOLOR=#FFFF00>
\r
22052 <B>Register Name</B>
\r
22054 <TD width=15% BGCOLOR=#FFFF00>
\r
22057 <TD width=10% BGCOLOR=#FFFF00>
\r
22060 <TD width=10% BGCOLOR=#FFFF00>
\r
22063 <TD width=15% BGCOLOR=#FFFF00>
\r
22064 <B>Reset Value</B>
\r
22066 <TD width=35% BGCOLOR=#FFFF00>
\r
22067 <B>Description</B>
\r
22070 <TR valign="top">
\r
22071 <TD width=15% BGCOLOR=#FBF5EF>
\r
22072 <B>MIO_PIN_38</B>
\r
22074 <TD width=15% BGCOLOR=#FBF5EF>
\r
22075 <B>0XFF180098</B>
\r
22077 <TD width=10% BGCOLOR=#FBF5EF>
\r
22080 <TD width=10% BGCOLOR=#FBF5EF>
\r
22083 <TD width=15% BGCOLOR=#FBF5EF>
\r
22084 <B>0x00000000</B>
\r
22086 <TD width=35% BGCOLOR=#FBF5EF>
\r
22092 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22093 <TR valign="top">
\r
22094 <TD width=15% BGCOLOR=#C0FFC0>
\r
22095 <B>Field Name</B>
\r
22097 <TD width=15% BGCOLOR=#C0FFC0>
\r
22100 <TD width=10% BGCOLOR=#C0FFC0>
\r
22103 <TD width=10% BGCOLOR=#C0FFC0>
\r
22106 <TD width=15% BGCOLOR=#C0FFC0>
\r
22107 <B>Shifted Value</B>
\r
22109 <TD width=35% BGCOLOR=#C0FFC0>
\r
22110 <B>Description</B>
\r
22113 <TR valign="top">
\r
22114 <TD width=15% BGCOLOR=#FBF5EF>
\r
22115 <B>PSU_IOU_SLCR_MIO_PIN_38_L0_SEL</B>
\r
22117 <TD width=15% BGCOLOR=#FBF5EF>
\r
22120 <TD width=10% BGCOLOR=#FBF5EF>
\r
22123 <TD width=10% BGCOLOR=#FBF5EF>
\r
22126 <TD width=15% BGCOLOR=#FBF5EF>
\r
22129 <TD width=35% BGCOLOR=#FBF5EF>
\r
22130 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</B>
\r
22133 <TR valign="top">
\r
22134 <TD width=15% BGCOLOR=#FBF5EF>
\r
22135 <B>PSU_IOU_SLCR_MIO_PIN_38_L1_SEL</B>
\r
22137 <TD width=15% BGCOLOR=#FBF5EF>
\r
22140 <TD width=10% BGCOLOR=#FBF5EF>
\r
22143 <TD width=10% BGCOLOR=#FBF5EF>
\r
22146 <TD width=15% BGCOLOR=#FBF5EF>
\r
22149 <TD width=35% BGCOLOR=#FBF5EF>
\r
22150 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22153 <TR valign="top">
\r
22154 <TD width=15% BGCOLOR=#FBF5EF>
\r
22155 <B>PSU_IOU_SLCR_MIO_PIN_38_L2_SEL</B>
\r
22157 <TD width=15% BGCOLOR=#FBF5EF>
\r
22160 <TD width=10% BGCOLOR=#FBF5EF>
\r
22163 <TD width=10% BGCOLOR=#FBF5EF>
\r
22166 <TD width=15% BGCOLOR=#FBF5EF>
\r
22169 <TD width=35% BGCOLOR=#FBF5EF>
\r
22170 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used</B>
\r
22173 <TR valign="top">
\r
22174 <TD width=15% BGCOLOR=#FBF5EF>
\r
22175 <B>PSU_IOU_SLCR_MIO_PIN_38_L3_SEL</B>
\r
22177 <TD width=15% BGCOLOR=#FBF5EF>
\r
22180 <TD width=10% BGCOLOR=#FBF5EF>
\r
22183 <TD width=10% BGCOLOR=#FBF5EF>
\r
22186 <TD width=15% BGCOLOR=#FBF5EF>
\r
22189 <TD width=35% BGCOLOR=#FBF5EF>
\r
22190 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- (Trace Port Clock)</B>
\r
22193 <TR valign="top">
\r
22194 <TD width=15% BGCOLOR=#C0C0C0>
\r
22195 <B>PSU_IOU_SLCR_MIO_PIN_38@0XFF180098</B>
\r
22197 <TD width=15% BGCOLOR=#C0C0C0>
\r
22200 <TD width=10% BGCOLOR=#C0C0C0>
\r
22203 <TD width=10% BGCOLOR=#C0C0C0>
\r
22206 <TD width=15% BGCOLOR=#C0C0C0>
\r
22209 <TD width=35% BGCOLOR=#C0C0C0>
\r
22210 <B>Configures MIO Pin 38 peripheral interface mapping</B>
\r
22215 <H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
\r
22216 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22217 <TR valign="top">
\r
22218 <TD width=15% BGCOLOR=#FFFF00>
\r
22219 <B>Register Name</B>
\r
22221 <TD width=15% BGCOLOR=#FFFF00>
\r
22224 <TD width=10% BGCOLOR=#FFFF00>
\r
22227 <TD width=10% BGCOLOR=#FFFF00>
\r
22230 <TD width=15% BGCOLOR=#FFFF00>
\r
22231 <B>Reset Value</B>
\r
22233 <TD width=35% BGCOLOR=#FFFF00>
\r
22234 <B>Description</B>
\r
22237 <TR valign="top">
\r
22238 <TD width=15% BGCOLOR=#FBF5EF>
\r
22239 <B>MIO_PIN_39</B>
\r
22241 <TD width=15% BGCOLOR=#FBF5EF>
\r
22242 <B>0XFF18009C</B>
\r
22244 <TD width=10% BGCOLOR=#FBF5EF>
\r
22247 <TD width=10% BGCOLOR=#FBF5EF>
\r
22250 <TD width=15% BGCOLOR=#FBF5EF>
\r
22251 <B>0x00000000</B>
\r
22253 <TD width=35% BGCOLOR=#FBF5EF>
\r
22259 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22260 <TR valign="top">
\r
22261 <TD width=15% BGCOLOR=#C0FFC0>
\r
22262 <B>Field Name</B>
\r
22264 <TD width=15% BGCOLOR=#C0FFC0>
\r
22267 <TD width=10% BGCOLOR=#C0FFC0>
\r
22270 <TD width=10% BGCOLOR=#C0FFC0>
\r
22273 <TD width=15% BGCOLOR=#C0FFC0>
\r
22274 <B>Shifted Value</B>
\r
22276 <TD width=35% BGCOLOR=#C0FFC0>
\r
22277 <B>Description</B>
\r
22280 <TR valign="top">
\r
22281 <TD width=15% BGCOLOR=#FBF5EF>
\r
22282 <B>PSU_IOU_SLCR_MIO_PIN_39_L0_SEL</B>
\r
22284 <TD width=15% BGCOLOR=#FBF5EF>
\r
22287 <TD width=10% BGCOLOR=#FBF5EF>
\r
22290 <TD width=10% BGCOLOR=#FBF5EF>
\r
22293 <TD width=15% BGCOLOR=#FBF5EF>
\r
22296 <TD width=35% BGCOLOR=#FBF5EF>
\r
22297 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</B>
\r
22300 <TR valign="top">
\r
22301 <TD width=15% BGCOLOR=#FBF5EF>
\r
22302 <B>PSU_IOU_SLCR_MIO_PIN_39_L1_SEL</B>
\r
22304 <TD width=15% BGCOLOR=#FBF5EF>
\r
22307 <TD width=10% BGCOLOR=#FBF5EF>
\r
22310 <TD width=10% BGCOLOR=#FBF5EF>
\r
22313 <TD width=15% BGCOLOR=#FBF5EF>
\r
22316 <TD width=35% BGCOLOR=#FBF5EF>
\r
22317 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22320 <TR valign="top">
\r
22321 <TD width=15% BGCOLOR=#FBF5EF>
\r
22322 <B>PSU_IOU_SLCR_MIO_PIN_39_L2_SEL</B>
\r
22324 <TD width=15% BGCOLOR=#FBF5EF>
\r
22327 <TD width=10% BGCOLOR=#FBF5EF>
\r
22330 <TD width=10% BGCOLOR=#FBF5EF>
\r
22333 <TD width=15% BGCOLOR=#FBF5EF>
\r
22336 <TD width=35% BGCOLOR=#FBF5EF>
\r
22337 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used</B>
\r
22340 <TR valign="top">
\r
22341 <TD width=15% BGCOLOR=#FBF5EF>
\r
22342 <B>PSU_IOU_SLCR_MIO_PIN_39_L3_SEL</B>
\r
22344 <TD width=15% BGCOLOR=#FBF5EF>
\r
22347 <TD width=10% BGCOLOR=#FBF5EF>
\r
22350 <TD width=10% BGCOLOR=#FBF5EF>
\r
22353 <TD width=15% BGCOLOR=#FBF5EF>
\r
22356 <TD width=35% BGCOLOR=#FBF5EF>
\r
22357 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B>
\r
22360 <TR valign="top">
\r
22361 <TD width=15% BGCOLOR=#C0C0C0>
\r
22362 <B>PSU_IOU_SLCR_MIO_PIN_39@0XFF18009C</B>
\r
22364 <TD width=15% BGCOLOR=#C0C0C0>
\r
22367 <TD width=10% BGCOLOR=#C0C0C0>
\r
22370 <TD width=10% BGCOLOR=#C0C0C0>
\r
22373 <TD width=15% BGCOLOR=#C0C0C0>
\r
22376 <TD width=35% BGCOLOR=#C0C0C0>
\r
22377 <B>Configures MIO Pin 39 peripheral interface mapping</B>
\r
22382 <H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
\r
22383 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22384 <TR valign="top">
\r
22385 <TD width=15% BGCOLOR=#FFFF00>
\r
22386 <B>Register Name</B>
\r
22388 <TD width=15% BGCOLOR=#FFFF00>
\r
22391 <TD width=10% BGCOLOR=#FFFF00>
\r
22394 <TD width=10% BGCOLOR=#FFFF00>
\r
22397 <TD width=15% BGCOLOR=#FFFF00>
\r
22398 <B>Reset Value</B>
\r
22400 <TD width=35% BGCOLOR=#FFFF00>
\r
22401 <B>Description</B>
\r
22404 <TR valign="top">
\r
22405 <TD width=15% BGCOLOR=#FBF5EF>
\r
22406 <B>MIO_PIN_40</B>
\r
22408 <TD width=15% BGCOLOR=#FBF5EF>
\r
22409 <B>0XFF1800A0</B>
\r
22411 <TD width=10% BGCOLOR=#FBF5EF>
\r
22414 <TD width=10% BGCOLOR=#FBF5EF>
\r
22417 <TD width=15% BGCOLOR=#FBF5EF>
\r
22418 <B>0x00000000</B>
\r
22420 <TD width=35% BGCOLOR=#FBF5EF>
\r
22426 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22427 <TR valign="top">
\r
22428 <TD width=15% BGCOLOR=#C0FFC0>
\r
22429 <B>Field Name</B>
\r
22431 <TD width=15% BGCOLOR=#C0FFC0>
\r
22434 <TD width=10% BGCOLOR=#C0FFC0>
\r
22437 <TD width=10% BGCOLOR=#C0FFC0>
\r
22440 <TD width=15% BGCOLOR=#C0FFC0>
\r
22441 <B>Shifted Value</B>
\r
22443 <TD width=35% BGCOLOR=#C0FFC0>
\r
22444 <B>Description</B>
\r
22447 <TR valign="top">
\r
22448 <TD width=15% BGCOLOR=#FBF5EF>
\r
22449 <B>PSU_IOU_SLCR_MIO_PIN_40_L0_SEL</B>
\r
22451 <TD width=15% BGCOLOR=#FBF5EF>
\r
22454 <TD width=10% BGCOLOR=#FBF5EF>
\r
22457 <TD width=10% BGCOLOR=#FBF5EF>
\r
22460 <TD width=15% BGCOLOR=#FBF5EF>
\r
22463 <TD width=35% BGCOLOR=#FBF5EF>
\r
22464 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</B>
\r
22467 <TR valign="top">
\r
22468 <TD width=15% BGCOLOR=#FBF5EF>
\r
22469 <B>PSU_IOU_SLCR_MIO_PIN_40_L1_SEL</B>
\r
22471 <TD width=15% BGCOLOR=#FBF5EF>
\r
22474 <TD width=10% BGCOLOR=#FBF5EF>
\r
22477 <TD width=10% BGCOLOR=#FBF5EF>
\r
22480 <TD width=15% BGCOLOR=#FBF5EF>
\r
22483 <TD width=35% BGCOLOR=#FBF5EF>
\r
22484 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22487 <TR valign="top">
\r
22488 <TD width=15% BGCOLOR=#FBF5EF>
\r
22489 <B>PSU_IOU_SLCR_MIO_PIN_40_L2_SEL</B>
\r
22491 <TD width=15% BGCOLOR=#FBF5EF>
\r
22494 <TD width=10% BGCOLOR=#FBF5EF>
\r
22497 <TD width=10% BGCOLOR=#FBF5EF>
\r
22500 <TD width=15% BGCOLOR=#FBF5EF>
\r
22503 <TD width=35% BGCOLOR=#FBF5EF>
\r
22504 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used</B>
\r
22507 <TR valign="top">
\r
22508 <TD width=15% BGCOLOR=#FBF5EF>
\r
22509 <B>PSU_IOU_SLCR_MIO_PIN_40_L3_SEL</B>
\r
22511 <TD width=15% BGCOLOR=#FBF5EF>
\r
22514 <TD width=10% BGCOLOR=#FBF5EF>
\r
22517 <TD width=10% BGCOLOR=#FBF5EF>
\r
22520 <TD width=15% BGCOLOR=#FBF5EF>
\r
22523 <TD width=35% BGCOLOR=#FBF5EF>
\r
22524 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B>
\r
22527 <TR valign="top">
\r
22528 <TD width=15% BGCOLOR=#C0C0C0>
\r
22529 <B>PSU_IOU_SLCR_MIO_PIN_40@0XFF1800A0</B>
\r
22531 <TD width=15% BGCOLOR=#C0C0C0>
\r
22534 <TD width=10% BGCOLOR=#C0C0C0>
\r
22537 <TD width=10% BGCOLOR=#C0C0C0>
\r
22540 <TD width=15% BGCOLOR=#C0C0C0>
\r
22543 <TD width=35% BGCOLOR=#C0C0C0>
\r
22544 <B>Configures MIO Pin 40 peripheral interface mapping</B>
\r
22549 <H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
\r
22550 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22551 <TR valign="top">
\r
22552 <TD width=15% BGCOLOR=#FFFF00>
\r
22553 <B>Register Name</B>
\r
22555 <TD width=15% BGCOLOR=#FFFF00>
\r
22558 <TD width=10% BGCOLOR=#FFFF00>
\r
22561 <TD width=10% BGCOLOR=#FFFF00>
\r
22564 <TD width=15% BGCOLOR=#FFFF00>
\r
22565 <B>Reset Value</B>
\r
22567 <TD width=35% BGCOLOR=#FFFF00>
\r
22568 <B>Description</B>
\r
22571 <TR valign="top">
\r
22572 <TD width=15% BGCOLOR=#FBF5EF>
\r
22573 <B>MIO_PIN_41</B>
\r
22575 <TD width=15% BGCOLOR=#FBF5EF>
\r
22576 <B>0XFF1800A4</B>
\r
22578 <TD width=10% BGCOLOR=#FBF5EF>
\r
22581 <TD width=10% BGCOLOR=#FBF5EF>
\r
22584 <TD width=15% BGCOLOR=#FBF5EF>
\r
22585 <B>0x00000000</B>
\r
22587 <TD width=35% BGCOLOR=#FBF5EF>
\r
22593 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22594 <TR valign="top">
\r
22595 <TD width=15% BGCOLOR=#C0FFC0>
\r
22596 <B>Field Name</B>
\r
22598 <TD width=15% BGCOLOR=#C0FFC0>
\r
22601 <TD width=10% BGCOLOR=#C0FFC0>
\r
22604 <TD width=10% BGCOLOR=#C0FFC0>
\r
22607 <TD width=15% BGCOLOR=#C0FFC0>
\r
22608 <B>Shifted Value</B>
\r
22610 <TD width=35% BGCOLOR=#C0FFC0>
\r
22611 <B>Description</B>
\r
22614 <TR valign="top">
\r
22615 <TD width=15% BGCOLOR=#FBF5EF>
\r
22616 <B>PSU_IOU_SLCR_MIO_PIN_41_L0_SEL</B>
\r
22618 <TD width=15% BGCOLOR=#FBF5EF>
\r
22621 <TD width=10% BGCOLOR=#FBF5EF>
\r
22624 <TD width=10% BGCOLOR=#FBF5EF>
\r
22627 <TD width=15% BGCOLOR=#FBF5EF>
\r
22630 <TD width=35% BGCOLOR=#FBF5EF>
\r
22631 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</B>
\r
22634 <TR valign="top">
\r
22635 <TD width=15% BGCOLOR=#FBF5EF>
\r
22636 <B>PSU_IOU_SLCR_MIO_PIN_41_L1_SEL</B>
\r
22638 <TD width=15% BGCOLOR=#FBF5EF>
\r
22641 <TD width=10% BGCOLOR=#FBF5EF>
\r
22644 <TD width=10% BGCOLOR=#FBF5EF>
\r
22647 <TD width=15% BGCOLOR=#FBF5EF>
\r
22650 <TD width=35% BGCOLOR=#FBF5EF>
\r
22651 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22654 <TR valign="top">
\r
22655 <TD width=15% BGCOLOR=#FBF5EF>
\r
22656 <B>PSU_IOU_SLCR_MIO_PIN_41_L2_SEL</B>
\r
22658 <TD width=15% BGCOLOR=#FBF5EF>
\r
22661 <TD width=10% BGCOLOR=#FBF5EF>
\r
22664 <TD width=10% BGCOLOR=#FBF5EF>
\r
22667 <TD width=15% BGCOLOR=#FBF5EF>
\r
22670 <TD width=35% BGCOLOR=#FBF5EF>
\r
22671 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used</B>
\r
22674 <TR valign="top">
\r
22675 <TD width=15% BGCOLOR=#FBF5EF>
\r
22676 <B>PSU_IOU_SLCR_MIO_PIN_41_L3_SEL</B>
\r
22678 <TD width=15% BGCOLOR=#FBF5EF>
\r
22681 <TD width=10% BGCOLOR=#FBF5EF>
\r
22684 <TD width=10% BGCOLOR=#FBF5EF>
\r
22687 <TD width=15% BGCOLOR=#FBF5EF>
\r
22690 <TD width=35% BGCOLOR=#FBF5EF>
\r
22691 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B>
\r
22694 <TR valign="top">
\r
22695 <TD width=15% BGCOLOR=#C0C0C0>
\r
22696 <B>PSU_IOU_SLCR_MIO_PIN_41@0XFF1800A4</B>
\r
22698 <TD width=15% BGCOLOR=#C0C0C0>
\r
22701 <TD width=10% BGCOLOR=#C0C0C0>
\r
22704 <TD width=10% BGCOLOR=#C0C0C0>
\r
22707 <TD width=15% BGCOLOR=#C0C0C0>
\r
22710 <TD width=35% BGCOLOR=#C0C0C0>
\r
22711 <B>Configures MIO Pin 41 peripheral interface mapping</B>
\r
22716 <H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
\r
22717 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22718 <TR valign="top">
\r
22719 <TD width=15% BGCOLOR=#FFFF00>
\r
22720 <B>Register Name</B>
\r
22722 <TD width=15% BGCOLOR=#FFFF00>
\r
22725 <TD width=10% BGCOLOR=#FFFF00>
\r
22728 <TD width=10% BGCOLOR=#FFFF00>
\r
22731 <TD width=15% BGCOLOR=#FFFF00>
\r
22732 <B>Reset Value</B>
\r
22734 <TD width=35% BGCOLOR=#FFFF00>
\r
22735 <B>Description</B>
\r
22738 <TR valign="top">
\r
22739 <TD width=15% BGCOLOR=#FBF5EF>
\r
22740 <B>MIO_PIN_42</B>
\r
22742 <TD width=15% BGCOLOR=#FBF5EF>
\r
22743 <B>0XFF1800A8</B>
\r
22745 <TD width=10% BGCOLOR=#FBF5EF>
\r
22748 <TD width=10% BGCOLOR=#FBF5EF>
\r
22751 <TD width=15% BGCOLOR=#FBF5EF>
\r
22752 <B>0x00000000</B>
\r
22754 <TD width=35% BGCOLOR=#FBF5EF>
\r
22760 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22761 <TR valign="top">
\r
22762 <TD width=15% BGCOLOR=#C0FFC0>
\r
22763 <B>Field Name</B>
\r
22765 <TD width=15% BGCOLOR=#C0FFC0>
\r
22768 <TD width=10% BGCOLOR=#C0FFC0>
\r
22771 <TD width=10% BGCOLOR=#C0FFC0>
\r
22774 <TD width=15% BGCOLOR=#C0FFC0>
\r
22775 <B>Shifted Value</B>
\r
22777 <TD width=35% BGCOLOR=#C0FFC0>
\r
22778 <B>Description</B>
\r
22781 <TR valign="top">
\r
22782 <TD width=15% BGCOLOR=#FBF5EF>
\r
22783 <B>PSU_IOU_SLCR_MIO_PIN_42_L0_SEL</B>
\r
22785 <TD width=15% BGCOLOR=#FBF5EF>
\r
22788 <TD width=10% BGCOLOR=#FBF5EF>
\r
22791 <TD width=10% BGCOLOR=#FBF5EF>
\r
22794 <TD width=15% BGCOLOR=#FBF5EF>
\r
22797 <TD width=35% BGCOLOR=#FBF5EF>
\r
22798 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</B>
\r
22801 <TR valign="top">
\r
22802 <TD width=15% BGCOLOR=#FBF5EF>
\r
22803 <B>PSU_IOU_SLCR_MIO_PIN_42_L1_SEL</B>
\r
22805 <TD width=15% BGCOLOR=#FBF5EF>
\r
22808 <TD width=10% BGCOLOR=#FBF5EF>
\r
22811 <TD width=10% BGCOLOR=#FBF5EF>
\r
22814 <TD width=15% BGCOLOR=#FBF5EF>
\r
22817 <TD width=35% BGCOLOR=#FBF5EF>
\r
22818 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22821 <TR valign="top">
\r
22822 <TD width=15% BGCOLOR=#FBF5EF>
\r
22823 <B>PSU_IOU_SLCR_MIO_PIN_42_L2_SEL</B>
\r
22825 <TD width=15% BGCOLOR=#FBF5EF>
\r
22828 <TD width=10% BGCOLOR=#FBF5EF>
\r
22831 <TD width=10% BGCOLOR=#FBF5EF>
\r
22834 <TD width=15% BGCOLOR=#FBF5EF>
\r
22837 <TD width=35% BGCOLOR=#FBF5EF>
\r
22838 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used</B>
\r
22841 <TR valign="top">
\r
22842 <TD width=15% BGCOLOR=#FBF5EF>
\r
22843 <B>PSU_IOU_SLCR_MIO_PIN_42_L3_SEL</B>
\r
22845 <TD width=15% BGCOLOR=#FBF5EF>
\r
22848 <TD width=10% BGCOLOR=#FBF5EF>
\r
22851 <TD width=10% BGCOLOR=#FBF5EF>
\r
22854 <TD width=15% BGCOLOR=#FBF5EF>
\r
22857 <TD width=35% BGCOLOR=#FBF5EF>
\r
22858 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B>
\r
22861 <TR valign="top">
\r
22862 <TD width=15% BGCOLOR=#C0C0C0>
\r
22863 <B>PSU_IOU_SLCR_MIO_PIN_42@0XFF1800A8</B>
\r
22865 <TD width=15% BGCOLOR=#C0C0C0>
\r
22868 <TD width=10% BGCOLOR=#C0C0C0>
\r
22871 <TD width=10% BGCOLOR=#C0C0C0>
\r
22874 <TD width=15% BGCOLOR=#C0C0C0>
\r
22877 <TD width=35% BGCOLOR=#C0C0C0>
\r
22878 <B>Configures MIO Pin 42 peripheral interface mapping</B>
\r
22883 <H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
\r
22884 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22885 <TR valign="top">
\r
22886 <TD width=15% BGCOLOR=#FFFF00>
\r
22887 <B>Register Name</B>
\r
22889 <TD width=15% BGCOLOR=#FFFF00>
\r
22892 <TD width=10% BGCOLOR=#FFFF00>
\r
22895 <TD width=10% BGCOLOR=#FFFF00>
\r
22898 <TD width=15% BGCOLOR=#FFFF00>
\r
22899 <B>Reset Value</B>
\r
22901 <TD width=35% BGCOLOR=#FFFF00>
\r
22902 <B>Description</B>
\r
22905 <TR valign="top">
\r
22906 <TD width=15% BGCOLOR=#FBF5EF>
\r
22907 <B>MIO_PIN_43</B>
\r
22909 <TD width=15% BGCOLOR=#FBF5EF>
\r
22910 <B>0XFF1800AC</B>
\r
22912 <TD width=10% BGCOLOR=#FBF5EF>
\r
22915 <TD width=10% BGCOLOR=#FBF5EF>
\r
22918 <TD width=15% BGCOLOR=#FBF5EF>
\r
22919 <B>0x00000000</B>
\r
22921 <TD width=35% BGCOLOR=#FBF5EF>
\r
22927 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
22928 <TR valign="top">
\r
22929 <TD width=15% BGCOLOR=#C0FFC0>
\r
22930 <B>Field Name</B>
\r
22932 <TD width=15% BGCOLOR=#C0FFC0>
\r
22935 <TD width=10% BGCOLOR=#C0FFC0>
\r
22938 <TD width=10% BGCOLOR=#C0FFC0>
\r
22941 <TD width=15% BGCOLOR=#C0FFC0>
\r
22942 <B>Shifted Value</B>
\r
22944 <TD width=35% BGCOLOR=#C0FFC0>
\r
22945 <B>Description</B>
\r
22948 <TR valign="top">
\r
22949 <TD width=15% BGCOLOR=#FBF5EF>
\r
22950 <B>PSU_IOU_SLCR_MIO_PIN_43_L0_SEL</B>
\r
22952 <TD width=15% BGCOLOR=#FBF5EF>
\r
22955 <TD width=10% BGCOLOR=#FBF5EF>
\r
22958 <TD width=10% BGCOLOR=#FBF5EF>
\r
22961 <TD width=15% BGCOLOR=#FBF5EF>
\r
22964 <TD width=35% BGCOLOR=#FBF5EF>
\r
22965 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</B>
\r
22968 <TR valign="top">
\r
22969 <TD width=15% BGCOLOR=#FBF5EF>
\r
22970 <B>PSU_IOU_SLCR_MIO_PIN_43_L1_SEL</B>
\r
22972 <TD width=15% BGCOLOR=#FBF5EF>
\r
22975 <TD width=10% BGCOLOR=#FBF5EF>
\r
22978 <TD width=10% BGCOLOR=#FBF5EF>
\r
22981 <TD width=15% BGCOLOR=#FBF5EF>
\r
22984 <TD width=35% BGCOLOR=#FBF5EF>
\r
22985 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
22988 <TR valign="top">
\r
22989 <TD width=15% BGCOLOR=#FBF5EF>
\r
22990 <B>PSU_IOU_SLCR_MIO_PIN_43_L2_SEL</B>
\r
22992 <TD width=15% BGCOLOR=#FBF5EF>
\r
22995 <TD width=10% BGCOLOR=#FBF5EF>
\r
22998 <TD width=10% BGCOLOR=#FBF5EF>
\r
23001 <TD width=15% BGCOLOR=#FBF5EF>
\r
23004 <TD width=35% BGCOLOR=#FBF5EF>
\r
23005 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used</B>
\r
23008 <TR valign="top">
\r
23009 <TD width=15% BGCOLOR=#FBF5EF>
\r
23010 <B>PSU_IOU_SLCR_MIO_PIN_43_L3_SEL</B>
\r
23012 <TD width=15% BGCOLOR=#FBF5EF>
\r
23015 <TD width=10% BGCOLOR=#FBF5EF>
\r
23018 <TD width=10% BGCOLOR=#FBF5EF>
\r
23021 <TD width=15% BGCOLOR=#FBF5EF>
\r
23024 <TD width=35% BGCOLOR=#FBF5EF>
\r
23025 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B>
\r
23028 <TR valign="top">
\r
23029 <TD width=15% BGCOLOR=#C0C0C0>
\r
23030 <B>PSU_IOU_SLCR_MIO_PIN_43@0XFF1800AC</B>
\r
23032 <TD width=15% BGCOLOR=#C0C0C0>
\r
23035 <TD width=10% BGCOLOR=#C0C0C0>
\r
23038 <TD width=10% BGCOLOR=#C0C0C0>
\r
23041 <TD width=15% BGCOLOR=#C0C0C0>
\r
23044 <TD width=35% BGCOLOR=#C0C0C0>
\r
23045 <B>Configures MIO Pin 43 peripheral interface mapping</B>
\r
23050 <H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
\r
23051 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23052 <TR valign="top">
\r
23053 <TD width=15% BGCOLOR=#FFFF00>
\r
23054 <B>Register Name</B>
\r
23056 <TD width=15% BGCOLOR=#FFFF00>
\r
23059 <TD width=10% BGCOLOR=#FFFF00>
\r
23062 <TD width=10% BGCOLOR=#FFFF00>
\r
23065 <TD width=15% BGCOLOR=#FFFF00>
\r
23066 <B>Reset Value</B>
\r
23068 <TD width=35% BGCOLOR=#FFFF00>
\r
23069 <B>Description</B>
\r
23072 <TR valign="top">
\r
23073 <TD width=15% BGCOLOR=#FBF5EF>
\r
23074 <B>MIO_PIN_44</B>
\r
23076 <TD width=15% BGCOLOR=#FBF5EF>
\r
23077 <B>0XFF1800B0</B>
\r
23079 <TD width=10% BGCOLOR=#FBF5EF>
\r
23082 <TD width=10% BGCOLOR=#FBF5EF>
\r
23085 <TD width=15% BGCOLOR=#FBF5EF>
\r
23086 <B>0x00000000</B>
\r
23088 <TD width=35% BGCOLOR=#FBF5EF>
\r
23094 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23095 <TR valign="top">
\r
23096 <TD width=15% BGCOLOR=#C0FFC0>
\r
23097 <B>Field Name</B>
\r
23099 <TD width=15% BGCOLOR=#C0FFC0>
\r
23102 <TD width=10% BGCOLOR=#C0FFC0>
\r
23105 <TD width=10% BGCOLOR=#C0FFC0>
\r
23108 <TD width=15% BGCOLOR=#C0FFC0>
\r
23109 <B>Shifted Value</B>
\r
23111 <TD width=35% BGCOLOR=#C0FFC0>
\r
23112 <B>Description</B>
\r
23115 <TR valign="top">
\r
23116 <TD width=15% BGCOLOR=#FBF5EF>
\r
23117 <B>PSU_IOU_SLCR_MIO_PIN_44_L0_SEL</B>
\r
23119 <TD width=15% BGCOLOR=#FBF5EF>
\r
23122 <TD width=10% BGCOLOR=#FBF5EF>
\r
23125 <TD width=10% BGCOLOR=#FBF5EF>
\r
23128 <TD width=15% BGCOLOR=#FBF5EF>
\r
23131 <TD width=35% BGCOLOR=#FBF5EF>
\r
23132 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</B>
\r
23135 <TR valign="top">
\r
23136 <TD width=15% BGCOLOR=#FBF5EF>
\r
23137 <B>PSU_IOU_SLCR_MIO_PIN_44_L1_SEL</B>
\r
23139 <TD width=15% BGCOLOR=#FBF5EF>
\r
23142 <TD width=10% BGCOLOR=#FBF5EF>
\r
23145 <TD width=10% BGCOLOR=#FBF5EF>
\r
23148 <TD width=15% BGCOLOR=#FBF5EF>
\r
23151 <TD width=35% BGCOLOR=#FBF5EF>
\r
23152 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23155 <TR valign="top">
\r
23156 <TD width=15% BGCOLOR=#FBF5EF>
\r
23157 <B>PSU_IOU_SLCR_MIO_PIN_44_L2_SEL</B>
\r
23159 <TD width=15% BGCOLOR=#FBF5EF>
\r
23162 <TD width=10% BGCOLOR=#FBF5EF>
\r
23165 <TD width=10% BGCOLOR=#FBF5EF>
\r
23168 <TD width=15% BGCOLOR=#FBF5EF>
\r
23171 <TD width=35% BGCOLOR=#FBF5EF>
\r
23172 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used</B>
\r
23175 <TR valign="top">
\r
23176 <TD width=15% BGCOLOR=#FBF5EF>
\r
23177 <B>PSU_IOU_SLCR_MIO_PIN_44_L3_SEL</B>
\r
23179 <TD width=15% BGCOLOR=#FBF5EF>
\r
23182 <TD width=10% BGCOLOR=#FBF5EF>
\r
23185 <TD width=10% BGCOLOR=#FBF5EF>
\r
23188 <TD width=15% BGCOLOR=#FBF5EF>
\r
23191 <TD width=35% BGCOLOR=#FBF5EF>
\r
23192 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B>
\r
23195 <TR valign="top">
\r
23196 <TD width=15% BGCOLOR=#C0C0C0>
\r
23197 <B>PSU_IOU_SLCR_MIO_PIN_44@0XFF1800B0</B>
\r
23199 <TD width=15% BGCOLOR=#C0C0C0>
\r
23202 <TD width=10% BGCOLOR=#C0C0C0>
\r
23205 <TD width=10% BGCOLOR=#C0C0C0>
\r
23208 <TD width=15% BGCOLOR=#C0C0C0>
\r
23211 <TD width=35% BGCOLOR=#C0C0C0>
\r
23212 <B>Configures MIO Pin 44 peripheral interface mapping</B>
\r
23217 <H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
\r
23218 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23219 <TR valign="top">
\r
23220 <TD width=15% BGCOLOR=#FFFF00>
\r
23221 <B>Register Name</B>
\r
23223 <TD width=15% BGCOLOR=#FFFF00>
\r
23226 <TD width=10% BGCOLOR=#FFFF00>
\r
23229 <TD width=10% BGCOLOR=#FFFF00>
\r
23232 <TD width=15% BGCOLOR=#FFFF00>
\r
23233 <B>Reset Value</B>
\r
23235 <TD width=35% BGCOLOR=#FFFF00>
\r
23236 <B>Description</B>
\r
23239 <TR valign="top">
\r
23240 <TD width=15% BGCOLOR=#FBF5EF>
\r
23241 <B>MIO_PIN_45</B>
\r
23243 <TD width=15% BGCOLOR=#FBF5EF>
\r
23244 <B>0XFF1800B4</B>
\r
23246 <TD width=10% BGCOLOR=#FBF5EF>
\r
23249 <TD width=10% BGCOLOR=#FBF5EF>
\r
23252 <TD width=15% BGCOLOR=#FBF5EF>
\r
23253 <B>0x00000000</B>
\r
23255 <TD width=35% BGCOLOR=#FBF5EF>
\r
23261 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23262 <TR valign="top">
\r
23263 <TD width=15% BGCOLOR=#C0FFC0>
\r
23264 <B>Field Name</B>
\r
23266 <TD width=15% BGCOLOR=#C0FFC0>
\r
23269 <TD width=10% BGCOLOR=#C0FFC0>
\r
23272 <TD width=10% BGCOLOR=#C0FFC0>
\r
23275 <TD width=15% BGCOLOR=#C0FFC0>
\r
23276 <B>Shifted Value</B>
\r
23278 <TD width=35% BGCOLOR=#C0FFC0>
\r
23279 <B>Description</B>
\r
23282 <TR valign="top">
\r
23283 <TD width=15% BGCOLOR=#FBF5EF>
\r
23284 <B>PSU_IOU_SLCR_MIO_PIN_45_L0_SEL</B>
\r
23286 <TD width=15% BGCOLOR=#FBF5EF>
\r
23289 <TD width=10% BGCOLOR=#FBF5EF>
\r
23292 <TD width=10% BGCOLOR=#FBF5EF>
\r
23295 <TD width=15% BGCOLOR=#FBF5EF>
\r
23298 <TD width=35% BGCOLOR=#FBF5EF>
\r
23299 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</B>
\r
23302 <TR valign="top">
\r
23303 <TD width=15% BGCOLOR=#FBF5EF>
\r
23304 <B>PSU_IOU_SLCR_MIO_PIN_45_L1_SEL</B>
\r
23306 <TD width=15% BGCOLOR=#FBF5EF>
\r
23309 <TD width=10% BGCOLOR=#FBF5EF>
\r
23312 <TD width=10% BGCOLOR=#FBF5EF>
\r
23315 <TD width=15% BGCOLOR=#FBF5EF>
\r
23318 <TD width=35% BGCOLOR=#FBF5EF>
\r
23319 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23322 <TR valign="top">
\r
23323 <TD width=15% BGCOLOR=#FBF5EF>
\r
23324 <B>PSU_IOU_SLCR_MIO_PIN_45_L2_SEL</B>
\r
23326 <TD width=15% BGCOLOR=#FBF5EF>
\r
23329 <TD width=10% BGCOLOR=#FBF5EF>
\r
23332 <TD width=10% BGCOLOR=#FBF5EF>
\r
23335 <TD width=15% BGCOLOR=#FBF5EF>
\r
23338 <TD width=35% BGCOLOR=#FBF5EF>
\r
23339 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used</B>
\r
23342 <TR valign="top">
\r
23343 <TD width=15% BGCOLOR=#FBF5EF>
\r
23344 <B>PSU_IOU_SLCR_MIO_PIN_45_L3_SEL</B>
\r
23346 <TD width=15% BGCOLOR=#FBF5EF>
\r
23349 <TD width=10% BGCOLOR=#FBF5EF>
\r
23352 <TD width=10% BGCOLOR=#FBF5EF>
\r
23355 <TD width=15% BGCOLOR=#FBF5EF>
\r
23358 <TD width=35% BGCOLOR=#FBF5EF>
\r
23359 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B>
\r
23362 <TR valign="top">
\r
23363 <TD width=15% BGCOLOR=#C0C0C0>
\r
23364 <B>PSU_IOU_SLCR_MIO_PIN_45@0XFF1800B4</B>
\r
23366 <TD width=15% BGCOLOR=#C0C0C0>
\r
23369 <TD width=10% BGCOLOR=#C0C0C0>
\r
23372 <TD width=10% BGCOLOR=#C0C0C0>
\r
23375 <TD width=15% BGCOLOR=#C0C0C0>
\r
23378 <TD width=35% BGCOLOR=#C0C0C0>
\r
23379 <B>Configures MIO Pin 45 peripheral interface mapping</B>
\r
23384 <H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
\r
23385 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23386 <TR valign="top">
\r
23387 <TD width=15% BGCOLOR=#FFFF00>
\r
23388 <B>Register Name</B>
\r
23390 <TD width=15% BGCOLOR=#FFFF00>
\r
23393 <TD width=10% BGCOLOR=#FFFF00>
\r
23396 <TD width=10% BGCOLOR=#FFFF00>
\r
23399 <TD width=15% BGCOLOR=#FFFF00>
\r
23400 <B>Reset Value</B>
\r
23402 <TD width=35% BGCOLOR=#FFFF00>
\r
23403 <B>Description</B>
\r
23406 <TR valign="top">
\r
23407 <TD width=15% BGCOLOR=#FBF5EF>
\r
23408 <B>MIO_PIN_46</B>
\r
23410 <TD width=15% BGCOLOR=#FBF5EF>
\r
23411 <B>0XFF1800B8</B>
\r
23413 <TD width=10% BGCOLOR=#FBF5EF>
\r
23416 <TD width=10% BGCOLOR=#FBF5EF>
\r
23419 <TD width=15% BGCOLOR=#FBF5EF>
\r
23420 <B>0x00000000</B>
\r
23422 <TD width=35% BGCOLOR=#FBF5EF>
\r
23428 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23429 <TR valign="top">
\r
23430 <TD width=15% BGCOLOR=#C0FFC0>
\r
23431 <B>Field Name</B>
\r
23433 <TD width=15% BGCOLOR=#C0FFC0>
\r
23436 <TD width=10% BGCOLOR=#C0FFC0>
\r
23439 <TD width=10% BGCOLOR=#C0FFC0>
\r
23442 <TD width=15% BGCOLOR=#C0FFC0>
\r
23443 <B>Shifted Value</B>
\r
23445 <TD width=35% BGCOLOR=#C0FFC0>
\r
23446 <B>Description</B>
\r
23449 <TR valign="top">
\r
23450 <TD width=15% BGCOLOR=#FBF5EF>
\r
23451 <B>PSU_IOU_SLCR_MIO_PIN_46_L0_SEL</B>
\r
23453 <TD width=15% BGCOLOR=#FBF5EF>
\r
23456 <TD width=10% BGCOLOR=#FBF5EF>
\r
23459 <TD width=10% BGCOLOR=#FBF5EF>
\r
23462 <TD width=15% BGCOLOR=#FBF5EF>
\r
23465 <TD width=35% BGCOLOR=#FBF5EF>
\r
23466 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</B>
\r
23469 <TR valign="top">
\r
23470 <TD width=15% BGCOLOR=#FBF5EF>
\r
23471 <B>PSU_IOU_SLCR_MIO_PIN_46_L1_SEL</B>
\r
23473 <TD width=15% BGCOLOR=#FBF5EF>
\r
23476 <TD width=10% BGCOLOR=#FBF5EF>
\r
23479 <TD width=10% BGCOLOR=#FBF5EF>
\r
23482 <TD width=15% BGCOLOR=#FBF5EF>
\r
23485 <TD width=35% BGCOLOR=#FBF5EF>
\r
23486 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23489 <TR valign="top">
\r
23490 <TD width=15% BGCOLOR=#FBF5EF>
\r
23491 <B>PSU_IOU_SLCR_MIO_PIN_46_L2_SEL</B>
\r
23493 <TD width=15% BGCOLOR=#FBF5EF>
\r
23496 <TD width=10% BGCOLOR=#FBF5EF>
\r
23499 <TD width=10% BGCOLOR=#FBF5EF>
\r
23502 <TD width=15% BGCOLOR=#FBF5EF>
\r
23505 <TD width=35% BGCOLOR=#FBF5EF>
\r
23506 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used</B>
\r
23509 <TR valign="top">
\r
23510 <TD width=15% BGCOLOR=#FBF5EF>
\r
23511 <B>PSU_IOU_SLCR_MIO_PIN_46_L3_SEL</B>
\r
23513 <TD width=15% BGCOLOR=#FBF5EF>
\r
23516 <TD width=10% BGCOLOR=#FBF5EF>
\r
23519 <TD width=10% BGCOLOR=#FBF5EF>
\r
23522 <TD width=15% BGCOLOR=#FBF5EF>
\r
23525 <TD width=35% BGCOLOR=#FBF5EF>
\r
23526 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
23529 <TR valign="top">
\r
23530 <TD width=15% BGCOLOR=#C0C0C0>
\r
23531 <B>PSU_IOU_SLCR_MIO_PIN_46@0XFF1800B8</B>
\r
23533 <TD width=15% BGCOLOR=#C0C0C0>
\r
23536 <TD width=10% BGCOLOR=#C0C0C0>
\r
23539 <TD width=10% BGCOLOR=#C0C0C0>
\r
23542 <TD width=15% BGCOLOR=#C0C0C0>
\r
23545 <TD width=35% BGCOLOR=#C0C0C0>
\r
23546 <B>Configures MIO Pin 46 peripheral interface mapping</B>
\r
23551 <H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
\r
23552 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23553 <TR valign="top">
\r
23554 <TD width=15% BGCOLOR=#FFFF00>
\r
23555 <B>Register Name</B>
\r
23557 <TD width=15% BGCOLOR=#FFFF00>
\r
23560 <TD width=10% BGCOLOR=#FFFF00>
\r
23563 <TD width=10% BGCOLOR=#FFFF00>
\r
23566 <TD width=15% BGCOLOR=#FFFF00>
\r
23567 <B>Reset Value</B>
\r
23569 <TD width=35% BGCOLOR=#FFFF00>
\r
23570 <B>Description</B>
\r
23573 <TR valign="top">
\r
23574 <TD width=15% BGCOLOR=#FBF5EF>
\r
23575 <B>MIO_PIN_47</B>
\r
23577 <TD width=15% BGCOLOR=#FBF5EF>
\r
23578 <B>0XFF1800BC</B>
\r
23580 <TD width=10% BGCOLOR=#FBF5EF>
\r
23583 <TD width=10% BGCOLOR=#FBF5EF>
\r
23586 <TD width=15% BGCOLOR=#FBF5EF>
\r
23587 <B>0x00000000</B>
\r
23589 <TD width=35% BGCOLOR=#FBF5EF>
\r
23595 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23596 <TR valign="top">
\r
23597 <TD width=15% BGCOLOR=#C0FFC0>
\r
23598 <B>Field Name</B>
\r
23600 <TD width=15% BGCOLOR=#C0FFC0>
\r
23603 <TD width=10% BGCOLOR=#C0FFC0>
\r
23606 <TD width=10% BGCOLOR=#C0FFC0>
\r
23609 <TD width=15% BGCOLOR=#C0FFC0>
\r
23610 <B>Shifted Value</B>
\r
23612 <TD width=35% BGCOLOR=#C0FFC0>
\r
23613 <B>Description</B>
\r
23616 <TR valign="top">
\r
23617 <TD width=15% BGCOLOR=#FBF5EF>
\r
23618 <B>PSU_IOU_SLCR_MIO_PIN_47_L0_SEL</B>
\r
23620 <TD width=15% BGCOLOR=#FBF5EF>
\r
23623 <TD width=10% BGCOLOR=#FBF5EF>
\r
23626 <TD width=10% BGCOLOR=#FBF5EF>
\r
23629 <TD width=15% BGCOLOR=#FBF5EF>
\r
23632 <TD width=35% BGCOLOR=#FBF5EF>
\r
23633 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</B>
\r
23636 <TR valign="top">
\r
23637 <TD width=15% BGCOLOR=#FBF5EF>
\r
23638 <B>PSU_IOU_SLCR_MIO_PIN_47_L1_SEL</B>
\r
23640 <TD width=15% BGCOLOR=#FBF5EF>
\r
23643 <TD width=10% BGCOLOR=#FBF5EF>
\r
23646 <TD width=10% BGCOLOR=#FBF5EF>
\r
23649 <TD width=15% BGCOLOR=#FBF5EF>
\r
23652 <TD width=35% BGCOLOR=#FBF5EF>
\r
23653 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23656 <TR valign="top">
\r
23657 <TD width=15% BGCOLOR=#FBF5EF>
\r
23658 <B>PSU_IOU_SLCR_MIO_PIN_47_L2_SEL</B>
\r
23660 <TD width=15% BGCOLOR=#FBF5EF>
\r
23663 <TD width=10% BGCOLOR=#FBF5EF>
\r
23666 <TD width=10% BGCOLOR=#FBF5EF>
\r
23669 <TD width=15% BGCOLOR=#FBF5EF>
\r
23672 <TD width=35% BGCOLOR=#FBF5EF>
\r
23673 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used</B>
\r
23676 <TR valign="top">
\r
23677 <TD width=15% BGCOLOR=#FBF5EF>
\r
23678 <B>PSU_IOU_SLCR_MIO_PIN_47_L3_SEL</B>
\r
23680 <TD width=15% BGCOLOR=#FBF5EF>
\r
23683 <TD width=10% BGCOLOR=#FBF5EF>
\r
23686 <TD width=10% BGCOLOR=#FBF5EF>
\r
23689 <TD width=15% BGCOLOR=#FBF5EF>
\r
23692 <TD width=35% BGCOLOR=#FBF5EF>
\r
23693 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
23696 <TR valign="top">
\r
23697 <TD width=15% BGCOLOR=#C0C0C0>
\r
23698 <B>PSU_IOU_SLCR_MIO_PIN_47@0XFF1800BC</B>
\r
23700 <TD width=15% BGCOLOR=#C0C0C0>
\r
23703 <TD width=10% BGCOLOR=#C0C0C0>
\r
23706 <TD width=10% BGCOLOR=#C0C0C0>
\r
23709 <TD width=15% BGCOLOR=#C0C0C0>
\r
23712 <TD width=35% BGCOLOR=#C0C0C0>
\r
23713 <B>Configures MIO Pin 47 peripheral interface mapping</B>
\r
23718 <H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
\r
23719 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23720 <TR valign="top">
\r
23721 <TD width=15% BGCOLOR=#FFFF00>
\r
23722 <B>Register Name</B>
\r
23724 <TD width=15% BGCOLOR=#FFFF00>
\r
23727 <TD width=10% BGCOLOR=#FFFF00>
\r
23730 <TD width=10% BGCOLOR=#FFFF00>
\r
23733 <TD width=15% BGCOLOR=#FFFF00>
\r
23734 <B>Reset Value</B>
\r
23736 <TD width=35% BGCOLOR=#FFFF00>
\r
23737 <B>Description</B>
\r
23740 <TR valign="top">
\r
23741 <TD width=15% BGCOLOR=#FBF5EF>
\r
23742 <B>MIO_PIN_48</B>
\r
23744 <TD width=15% BGCOLOR=#FBF5EF>
\r
23745 <B>0XFF1800C0</B>
\r
23747 <TD width=10% BGCOLOR=#FBF5EF>
\r
23750 <TD width=10% BGCOLOR=#FBF5EF>
\r
23753 <TD width=15% BGCOLOR=#FBF5EF>
\r
23754 <B>0x00000000</B>
\r
23756 <TD width=35% BGCOLOR=#FBF5EF>
\r
23762 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23763 <TR valign="top">
\r
23764 <TD width=15% BGCOLOR=#C0FFC0>
\r
23765 <B>Field Name</B>
\r
23767 <TD width=15% BGCOLOR=#C0FFC0>
\r
23770 <TD width=10% BGCOLOR=#C0FFC0>
\r
23773 <TD width=10% BGCOLOR=#C0FFC0>
\r
23776 <TD width=15% BGCOLOR=#C0FFC0>
\r
23777 <B>Shifted Value</B>
\r
23779 <TD width=35% BGCOLOR=#C0FFC0>
\r
23780 <B>Description</B>
\r
23783 <TR valign="top">
\r
23784 <TD width=15% BGCOLOR=#FBF5EF>
\r
23785 <B>PSU_IOU_SLCR_MIO_PIN_48_L0_SEL</B>
\r
23787 <TD width=15% BGCOLOR=#FBF5EF>
\r
23790 <TD width=10% BGCOLOR=#FBF5EF>
\r
23793 <TD width=10% BGCOLOR=#FBF5EF>
\r
23796 <TD width=15% BGCOLOR=#FBF5EF>
\r
23799 <TD width=35% BGCOLOR=#FBF5EF>
\r
23800 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</B>
\r
23803 <TR valign="top">
\r
23804 <TD width=15% BGCOLOR=#FBF5EF>
\r
23805 <B>PSU_IOU_SLCR_MIO_PIN_48_L1_SEL</B>
\r
23807 <TD width=15% BGCOLOR=#FBF5EF>
\r
23810 <TD width=10% BGCOLOR=#FBF5EF>
\r
23813 <TD width=10% BGCOLOR=#FBF5EF>
\r
23816 <TD width=15% BGCOLOR=#FBF5EF>
\r
23819 <TD width=35% BGCOLOR=#FBF5EF>
\r
23820 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23823 <TR valign="top">
\r
23824 <TD width=15% BGCOLOR=#FBF5EF>
\r
23825 <B>PSU_IOU_SLCR_MIO_PIN_48_L2_SEL</B>
\r
23827 <TD width=15% BGCOLOR=#FBF5EF>
\r
23830 <TD width=10% BGCOLOR=#FBF5EF>
\r
23833 <TD width=10% BGCOLOR=#FBF5EF>
\r
23836 <TD width=15% BGCOLOR=#FBF5EF>
\r
23839 <TD width=35% BGCOLOR=#FBF5EF>
\r
23840 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used</B>
\r
23843 <TR valign="top">
\r
23844 <TD width=15% BGCOLOR=#FBF5EF>
\r
23845 <B>PSU_IOU_SLCR_MIO_PIN_48_L3_SEL</B>
\r
23847 <TD width=15% BGCOLOR=#FBF5EF>
\r
23850 <TD width=10% BGCOLOR=#FBF5EF>
\r
23853 <TD width=10% BGCOLOR=#FBF5EF>
\r
23856 <TD width=15% BGCOLOR=#FBF5EF>
\r
23859 <TD width=35% BGCOLOR=#FBF5EF>
\r
23860 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B>
\r
23863 <TR valign="top">
\r
23864 <TD width=15% BGCOLOR=#C0C0C0>
\r
23865 <B>PSU_IOU_SLCR_MIO_PIN_48@0XFF1800C0</B>
\r
23867 <TD width=15% BGCOLOR=#C0C0C0>
\r
23870 <TD width=10% BGCOLOR=#C0C0C0>
\r
23873 <TD width=10% BGCOLOR=#C0C0C0>
\r
23876 <TD width=15% BGCOLOR=#C0C0C0>
\r
23879 <TD width=35% BGCOLOR=#C0C0C0>
\r
23880 <B>Configures MIO Pin 48 peripheral interface mapping</B>
\r
23885 <H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
\r
23886 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23887 <TR valign="top">
\r
23888 <TD width=15% BGCOLOR=#FFFF00>
\r
23889 <B>Register Name</B>
\r
23891 <TD width=15% BGCOLOR=#FFFF00>
\r
23894 <TD width=10% BGCOLOR=#FFFF00>
\r
23897 <TD width=10% BGCOLOR=#FFFF00>
\r
23900 <TD width=15% BGCOLOR=#FFFF00>
\r
23901 <B>Reset Value</B>
\r
23903 <TD width=35% BGCOLOR=#FFFF00>
\r
23904 <B>Description</B>
\r
23907 <TR valign="top">
\r
23908 <TD width=15% BGCOLOR=#FBF5EF>
\r
23909 <B>MIO_PIN_49</B>
\r
23911 <TD width=15% BGCOLOR=#FBF5EF>
\r
23912 <B>0XFF1800C4</B>
\r
23914 <TD width=10% BGCOLOR=#FBF5EF>
\r
23917 <TD width=10% BGCOLOR=#FBF5EF>
\r
23920 <TD width=15% BGCOLOR=#FBF5EF>
\r
23921 <B>0x00000000</B>
\r
23923 <TD width=35% BGCOLOR=#FBF5EF>
\r
23929 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
23930 <TR valign="top">
\r
23931 <TD width=15% BGCOLOR=#C0FFC0>
\r
23932 <B>Field Name</B>
\r
23934 <TD width=15% BGCOLOR=#C0FFC0>
\r
23937 <TD width=10% BGCOLOR=#C0FFC0>
\r
23940 <TD width=10% BGCOLOR=#C0FFC0>
\r
23943 <TD width=15% BGCOLOR=#C0FFC0>
\r
23944 <B>Shifted Value</B>
\r
23946 <TD width=35% BGCOLOR=#C0FFC0>
\r
23947 <B>Description</B>
\r
23950 <TR valign="top">
\r
23951 <TD width=15% BGCOLOR=#FBF5EF>
\r
23952 <B>PSU_IOU_SLCR_MIO_PIN_49_L0_SEL</B>
\r
23954 <TD width=15% BGCOLOR=#FBF5EF>
\r
23957 <TD width=10% BGCOLOR=#FBF5EF>
\r
23960 <TD width=10% BGCOLOR=#FBF5EF>
\r
23963 <TD width=15% BGCOLOR=#FBF5EF>
\r
23966 <TD width=35% BGCOLOR=#FBF5EF>
\r
23967 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</B>
\r
23970 <TR valign="top">
\r
23971 <TD width=15% BGCOLOR=#FBF5EF>
\r
23972 <B>PSU_IOU_SLCR_MIO_PIN_49_L1_SEL</B>
\r
23974 <TD width=15% BGCOLOR=#FBF5EF>
\r
23977 <TD width=10% BGCOLOR=#FBF5EF>
\r
23980 <TD width=10% BGCOLOR=#FBF5EF>
\r
23983 <TD width=15% BGCOLOR=#FBF5EF>
\r
23986 <TD width=35% BGCOLOR=#FBF5EF>
\r
23987 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
23990 <TR valign="top">
\r
23991 <TD width=15% BGCOLOR=#FBF5EF>
\r
23992 <B>PSU_IOU_SLCR_MIO_PIN_49_L2_SEL</B>
\r
23994 <TD width=15% BGCOLOR=#FBF5EF>
\r
23997 <TD width=10% BGCOLOR=#FBF5EF>
\r
24000 <TD width=10% BGCOLOR=#FBF5EF>
\r
24003 <TD width=15% BGCOLOR=#FBF5EF>
\r
24006 <TD width=35% BGCOLOR=#FBF5EF>
\r
24007 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used</B>
\r
24010 <TR valign="top">
\r
24011 <TD width=15% BGCOLOR=#FBF5EF>
\r
24012 <B>PSU_IOU_SLCR_MIO_PIN_49_L3_SEL</B>
\r
24014 <TD width=15% BGCOLOR=#FBF5EF>
\r
24017 <TD width=10% BGCOLOR=#FBF5EF>
\r
24020 <TD width=10% BGCOLOR=#FBF5EF>
\r
24023 <TD width=15% BGCOLOR=#FBF5EF>
\r
24026 <TD width=35% BGCOLOR=#FBF5EF>
\r
24027 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B>
\r
24030 <TR valign="top">
\r
24031 <TD width=15% BGCOLOR=#C0C0C0>
\r
24032 <B>PSU_IOU_SLCR_MIO_PIN_49@0XFF1800C4</B>
\r
24034 <TD width=15% BGCOLOR=#C0C0C0>
\r
24037 <TD width=10% BGCOLOR=#C0C0C0>
\r
24040 <TD width=10% BGCOLOR=#C0C0C0>
\r
24043 <TD width=15% BGCOLOR=#C0C0C0>
\r
24046 <TD width=35% BGCOLOR=#C0C0C0>
\r
24047 <B>Configures MIO Pin 49 peripheral interface mapping</B>
\r
24052 <H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
\r
24053 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24054 <TR valign="top">
\r
24055 <TD width=15% BGCOLOR=#FFFF00>
\r
24056 <B>Register Name</B>
\r
24058 <TD width=15% BGCOLOR=#FFFF00>
\r
24061 <TD width=10% BGCOLOR=#FFFF00>
\r
24064 <TD width=10% BGCOLOR=#FFFF00>
\r
24067 <TD width=15% BGCOLOR=#FFFF00>
\r
24068 <B>Reset Value</B>
\r
24070 <TD width=35% BGCOLOR=#FFFF00>
\r
24071 <B>Description</B>
\r
24074 <TR valign="top">
\r
24075 <TD width=15% BGCOLOR=#FBF5EF>
\r
24076 <B>MIO_PIN_50</B>
\r
24078 <TD width=15% BGCOLOR=#FBF5EF>
\r
24079 <B>0XFF1800C8</B>
\r
24081 <TD width=10% BGCOLOR=#FBF5EF>
\r
24084 <TD width=10% BGCOLOR=#FBF5EF>
\r
24087 <TD width=15% BGCOLOR=#FBF5EF>
\r
24088 <B>0x00000000</B>
\r
24090 <TD width=35% BGCOLOR=#FBF5EF>
\r
24096 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24097 <TR valign="top">
\r
24098 <TD width=15% BGCOLOR=#C0FFC0>
\r
24099 <B>Field Name</B>
\r
24101 <TD width=15% BGCOLOR=#C0FFC0>
\r
24104 <TD width=10% BGCOLOR=#C0FFC0>
\r
24107 <TD width=10% BGCOLOR=#C0FFC0>
\r
24110 <TD width=15% BGCOLOR=#C0FFC0>
\r
24111 <B>Shifted Value</B>
\r
24113 <TD width=35% BGCOLOR=#C0FFC0>
\r
24114 <B>Description</B>
\r
24117 <TR valign="top">
\r
24118 <TD width=15% BGCOLOR=#FBF5EF>
\r
24119 <B>PSU_IOU_SLCR_MIO_PIN_50_L0_SEL</B>
\r
24121 <TD width=15% BGCOLOR=#FBF5EF>
\r
24124 <TD width=10% BGCOLOR=#FBF5EF>
\r
24127 <TD width=10% BGCOLOR=#FBF5EF>
\r
24130 <TD width=15% BGCOLOR=#FBF5EF>
\r
24133 <TD width=35% BGCOLOR=#FBF5EF>
\r
24134 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)</B>
\r
24137 <TR valign="top">
\r
24138 <TD width=15% BGCOLOR=#FBF5EF>
\r
24139 <B>PSU_IOU_SLCR_MIO_PIN_50_L1_SEL</B>
\r
24141 <TD width=15% BGCOLOR=#FBF5EF>
\r
24144 <TD width=10% BGCOLOR=#FBF5EF>
\r
24147 <TD width=10% BGCOLOR=#FBF5EF>
\r
24150 <TD width=15% BGCOLOR=#FBF5EF>
\r
24153 <TD width=35% BGCOLOR=#FBF5EF>
\r
24154 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
24157 <TR valign="top">
\r
24158 <TD width=15% BGCOLOR=#FBF5EF>
\r
24159 <B>PSU_IOU_SLCR_MIO_PIN_50_L2_SEL</B>
\r
24161 <TD width=15% BGCOLOR=#FBF5EF>
\r
24164 <TD width=10% BGCOLOR=#FBF5EF>
\r
24167 <TD width=10% BGCOLOR=#FBF5EF>
\r
24170 <TD width=15% BGCOLOR=#FBF5EF>
\r
24173 <TD width=35% BGCOLOR=#FBF5EF>
\r
24174 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used</B>
\r
24177 <TR valign="top">
\r
24178 <TD width=15% BGCOLOR=#FBF5EF>
\r
24179 <B>PSU_IOU_SLCR_MIO_PIN_50_L3_SEL</B>
\r
24181 <TD width=15% BGCOLOR=#FBF5EF>
\r
24184 <TD width=10% BGCOLOR=#FBF5EF>
\r
24187 <TD width=10% BGCOLOR=#FBF5EF>
\r
24190 <TD width=15% BGCOLOR=#FBF5EF>
\r
24193 <TD width=35% BGCOLOR=#FBF5EF>
\r
24194 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
24197 <TR valign="top">
\r
24198 <TD width=15% BGCOLOR=#C0C0C0>
\r
24199 <B>PSU_IOU_SLCR_MIO_PIN_50@0XFF1800C8</B>
\r
24201 <TD width=15% BGCOLOR=#C0C0C0>
\r
24204 <TD width=10% BGCOLOR=#C0C0C0>
\r
24207 <TD width=10% BGCOLOR=#C0C0C0>
\r
24210 <TD width=15% BGCOLOR=#C0C0C0>
\r
24213 <TD width=35% BGCOLOR=#C0C0C0>
\r
24214 <B>Configures MIO Pin 50 peripheral interface mapping</B>
\r
24219 <H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
\r
24220 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24221 <TR valign="top">
\r
24222 <TD width=15% BGCOLOR=#FFFF00>
\r
24223 <B>Register Name</B>
\r
24225 <TD width=15% BGCOLOR=#FFFF00>
\r
24228 <TD width=10% BGCOLOR=#FFFF00>
\r
24231 <TD width=10% BGCOLOR=#FFFF00>
\r
24234 <TD width=15% BGCOLOR=#FFFF00>
\r
24235 <B>Reset Value</B>
\r
24237 <TD width=35% BGCOLOR=#FFFF00>
\r
24238 <B>Description</B>
\r
24241 <TR valign="top">
\r
24242 <TD width=15% BGCOLOR=#FBF5EF>
\r
24243 <B>MIO_PIN_51</B>
\r
24245 <TD width=15% BGCOLOR=#FBF5EF>
\r
24246 <B>0XFF1800CC</B>
\r
24248 <TD width=10% BGCOLOR=#FBF5EF>
\r
24251 <TD width=10% BGCOLOR=#FBF5EF>
\r
24254 <TD width=15% BGCOLOR=#FBF5EF>
\r
24255 <B>0x00000000</B>
\r
24257 <TD width=35% BGCOLOR=#FBF5EF>
\r
24263 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24264 <TR valign="top">
\r
24265 <TD width=15% BGCOLOR=#C0FFC0>
\r
24266 <B>Field Name</B>
\r
24268 <TD width=15% BGCOLOR=#C0FFC0>
\r
24271 <TD width=10% BGCOLOR=#C0FFC0>
\r
24274 <TD width=10% BGCOLOR=#C0FFC0>
\r
24277 <TD width=15% BGCOLOR=#C0FFC0>
\r
24278 <B>Shifted Value</B>
\r
24280 <TD width=35% BGCOLOR=#C0FFC0>
\r
24281 <B>Description</B>
\r
24284 <TR valign="top">
\r
24285 <TD width=15% BGCOLOR=#FBF5EF>
\r
24286 <B>PSU_IOU_SLCR_MIO_PIN_51_L0_SEL</B>
\r
24288 <TD width=15% BGCOLOR=#FBF5EF>
\r
24291 <TD width=10% BGCOLOR=#FBF5EF>
\r
24294 <TD width=10% BGCOLOR=#FBF5EF>
\r
24297 <TD width=15% BGCOLOR=#FBF5EF>
\r
24300 <TD width=35% BGCOLOR=#FBF5EF>
\r
24301 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)</B>
\r
24304 <TR valign="top">
\r
24305 <TD width=15% BGCOLOR=#FBF5EF>
\r
24306 <B>PSU_IOU_SLCR_MIO_PIN_51_L1_SEL</B>
\r
24308 <TD width=15% BGCOLOR=#FBF5EF>
\r
24311 <TD width=10% BGCOLOR=#FBF5EF>
\r
24314 <TD width=10% BGCOLOR=#FBF5EF>
\r
24317 <TD width=15% BGCOLOR=#FBF5EF>
\r
24320 <TD width=35% BGCOLOR=#FBF5EF>
\r
24321 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
24324 <TR valign="top">
\r
24325 <TD width=15% BGCOLOR=#FBF5EF>
\r
24326 <B>PSU_IOU_SLCR_MIO_PIN_51_L2_SEL</B>
\r
24328 <TD width=15% BGCOLOR=#FBF5EF>
\r
24331 <TD width=10% BGCOLOR=#FBF5EF>
\r
24334 <TD width=10% BGCOLOR=#FBF5EF>
\r
24337 <TD width=15% BGCOLOR=#FBF5EF>
\r
24340 <TD width=35% BGCOLOR=#FBF5EF>
\r
24341 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used</B>
\r
24344 <TR valign="top">
\r
24345 <TD width=15% BGCOLOR=#FBF5EF>
\r
24346 <B>PSU_IOU_SLCR_MIO_PIN_51_L3_SEL</B>
\r
24348 <TD width=15% BGCOLOR=#FBF5EF>
\r
24351 <TD width=10% BGCOLOR=#FBF5EF>
\r
24354 <TD width=10% BGCOLOR=#FBF5EF>
\r
24357 <TD width=15% BGCOLOR=#FBF5EF>
\r
24360 <TD width=35% BGCOLOR=#FBF5EF>
\r
24361 <B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
24364 <TR valign="top">
\r
24365 <TD width=15% BGCOLOR=#C0C0C0>
\r
24366 <B>PSU_IOU_SLCR_MIO_PIN_51@0XFF1800CC</B>
\r
24368 <TD width=15% BGCOLOR=#C0C0C0>
\r
24371 <TD width=10% BGCOLOR=#C0C0C0>
\r
24374 <TD width=10% BGCOLOR=#C0C0C0>
\r
24377 <TD width=15% BGCOLOR=#C0C0C0>
\r
24380 <TD width=35% BGCOLOR=#C0C0C0>
\r
24381 <B>Configures MIO Pin 51 peripheral interface mapping</B>
\r
24386 <H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
\r
24387 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24388 <TR valign="top">
\r
24389 <TD width=15% BGCOLOR=#FFFF00>
\r
24390 <B>Register Name</B>
\r
24392 <TD width=15% BGCOLOR=#FFFF00>
\r
24395 <TD width=10% BGCOLOR=#FFFF00>
\r
24398 <TD width=10% BGCOLOR=#FFFF00>
\r
24401 <TD width=15% BGCOLOR=#FFFF00>
\r
24402 <B>Reset Value</B>
\r
24404 <TD width=35% BGCOLOR=#FFFF00>
\r
24405 <B>Description</B>
\r
24408 <TR valign="top">
\r
24409 <TD width=15% BGCOLOR=#FBF5EF>
\r
24410 <B>MIO_PIN_52</B>
\r
24412 <TD width=15% BGCOLOR=#FBF5EF>
\r
24413 <B>0XFF1800D0</B>
\r
24415 <TD width=10% BGCOLOR=#FBF5EF>
\r
24418 <TD width=10% BGCOLOR=#FBF5EF>
\r
24421 <TD width=15% BGCOLOR=#FBF5EF>
\r
24422 <B>0x00000000</B>
\r
24424 <TD width=35% BGCOLOR=#FBF5EF>
\r
24430 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24431 <TR valign="top">
\r
24432 <TD width=15% BGCOLOR=#C0FFC0>
\r
24433 <B>Field Name</B>
\r
24435 <TD width=15% BGCOLOR=#C0FFC0>
\r
24438 <TD width=10% BGCOLOR=#C0FFC0>
\r
24441 <TD width=10% BGCOLOR=#C0FFC0>
\r
24444 <TD width=15% BGCOLOR=#C0FFC0>
\r
24445 <B>Shifted Value</B>
\r
24447 <TD width=35% BGCOLOR=#C0FFC0>
\r
24448 <B>Description</B>
\r
24451 <TR valign="top">
\r
24452 <TD width=15% BGCOLOR=#FBF5EF>
\r
24453 <B>PSU_IOU_SLCR_MIO_PIN_52_L0_SEL</B>
\r
24455 <TD width=15% BGCOLOR=#FBF5EF>
\r
24458 <TD width=10% BGCOLOR=#FBF5EF>
\r
24461 <TD width=10% BGCOLOR=#FBF5EF>
\r
24464 <TD width=15% BGCOLOR=#FBF5EF>
\r
24467 <TD width=35% BGCOLOR=#FBF5EF>
\r
24468 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)</B>
\r
24471 <TR valign="top">
\r
24472 <TD width=15% BGCOLOR=#FBF5EF>
\r
24473 <B>PSU_IOU_SLCR_MIO_PIN_52_L1_SEL</B>
\r
24475 <TD width=15% BGCOLOR=#FBF5EF>
\r
24478 <TD width=10% BGCOLOR=#FBF5EF>
\r
24481 <TD width=10% BGCOLOR=#FBF5EF>
\r
24484 <TD width=15% BGCOLOR=#FBF5EF>
\r
24487 <TD width=35% BGCOLOR=#FBF5EF>
\r
24488 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)</B>
\r
24491 <TR valign="top">
\r
24492 <TD width=15% BGCOLOR=#FBF5EF>
\r
24493 <B>PSU_IOU_SLCR_MIO_PIN_52_L2_SEL</B>
\r
24495 <TD width=15% BGCOLOR=#FBF5EF>
\r
24498 <TD width=10% BGCOLOR=#FBF5EF>
\r
24501 <TD width=10% BGCOLOR=#FBF5EF>
\r
24504 <TD width=15% BGCOLOR=#FBF5EF>
\r
24507 <TD width=35% BGCOLOR=#FBF5EF>
\r
24508 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
24511 <TR valign="top">
\r
24512 <TD width=15% BGCOLOR=#FBF5EF>
\r
24513 <B>PSU_IOU_SLCR_MIO_PIN_52_L3_SEL</B>
\r
24515 <TD width=15% BGCOLOR=#FBF5EF>
\r
24518 <TD width=10% BGCOLOR=#FBF5EF>
\r
24521 <TD width=10% BGCOLOR=#FBF5EF>
\r
24524 <TD width=15% BGCOLOR=#FBF5EF>
\r
24527 <TD width=35% BGCOLOR=#FBF5EF>
\r
24528 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)</B>
\r
24531 <TR valign="top">
\r
24532 <TD width=15% BGCOLOR=#C0C0C0>
\r
24533 <B>PSU_IOU_SLCR_MIO_PIN_52@0XFF1800D0</B>
\r
24535 <TD width=15% BGCOLOR=#C0C0C0>
\r
24538 <TD width=10% BGCOLOR=#C0C0C0>
\r
24541 <TD width=10% BGCOLOR=#C0C0C0>
\r
24544 <TD width=15% BGCOLOR=#C0C0C0>
\r
24547 <TD width=35% BGCOLOR=#C0C0C0>
\r
24548 <B>Configures MIO Pin 52 peripheral interface mapping</B>
\r
24553 <H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
\r
24554 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24555 <TR valign="top">
\r
24556 <TD width=15% BGCOLOR=#FFFF00>
\r
24557 <B>Register Name</B>
\r
24559 <TD width=15% BGCOLOR=#FFFF00>
\r
24562 <TD width=10% BGCOLOR=#FFFF00>
\r
24565 <TD width=10% BGCOLOR=#FFFF00>
\r
24568 <TD width=15% BGCOLOR=#FFFF00>
\r
24569 <B>Reset Value</B>
\r
24571 <TD width=35% BGCOLOR=#FFFF00>
\r
24572 <B>Description</B>
\r
24575 <TR valign="top">
\r
24576 <TD width=15% BGCOLOR=#FBF5EF>
\r
24577 <B>MIO_PIN_53</B>
\r
24579 <TD width=15% BGCOLOR=#FBF5EF>
\r
24580 <B>0XFF1800D4</B>
\r
24582 <TD width=10% BGCOLOR=#FBF5EF>
\r
24585 <TD width=10% BGCOLOR=#FBF5EF>
\r
24588 <TD width=15% BGCOLOR=#FBF5EF>
\r
24589 <B>0x00000000</B>
\r
24591 <TD width=35% BGCOLOR=#FBF5EF>
\r
24597 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24598 <TR valign="top">
\r
24599 <TD width=15% BGCOLOR=#C0FFC0>
\r
24600 <B>Field Name</B>
\r
24602 <TD width=15% BGCOLOR=#C0FFC0>
\r
24605 <TD width=10% BGCOLOR=#C0FFC0>
\r
24608 <TD width=10% BGCOLOR=#C0FFC0>
\r
24611 <TD width=15% BGCOLOR=#C0FFC0>
\r
24612 <B>Shifted Value</B>
\r
24614 <TD width=35% BGCOLOR=#C0FFC0>
\r
24615 <B>Description</B>
\r
24618 <TR valign="top">
\r
24619 <TD width=15% BGCOLOR=#FBF5EF>
\r
24620 <B>PSU_IOU_SLCR_MIO_PIN_53_L0_SEL</B>
\r
24622 <TD width=15% BGCOLOR=#FBF5EF>
\r
24625 <TD width=10% BGCOLOR=#FBF5EF>
\r
24628 <TD width=10% BGCOLOR=#FBF5EF>
\r
24631 <TD width=15% BGCOLOR=#FBF5EF>
\r
24634 <TD width=35% BGCOLOR=#FBF5EF>
\r
24635 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)</B>
\r
24638 <TR valign="top">
\r
24639 <TD width=15% BGCOLOR=#FBF5EF>
\r
24640 <B>PSU_IOU_SLCR_MIO_PIN_53_L1_SEL</B>
\r
24642 <TD width=15% BGCOLOR=#FBF5EF>
\r
24645 <TD width=10% BGCOLOR=#FBF5EF>
\r
24648 <TD width=10% BGCOLOR=#FBF5EF>
\r
24651 <TD width=15% BGCOLOR=#FBF5EF>
\r
24654 <TD width=35% BGCOLOR=#FBF5EF>
\r
24655 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</B>
\r
24658 <TR valign="top">
\r
24659 <TD width=15% BGCOLOR=#FBF5EF>
\r
24660 <B>PSU_IOU_SLCR_MIO_PIN_53_L2_SEL</B>
\r
24662 <TD width=15% BGCOLOR=#FBF5EF>
\r
24665 <TD width=10% BGCOLOR=#FBF5EF>
\r
24668 <TD width=10% BGCOLOR=#FBF5EF>
\r
24671 <TD width=15% BGCOLOR=#FBF5EF>
\r
24674 <TD width=35% BGCOLOR=#FBF5EF>
\r
24675 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
24678 <TR valign="top">
\r
24679 <TD width=15% BGCOLOR=#FBF5EF>
\r
24680 <B>PSU_IOU_SLCR_MIO_PIN_53_L3_SEL</B>
\r
24682 <TD width=15% BGCOLOR=#FBF5EF>
\r
24685 <TD width=10% BGCOLOR=#FBF5EF>
\r
24688 <TD width=10% BGCOLOR=#FBF5EF>
\r
24691 <TD width=15% BGCOLOR=#FBF5EF>
\r
24694 <TD width=35% BGCOLOR=#FBF5EF>
\r
24695 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)</B>
\r
24698 <TR valign="top">
\r
24699 <TD width=15% BGCOLOR=#C0C0C0>
\r
24700 <B>PSU_IOU_SLCR_MIO_PIN_53@0XFF1800D4</B>
\r
24702 <TD width=15% BGCOLOR=#C0C0C0>
\r
24705 <TD width=10% BGCOLOR=#C0C0C0>
\r
24708 <TD width=10% BGCOLOR=#C0C0C0>
\r
24711 <TD width=15% BGCOLOR=#C0C0C0>
\r
24714 <TD width=35% BGCOLOR=#C0C0C0>
\r
24715 <B>Configures MIO Pin 53 peripheral interface mapping</B>
\r
24720 <H2><a name="MIO_PIN_54">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_54</a></H2>
\r
24721 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24722 <TR valign="top">
\r
24723 <TD width=15% BGCOLOR=#FFFF00>
\r
24724 <B>Register Name</B>
\r
24726 <TD width=15% BGCOLOR=#FFFF00>
\r
24729 <TD width=10% BGCOLOR=#FFFF00>
\r
24732 <TD width=10% BGCOLOR=#FFFF00>
\r
24735 <TD width=15% BGCOLOR=#FFFF00>
\r
24736 <B>Reset Value</B>
\r
24738 <TD width=35% BGCOLOR=#FFFF00>
\r
24739 <B>Description</B>
\r
24742 <TR valign="top">
\r
24743 <TD width=15% BGCOLOR=#FBF5EF>
\r
24744 <B>MIO_PIN_54</B>
\r
24746 <TD width=15% BGCOLOR=#FBF5EF>
\r
24747 <B>0XFF1800D8</B>
\r
24749 <TD width=10% BGCOLOR=#FBF5EF>
\r
24752 <TD width=10% BGCOLOR=#FBF5EF>
\r
24755 <TD width=15% BGCOLOR=#FBF5EF>
\r
24756 <B>0x00000000</B>
\r
24758 <TD width=35% BGCOLOR=#FBF5EF>
\r
24764 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24765 <TR valign="top">
\r
24766 <TD width=15% BGCOLOR=#C0FFC0>
\r
24767 <B>Field Name</B>
\r
24769 <TD width=15% BGCOLOR=#C0FFC0>
\r
24772 <TD width=10% BGCOLOR=#C0FFC0>
\r
24775 <TD width=10% BGCOLOR=#C0FFC0>
\r
24778 <TD width=15% BGCOLOR=#C0FFC0>
\r
24779 <B>Shifted Value</B>
\r
24781 <TD width=35% BGCOLOR=#C0FFC0>
\r
24782 <B>Description</B>
\r
24785 <TR valign="top">
\r
24786 <TD width=15% BGCOLOR=#FBF5EF>
\r
24787 <B>PSU_IOU_SLCR_MIO_PIN_54_L0_SEL</B>
\r
24789 <TD width=15% BGCOLOR=#FBF5EF>
\r
24792 <TD width=10% BGCOLOR=#FBF5EF>
\r
24795 <TD width=10% BGCOLOR=#FBF5EF>
\r
24798 <TD width=15% BGCOLOR=#FBF5EF>
\r
24801 <TD width=35% BGCOLOR=#FBF5EF>
\r
24802 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)</B>
\r
24805 <TR valign="top">
\r
24806 <TD width=15% BGCOLOR=#FBF5EF>
\r
24807 <B>PSU_IOU_SLCR_MIO_PIN_54_L1_SEL</B>
\r
24809 <TD width=15% BGCOLOR=#FBF5EF>
\r
24812 <TD width=10% BGCOLOR=#FBF5EF>
\r
24815 <TD width=10% BGCOLOR=#FBF5EF>
\r
24818 <TD width=15% BGCOLOR=#FBF5EF>
\r
24821 <TD width=35% BGCOLOR=#FBF5EF>
\r
24822 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</B>
\r
24825 <TR valign="top">
\r
24826 <TD width=15% BGCOLOR=#FBF5EF>
\r
24827 <B>PSU_IOU_SLCR_MIO_PIN_54_L2_SEL</B>
\r
24829 <TD width=15% BGCOLOR=#FBF5EF>
\r
24832 <TD width=10% BGCOLOR=#FBF5EF>
\r
24835 <TD width=10% BGCOLOR=#FBF5EF>
\r
24838 <TD width=15% BGCOLOR=#FBF5EF>
\r
24841 <TD width=35% BGCOLOR=#FBF5EF>
\r
24842 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
24845 <TR valign="top">
\r
24846 <TD width=15% BGCOLOR=#FBF5EF>
\r
24847 <B>PSU_IOU_SLCR_MIO_PIN_54_L3_SEL</B>
\r
24849 <TD width=15% BGCOLOR=#FBF5EF>
\r
24852 <TD width=10% BGCOLOR=#FBF5EF>
\r
24855 <TD width=10% BGCOLOR=#FBF5EF>
\r
24858 <TD width=15% BGCOLOR=#FBF5EF>
\r
24861 <TD width=35% BGCOLOR=#FBF5EF>
\r
24862 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)</B>
\r
24865 <TR valign="top">
\r
24866 <TD width=15% BGCOLOR=#C0C0C0>
\r
24867 <B>PSU_IOU_SLCR_MIO_PIN_54@0XFF1800D8</B>
\r
24869 <TD width=15% BGCOLOR=#C0C0C0>
\r
24872 <TD width=10% BGCOLOR=#C0C0C0>
\r
24875 <TD width=10% BGCOLOR=#C0C0C0>
\r
24878 <TD width=15% BGCOLOR=#C0C0C0>
\r
24881 <TD width=35% BGCOLOR=#C0C0C0>
\r
24882 <B>Configures MIO Pin 54 peripheral interface mapping</B>
\r
24887 <H2><a name="MIO_PIN_55">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_55</a></H2>
\r
24888 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24889 <TR valign="top">
\r
24890 <TD width=15% BGCOLOR=#FFFF00>
\r
24891 <B>Register Name</B>
\r
24893 <TD width=15% BGCOLOR=#FFFF00>
\r
24896 <TD width=10% BGCOLOR=#FFFF00>
\r
24899 <TD width=10% BGCOLOR=#FFFF00>
\r
24902 <TD width=15% BGCOLOR=#FFFF00>
\r
24903 <B>Reset Value</B>
\r
24905 <TD width=35% BGCOLOR=#FFFF00>
\r
24906 <B>Description</B>
\r
24909 <TR valign="top">
\r
24910 <TD width=15% BGCOLOR=#FBF5EF>
\r
24911 <B>MIO_PIN_55</B>
\r
24913 <TD width=15% BGCOLOR=#FBF5EF>
\r
24914 <B>0XFF1800DC</B>
\r
24916 <TD width=10% BGCOLOR=#FBF5EF>
\r
24919 <TD width=10% BGCOLOR=#FBF5EF>
\r
24922 <TD width=15% BGCOLOR=#FBF5EF>
\r
24923 <B>0x00000000</B>
\r
24925 <TD width=35% BGCOLOR=#FBF5EF>
\r
24931 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
24932 <TR valign="top">
\r
24933 <TD width=15% BGCOLOR=#C0FFC0>
\r
24934 <B>Field Name</B>
\r
24936 <TD width=15% BGCOLOR=#C0FFC0>
\r
24939 <TD width=10% BGCOLOR=#C0FFC0>
\r
24942 <TD width=10% BGCOLOR=#C0FFC0>
\r
24945 <TD width=15% BGCOLOR=#C0FFC0>
\r
24946 <B>Shifted Value</B>
\r
24948 <TD width=35% BGCOLOR=#C0FFC0>
\r
24949 <B>Description</B>
\r
24952 <TR valign="top">
\r
24953 <TD width=15% BGCOLOR=#FBF5EF>
\r
24954 <B>PSU_IOU_SLCR_MIO_PIN_55_L0_SEL</B>
\r
24956 <TD width=15% BGCOLOR=#FBF5EF>
\r
24959 <TD width=10% BGCOLOR=#FBF5EF>
\r
24962 <TD width=10% BGCOLOR=#FBF5EF>
\r
24965 <TD width=15% BGCOLOR=#FBF5EF>
\r
24968 <TD width=35% BGCOLOR=#FBF5EF>
\r
24969 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)</B>
\r
24972 <TR valign="top">
\r
24973 <TD width=15% BGCOLOR=#FBF5EF>
\r
24974 <B>PSU_IOU_SLCR_MIO_PIN_55_L1_SEL</B>
\r
24976 <TD width=15% BGCOLOR=#FBF5EF>
\r
24979 <TD width=10% BGCOLOR=#FBF5EF>
\r
24982 <TD width=10% BGCOLOR=#FBF5EF>
\r
24985 <TD width=15% BGCOLOR=#FBF5EF>
\r
24988 <TD width=35% BGCOLOR=#FBF5EF>
\r
24989 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</B>
\r
24992 <TR valign="top">
\r
24993 <TD width=15% BGCOLOR=#FBF5EF>
\r
24994 <B>PSU_IOU_SLCR_MIO_PIN_55_L2_SEL</B>
\r
24996 <TD width=15% BGCOLOR=#FBF5EF>
\r
24999 <TD width=10% BGCOLOR=#FBF5EF>
\r
25002 <TD width=10% BGCOLOR=#FBF5EF>
\r
25005 <TD width=15% BGCOLOR=#FBF5EF>
\r
25008 <TD width=35% BGCOLOR=#FBF5EF>
\r
25009 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25012 <TR valign="top">
\r
25013 <TD width=15% BGCOLOR=#FBF5EF>
\r
25014 <B>PSU_IOU_SLCR_MIO_PIN_55_L3_SEL</B>
\r
25016 <TD width=15% BGCOLOR=#FBF5EF>
\r
25019 <TD width=10% BGCOLOR=#FBF5EF>
\r
25022 <TD width=10% BGCOLOR=#FBF5EF>
\r
25025 <TD width=15% BGCOLOR=#FBF5EF>
\r
25028 <TD width=35% BGCOLOR=#FBF5EF>
\r
25029 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)</B>
\r
25032 <TR valign="top">
\r
25033 <TD width=15% BGCOLOR=#C0C0C0>
\r
25034 <B>PSU_IOU_SLCR_MIO_PIN_55@0XFF1800DC</B>
\r
25036 <TD width=15% BGCOLOR=#C0C0C0>
\r
25039 <TD width=10% BGCOLOR=#C0C0C0>
\r
25042 <TD width=10% BGCOLOR=#C0C0C0>
\r
25045 <TD width=15% BGCOLOR=#C0C0C0>
\r
25048 <TD width=35% BGCOLOR=#C0C0C0>
\r
25049 <B>Configures MIO Pin 55 peripheral interface mapping</B>
\r
25054 <H2><a name="MIO_PIN_56">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_56</a></H2>
\r
25055 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25056 <TR valign="top">
\r
25057 <TD width=15% BGCOLOR=#FFFF00>
\r
25058 <B>Register Name</B>
\r
25060 <TD width=15% BGCOLOR=#FFFF00>
\r
25063 <TD width=10% BGCOLOR=#FFFF00>
\r
25066 <TD width=10% BGCOLOR=#FFFF00>
\r
25069 <TD width=15% BGCOLOR=#FFFF00>
\r
25070 <B>Reset Value</B>
\r
25072 <TD width=35% BGCOLOR=#FFFF00>
\r
25073 <B>Description</B>
\r
25076 <TR valign="top">
\r
25077 <TD width=15% BGCOLOR=#FBF5EF>
\r
25078 <B>MIO_PIN_56</B>
\r
25080 <TD width=15% BGCOLOR=#FBF5EF>
\r
25081 <B>0XFF1800E0</B>
\r
25083 <TD width=10% BGCOLOR=#FBF5EF>
\r
25086 <TD width=10% BGCOLOR=#FBF5EF>
\r
25089 <TD width=15% BGCOLOR=#FBF5EF>
\r
25090 <B>0x00000000</B>
\r
25092 <TD width=35% BGCOLOR=#FBF5EF>
\r
25098 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25099 <TR valign="top">
\r
25100 <TD width=15% BGCOLOR=#C0FFC0>
\r
25101 <B>Field Name</B>
\r
25103 <TD width=15% BGCOLOR=#C0FFC0>
\r
25106 <TD width=10% BGCOLOR=#C0FFC0>
\r
25109 <TD width=10% BGCOLOR=#C0FFC0>
\r
25112 <TD width=15% BGCOLOR=#C0FFC0>
\r
25113 <B>Shifted Value</B>
\r
25115 <TD width=35% BGCOLOR=#C0FFC0>
\r
25116 <B>Description</B>
\r
25119 <TR valign="top">
\r
25120 <TD width=15% BGCOLOR=#FBF5EF>
\r
25121 <B>PSU_IOU_SLCR_MIO_PIN_56_L0_SEL</B>
\r
25123 <TD width=15% BGCOLOR=#FBF5EF>
\r
25126 <TD width=10% BGCOLOR=#FBF5EF>
\r
25129 <TD width=10% BGCOLOR=#FBF5EF>
\r
25132 <TD width=15% BGCOLOR=#FBF5EF>
\r
25135 <TD width=35% BGCOLOR=#FBF5EF>
\r
25136 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)</B>
\r
25139 <TR valign="top">
\r
25140 <TD width=15% BGCOLOR=#FBF5EF>
\r
25141 <B>PSU_IOU_SLCR_MIO_PIN_56_L1_SEL</B>
\r
25143 <TD width=15% BGCOLOR=#FBF5EF>
\r
25146 <TD width=10% BGCOLOR=#FBF5EF>
\r
25149 <TD width=10% BGCOLOR=#FBF5EF>
\r
25152 <TD width=15% BGCOLOR=#FBF5EF>
\r
25155 <TD width=35% BGCOLOR=#FBF5EF>
\r
25156 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</B>
\r
25159 <TR valign="top">
\r
25160 <TD width=15% BGCOLOR=#FBF5EF>
\r
25161 <B>PSU_IOU_SLCR_MIO_PIN_56_L2_SEL</B>
\r
25163 <TD width=15% BGCOLOR=#FBF5EF>
\r
25166 <TD width=10% BGCOLOR=#FBF5EF>
\r
25169 <TD width=10% BGCOLOR=#FBF5EF>
\r
25172 <TD width=15% BGCOLOR=#FBF5EF>
\r
25175 <TD width=35% BGCOLOR=#FBF5EF>
\r
25176 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25179 <TR valign="top">
\r
25180 <TD width=15% BGCOLOR=#FBF5EF>
\r
25181 <B>PSU_IOU_SLCR_MIO_PIN_56_L3_SEL</B>
\r
25183 <TD width=15% BGCOLOR=#FBF5EF>
\r
25186 <TD width=10% BGCOLOR=#FBF5EF>
\r
25189 <TD width=10% BGCOLOR=#FBF5EF>
\r
25192 <TD width=15% BGCOLOR=#FBF5EF>
\r
25195 <TD width=35% BGCOLOR=#FBF5EF>
\r
25196 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)</B>
\r
25199 <TR valign="top">
\r
25200 <TD width=15% BGCOLOR=#C0C0C0>
\r
25201 <B>PSU_IOU_SLCR_MIO_PIN_56@0XFF1800E0</B>
\r
25203 <TD width=15% BGCOLOR=#C0C0C0>
\r
25206 <TD width=10% BGCOLOR=#C0C0C0>
\r
25209 <TD width=10% BGCOLOR=#C0C0C0>
\r
25212 <TD width=15% BGCOLOR=#C0C0C0>
\r
25215 <TD width=35% BGCOLOR=#C0C0C0>
\r
25216 <B>Configures MIO Pin 56 peripheral interface mapping</B>
\r
25221 <H2><a name="MIO_PIN_57">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_57</a></H2>
\r
25222 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25223 <TR valign="top">
\r
25224 <TD width=15% BGCOLOR=#FFFF00>
\r
25225 <B>Register Name</B>
\r
25227 <TD width=15% BGCOLOR=#FFFF00>
\r
25230 <TD width=10% BGCOLOR=#FFFF00>
\r
25233 <TD width=10% BGCOLOR=#FFFF00>
\r
25236 <TD width=15% BGCOLOR=#FFFF00>
\r
25237 <B>Reset Value</B>
\r
25239 <TD width=35% BGCOLOR=#FFFF00>
\r
25240 <B>Description</B>
\r
25243 <TR valign="top">
\r
25244 <TD width=15% BGCOLOR=#FBF5EF>
\r
25245 <B>MIO_PIN_57</B>
\r
25247 <TD width=15% BGCOLOR=#FBF5EF>
\r
25248 <B>0XFF1800E4</B>
\r
25250 <TD width=10% BGCOLOR=#FBF5EF>
\r
25253 <TD width=10% BGCOLOR=#FBF5EF>
\r
25256 <TD width=15% BGCOLOR=#FBF5EF>
\r
25257 <B>0x00000000</B>
\r
25259 <TD width=35% BGCOLOR=#FBF5EF>
\r
25265 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25266 <TR valign="top">
\r
25267 <TD width=15% BGCOLOR=#C0FFC0>
\r
25268 <B>Field Name</B>
\r
25270 <TD width=15% BGCOLOR=#C0FFC0>
\r
25273 <TD width=10% BGCOLOR=#C0FFC0>
\r
25276 <TD width=10% BGCOLOR=#C0FFC0>
\r
25279 <TD width=15% BGCOLOR=#C0FFC0>
\r
25280 <B>Shifted Value</B>
\r
25282 <TD width=35% BGCOLOR=#C0FFC0>
\r
25283 <B>Description</B>
\r
25286 <TR valign="top">
\r
25287 <TD width=15% BGCOLOR=#FBF5EF>
\r
25288 <B>PSU_IOU_SLCR_MIO_PIN_57_L0_SEL</B>
\r
25290 <TD width=15% BGCOLOR=#FBF5EF>
\r
25293 <TD width=10% BGCOLOR=#FBF5EF>
\r
25296 <TD width=10% BGCOLOR=#FBF5EF>
\r
25299 <TD width=15% BGCOLOR=#FBF5EF>
\r
25302 <TD width=35% BGCOLOR=#FBF5EF>
\r
25303 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)</B>
\r
25306 <TR valign="top">
\r
25307 <TD width=15% BGCOLOR=#FBF5EF>
\r
25308 <B>PSU_IOU_SLCR_MIO_PIN_57_L1_SEL</B>
\r
25310 <TD width=15% BGCOLOR=#FBF5EF>
\r
25313 <TD width=10% BGCOLOR=#FBF5EF>
\r
25316 <TD width=10% BGCOLOR=#FBF5EF>
\r
25319 <TD width=15% BGCOLOR=#FBF5EF>
\r
25322 <TD width=35% BGCOLOR=#FBF5EF>
\r
25323 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</B>
\r
25326 <TR valign="top">
\r
25327 <TD width=15% BGCOLOR=#FBF5EF>
\r
25328 <B>PSU_IOU_SLCR_MIO_PIN_57_L2_SEL</B>
\r
25330 <TD width=15% BGCOLOR=#FBF5EF>
\r
25333 <TD width=10% BGCOLOR=#FBF5EF>
\r
25336 <TD width=10% BGCOLOR=#FBF5EF>
\r
25339 <TD width=15% BGCOLOR=#FBF5EF>
\r
25342 <TD width=35% BGCOLOR=#FBF5EF>
\r
25343 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25346 <TR valign="top">
\r
25347 <TD width=15% BGCOLOR=#FBF5EF>
\r
25348 <B>PSU_IOU_SLCR_MIO_PIN_57_L3_SEL</B>
\r
25350 <TD width=15% BGCOLOR=#FBF5EF>
\r
25353 <TD width=10% BGCOLOR=#FBF5EF>
\r
25356 <TD width=10% BGCOLOR=#FBF5EF>
\r
25359 <TD width=15% BGCOLOR=#FBF5EF>
\r
25362 <TD width=35% BGCOLOR=#FBF5EF>
\r
25363 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)</B>
\r
25366 <TR valign="top">
\r
25367 <TD width=15% BGCOLOR=#C0C0C0>
\r
25368 <B>PSU_IOU_SLCR_MIO_PIN_57@0XFF1800E4</B>
\r
25370 <TD width=15% BGCOLOR=#C0C0C0>
\r
25373 <TD width=10% BGCOLOR=#C0C0C0>
\r
25376 <TD width=10% BGCOLOR=#C0C0C0>
\r
25379 <TD width=15% BGCOLOR=#C0C0C0>
\r
25382 <TD width=35% BGCOLOR=#C0C0C0>
\r
25383 <B>Configures MIO Pin 57 peripheral interface mapping</B>
\r
25388 <H2><a name="MIO_PIN_58">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_58</a></H2>
\r
25389 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25390 <TR valign="top">
\r
25391 <TD width=15% BGCOLOR=#FFFF00>
\r
25392 <B>Register Name</B>
\r
25394 <TD width=15% BGCOLOR=#FFFF00>
\r
25397 <TD width=10% BGCOLOR=#FFFF00>
\r
25400 <TD width=10% BGCOLOR=#FFFF00>
\r
25403 <TD width=15% BGCOLOR=#FFFF00>
\r
25404 <B>Reset Value</B>
\r
25406 <TD width=35% BGCOLOR=#FFFF00>
\r
25407 <B>Description</B>
\r
25410 <TR valign="top">
\r
25411 <TD width=15% BGCOLOR=#FBF5EF>
\r
25412 <B>MIO_PIN_58</B>
\r
25414 <TD width=15% BGCOLOR=#FBF5EF>
\r
25415 <B>0XFF1800E8</B>
\r
25417 <TD width=10% BGCOLOR=#FBF5EF>
\r
25420 <TD width=10% BGCOLOR=#FBF5EF>
\r
25423 <TD width=15% BGCOLOR=#FBF5EF>
\r
25424 <B>0x00000000</B>
\r
25426 <TD width=35% BGCOLOR=#FBF5EF>
\r
25432 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25433 <TR valign="top">
\r
25434 <TD width=15% BGCOLOR=#C0FFC0>
\r
25435 <B>Field Name</B>
\r
25437 <TD width=15% BGCOLOR=#C0FFC0>
\r
25440 <TD width=10% BGCOLOR=#C0FFC0>
\r
25443 <TD width=10% BGCOLOR=#C0FFC0>
\r
25446 <TD width=15% BGCOLOR=#C0FFC0>
\r
25447 <B>Shifted Value</B>
\r
25449 <TD width=35% BGCOLOR=#C0FFC0>
\r
25450 <B>Description</B>
\r
25453 <TR valign="top">
\r
25454 <TD width=15% BGCOLOR=#FBF5EF>
\r
25455 <B>PSU_IOU_SLCR_MIO_PIN_58_L0_SEL</B>
\r
25457 <TD width=15% BGCOLOR=#FBF5EF>
\r
25460 <TD width=10% BGCOLOR=#FBF5EF>
\r
25463 <TD width=10% BGCOLOR=#FBF5EF>
\r
25466 <TD width=15% BGCOLOR=#FBF5EF>
\r
25469 <TD width=35% BGCOLOR=#FBF5EF>
\r
25470 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)</B>
\r
25473 <TR valign="top">
\r
25474 <TD width=15% BGCOLOR=#FBF5EF>
\r
25475 <B>PSU_IOU_SLCR_MIO_PIN_58_L1_SEL</B>
\r
25477 <TD width=15% BGCOLOR=#FBF5EF>
\r
25480 <TD width=10% BGCOLOR=#FBF5EF>
\r
25483 <TD width=10% BGCOLOR=#FBF5EF>
\r
25486 <TD width=15% BGCOLOR=#FBF5EF>
\r
25489 <TD width=35% BGCOLOR=#FBF5EF>
\r
25490 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</B>
\r
25493 <TR valign="top">
\r
25494 <TD width=15% BGCOLOR=#FBF5EF>
\r
25495 <B>PSU_IOU_SLCR_MIO_PIN_58_L2_SEL</B>
\r
25497 <TD width=15% BGCOLOR=#FBF5EF>
\r
25500 <TD width=10% BGCOLOR=#FBF5EF>
\r
25503 <TD width=10% BGCOLOR=#FBF5EF>
\r
25506 <TD width=15% BGCOLOR=#FBF5EF>
\r
25509 <TD width=35% BGCOLOR=#FBF5EF>
\r
25510 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25513 <TR valign="top">
\r
25514 <TD width=15% BGCOLOR=#FBF5EF>
\r
25515 <B>PSU_IOU_SLCR_MIO_PIN_58_L3_SEL</B>
\r
25517 <TD width=15% BGCOLOR=#FBF5EF>
\r
25520 <TD width=10% BGCOLOR=#FBF5EF>
\r
25523 <TD width=10% BGCOLOR=#FBF5EF>
\r
25526 <TD width=15% BGCOLOR=#FBF5EF>
\r
25529 <TD width=35% BGCOLOR=#FBF5EF>
\r
25530 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)</B>
\r
25533 <TR valign="top">
\r
25534 <TD width=15% BGCOLOR=#C0C0C0>
\r
25535 <B>PSU_IOU_SLCR_MIO_PIN_58@0XFF1800E8</B>
\r
25537 <TD width=15% BGCOLOR=#C0C0C0>
\r
25540 <TD width=10% BGCOLOR=#C0C0C0>
\r
25543 <TD width=10% BGCOLOR=#C0C0C0>
\r
25546 <TD width=15% BGCOLOR=#C0C0C0>
\r
25549 <TD width=35% BGCOLOR=#C0C0C0>
\r
25550 <B>Configures MIO Pin 58 peripheral interface mapping</B>
\r
25555 <H2><a name="MIO_PIN_59">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_59</a></H2>
\r
25556 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25557 <TR valign="top">
\r
25558 <TD width=15% BGCOLOR=#FFFF00>
\r
25559 <B>Register Name</B>
\r
25561 <TD width=15% BGCOLOR=#FFFF00>
\r
25564 <TD width=10% BGCOLOR=#FFFF00>
\r
25567 <TD width=10% BGCOLOR=#FFFF00>
\r
25570 <TD width=15% BGCOLOR=#FFFF00>
\r
25571 <B>Reset Value</B>
\r
25573 <TD width=35% BGCOLOR=#FFFF00>
\r
25574 <B>Description</B>
\r
25577 <TR valign="top">
\r
25578 <TD width=15% BGCOLOR=#FBF5EF>
\r
25579 <B>MIO_PIN_59</B>
\r
25581 <TD width=15% BGCOLOR=#FBF5EF>
\r
25582 <B>0XFF1800EC</B>
\r
25584 <TD width=10% BGCOLOR=#FBF5EF>
\r
25587 <TD width=10% BGCOLOR=#FBF5EF>
\r
25590 <TD width=15% BGCOLOR=#FBF5EF>
\r
25591 <B>0x00000000</B>
\r
25593 <TD width=35% BGCOLOR=#FBF5EF>
\r
25599 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25600 <TR valign="top">
\r
25601 <TD width=15% BGCOLOR=#C0FFC0>
\r
25602 <B>Field Name</B>
\r
25604 <TD width=15% BGCOLOR=#C0FFC0>
\r
25607 <TD width=10% BGCOLOR=#C0FFC0>
\r
25610 <TD width=10% BGCOLOR=#C0FFC0>
\r
25613 <TD width=15% BGCOLOR=#C0FFC0>
\r
25614 <B>Shifted Value</B>
\r
25616 <TD width=35% BGCOLOR=#C0FFC0>
\r
25617 <B>Description</B>
\r
25620 <TR valign="top">
\r
25621 <TD width=15% BGCOLOR=#FBF5EF>
\r
25622 <B>PSU_IOU_SLCR_MIO_PIN_59_L0_SEL</B>
\r
25624 <TD width=15% BGCOLOR=#FBF5EF>
\r
25627 <TD width=10% BGCOLOR=#FBF5EF>
\r
25630 <TD width=10% BGCOLOR=#FBF5EF>
\r
25633 <TD width=15% BGCOLOR=#FBF5EF>
\r
25636 <TD width=35% BGCOLOR=#FBF5EF>
\r
25637 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)</B>
\r
25640 <TR valign="top">
\r
25641 <TD width=15% BGCOLOR=#FBF5EF>
\r
25642 <B>PSU_IOU_SLCR_MIO_PIN_59_L1_SEL</B>
\r
25644 <TD width=15% BGCOLOR=#FBF5EF>
\r
25647 <TD width=10% BGCOLOR=#FBF5EF>
\r
25650 <TD width=10% BGCOLOR=#FBF5EF>
\r
25653 <TD width=15% BGCOLOR=#FBF5EF>
\r
25656 <TD width=35% BGCOLOR=#FBF5EF>
\r
25657 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</B>
\r
25660 <TR valign="top">
\r
25661 <TD width=15% BGCOLOR=#FBF5EF>
\r
25662 <B>PSU_IOU_SLCR_MIO_PIN_59_L2_SEL</B>
\r
25664 <TD width=15% BGCOLOR=#FBF5EF>
\r
25667 <TD width=10% BGCOLOR=#FBF5EF>
\r
25670 <TD width=10% BGCOLOR=#FBF5EF>
\r
25673 <TD width=15% BGCOLOR=#FBF5EF>
\r
25676 <TD width=35% BGCOLOR=#FBF5EF>
\r
25677 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25680 <TR valign="top">
\r
25681 <TD width=15% BGCOLOR=#FBF5EF>
\r
25682 <B>PSU_IOU_SLCR_MIO_PIN_59_L3_SEL</B>
\r
25684 <TD width=15% BGCOLOR=#FBF5EF>
\r
25687 <TD width=10% BGCOLOR=#FBF5EF>
\r
25690 <TD width=10% BGCOLOR=#FBF5EF>
\r
25693 <TD width=15% BGCOLOR=#FBF5EF>
\r
25696 <TD width=35% BGCOLOR=#FBF5EF>
\r
25697 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)</B>
\r
25700 <TR valign="top">
\r
25701 <TD width=15% BGCOLOR=#C0C0C0>
\r
25702 <B>PSU_IOU_SLCR_MIO_PIN_59@0XFF1800EC</B>
\r
25704 <TD width=15% BGCOLOR=#C0C0C0>
\r
25707 <TD width=10% BGCOLOR=#C0C0C0>
\r
25710 <TD width=10% BGCOLOR=#C0C0C0>
\r
25713 <TD width=15% BGCOLOR=#C0C0C0>
\r
25716 <TD width=35% BGCOLOR=#C0C0C0>
\r
25717 <B>Configures MIO Pin 59 peripheral interface mapping</B>
\r
25722 <H2><a name="MIO_PIN_60">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_60</a></H2>
\r
25723 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25724 <TR valign="top">
\r
25725 <TD width=15% BGCOLOR=#FFFF00>
\r
25726 <B>Register Name</B>
\r
25728 <TD width=15% BGCOLOR=#FFFF00>
\r
25731 <TD width=10% BGCOLOR=#FFFF00>
\r
25734 <TD width=10% BGCOLOR=#FFFF00>
\r
25737 <TD width=15% BGCOLOR=#FFFF00>
\r
25738 <B>Reset Value</B>
\r
25740 <TD width=35% BGCOLOR=#FFFF00>
\r
25741 <B>Description</B>
\r
25744 <TR valign="top">
\r
25745 <TD width=15% BGCOLOR=#FBF5EF>
\r
25746 <B>MIO_PIN_60</B>
\r
25748 <TD width=15% BGCOLOR=#FBF5EF>
\r
25749 <B>0XFF1800F0</B>
\r
25751 <TD width=10% BGCOLOR=#FBF5EF>
\r
25754 <TD width=10% BGCOLOR=#FBF5EF>
\r
25757 <TD width=15% BGCOLOR=#FBF5EF>
\r
25758 <B>0x00000000</B>
\r
25760 <TD width=35% BGCOLOR=#FBF5EF>
\r
25766 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25767 <TR valign="top">
\r
25768 <TD width=15% BGCOLOR=#C0FFC0>
\r
25769 <B>Field Name</B>
\r
25771 <TD width=15% BGCOLOR=#C0FFC0>
\r
25774 <TD width=10% BGCOLOR=#C0FFC0>
\r
25777 <TD width=10% BGCOLOR=#C0FFC0>
\r
25780 <TD width=15% BGCOLOR=#C0FFC0>
\r
25781 <B>Shifted Value</B>
\r
25783 <TD width=35% BGCOLOR=#C0FFC0>
\r
25784 <B>Description</B>
\r
25787 <TR valign="top">
\r
25788 <TD width=15% BGCOLOR=#FBF5EF>
\r
25789 <B>PSU_IOU_SLCR_MIO_PIN_60_L0_SEL</B>
\r
25791 <TD width=15% BGCOLOR=#FBF5EF>
\r
25794 <TD width=10% BGCOLOR=#FBF5EF>
\r
25797 <TD width=10% BGCOLOR=#FBF5EF>
\r
25800 <TD width=15% BGCOLOR=#FBF5EF>
\r
25803 <TD width=35% BGCOLOR=#FBF5EF>
\r
25804 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)</B>
\r
25807 <TR valign="top">
\r
25808 <TD width=15% BGCOLOR=#FBF5EF>
\r
25809 <B>PSU_IOU_SLCR_MIO_PIN_60_L1_SEL</B>
\r
25811 <TD width=15% BGCOLOR=#FBF5EF>
\r
25814 <TD width=10% BGCOLOR=#FBF5EF>
\r
25817 <TD width=10% BGCOLOR=#FBF5EF>
\r
25820 <TD width=15% BGCOLOR=#FBF5EF>
\r
25823 <TD width=35% BGCOLOR=#FBF5EF>
\r
25824 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</B>
\r
25827 <TR valign="top">
\r
25828 <TD width=15% BGCOLOR=#FBF5EF>
\r
25829 <B>PSU_IOU_SLCR_MIO_PIN_60_L2_SEL</B>
\r
25831 <TD width=15% BGCOLOR=#FBF5EF>
\r
25834 <TD width=10% BGCOLOR=#FBF5EF>
\r
25837 <TD width=10% BGCOLOR=#FBF5EF>
\r
25840 <TD width=15% BGCOLOR=#FBF5EF>
\r
25843 <TD width=35% BGCOLOR=#FBF5EF>
\r
25844 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
25847 <TR valign="top">
\r
25848 <TD width=15% BGCOLOR=#FBF5EF>
\r
25849 <B>PSU_IOU_SLCR_MIO_PIN_60_L3_SEL</B>
\r
25851 <TD width=15% BGCOLOR=#FBF5EF>
\r
25854 <TD width=10% BGCOLOR=#FBF5EF>
\r
25857 <TD width=10% BGCOLOR=#FBF5EF>
\r
25860 <TD width=15% BGCOLOR=#FBF5EF>
\r
25863 <TD width=35% BGCOLOR=#FBF5EF>
\r
25864 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)</B>
\r
25867 <TR valign="top">
\r
25868 <TD width=15% BGCOLOR=#C0C0C0>
\r
25869 <B>PSU_IOU_SLCR_MIO_PIN_60@0XFF1800F0</B>
\r
25871 <TD width=15% BGCOLOR=#C0C0C0>
\r
25874 <TD width=10% BGCOLOR=#C0C0C0>
\r
25877 <TD width=10% BGCOLOR=#C0C0C0>
\r
25880 <TD width=15% BGCOLOR=#C0C0C0>
\r
25883 <TD width=35% BGCOLOR=#C0C0C0>
\r
25884 <B>Configures MIO Pin 60 peripheral interface mapping</B>
\r
25889 <H2><a name="MIO_PIN_61">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_61</a></H2>
\r
25890 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25891 <TR valign="top">
\r
25892 <TD width=15% BGCOLOR=#FFFF00>
\r
25893 <B>Register Name</B>
\r
25895 <TD width=15% BGCOLOR=#FFFF00>
\r
25898 <TD width=10% BGCOLOR=#FFFF00>
\r
25901 <TD width=10% BGCOLOR=#FFFF00>
\r
25904 <TD width=15% BGCOLOR=#FFFF00>
\r
25905 <B>Reset Value</B>
\r
25907 <TD width=35% BGCOLOR=#FFFF00>
\r
25908 <B>Description</B>
\r
25911 <TR valign="top">
\r
25912 <TD width=15% BGCOLOR=#FBF5EF>
\r
25913 <B>MIO_PIN_61</B>
\r
25915 <TD width=15% BGCOLOR=#FBF5EF>
\r
25916 <B>0XFF1800F4</B>
\r
25918 <TD width=10% BGCOLOR=#FBF5EF>
\r
25921 <TD width=10% BGCOLOR=#FBF5EF>
\r
25924 <TD width=15% BGCOLOR=#FBF5EF>
\r
25925 <B>0x00000000</B>
\r
25927 <TD width=35% BGCOLOR=#FBF5EF>
\r
25933 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
25934 <TR valign="top">
\r
25935 <TD width=15% BGCOLOR=#C0FFC0>
\r
25936 <B>Field Name</B>
\r
25938 <TD width=15% BGCOLOR=#C0FFC0>
\r
25941 <TD width=10% BGCOLOR=#C0FFC0>
\r
25944 <TD width=10% BGCOLOR=#C0FFC0>
\r
25947 <TD width=15% BGCOLOR=#C0FFC0>
\r
25948 <B>Shifted Value</B>
\r
25950 <TD width=35% BGCOLOR=#C0FFC0>
\r
25951 <B>Description</B>
\r
25954 <TR valign="top">
\r
25955 <TD width=15% BGCOLOR=#FBF5EF>
\r
25956 <B>PSU_IOU_SLCR_MIO_PIN_61_L0_SEL</B>
\r
25958 <TD width=15% BGCOLOR=#FBF5EF>
\r
25961 <TD width=10% BGCOLOR=#FBF5EF>
\r
25964 <TD width=10% BGCOLOR=#FBF5EF>
\r
25967 <TD width=15% BGCOLOR=#FBF5EF>
\r
25970 <TD width=35% BGCOLOR=#FBF5EF>
\r
25971 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)</B>
\r
25974 <TR valign="top">
\r
25975 <TD width=15% BGCOLOR=#FBF5EF>
\r
25976 <B>PSU_IOU_SLCR_MIO_PIN_61_L1_SEL</B>
\r
25978 <TD width=15% BGCOLOR=#FBF5EF>
\r
25981 <TD width=10% BGCOLOR=#FBF5EF>
\r
25984 <TD width=10% BGCOLOR=#FBF5EF>
\r
25987 <TD width=15% BGCOLOR=#FBF5EF>
\r
25990 <TD width=35% BGCOLOR=#FBF5EF>
\r
25991 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</B>
\r
25994 <TR valign="top">
\r
25995 <TD width=15% BGCOLOR=#FBF5EF>
\r
25996 <B>PSU_IOU_SLCR_MIO_PIN_61_L2_SEL</B>
\r
25998 <TD width=15% BGCOLOR=#FBF5EF>
\r
26001 <TD width=10% BGCOLOR=#FBF5EF>
\r
26004 <TD width=10% BGCOLOR=#FBF5EF>
\r
26007 <TD width=15% BGCOLOR=#FBF5EF>
\r
26010 <TD width=35% BGCOLOR=#FBF5EF>
\r
26011 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
26014 <TR valign="top">
\r
26015 <TD width=15% BGCOLOR=#FBF5EF>
\r
26016 <B>PSU_IOU_SLCR_MIO_PIN_61_L3_SEL</B>
\r
26018 <TD width=15% BGCOLOR=#FBF5EF>
\r
26021 <TD width=10% BGCOLOR=#FBF5EF>
\r
26024 <TD width=10% BGCOLOR=#FBF5EF>
\r
26027 <TD width=15% BGCOLOR=#FBF5EF>
\r
26030 <TD width=35% BGCOLOR=#FBF5EF>
\r
26031 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)</B>
\r
26034 <TR valign="top">
\r
26035 <TD width=15% BGCOLOR=#C0C0C0>
\r
26036 <B>PSU_IOU_SLCR_MIO_PIN_61@0XFF1800F4</B>
\r
26038 <TD width=15% BGCOLOR=#C0C0C0>
\r
26041 <TD width=10% BGCOLOR=#C0C0C0>
\r
26044 <TD width=10% BGCOLOR=#C0C0C0>
\r
26047 <TD width=15% BGCOLOR=#C0C0C0>
\r
26050 <TD width=35% BGCOLOR=#C0C0C0>
\r
26051 <B>Configures MIO Pin 61 peripheral interface mapping</B>
\r
26056 <H2><a name="MIO_PIN_62">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_62</a></H2>
\r
26057 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26058 <TR valign="top">
\r
26059 <TD width=15% BGCOLOR=#FFFF00>
\r
26060 <B>Register Name</B>
\r
26062 <TD width=15% BGCOLOR=#FFFF00>
\r
26065 <TD width=10% BGCOLOR=#FFFF00>
\r
26068 <TD width=10% BGCOLOR=#FFFF00>
\r
26071 <TD width=15% BGCOLOR=#FFFF00>
\r
26072 <B>Reset Value</B>
\r
26074 <TD width=35% BGCOLOR=#FFFF00>
\r
26075 <B>Description</B>
\r
26078 <TR valign="top">
\r
26079 <TD width=15% BGCOLOR=#FBF5EF>
\r
26080 <B>MIO_PIN_62</B>
\r
26082 <TD width=15% BGCOLOR=#FBF5EF>
\r
26083 <B>0XFF1800F8</B>
\r
26085 <TD width=10% BGCOLOR=#FBF5EF>
\r
26088 <TD width=10% BGCOLOR=#FBF5EF>
\r
26091 <TD width=15% BGCOLOR=#FBF5EF>
\r
26092 <B>0x00000000</B>
\r
26094 <TD width=35% BGCOLOR=#FBF5EF>
\r
26100 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26101 <TR valign="top">
\r
26102 <TD width=15% BGCOLOR=#C0FFC0>
\r
26103 <B>Field Name</B>
\r
26105 <TD width=15% BGCOLOR=#C0FFC0>
\r
26108 <TD width=10% BGCOLOR=#C0FFC0>
\r
26111 <TD width=10% BGCOLOR=#C0FFC0>
\r
26114 <TD width=15% BGCOLOR=#C0FFC0>
\r
26115 <B>Shifted Value</B>
\r
26117 <TD width=35% BGCOLOR=#C0FFC0>
\r
26118 <B>Description</B>
\r
26121 <TR valign="top">
\r
26122 <TD width=15% BGCOLOR=#FBF5EF>
\r
26123 <B>PSU_IOU_SLCR_MIO_PIN_62_L0_SEL</B>
\r
26125 <TD width=15% BGCOLOR=#FBF5EF>
\r
26128 <TD width=10% BGCOLOR=#FBF5EF>
\r
26131 <TD width=10% BGCOLOR=#FBF5EF>
\r
26134 <TD width=15% BGCOLOR=#FBF5EF>
\r
26137 <TD width=35% BGCOLOR=#FBF5EF>
\r
26138 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)</B>
\r
26141 <TR valign="top">
\r
26142 <TD width=15% BGCOLOR=#FBF5EF>
\r
26143 <B>PSU_IOU_SLCR_MIO_PIN_62_L1_SEL</B>
\r
26145 <TD width=15% BGCOLOR=#FBF5EF>
\r
26148 <TD width=10% BGCOLOR=#FBF5EF>
\r
26151 <TD width=10% BGCOLOR=#FBF5EF>
\r
26154 <TD width=15% BGCOLOR=#FBF5EF>
\r
26157 <TD width=35% BGCOLOR=#FBF5EF>
\r
26158 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</B>
\r
26161 <TR valign="top">
\r
26162 <TD width=15% BGCOLOR=#FBF5EF>
\r
26163 <B>PSU_IOU_SLCR_MIO_PIN_62_L2_SEL</B>
\r
26165 <TD width=15% BGCOLOR=#FBF5EF>
\r
26168 <TD width=10% BGCOLOR=#FBF5EF>
\r
26171 <TD width=10% BGCOLOR=#FBF5EF>
\r
26174 <TD width=15% BGCOLOR=#FBF5EF>
\r
26177 <TD width=35% BGCOLOR=#FBF5EF>
\r
26178 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
26181 <TR valign="top">
\r
26182 <TD width=15% BGCOLOR=#FBF5EF>
\r
26183 <B>PSU_IOU_SLCR_MIO_PIN_62_L3_SEL</B>
\r
26185 <TD width=15% BGCOLOR=#FBF5EF>
\r
26188 <TD width=10% BGCOLOR=#FBF5EF>
\r
26191 <TD width=10% BGCOLOR=#FBF5EF>
\r
26194 <TD width=15% BGCOLOR=#FBF5EF>
\r
26197 <TD width=35% BGCOLOR=#FBF5EF>
\r
26198 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)</B>
\r
26201 <TR valign="top">
\r
26202 <TD width=15% BGCOLOR=#C0C0C0>
\r
26203 <B>PSU_IOU_SLCR_MIO_PIN_62@0XFF1800F8</B>
\r
26205 <TD width=15% BGCOLOR=#C0C0C0>
\r
26208 <TD width=10% BGCOLOR=#C0C0C0>
\r
26211 <TD width=10% BGCOLOR=#C0C0C0>
\r
26214 <TD width=15% BGCOLOR=#C0C0C0>
\r
26217 <TD width=35% BGCOLOR=#C0C0C0>
\r
26218 <B>Configures MIO Pin 62 peripheral interface mapping</B>
\r
26223 <H2><a name="MIO_PIN_63">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_63</a></H2>
\r
26224 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26225 <TR valign="top">
\r
26226 <TD width=15% BGCOLOR=#FFFF00>
\r
26227 <B>Register Name</B>
\r
26229 <TD width=15% BGCOLOR=#FFFF00>
\r
26232 <TD width=10% BGCOLOR=#FFFF00>
\r
26235 <TD width=10% BGCOLOR=#FFFF00>
\r
26238 <TD width=15% BGCOLOR=#FFFF00>
\r
26239 <B>Reset Value</B>
\r
26241 <TD width=35% BGCOLOR=#FFFF00>
\r
26242 <B>Description</B>
\r
26245 <TR valign="top">
\r
26246 <TD width=15% BGCOLOR=#FBF5EF>
\r
26247 <B>MIO_PIN_63</B>
\r
26249 <TD width=15% BGCOLOR=#FBF5EF>
\r
26250 <B>0XFF1800FC</B>
\r
26252 <TD width=10% BGCOLOR=#FBF5EF>
\r
26255 <TD width=10% BGCOLOR=#FBF5EF>
\r
26258 <TD width=15% BGCOLOR=#FBF5EF>
\r
26259 <B>0x00000000</B>
\r
26261 <TD width=35% BGCOLOR=#FBF5EF>
\r
26267 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26268 <TR valign="top">
\r
26269 <TD width=15% BGCOLOR=#C0FFC0>
\r
26270 <B>Field Name</B>
\r
26272 <TD width=15% BGCOLOR=#C0FFC0>
\r
26275 <TD width=10% BGCOLOR=#C0FFC0>
\r
26278 <TD width=10% BGCOLOR=#C0FFC0>
\r
26281 <TD width=15% BGCOLOR=#C0FFC0>
\r
26282 <B>Shifted Value</B>
\r
26284 <TD width=35% BGCOLOR=#C0FFC0>
\r
26285 <B>Description</B>
\r
26288 <TR valign="top">
\r
26289 <TD width=15% BGCOLOR=#FBF5EF>
\r
26290 <B>PSU_IOU_SLCR_MIO_PIN_63_L0_SEL</B>
\r
26292 <TD width=15% BGCOLOR=#FBF5EF>
\r
26295 <TD width=10% BGCOLOR=#FBF5EF>
\r
26298 <TD width=10% BGCOLOR=#FBF5EF>
\r
26301 <TD width=15% BGCOLOR=#FBF5EF>
\r
26304 <TD width=35% BGCOLOR=#FBF5EF>
\r
26305 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )</B>
\r
26308 <TR valign="top">
\r
26309 <TD width=15% BGCOLOR=#FBF5EF>
\r
26310 <B>PSU_IOU_SLCR_MIO_PIN_63_L1_SEL</B>
\r
26312 <TD width=15% BGCOLOR=#FBF5EF>
\r
26315 <TD width=10% BGCOLOR=#FBF5EF>
\r
26318 <TD width=10% BGCOLOR=#FBF5EF>
\r
26321 <TD width=15% BGCOLOR=#FBF5EF>
\r
26324 <TD width=35% BGCOLOR=#FBF5EF>
\r
26325 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</B>
\r
26328 <TR valign="top">
\r
26329 <TD width=15% BGCOLOR=#FBF5EF>
\r
26330 <B>PSU_IOU_SLCR_MIO_PIN_63_L2_SEL</B>
\r
26332 <TD width=15% BGCOLOR=#FBF5EF>
\r
26335 <TD width=10% BGCOLOR=#FBF5EF>
\r
26338 <TD width=10% BGCOLOR=#FBF5EF>
\r
26341 <TD width=15% BGCOLOR=#FBF5EF>
\r
26344 <TD width=35% BGCOLOR=#FBF5EF>
\r
26345 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used</B>
\r
26348 <TR valign="top">
\r
26349 <TD width=15% BGCOLOR=#FBF5EF>
\r
26350 <B>PSU_IOU_SLCR_MIO_PIN_63_L3_SEL</B>
\r
26352 <TD width=15% BGCOLOR=#FBF5EF>
\r
26355 <TD width=10% BGCOLOR=#FBF5EF>
\r
26358 <TD width=10% BGCOLOR=#FBF5EF>
\r
26361 <TD width=15% BGCOLOR=#FBF5EF>
\r
26364 <TD width=35% BGCOLOR=#FBF5EF>
\r
26365 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)</B>
\r
26368 <TR valign="top">
\r
26369 <TD width=15% BGCOLOR=#C0C0C0>
\r
26370 <B>PSU_IOU_SLCR_MIO_PIN_63@0XFF1800FC</B>
\r
26372 <TD width=15% BGCOLOR=#C0C0C0>
\r
26375 <TD width=10% BGCOLOR=#C0C0C0>
\r
26378 <TD width=10% BGCOLOR=#C0C0C0>
\r
26381 <TD width=15% BGCOLOR=#C0C0C0>
\r
26384 <TD width=35% BGCOLOR=#C0C0C0>
\r
26385 <B>Configures MIO Pin 63 peripheral interface mapping</B>
\r
26390 <H2><a name="MIO_PIN_64">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_64</a></H2>
\r
26391 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26392 <TR valign="top">
\r
26393 <TD width=15% BGCOLOR=#FFFF00>
\r
26394 <B>Register Name</B>
\r
26396 <TD width=15% BGCOLOR=#FFFF00>
\r
26399 <TD width=10% BGCOLOR=#FFFF00>
\r
26402 <TD width=10% BGCOLOR=#FFFF00>
\r
26405 <TD width=15% BGCOLOR=#FFFF00>
\r
26406 <B>Reset Value</B>
\r
26408 <TD width=35% BGCOLOR=#FFFF00>
\r
26409 <B>Description</B>
\r
26412 <TR valign="top">
\r
26413 <TD width=15% BGCOLOR=#FBF5EF>
\r
26414 <B>MIO_PIN_64</B>
\r
26416 <TD width=15% BGCOLOR=#FBF5EF>
\r
26417 <B>0XFF180100</B>
\r
26419 <TD width=10% BGCOLOR=#FBF5EF>
\r
26422 <TD width=10% BGCOLOR=#FBF5EF>
\r
26425 <TD width=15% BGCOLOR=#FBF5EF>
\r
26426 <B>0x00000000</B>
\r
26428 <TD width=35% BGCOLOR=#FBF5EF>
\r
26434 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26435 <TR valign="top">
\r
26436 <TD width=15% BGCOLOR=#C0FFC0>
\r
26437 <B>Field Name</B>
\r
26439 <TD width=15% BGCOLOR=#C0FFC0>
\r
26442 <TD width=10% BGCOLOR=#C0FFC0>
\r
26445 <TD width=10% BGCOLOR=#C0FFC0>
\r
26448 <TD width=15% BGCOLOR=#C0FFC0>
\r
26449 <B>Shifted Value</B>
\r
26451 <TD width=35% BGCOLOR=#C0FFC0>
\r
26452 <B>Description</B>
\r
26455 <TR valign="top">
\r
26456 <TD width=15% BGCOLOR=#FBF5EF>
\r
26457 <B>PSU_IOU_SLCR_MIO_PIN_64_L0_SEL</B>
\r
26459 <TD width=15% BGCOLOR=#FBF5EF>
\r
26462 <TD width=10% BGCOLOR=#FBF5EF>
\r
26465 <TD width=10% BGCOLOR=#FBF5EF>
\r
26468 <TD width=15% BGCOLOR=#FBF5EF>
\r
26471 <TD width=35% BGCOLOR=#FBF5EF>
\r
26472 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)</B>
\r
26475 <TR valign="top">
\r
26476 <TD width=15% BGCOLOR=#FBF5EF>
\r
26477 <B>PSU_IOU_SLCR_MIO_PIN_64_L1_SEL</B>
\r
26479 <TD width=15% BGCOLOR=#FBF5EF>
\r
26482 <TD width=10% BGCOLOR=#FBF5EF>
\r
26485 <TD width=10% BGCOLOR=#FBF5EF>
\r
26488 <TD width=15% BGCOLOR=#FBF5EF>
\r
26491 <TD width=35% BGCOLOR=#FBF5EF>
\r
26492 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)</B>
\r
26495 <TR valign="top">
\r
26496 <TD width=15% BGCOLOR=#FBF5EF>
\r
26497 <B>PSU_IOU_SLCR_MIO_PIN_64_L2_SEL</B>
\r
26499 <TD width=15% BGCOLOR=#FBF5EF>
\r
26502 <TD width=10% BGCOLOR=#FBF5EF>
\r
26505 <TD width=10% BGCOLOR=#FBF5EF>
\r
26508 <TD width=15% BGCOLOR=#FBF5EF>
\r
26511 <TD width=35% BGCOLOR=#FBF5EF>
\r
26512 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used</B>
\r
26515 <TR valign="top">
\r
26516 <TD width=15% BGCOLOR=#FBF5EF>
\r
26517 <B>PSU_IOU_SLCR_MIO_PIN_64_L3_SEL</B>
\r
26519 <TD width=15% BGCOLOR=#FBF5EF>
\r
26522 <TD width=10% BGCOLOR=#FBF5EF>
\r
26525 <TD width=10% BGCOLOR=#FBF5EF>
\r
26528 <TD width=15% BGCOLOR=#FBF5EF>
\r
26531 <TD width=35% BGCOLOR=#FBF5EF>
\r
26532 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)</B>
\r
26535 <TR valign="top">
\r
26536 <TD width=15% BGCOLOR=#C0C0C0>
\r
26537 <B>PSU_IOU_SLCR_MIO_PIN_64@0XFF180100</B>
\r
26539 <TD width=15% BGCOLOR=#C0C0C0>
\r
26542 <TD width=10% BGCOLOR=#C0C0C0>
\r
26545 <TD width=10% BGCOLOR=#C0C0C0>
\r
26548 <TD width=15% BGCOLOR=#C0C0C0>
\r
26551 <TD width=35% BGCOLOR=#C0C0C0>
\r
26552 <B>Configures MIO Pin 64 peripheral interface mapping</B>
\r
26557 <H2><a name="MIO_PIN_65">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_65</a></H2>
\r
26558 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26559 <TR valign="top">
\r
26560 <TD width=15% BGCOLOR=#FFFF00>
\r
26561 <B>Register Name</B>
\r
26563 <TD width=15% BGCOLOR=#FFFF00>
\r
26566 <TD width=10% BGCOLOR=#FFFF00>
\r
26569 <TD width=10% BGCOLOR=#FFFF00>
\r
26572 <TD width=15% BGCOLOR=#FFFF00>
\r
26573 <B>Reset Value</B>
\r
26575 <TD width=35% BGCOLOR=#FFFF00>
\r
26576 <B>Description</B>
\r
26579 <TR valign="top">
\r
26580 <TD width=15% BGCOLOR=#FBF5EF>
\r
26581 <B>MIO_PIN_65</B>
\r
26583 <TD width=15% BGCOLOR=#FBF5EF>
\r
26584 <B>0XFF180104</B>
\r
26586 <TD width=10% BGCOLOR=#FBF5EF>
\r
26589 <TD width=10% BGCOLOR=#FBF5EF>
\r
26592 <TD width=15% BGCOLOR=#FBF5EF>
\r
26593 <B>0x00000000</B>
\r
26595 <TD width=35% BGCOLOR=#FBF5EF>
\r
26601 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26602 <TR valign="top">
\r
26603 <TD width=15% BGCOLOR=#C0FFC0>
\r
26604 <B>Field Name</B>
\r
26606 <TD width=15% BGCOLOR=#C0FFC0>
\r
26609 <TD width=10% BGCOLOR=#C0FFC0>
\r
26612 <TD width=10% BGCOLOR=#C0FFC0>
\r
26615 <TD width=15% BGCOLOR=#C0FFC0>
\r
26616 <B>Shifted Value</B>
\r
26618 <TD width=35% BGCOLOR=#C0FFC0>
\r
26619 <B>Description</B>
\r
26622 <TR valign="top">
\r
26623 <TD width=15% BGCOLOR=#FBF5EF>
\r
26624 <B>PSU_IOU_SLCR_MIO_PIN_65_L0_SEL</B>
\r
26626 <TD width=15% BGCOLOR=#FBF5EF>
\r
26629 <TD width=10% BGCOLOR=#FBF5EF>
\r
26632 <TD width=10% BGCOLOR=#FBF5EF>
\r
26635 <TD width=15% BGCOLOR=#FBF5EF>
\r
26638 <TD width=35% BGCOLOR=#FBF5EF>
\r
26639 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)</B>
\r
26642 <TR valign="top">
\r
26643 <TD width=15% BGCOLOR=#FBF5EF>
\r
26644 <B>PSU_IOU_SLCR_MIO_PIN_65_L1_SEL</B>
\r
26646 <TD width=15% BGCOLOR=#FBF5EF>
\r
26649 <TD width=10% BGCOLOR=#FBF5EF>
\r
26652 <TD width=10% BGCOLOR=#FBF5EF>
\r
26655 <TD width=15% BGCOLOR=#FBF5EF>
\r
26658 <TD width=35% BGCOLOR=#FBF5EF>
\r
26659 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</B>
\r
26662 <TR valign="top">
\r
26663 <TD width=15% BGCOLOR=#FBF5EF>
\r
26664 <B>PSU_IOU_SLCR_MIO_PIN_65_L2_SEL</B>
\r
26666 <TD width=15% BGCOLOR=#FBF5EF>
\r
26669 <TD width=10% BGCOLOR=#FBF5EF>
\r
26672 <TD width=10% BGCOLOR=#FBF5EF>
\r
26675 <TD width=15% BGCOLOR=#FBF5EF>
\r
26678 <TD width=35% BGCOLOR=#FBF5EF>
\r
26679 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used</B>
\r
26682 <TR valign="top">
\r
26683 <TD width=15% BGCOLOR=#FBF5EF>
\r
26684 <B>PSU_IOU_SLCR_MIO_PIN_65_L3_SEL</B>
\r
26686 <TD width=15% BGCOLOR=#FBF5EF>
\r
26689 <TD width=10% BGCOLOR=#FBF5EF>
\r
26692 <TD width=10% BGCOLOR=#FBF5EF>
\r
26695 <TD width=15% BGCOLOR=#FBF5EF>
\r
26698 <TD width=35% BGCOLOR=#FBF5EF>
\r
26699 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)</B>
\r
26702 <TR valign="top">
\r
26703 <TD width=15% BGCOLOR=#C0C0C0>
\r
26704 <B>PSU_IOU_SLCR_MIO_PIN_65@0XFF180104</B>
\r
26706 <TD width=15% BGCOLOR=#C0C0C0>
\r
26709 <TD width=10% BGCOLOR=#C0C0C0>
\r
26712 <TD width=10% BGCOLOR=#C0C0C0>
\r
26715 <TD width=15% BGCOLOR=#C0C0C0>
\r
26718 <TD width=35% BGCOLOR=#C0C0C0>
\r
26719 <B>Configures MIO Pin 65 peripheral interface mapping</B>
\r
26724 <H2><a name="MIO_PIN_66">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_66</a></H2>
\r
26725 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26726 <TR valign="top">
\r
26727 <TD width=15% BGCOLOR=#FFFF00>
\r
26728 <B>Register Name</B>
\r
26730 <TD width=15% BGCOLOR=#FFFF00>
\r
26733 <TD width=10% BGCOLOR=#FFFF00>
\r
26736 <TD width=10% BGCOLOR=#FFFF00>
\r
26739 <TD width=15% BGCOLOR=#FFFF00>
\r
26740 <B>Reset Value</B>
\r
26742 <TD width=35% BGCOLOR=#FFFF00>
\r
26743 <B>Description</B>
\r
26746 <TR valign="top">
\r
26747 <TD width=15% BGCOLOR=#FBF5EF>
\r
26748 <B>MIO_PIN_66</B>
\r
26750 <TD width=15% BGCOLOR=#FBF5EF>
\r
26751 <B>0XFF180108</B>
\r
26753 <TD width=10% BGCOLOR=#FBF5EF>
\r
26756 <TD width=10% BGCOLOR=#FBF5EF>
\r
26759 <TD width=15% BGCOLOR=#FBF5EF>
\r
26760 <B>0x00000000</B>
\r
26762 <TD width=35% BGCOLOR=#FBF5EF>
\r
26768 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26769 <TR valign="top">
\r
26770 <TD width=15% BGCOLOR=#C0FFC0>
\r
26771 <B>Field Name</B>
\r
26773 <TD width=15% BGCOLOR=#C0FFC0>
\r
26776 <TD width=10% BGCOLOR=#C0FFC0>
\r
26779 <TD width=10% BGCOLOR=#C0FFC0>
\r
26782 <TD width=15% BGCOLOR=#C0FFC0>
\r
26783 <B>Shifted Value</B>
\r
26785 <TD width=35% BGCOLOR=#C0FFC0>
\r
26786 <B>Description</B>
\r
26789 <TR valign="top">
\r
26790 <TD width=15% BGCOLOR=#FBF5EF>
\r
26791 <B>PSU_IOU_SLCR_MIO_PIN_66_L0_SEL</B>
\r
26793 <TD width=15% BGCOLOR=#FBF5EF>
\r
26796 <TD width=10% BGCOLOR=#FBF5EF>
\r
26799 <TD width=10% BGCOLOR=#FBF5EF>
\r
26802 <TD width=15% BGCOLOR=#FBF5EF>
\r
26805 <TD width=35% BGCOLOR=#FBF5EF>
\r
26806 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)</B>
\r
26809 <TR valign="top">
\r
26810 <TD width=15% BGCOLOR=#FBF5EF>
\r
26811 <B>PSU_IOU_SLCR_MIO_PIN_66_L1_SEL</B>
\r
26813 <TD width=15% BGCOLOR=#FBF5EF>
\r
26816 <TD width=10% BGCOLOR=#FBF5EF>
\r
26819 <TD width=10% BGCOLOR=#FBF5EF>
\r
26822 <TD width=15% BGCOLOR=#FBF5EF>
\r
26825 <TD width=35% BGCOLOR=#FBF5EF>
\r
26826 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)</B>
\r
26829 <TR valign="top">
\r
26830 <TD width=15% BGCOLOR=#FBF5EF>
\r
26831 <B>PSU_IOU_SLCR_MIO_PIN_66_L2_SEL</B>
\r
26833 <TD width=15% BGCOLOR=#FBF5EF>
\r
26836 <TD width=10% BGCOLOR=#FBF5EF>
\r
26839 <TD width=10% BGCOLOR=#FBF5EF>
\r
26842 <TD width=15% BGCOLOR=#FBF5EF>
\r
26845 <TD width=35% BGCOLOR=#FBF5EF>
\r
26846 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not Used 3= Not Used</B>
\r
26849 <TR valign="top">
\r
26850 <TD width=15% BGCOLOR=#FBF5EF>
\r
26851 <B>PSU_IOU_SLCR_MIO_PIN_66_L3_SEL</B>
\r
26853 <TD width=15% BGCOLOR=#FBF5EF>
\r
26856 <TD width=10% BGCOLOR=#FBF5EF>
\r
26859 <TD width=10% BGCOLOR=#FBF5EF>
\r
26862 <TD width=15% BGCOLOR=#FBF5EF>
\r
26865 <TD width=35% BGCOLOR=#FBF5EF>
\r
26866 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)</B>
\r
26869 <TR valign="top">
\r
26870 <TD width=15% BGCOLOR=#C0C0C0>
\r
26871 <B>PSU_IOU_SLCR_MIO_PIN_66@0XFF180108</B>
\r
26873 <TD width=15% BGCOLOR=#C0C0C0>
\r
26876 <TD width=10% BGCOLOR=#C0C0C0>
\r
26879 <TD width=10% BGCOLOR=#C0C0C0>
\r
26882 <TD width=15% BGCOLOR=#C0C0C0>
\r
26885 <TD width=35% BGCOLOR=#C0C0C0>
\r
26886 <B>Configures MIO Pin 66 peripheral interface mapping</B>
\r
26891 <H2><a name="MIO_PIN_67">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_67</a></H2>
\r
26892 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26893 <TR valign="top">
\r
26894 <TD width=15% BGCOLOR=#FFFF00>
\r
26895 <B>Register Name</B>
\r
26897 <TD width=15% BGCOLOR=#FFFF00>
\r
26900 <TD width=10% BGCOLOR=#FFFF00>
\r
26903 <TD width=10% BGCOLOR=#FFFF00>
\r
26906 <TD width=15% BGCOLOR=#FFFF00>
\r
26907 <B>Reset Value</B>
\r
26909 <TD width=35% BGCOLOR=#FFFF00>
\r
26910 <B>Description</B>
\r
26913 <TR valign="top">
\r
26914 <TD width=15% BGCOLOR=#FBF5EF>
\r
26915 <B>MIO_PIN_67</B>
\r
26917 <TD width=15% BGCOLOR=#FBF5EF>
\r
26918 <B>0XFF18010C</B>
\r
26920 <TD width=10% BGCOLOR=#FBF5EF>
\r
26923 <TD width=10% BGCOLOR=#FBF5EF>
\r
26926 <TD width=15% BGCOLOR=#FBF5EF>
\r
26927 <B>0x00000000</B>
\r
26929 <TD width=35% BGCOLOR=#FBF5EF>
\r
26935 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
26936 <TR valign="top">
\r
26937 <TD width=15% BGCOLOR=#C0FFC0>
\r
26938 <B>Field Name</B>
\r
26940 <TD width=15% BGCOLOR=#C0FFC0>
\r
26943 <TD width=10% BGCOLOR=#C0FFC0>
\r
26946 <TD width=10% BGCOLOR=#C0FFC0>
\r
26949 <TD width=15% BGCOLOR=#C0FFC0>
\r
26950 <B>Shifted Value</B>
\r
26952 <TD width=35% BGCOLOR=#C0FFC0>
\r
26953 <B>Description</B>
\r
26956 <TR valign="top">
\r
26957 <TD width=15% BGCOLOR=#FBF5EF>
\r
26958 <B>PSU_IOU_SLCR_MIO_PIN_67_L0_SEL</B>
\r
26960 <TD width=15% BGCOLOR=#FBF5EF>
\r
26963 <TD width=10% BGCOLOR=#FBF5EF>
\r
26966 <TD width=10% BGCOLOR=#FBF5EF>
\r
26969 <TD width=15% BGCOLOR=#FBF5EF>
\r
26972 <TD width=35% BGCOLOR=#FBF5EF>
\r
26973 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)</B>
\r
26976 <TR valign="top">
\r
26977 <TD width=15% BGCOLOR=#FBF5EF>
\r
26978 <B>PSU_IOU_SLCR_MIO_PIN_67_L1_SEL</B>
\r
26980 <TD width=15% BGCOLOR=#FBF5EF>
\r
26983 <TD width=10% BGCOLOR=#FBF5EF>
\r
26986 <TD width=10% BGCOLOR=#FBF5EF>
\r
26989 <TD width=15% BGCOLOR=#FBF5EF>
\r
26992 <TD width=35% BGCOLOR=#FBF5EF>
\r
26993 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</B>
\r
26996 <TR valign="top">
\r
26997 <TD width=15% BGCOLOR=#FBF5EF>
\r
26998 <B>PSU_IOU_SLCR_MIO_PIN_67_L2_SEL</B>
\r
27000 <TD width=15% BGCOLOR=#FBF5EF>
\r
27003 <TD width=10% BGCOLOR=#FBF5EF>
\r
27006 <TD width=10% BGCOLOR=#FBF5EF>
\r
27009 <TD width=15% BGCOLOR=#FBF5EF>
\r
27012 <TD width=35% BGCOLOR=#FBF5EF>
\r
27013 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= Not Used 3= Not Used</B>
\r
27016 <TR valign="top">
\r
27017 <TD width=15% BGCOLOR=#FBF5EF>
\r
27018 <B>PSU_IOU_SLCR_MIO_PIN_67_L3_SEL</B>
\r
27020 <TD width=15% BGCOLOR=#FBF5EF>
\r
27023 <TD width=10% BGCOLOR=#FBF5EF>
\r
27026 <TD width=10% BGCOLOR=#FBF5EF>
\r
27029 <TD width=15% BGCOLOR=#FBF5EF>
\r
27032 <TD width=35% BGCOLOR=#FBF5EF>
\r
27033 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)</B>
\r
27036 <TR valign="top">
\r
27037 <TD width=15% BGCOLOR=#C0C0C0>
\r
27038 <B>PSU_IOU_SLCR_MIO_PIN_67@0XFF18010C</B>
\r
27040 <TD width=15% BGCOLOR=#C0C0C0>
\r
27043 <TD width=10% BGCOLOR=#C0C0C0>
\r
27046 <TD width=10% BGCOLOR=#C0C0C0>
\r
27049 <TD width=15% BGCOLOR=#C0C0C0>
\r
27052 <TD width=35% BGCOLOR=#C0C0C0>
\r
27053 <B>Configures MIO Pin 67 peripheral interface mapping</B>
\r
27058 <H2><a name="MIO_PIN_68">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_68</a></H2>
\r
27059 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27060 <TR valign="top">
\r
27061 <TD width=15% BGCOLOR=#FFFF00>
\r
27062 <B>Register Name</B>
\r
27064 <TD width=15% BGCOLOR=#FFFF00>
\r
27067 <TD width=10% BGCOLOR=#FFFF00>
\r
27070 <TD width=10% BGCOLOR=#FFFF00>
\r
27073 <TD width=15% BGCOLOR=#FFFF00>
\r
27074 <B>Reset Value</B>
\r
27076 <TD width=35% BGCOLOR=#FFFF00>
\r
27077 <B>Description</B>
\r
27080 <TR valign="top">
\r
27081 <TD width=15% BGCOLOR=#FBF5EF>
\r
27082 <B>MIO_PIN_68</B>
\r
27084 <TD width=15% BGCOLOR=#FBF5EF>
\r
27085 <B>0XFF180110</B>
\r
27087 <TD width=10% BGCOLOR=#FBF5EF>
\r
27090 <TD width=10% BGCOLOR=#FBF5EF>
\r
27093 <TD width=15% BGCOLOR=#FBF5EF>
\r
27094 <B>0x00000000</B>
\r
27096 <TD width=35% BGCOLOR=#FBF5EF>
\r
27102 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27103 <TR valign="top">
\r
27104 <TD width=15% BGCOLOR=#C0FFC0>
\r
27105 <B>Field Name</B>
\r
27107 <TD width=15% BGCOLOR=#C0FFC0>
\r
27110 <TD width=10% BGCOLOR=#C0FFC0>
\r
27113 <TD width=10% BGCOLOR=#C0FFC0>
\r
27116 <TD width=15% BGCOLOR=#C0FFC0>
\r
27117 <B>Shifted Value</B>
\r
27119 <TD width=35% BGCOLOR=#C0FFC0>
\r
27120 <B>Description</B>
\r
27123 <TR valign="top">
\r
27124 <TD width=15% BGCOLOR=#FBF5EF>
\r
27125 <B>PSU_IOU_SLCR_MIO_PIN_68_L0_SEL</B>
\r
27127 <TD width=15% BGCOLOR=#FBF5EF>
\r
27130 <TD width=10% BGCOLOR=#FBF5EF>
\r
27133 <TD width=10% BGCOLOR=#FBF5EF>
\r
27136 <TD width=15% BGCOLOR=#FBF5EF>
\r
27139 <TD width=35% BGCOLOR=#FBF5EF>
\r
27140 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)</B>
\r
27143 <TR valign="top">
\r
27144 <TD width=15% BGCOLOR=#FBF5EF>
\r
27145 <B>PSU_IOU_SLCR_MIO_PIN_68_L1_SEL</B>
\r
27147 <TD width=15% BGCOLOR=#FBF5EF>
\r
27150 <TD width=10% BGCOLOR=#FBF5EF>
\r
27153 <TD width=10% BGCOLOR=#FBF5EF>
\r
27156 <TD width=15% BGCOLOR=#FBF5EF>
\r
27159 <TD width=35% BGCOLOR=#FBF5EF>
\r
27160 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</B>
\r
27163 <TR valign="top">
\r
27164 <TD width=15% BGCOLOR=#FBF5EF>
\r
27165 <B>PSU_IOU_SLCR_MIO_PIN_68_L2_SEL</B>
\r
27167 <TD width=15% BGCOLOR=#FBF5EF>
\r
27170 <TD width=10% BGCOLOR=#FBF5EF>
\r
27173 <TD width=10% BGCOLOR=#FBF5EF>
\r
27176 <TD width=15% BGCOLOR=#FBF5EF>
\r
27179 <TD width=35% BGCOLOR=#FBF5EF>
\r
27180 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= Not Used 3= Not Used</B>
\r
27183 <TR valign="top">
\r
27184 <TD width=15% BGCOLOR=#FBF5EF>
\r
27185 <B>PSU_IOU_SLCR_MIO_PIN_68_L3_SEL</B>
\r
27187 <TD width=15% BGCOLOR=#FBF5EF>
\r
27190 <TD width=10% BGCOLOR=#FBF5EF>
\r
27193 <TD width=10% BGCOLOR=#FBF5EF>
\r
27196 <TD width=15% BGCOLOR=#FBF5EF>
\r
27199 <TD width=35% BGCOLOR=#FBF5EF>
\r
27200 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)</B>
\r
27203 <TR valign="top">
\r
27204 <TD width=15% BGCOLOR=#C0C0C0>
\r
27205 <B>PSU_IOU_SLCR_MIO_PIN_68@0XFF180110</B>
\r
27207 <TD width=15% BGCOLOR=#C0C0C0>
\r
27210 <TD width=10% BGCOLOR=#C0C0C0>
\r
27213 <TD width=10% BGCOLOR=#C0C0C0>
\r
27216 <TD width=15% BGCOLOR=#C0C0C0>
\r
27219 <TD width=35% BGCOLOR=#C0C0C0>
\r
27220 <B>Configures MIO Pin 68 peripheral interface mapping</B>
\r
27225 <H2><a name="MIO_PIN_69">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_69</a></H2>
\r
27226 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27227 <TR valign="top">
\r
27228 <TD width=15% BGCOLOR=#FFFF00>
\r
27229 <B>Register Name</B>
\r
27231 <TD width=15% BGCOLOR=#FFFF00>
\r
27234 <TD width=10% BGCOLOR=#FFFF00>
\r
27237 <TD width=10% BGCOLOR=#FFFF00>
\r
27240 <TD width=15% BGCOLOR=#FFFF00>
\r
27241 <B>Reset Value</B>
\r
27243 <TD width=35% BGCOLOR=#FFFF00>
\r
27244 <B>Description</B>
\r
27247 <TR valign="top">
\r
27248 <TD width=15% BGCOLOR=#FBF5EF>
\r
27249 <B>MIO_PIN_69</B>
\r
27251 <TD width=15% BGCOLOR=#FBF5EF>
\r
27252 <B>0XFF180114</B>
\r
27254 <TD width=10% BGCOLOR=#FBF5EF>
\r
27257 <TD width=10% BGCOLOR=#FBF5EF>
\r
27260 <TD width=15% BGCOLOR=#FBF5EF>
\r
27261 <B>0x00000000</B>
\r
27263 <TD width=35% BGCOLOR=#FBF5EF>
\r
27269 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27270 <TR valign="top">
\r
27271 <TD width=15% BGCOLOR=#C0FFC0>
\r
27272 <B>Field Name</B>
\r
27274 <TD width=15% BGCOLOR=#C0FFC0>
\r
27277 <TD width=10% BGCOLOR=#C0FFC0>
\r
27280 <TD width=10% BGCOLOR=#C0FFC0>
\r
27283 <TD width=15% BGCOLOR=#C0FFC0>
\r
27284 <B>Shifted Value</B>
\r
27286 <TD width=35% BGCOLOR=#C0FFC0>
\r
27287 <B>Description</B>
\r
27290 <TR valign="top">
\r
27291 <TD width=15% BGCOLOR=#FBF5EF>
\r
27292 <B>PSU_IOU_SLCR_MIO_PIN_69_L0_SEL</B>
\r
27294 <TD width=15% BGCOLOR=#FBF5EF>
\r
27297 <TD width=10% BGCOLOR=#FBF5EF>
\r
27300 <TD width=10% BGCOLOR=#FBF5EF>
\r
27303 <TD width=15% BGCOLOR=#FBF5EF>
\r
27306 <TD width=35% BGCOLOR=#FBF5EF>
\r
27307 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)</B>
\r
27310 <TR valign="top">
\r
27311 <TD width=15% BGCOLOR=#FBF5EF>
\r
27312 <B>PSU_IOU_SLCR_MIO_PIN_69_L1_SEL</B>
\r
27314 <TD width=15% BGCOLOR=#FBF5EF>
\r
27317 <TD width=10% BGCOLOR=#FBF5EF>
\r
27320 <TD width=10% BGCOLOR=#FBF5EF>
\r
27323 <TD width=15% BGCOLOR=#FBF5EF>
\r
27326 <TD width=35% BGCOLOR=#FBF5EF>
\r
27327 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</B>
\r
27330 <TR valign="top">
\r
27331 <TD width=15% BGCOLOR=#FBF5EF>
\r
27332 <B>PSU_IOU_SLCR_MIO_PIN_69_L2_SEL</B>
\r
27334 <TD width=15% BGCOLOR=#FBF5EF>
\r
27337 <TD width=10% BGCOLOR=#FBF5EF>
\r
27340 <TD width=10% BGCOLOR=#FBF5EF>
\r
27343 <TD width=15% BGCOLOR=#FBF5EF>
\r
27346 <TD width=35% BGCOLOR=#FBF5EF>
\r
27347 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used</B>
\r
27350 <TR valign="top">
\r
27351 <TD width=15% BGCOLOR=#FBF5EF>
\r
27352 <B>PSU_IOU_SLCR_MIO_PIN_69_L3_SEL</B>
\r
27354 <TD width=15% BGCOLOR=#FBF5EF>
\r
27357 <TD width=10% BGCOLOR=#FBF5EF>
\r
27360 <TD width=10% BGCOLOR=#FBF5EF>
\r
27363 <TD width=15% BGCOLOR=#FBF5EF>
\r
27366 <TD width=35% BGCOLOR=#FBF5EF>
\r
27367 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)</B>
\r
27370 <TR valign="top">
\r
27371 <TD width=15% BGCOLOR=#C0C0C0>
\r
27372 <B>PSU_IOU_SLCR_MIO_PIN_69@0XFF180114</B>
\r
27374 <TD width=15% BGCOLOR=#C0C0C0>
\r
27377 <TD width=10% BGCOLOR=#C0C0C0>
\r
27380 <TD width=10% BGCOLOR=#C0C0C0>
\r
27383 <TD width=15% BGCOLOR=#C0C0C0>
\r
27386 <TD width=35% BGCOLOR=#C0C0C0>
\r
27387 <B>Configures MIO Pin 69 peripheral interface mapping</B>
\r
27392 <H2><a name="MIO_PIN_70">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_70</a></H2>
\r
27393 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27394 <TR valign="top">
\r
27395 <TD width=15% BGCOLOR=#FFFF00>
\r
27396 <B>Register Name</B>
\r
27398 <TD width=15% BGCOLOR=#FFFF00>
\r
27401 <TD width=10% BGCOLOR=#FFFF00>
\r
27404 <TD width=10% BGCOLOR=#FFFF00>
\r
27407 <TD width=15% BGCOLOR=#FFFF00>
\r
27408 <B>Reset Value</B>
\r
27410 <TD width=35% BGCOLOR=#FFFF00>
\r
27411 <B>Description</B>
\r
27414 <TR valign="top">
\r
27415 <TD width=15% BGCOLOR=#FBF5EF>
\r
27416 <B>MIO_PIN_70</B>
\r
27418 <TD width=15% BGCOLOR=#FBF5EF>
\r
27419 <B>0XFF180118</B>
\r
27421 <TD width=10% BGCOLOR=#FBF5EF>
\r
27424 <TD width=10% BGCOLOR=#FBF5EF>
\r
27427 <TD width=15% BGCOLOR=#FBF5EF>
\r
27428 <B>0x00000000</B>
\r
27430 <TD width=35% BGCOLOR=#FBF5EF>
\r
27436 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27437 <TR valign="top">
\r
27438 <TD width=15% BGCOLOR=#C0FFC0>
\r
27439 <B>Field Name</B>
\r
27441 <TD width=15% BGCOLOR=#C0FFC0>
\r
27444 <TD width=10% BGCOLOR=#C0FFC0>
\r
27447 <TD width=10% BGCOLOR=#C0FFC0>
\r
27450 <TD width=15% BGCOLOR=#C0FFC0>
\r
27451 <B>Shifted Value</B>
\r
27453 <TD width=35% BGCOLOR=#C0FFC0>
\r
27454 <B>Description</B>
\r
27457 <TR valign="top">
\r
27458 <TD width=15% BGCOLOR=#FBF5EF>
\r
27459 <B>PSU_IOU_SLCR_MIO_PIN_70_L0_SEL</B>
\r
27461 <TD width=15% BGCOLOR=#FBF5EF>
\r
27464 <TD width=10% BGCOLOR=#FBF5EF>
\r
27467 <TD width=10% BGCOLOR=#FBF5EF>
\r
27470 <TD width=15% BGCOLOR=#FBF5EF>
\r
27473 <TD width=35% BGCOLOR=#FBF5EF>
\r
27474 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)</B>
\r
27477 <TR valign="top">
\r
27478 <TD width=15% BGCOLOR=#FBF5EF>
\r
27479 <B>PSU_IOU_SLCR_MIO_PIN_70_L1_SEL</B>
\r
27481 <TD width=15% BGCOLOR=#FBF5EF>
\r
27484 <TD width=10% BGCOLOR=#FBF5EF>
\r
27487 <TD width=10% BGCOLOR=#FBF5EF>
\r
27490 <TD width=15% BGCOLOR=#FBF5EF>
\r
27493 <TD width=35% BGCOLOR=#FBF5EF>
\r
27494 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</B>
\r
27497 <TR valign="top">
\r
27498 <TD width=15% BGCOLOR=#FBF5EF>
\r
27499 <B>PSU_IOU_SLCR_MIO_PIN_70_L2_SEL</B>
\r
27501 <TD width=15% BGCOLOR=#FBF5EF>
\r
27504 <TD width=10% BGCOLOR=#FBF5EF>
\r
27507 <TD width=10% BGCOLOR=#FBF5EF>
\r
27510 <TD width=15% BGCOLOR=#FBF5EF>
\r
27513 <TD width=35% BGCOLOR=#FBF5EF>
\r
27514 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used</B>
\r
27517 <TR valign="top">
\r
27518 <TD width=15% BGCOLOR=#FBF5EF>
\r
27519 <B>PSU_IOU_SLCR_MIO_PIN_70_L3_SEL</B>
\r
27521 <TD width=15% BGCOLOR=#FBF5EF>
\r
27524 <TD width=10% BGCOLOR=#FBF5EF>
\r
27527 <TD width=10% BGCOLOR=#FBF5EF>
\r
27530 <TD width=15% BGCOLOR=#FBF5EF>
\r
27533 <TD width=35% BGCOLOR=#FBF5EF>
\r
27534 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
27537 <TR valign="top">
\r
27538 <TD width=15% BGCOLOR=#C0C0C0>
\r
27539 <B>PSU_IOU_SLCR_MIO_PIN_70@0XFF180118</B>
\r
27541 <TD width=15% BGCOLOR=#C0C0C0>
\r
27544 <TD width=10% BGCOLOR=#C0C0C0>
\r
27547 <TD width=10% BGCOLOR=#C0C0C0>
\r
27550 <TD width=15% BGCOLOR=#C0C0C0>
\r
27553 <TD width=35% BGCOLOR=#C0C0C0>
\r
27554 <B>Configures MIO Pin 70 peripheral interface mapping</B>
\r
27559 <H2><a name="MIO_PIN_71">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_71</a></H2>
\r
27560 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27561 <TR valign="top">
\r
27562 <TD width=15% BGCOLOR=#FFFF00>
\r
27563 <B>Register Name</B>
\r
27565 <TD width=15% BGCOLOR=#FFFF00>
\r
27568 <TD width=10% BGCOLOR=#FFFF00>
\r
27571 <TD width=10% BGCOLOR=#FFFF00>
\r
27574 <TD width=15% BGCOLOR=#FFFF00>
\r
27575 <B>Reset Value</B>
\r
27577 <TD width=35% BGCOLOR=#FFFF00>
\r
27578 <B>Description</B>
\r
27581 <TR valign="top">
\r
27582 <TD width=15% BGCOLOR=#FBF5EF>
\r
27583 <B>MIO_PIN_71</B>
\r
27585 <TD width=15% BGCOLOR=#FBF5EF>
\r
27586 <B>0XFF18011C</B>
\r
27588 <TD width=10% BGCOLOR=#FBF5EF>
\r
27591 <TD width=10% BGCOLOR=#FBF5EF>
\r
27594 <TD width=15% BGCOLOR=#FBF5EF>
\r
27595 <B>0x00000000</B>
\r
27597 <TD width=35% BGCOLOR=#FBF5EF>
\r
27603 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27604 <TR valign="top">
\r
27605 <TD width=15% BGCOLOR=#C0FFC0>
\r
27606 <B>Field Name</B>
\r
27608 <TD width=15% BGCOLOR=#C0FFC0>
\r
27611 <TD width=10% BGCOLOR=#C0FFC0>
\r
27614 <TD width=10% BGCOLOR=#C0FFC0>
\r
27617 <TD width=15% BGCOLOR=#C0FFC0>
\r
27618 <B>Shifted Value</B>
\r
27620 <TD width=35% BGCOLOR=#C0FFC0>
\r
27621 <B>Description</B>
\r
27624 <TR valign="top">
\r
27625 <TD width=15% BGCOLOR=#FBF5EF>
\r
27626 <B>PSU_IOU_SLCR_MIO_PIN_71_L0_SEL</B>
\r
27628 <TD width=15% BGCOLOR=#FBF5EF>
\r
27631 <TD width=10% BGCOLOR=#FBF5EF>
\r
27634 <TD width=10% BGCOLOR=#FBF5EF>
\r
27637 <TD width=15% BGCOLOR=#FBF5EF>
\r
27640 <TD width=35% BGCOLOR=#FBF5EF>
\r
27641 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)</B>
\r
27644 <TR valign="top">
\r
27645 <TD width=15% BGCOLOR=#FBF5EF>
\r
27646 <B>PSU_IOU_SLCR_MIO_PIN_71_L1_SEL</B>
\r
27648 <TD width=15% BGCOLOR=#FBF5EF>
\r
27651 <TD width=10% BGCOLOR=#FBF5EF>
\r
27654 <TD width=10% BGCOLOR=#FBF5EF>
\r
27657 <TD width=15% BGCOLOR=#FBF5EF>
\r
27660 <TD width=35% BGCOLOR=#FBF5EF>
\r
27661 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)</B>
\r
27664 <TR valign="top">
\r
27665 <TD width=15% BGCOLOR=#FBF5EF>
\r
27666 <B>PSU_IOU_SLCR_MIO_PIN_71_L2_SEL</B>
\r
27668 <TD width=15% BGCOLOR=#FBF5EF>
\r
27671 <TD width=10% BGCOLOR=#FBF5EF>
\r
27674 <TD width=10% BGCOLOR=#FBF5EF>
\r
27677 <TD width=15% BGCOLOR=#FBF5EF>
\r
27680 <TD width=35% BGCOLOR=#FBF5EF>
\r
27681 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used</B>
\r
27684 <TR valign="top">
\r
27685 <TD width=15% BGCOLOR=#FBF5EF>
\r
27686 <B>PSU_IOU_SLCR_MIO_PIN_71_L3_SEL</B>
\r
27688 <TD width=15% BGCOLOR=#FBF5EF>
\r
27691 <TD width=10% BGCOLOR=#FBF5EF>
\r
27694 <TD width=10% BGCOLOR=#FBF5EF>
\r
27697 <TD width=15% BGCOLOR=#FBF5EF>
\r
27700 <TD width=35% BGCOLOR=#FBF5EF>
\r
27701 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
27704 <TR valign="top">
\r
27705 <TD width=15% BGCOLOR=#C0C0C0>
\r
27706 <B>PSU_IOU_SLCR_MIO_PIN_71@0XFF18011C</B>
\r
27708 <TD width=15% BGCOLOR=#C0C0C0>
\r
27711 <TD width=10% BGCOLOR=#C0C0C0>
\r
27714 <TD width=10% BGCOLOR=#C0C0C0>
\r
27717 <TD width=15% BGCOLOR=#C0C0C0>
\r
27720 <TD width=35% BGCOLOR=#C0C0C0>
\r
27721 <B>Configures MIO Pin 71 peripheral interface mapping</B>
\r
27726 <H2><a name="MIO_PIN_72">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_72</a></H2>
\r
27727 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27728 <TR valign="top">
\r
27729 <TD width=15% BGCOLOR=#FFFF00>
\r
27730 <B>Register Name</B>
\r
27732 <TD width=15% BGCOLOR=#FFFF00>
\r
27735 <TD width=10% BGCOLOR=#FFFF00>
\r
27738 <TD width=10% BGCOLOR=#FFFF00>
\r
27741 <TD width=15% BGCOLOR=#FFFF00>
\r
27742 <B>Reset Value</B>
\r
27744 <TD width=35% BGCOLOR=#FFFF00>
\r
27745 <B>Description</B>
\r
27748 <TR valign="top">
\r
27749 <TD width=15% BGCOLOR=#FBF5EF>
\r
27750 <B>MIO_PIN_72</B>
\r
27752 <TD width=15% BGCOLOR=#FBF5EF>
\r
27753 <B>0XFF180120</B>
\r
27755 <TD width=10% BGCOLOR=#FBF5EF>
\r
27758 <TD width=10% BGCOLOR=#FBF5EF>
\r
27761 <TD width=15% BGCOLOR=#FBF5EF>
\r
27762 <B>0x00000000</B>
\r
27764 <TD width=35% BGCOLOR=#FBF5EF>
\r
27770 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27771 <TR valign="top">
\r
27772 <TD width=15% BGCOLOR=#C0FFC0>
\r
27773 <B>Field Name</B>
\r
27775 <TD width=15% BGCOLOR=#C0FFC0>
\r
27778 <TD width=10% BGCOLOR=#C0FFC0>
\r
27781 <TD width=10% BGCOLOR=#C0FFC0>
\r
27784 <TD width=15% BGCOLOR=#C0FFC0>
\r
27785 <B>Shifted Value</B>
\r
27787 <TD width=35% BGCOLOR=#C0FFC0>
\r
27788 <B>Description</B>
\r
27791 <TR valign="top">
\r
27792 <TD width=15% BGCOLOR=#FBF5EF>
\r
27793 <B>PSU_IOU_SLCR_MIO_PIN_72_L0_SEL</B>
\r
27795 <TD width=15% BGCOLOR=#FBF5EF>
\r
27798 <TD width=10% BGCOLOR=#FBF5EF>
\r
27801 <TD width=10% BGCOLOR=#FBF5EF>
\r
27804 <TD width=15% BGCOLOR=#FBF5EF>
\r
27807 <TD width=35% BGCOLOR=#FBF5EF>
\r
27808 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)</B>
\r
27811 <TR valign="top">
\r
27812 <TD width=15% BGCOLOR=#FBF5EF>
\r
27813 <B>PSU_IOU_SLCR_MIO_PIN_72_L1_SEL</B>
\r
27815 <TD width=15% BGCOLOR=#FBF5EF>
\r
27818 <TD width=10% BGCOLOR=#FBF5EF>
\r
27821 <TD width=10% BGCOLOR=#FBF5EF>
\r
27824 <TD width=15% BGCOLOR=#FBF5EF>
\r
27827 <TD width=35% BGCOLOR=#FBF5EF>
\r
27828 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</B>
\r
27831 <TR valign="top">
\r
27832 <TD width=15% BGCOLOR=#FBF5EF>
\r
27833 <B>PSU_IOU_SLCR_MIO_PIN_72_L2_SEL</B>
\r
27835 <TD width=15% BGCOLOR=#FBF5EF>
\r
27838 <TD width=10% BGCOLOR=#FBF5EF>
\r
27841 <TD width=10% BGCOLOR=#FBF5EF>
\r
27844 <TD width=15% BGCOLOR=#FBF5EF>
\r
27847 <TD width=35% BGCOLOR=#FBF5EF>
\r
27848 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used</B>
\r
27851 <TR valign="top">
\r
27852 <TD width=15% BGCOLOR=#FBF5EF>
\r
27853 <B>PSU_IOU_SLCR_MIO_PIN_72_L3_SEL</B>
\r
27855 <TD width=15% BGCOLOR=#FBF5EF>
\r
27858 <TD width=10% BGCOLOR=#FBF5EF>
\r
27861 <TD width=10% BGCOLOR=#FBF5EF>
\r
27864 <TD width=15% BGCOLOR=#FBF5EF>
\r
27867 <TD width=35% BGCOLOR=#FBF5EF>
\r
27868 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used</B>
\r
27871 <TR valign="top">
\r
27872 <TD width=15% BGCOLOR=#C0C0C0>
\r
27873 <B>PSU_IOU_SLCR_MIO_PIN_72@0XFF180120</B>
\r
27875 <TD width=15% BGCOLOR=#C0C0C0>
\r
27878 <TD width=10% BGCOLOR=#C0C0C0>
\r
27881 <TD width=10% BGCOLOR=#C0C0C0>
\r
27884 <TD width=15% BGCOLOR=#C0C0C0>
\r
27887 <TD width=35% BGCOLOR=#C0C0C0>
\r
27888 <B>Configures MIO Pin 72 peripheral interface mapping</B>
\r
27893 <H2><a name="MIO_PIN_73">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_73</a></H2>
\r
27894 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27895 <TR valign="top">
\r
27896 <TD width=15% BGCOLOR=#FFFF00>
\r
27897 <B>Register Name</B>
\r
27899 <TD width=15% BGCOLOR=#FFFF00>
\r
27902 <TD width=10% BGCOLOR=#FFFF00>
\r
27905 <TD width=10% BGCOLOR=#FFFF00>
\r
27908 <TD width=15% BGCOLOR=#FFFF00>
\r
27909 <B>Reset Value</B>
\r
27911 <TD width=35% BGCOLOR=#FFFF00>
\r
27912 <B>Description</B>
\r
27915 <TR valign="top">
\r
27916 <TD width=15% BGCOLOR=#FBF5EF>
\r
27917 <B>MIO_PIN_73</B>
\r
27919 <TD width=15% BGCOLOR=#FBF5EF>
\r
27920 <B>0XFF180124</B>
\r
27922 <TD width=10% BGCOLOR=#FBF5EF>
\r
27925 <TD width=10% BGCOLOR=#FBF5EF>
\r
27928 <TD width=15% BGCOLOR=#FBF5EF>
\r
27929 <B>0x00000000</B>
\r
27931 <TD width=35% BGCOLOR=#FBF5EF>
\r
27937 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
27938 <TR valign="top">
\r
27939 <TD width=15% BGCOLOR=#C0FFC0>
\r
27940 <B>Field Name</B>
\r
27942 <TD width=15% BGCOLOR=#C0FFC0>
\r
27945 <TD width=10% BGCOLOR=#C0FFC0>
\r
27948 <TD width=10% BGCOLOR=#C0FFC0>
\r
27951 <TD width=15% BGCOLOR=#C0FFC0>
\r
27952 <B>Shifted Value</B>
\r
27954 <TD width=35% BGCOLOR=#C0FFC0>
\r
27955 <B>Description</B>
\r
27958 <TR valign="top">
\r
27959 <TD width=15% BGCOLOR=#FBF5EF>
\r
27960 <B>PSU_IOU_SLCR_MIO_PIN_73_L0_SEL</B>
\r
27962 <TD width=15% BGCOLOR=#FBF5EF>
\r
27965 <TD width=10% BGCOLOR=#FBF5EF>
\r
27968 <TD width=10% BGCOLOR=#FBF5EF>
\r
27971 <TD width=15% BGCOLOR=#FBF5EF>
\r
27974 <TD width=35% BGCOLOR=#FBF5EF>
\r
27975 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)</B>
\r
27978 <TR valign="top">
\r
27979 <TD width=15% BGCOLOR=#FBF5EF>
\r
27980 <B>PSU_IOU_SLCR_MIO_PIN_73_L1_SEL</B>
\r
27982 <TD width=15% BGCOLOR=#FBF5EF>
\r
27985 <TD width=10% BGCOLOR=#FBF5EF>
\r
27988 <TD width=10% BGCOLOR=#FBF5EF>
\r
27991 <TD width=15% BGCOLOR=#FBF5EF>
\r
27994 <TD width=35% BGCOLOR=#FBF5EF>
\r
27995 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</B>
\r
27998 <TR valign="top">
\r
27999 <TD width=15% BGCOLOR=#FBF5EF>
\r
28000 <B>PSU_IOU_SLCR_MIO_PIN_73_L2_SEL</B>
\r
28002 <TD width=15% BGCOLOR=#FBF5EF>
\r
28005 <TD width=10% BGCOLOR=#FBF5EF>
\r
28008 <TD width=10% BGCOLOR=#FBF5EF>
\r
28011 <TD width=15% BGCOLOR=#FBF5EF>
\r
28014 <TD width=35% BGCOLOR=#FBF5EF>
\r
28015 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used</B>
\r
28018 <TR valign="top">
\r
28019 <TD width=15% BGCOLOR=#FBF5EF>
\r
28020 <B>PSU_IOU_SLCR_MIO_PIN_73_L3_SEL</B>
\r
28022 <TD width=15% BGCOLOR=#FBF5EF>
\r
28025 <TD width=10% BGCOLOR=#FBF5EF>
\r
28028 <TD width=10% BGCOLOR=#FBF5EF>
\r
28031 <TD width=15% BGCOLOR=#FBF5EF>
\r
28034 <TD width=35% BGCOLOR=#FBF5EF>
\r
28035 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used</B>
\r
28038 <TR valign="top">
\r
28039 <TD width=15% BGCOLOR=#C0C0C0>
\r
28040 <B>PSU_IOU_SLCR_MIO_PIN_73@0XFF180124</B>
\r
28042 <TD width=15% BGCOLOR=#C0C0C0>
\r
28045 <TD width=10% BGCOLOR=#C0C0C0>
\r
28048 <TD width=10% BGCOLOR=#C0C0C0>
\r
28051 <TD width=15% BGCOLOR=#C0C0C0>
\r
28054 <TD width=35% BGCOLOR=#C0C0C0>
\r
28055 <B>Configures MIO Pin 73 peripheral interface mapping</B>
\r
28060 <H2><a name="MIO_PIN_74">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_74</a></H2>
\r
28061 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28062 <TR valign="top">
\r
28063 <TD width=15% BGCOLOR=#FFFF00>
\r
28064 <B>Register Name</B>
\r
28066 <TD width=15% BGCOLOR=#FFFF00>
\r
28069 <TD width=10% BGCOLOR=#FFFF00>
\r
28072 <TD width=10% BGCOLOR=#FFFF00>
\r
28075 <TD width=15% BGCOLOR=#FFFF00>
\r
28076 <B>Reset Value</B>
\r
28078 <TD width=35% BGCOLOR=#FFFF00>
\r
28079 <B>Description</B>
\r
28082 <TR valign="top">
\r
28083 <TD width=15% BGCOLOR=#FBF5EF>
\r
28084 <B>MIO_PIN_74</B>
\r
28086 <TD width=15% BGCOLOR=#FBF5EF>
\r
28087 <B>0XFF180128</B>
\r
28089 <TD width=10% BGCOLOR=#FBF5EF>
\r
28092 <TD width=10% BGCOLOR=#FBF5EF>
\r
28095 <TD width=15% BGCOLOR=#FBF5EF>
\r
28096 <B>0x00000000</B>
\r
28098 <TD width=35% BGCOLOR=#FBF5EF>
\r
28104 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28105 <TR valign="top">
\r
28106 <TD width=15% BGCOLOR=#C0FFC0>
\r
28107 <B>Field Name</B>
\r
28109 <TD width=15% BGCOLOR=#C0FFC0>
\r
28112 <TD width=10% BGCOLOR=#C0FFC0>
\r
28115 <TD width=10% BGCOLOR=#C0FFC0>
\r
28118 <TD width=15% BGCOLOR=#C0FFC0>
\r
28119 <B>Shifted Value</B>
\r
28121 <TD width=35% BGCOLOR=#C0FFC0>
\r
28122 <B>Description</B>
\r
28125 <TR valign="top">
\r
28126 <TD width=15% BGCOLOR=#FBF5EF>
\r
28127 <B>PSU_IOU_SLCR_MIO_PIN_74_L0_SEL</B>
\r
28129 <TD width=15% BGCOLOR=#FBF5EF>
\r
28132 <TD width=10% BGCOLOR=#FBF5EF>
\r
28135 <TD width=10% BGCOLOR=#FBF5EF>
\r
28138 <TD width=15% BGCOLOR=#FBF5EF>
\r
28141 <TD width=35% BGCOLOR=#FBF5EF>
\r
28142 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)</B>
\r
28145 <TR valign="top">
\r
28146 <TD width=15% BGCOLOR=#FBF5EF>
\r
28147 <B>PSU_IOU_SLCR_MIO_PIN_74_L1_SEL</B>
\r
28149 <TD width=15% BGCOLOR=#FBF5EF>
\r
28152 <TD width=10% BGCOLOR=#FBF5EF>
\r
28155 <TD width=10% BGCOLOR=#FBF5EF>
\r
28158 <TD width=15% BGCOLOR=#FBF5EF>
\r
28161 <TD width=35% BGCOLOR=#FBF5EF>
\r
28162 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)</B>
\r
28165 <TR valign="top">
\r
28166 <TD width=15% BGCOLOR=#FBF5EF>
\r
28167 <B>PSU_IOU_SLCR_MIO_PIN_74_L2_SEL</B>
\r
28169 <TD width=15% BGCOLOR=#FBF5EF>
\r
28172 <TD width=10% BGCOLOR=#FBF5EF>
\r
28175 <TD width=10% BGCOLOR=#FBF5EF>
\r
28178 <TD width=15% BGCOLOR=#FBF5EF>
\r
28181 <TD width=35% BGCOLOR=#FBF5EF>
\r
28182 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used</B>
\r
28185 <TR valign="top">
\r
28186 <TD width=15% BGCOLOR=#FBF5EF>
\r
28187 <B>PSU_IOU_SLCR_MIO_PIN_74_L3_SEL</B>
\r
28189 <TD width=15% BGCOLOR=#FBF5EF>
\r
28192 <TD width=10% BGCOLOR=#FBF5EF>
\r
28195 <TD width=10% BGCOLOR=#FBF5EF>
\r
28198 <TD width=15% BGCOLOR=#FBF5EF>
\r
28201 <TD width=35% BGCOLOR=#FBF5EF>
\r
28202 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used</B>
\r
28205 <TR valign="top">
\r
28206 <TD width=15% BGCOLOR=#C0C0C0>
\r
28207 <B>PSU_IOU_SLCR_MIO_PIN_74@0XFF180128</B>
\r
28209 <TD width=15% BGCOLOR=#C0C0C0>
\r
28212 <TD width=10% BGCOLOR=#C0C0C0>
\r
28215 <TD width=10% BGCOLOR=#C0C0C0>
\r
28218 <TD width=15% BGCOLOR=#C0C0C0>
\r
28221 <TD width=35% BGCOLOR=#C0C0C0>
\r
28222 <B>Configures MIO Pin 74 peripheral interface mapping</B>
\r
28227 <H2><a name="MIO_PIN_75">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_75</a></H2>
\r
28228 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28229 <TR valign="top">
\r
28230 <TD width=15% BGCOLOR=#FFFF00>
\r
28231 <B>Register Name</B>
\r
28233 <TD width=15% BGCOLOR=#FFFF00>
\r
28236 <TD width=10% BGCOLOR=#FFFF00>
\r
28239 <TD width=10% BGCOLOR=#FFFF00>
\r
28242 <TD width=15% BGCOLOR=#FFFF00>
\r
28243 <B>Reset Value</B>
\r
28245 <TD width=35% BGCOLOR=#FFFF00>
\r
28246 <B>Description</B>
\r
28249 <TR valign="top">
\r
28250 <TD width=15% BGCOLOR=#FBF5EF>
\r
28251 <B>MIO_PIN_75</B>
\r
28253 <TD width=15% BGCOLOR=#FBF5EF>
\r
28254 <B>0XFF18012C</B>
\r
28256 <TD width=10% BGCOLOR=#FBF5EF>
\r
28259 <TD width=10% BGCOLOR=#FBF5EF>
\r
28262 <TD width=15% BGCOLOR=#FBF5EF>
\r
28263 <B>0x00000000</B>
\r
28265 <TD width=35% BGCOLOR=#FBF5EF>
\r
28271 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28272 <TR valign="top">
\r
28273 <TD width=15% BGCOLOR=#C0FFC0>
\r
28274 <B>Field Name</B>
\r
28276 <TD width=15% BGCOLOR=#C0FFC0>
\r
28279 <TD width=10% BGCOLOR=#C0FFC0>
\r
28282 <TD width=10% BGCOLOR=#C0FFC0>
\r
28285 <TD width=15% BGCOLOR=#C0FFC0>
\r
28286 <B>Shifted Value</B>
\r
28288 <TD width=35% BGCOLOR=#C0FFC0>
\r
28289 <B>Description</B>
\r
28292 <TR valign="top">
\r
28293 <TD width=15% BGCOLOR=#FBF5EF>
\r
28294 <B>PSU_IOU_SLCR_MIO_PIN_75_L0_SEL</B>
\r
28296 <TD width=15% BGCOLOR=#FBF5EF>
\r
28299 <TD width=10% BGCOLOR=#FBF5EF>
\r
28302 <TD width=10% BGCOLOR=#FBF5EF>
\r
28305 <TD width=15% BGCOLOR=#FBF5EF>
\r
28308 <TD width=35% BGCOLOR=#FBF5EF>
\r
28309 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )</B>
\r
28312 <TR valign="top">
\r
28313 <TD width=15% BGCOLOR=#FBF5EF>
\r
28314 <B>PSU_IOU_SLCR_MIO_PIN_75_L1_SEL</B>
\r
28316 <TD width=15% BGCOLOR=#FBF5EF>
\r
28319 <TD width=10% BGCOLOR=#FBF5EF>
\r
28322 <TD width=10% BGCOLOR=#FBF5EF>
\r
28325 <TD width=15% BGCOLOR=#FBF5EF>
\r
28328 <TD width=35% BGCOLOR=#FBF5EF>
\r
28329 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</B>
\r
28332 <TR valign="top">
\r
28333 <TD width=15% BGCOLOR=#FBF5EF>
\r
28334 <B>PSU_IOU_SLCR_MIO_PIN_75_L2_SEL</B>
\r
28336 <TD width=15% BGCOLOR=#FBF5EF>
\r
28339 <TD width=10% BGCOLOR=#FBF5EF>
\r
28342 <TD width=10% BGCOLOR=#FBF5EF>
\r
28345 <TD width=15% BGCOLOR=#FBF5EF>
\r
28348 <TD width=35% BGCOLOR=#FBF5EF>
\r
28349 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used</B>
\r
28352 <TR valign="top">
\r
28353 <TD width=15% BGCOLOR=#FBF5EF>
\r
28354 <B>PSU_IOU_SLCR_MIO_PIN_75_L3_SEL</B>
\r
28356 <TD width=15% BGCOLOR=#FBF5EF>
\r
28359 <TD width=10% BGCOLOR=#FBF5EF>
\r
28362 <TD width=10% BGCOLOR=#FBF5EF>
\r
28365 <TD width=15% BGCOLOR=#FBF5EF>
\r
28368 <TD width=35% BGCOLOR=#FBF5EF>
\r
28369 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used</B>
\r
28372 <TR valign="top">
\r
28373 <TD width=15% BGCOLOR=#C0C0C0>
\r
28374 <B>PSU_IOU_SLCR_MIO_PIN_75@0XFF18012C</B>
\r
28376 <TD width=15% BGCOLOR=#C0C0C0>
\r
28379 <TD width=10% BGCOLOR=#C0C0C0>
\r
28382 <TD width=10% BGCOLOR=#C0C0C0>
\r
28385 <TD width=15% BGCOLOR=#C0C0C0>
\r
28388 <TD width=35% BGCOLOR=#C0C0C0>
\r
28389 <B>Configures MIO Pin 75 peripheral interface mapping</B>
\r
28394 <H2><a name="MIO_PIN_76">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_76</a></H2>
\r
28395 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28396 <TR valign="top">
\r
28397 <TD width=15% BGCOLOR=#FFFF00>
\r
28398 <B>Register Name</B>
\r
28400 <TD width=15% BGCOLOR=#FFFF00>
\r
28403 <TD width=10% BGCOLOR=#FFFF00>
\r
28406 <TD width=10% BGCOLOR=#FFFF00>
\r
28409 <TD width=15% BGCOLOR=#FFFF00>
\r
28410 <B>Reset Value</B>
\r
28412 <TD width=35% BGCOLOR=#FFFF00>
\r
28413 <B>Description</B>
\r
28416 <TR valign="top">
\r
28417 <TD width=15% BGCOLOR=#FBF5EF>
\r
28418 <B>MIO_PIN_76</B>
\r
28420 <TD width=15% BGCOLOR=#FBF5EF>
\r
28421 <B>0XFF180130</B>
\r
28423 <TD width=10% BGCOLOR=#FBF5EF>
\r
28426 <TD width=10% BGCOLOR=#FBF5EF>
\r
28429 <TD width=15% BGCOLOR=#FBF5EF>
\r
28430 <B>0x00000000</B>
\r
28432 <TD width=35% BGCOLOR=#FBF5EF>
\r
28438 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28439 <TR valign="top">
\r
28440 <TD width=15% BGCOLOR=#C0FFC0>
\r
28441 <B>Field Name</B>
\r
28443 <TD width=15% BGCOLOR=#C0FFC0>
\r
28446 <TD width=10% BGCOLOR=#C0FFC0>
\r
28449 <TD width=10% BGCOLOR=#C0FFC0>
\r
28452 <TD width=15% BGCOLOR=#C0FFC0>
\r
28453 <B>Shifted Value</B>
\r
28455 <TD width=35% BGCOLOR=#C0FFC0>
\r
28456 <B>Description</B>
\r
28459 <TR valign="top">
\r
28460 <TD width=15% BGCOLOR=#FBF5EF>
\r
28461 <B>PSU_IOU_SLCR_MIO_PIN_76_L0_SEL</B>
\r
28463 <TD width=15% BGCOLOR=#FBF5EF>
\r
28466 <TD width=10% BGCOLOR=#FBF5EF>
\r
28469 <TD width=10% BGCOLOR=#FBF5EF>
\r
28472 <TD width=15% BGCOLOR=#FBF5EF>
\r
28475 <TD width=35% BGCOLOR=#FBF5EF>
\r
28476 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
28479 <TR valign="top">
\r
28480 <TD width=15% BGCOLOR=#FBF5EF>
\r
28481 <B>PSU_IOU_SLCR_MIO_PIN_76_L1_SEL</B>
\r
28483 <TD width=15% BGCOLOR=#FBF5EF>
\r
28486 <TD width=10% BGCOLOR=#FBF5EF>
\r
28489 <TD width=10% BGCOLOR=#FBF5EF>
\r
28492 <TD width=15% BGCOLOR=#FBF5EF>
\r
28495 <TD width=35% BGCOLOR=#FBF5EF>
\r
28496 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
28499 <TR valign="top">
\r
28500 <TD width=15% BGCOLOR=#FBF5EF>
\r
28501 <B>PSU_IOU_SLCR_MIO_PIN_76_L2_SEL</B>
\r
28503 <TD width=15% BGCOLOR=#FBF5EF>
\r
28506 <TD width=10% BGCOLOR=#FBF5EF>
\r
28509 <TD width=10% BGCOLOR=#FBF5EF>
\r
28512 <TD width=15% BGCOLOR=#FBF5EF>
\r
28515 <TD width=35% BGCOLOR=#FBF5EF>
\r
28516 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used</B>
\r
28519 <TR valign="top">
\r
28520 <TD width=15% BGCOLOR=#FBF5EF>
\r
28521 <B>PSU_IOU_SLCR_MIO_PIN_76_L3_SEL</B>
\r
28523 <TD width=15% BGCOLOR=#FBF5EF>
\r
28526 <TD width=10% BGCOLOR=#FBF5EF>
\r
28529 <TD width=10% BGCOLOR=#FBF5EF>
\r
28532 <TD width=15% BGCOLOR=#FBF5EF>
\r
28535 <TD width=35% BGCOLOR=#FBF5EF>
\r
28536 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used</B>
\r
28539 <TR valign="top">
\r
28540 <TD width=15% BGCOLOR=#C0C0C0>
\r
28541 <B>PSU_IOU_SLCR_MIO_PIN_76@0XFF180130</B>
\r
28543 <TD width=15% BGCOLOR=#C0C0C0>
\r
28546 <TD width=10% BGCOLOR=#C0C0C0>
\r
28549 <TD width=10% BGCOLOR=#C0C0C0>
\r
28552 <TD width=15% BGCOLOR=#C0C0C0>
\r
28555 <TD width=35% BGCOLOR=#C0C0C0>
\r
28556 <B>Configures MIO Pin 76 peripheral interface mapping</B>
\r
28561 <H2><a name="MIO_PIN_77">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_77</a></H2>
\r
28562 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28563 <TR valign="top">
\r
28564 <TD width=15% BGCOLOR=#FFFF00>
\r
28565 <B>Register Name</B>
\r
28567 <TD width=15% BGCOLOR=#FFFF00>
\r
28570 <TD width=10% BGCOLOR=#FFFF00>
\r
28573 <TD width=10% BGCOLOR=#FFFF00>
\r
28576 <TD width=15% BGCOLOR=#FFFF00>
\r
28577 <B>Reset Value</B>
\r
28579 <TD width=35% BGCOLOR=#FFFF00>
\r
28580 <B>Description</B>
\r
28583 <TR valign="top">
\r
28584 <TD width=15% BGCOLOR=#FBF5EF>
\r
28585 <B>MIO_PIN_77</B>
\r
28587 <TD width=15% BGCOLOR=#FBF5EF>
\r
28588 <B>0XFF180134</B>
\r
28590 <TD width=10% BGCOLOR=#FBF5EF>
\r
28593 <TD width=10% BGCOLOR=#FBF5EF>
\r
28596 <TD width=15% BGCOLOR=#FBF5EF>
\r
28597 <B>0x00000000</B>
\r
28599 <TD width=35% BGCOLOR=#FBF5EF>
\r
28605 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28606 <TR valign="top">
\r
28607 <TD width=15% BGCOLOR=#C0FFC0>
\r
28608 <B>Field Name</B>
\r
28610 <TD width=15% BGCOLOR=#C0FFC0>
\r
28613 <TD width=10% BGCOLOR=#C0FFC0>
\r
28616 <TD width=10% BGCOLOR=#C0FFC0>
\r
28619 <TD width=15% BGCOLOR=#C0FFC0>
\r
28620 <B>Shifted Value</B>
\r
28622 <TD width=35% BGCOLOR=#C0FFC0>
\r
28623 <B>Description</B>
\r
28626 <TR valign="top">
\r
28627 <TD width=15% BGCOLOR=#FBF5EF>
\r
28628 <B>PSU_IOU_SLCR_MIO_PIN_77_L0_SEL</B>
\r
28630 <TD width=15% BGCOLOR=#FBF5EF>
\r
28633 <TD width=10% BGCOLOR=#FBF5EF>
\r
28636 <TD width=10% BGCOLOR=#FBF5EF>
\r
28639 <TD width=15% BGCOLOR=#FBF5EF>
\r
28642 <TD width=35% BGCOLOR=#FBF5EF>
\r
28643 <B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
\r
28646 <TR valign="top">
\r
28647 <TD width=15% BGCOLOR=#FBF5EF>
\r
28648 <B>PSU_IOU_SLCR_MIO_PIN_77_L1_SEL</B>
\r
28650 <TD width=15% BGCOLOR=#FBF5EF>
\r
28653 <TD width=10% BGCOLOR=#FBF5EF>
\r
28656 <TD width=10% BGCOLOR=#FBF5EF>
\r
28659 <TD width=15% BGCOLOR=#FBF5EF>
\r
28662 <TD width=35% BGCOLOR=#FBF5EF>
\r
28663 <B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
\r
28666 <TR valign="top">
\r
28667 <TD width=15% BGCOLOR=#FBF5EF>
\r
28668 <B>PSU_IOU_SLCR_MIO_PIN_77_L2_SEL</B>
\r
28670 <TD width=15% BGCOLOR=#FBF5EF>
\r
28673 <TD width=10% BGCOLOR=#FBF5EF>
\r
28676 <TD width=10% BGCOLOR=#FBF5EF>
\r
28679 <TD width=15% BGCOLOR=#FBF5EF>
\r
28682 <TD width=35% BGCOLOR=#FBF5EF>
\r
28683 <B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used</B>
\r
28686 <TR valign="top">
\r
28687 <TD width=15% BGCOLOR=#FBF5EF>
\r
28688 <B>PSU_IOU_SLCR_MIO_PIN_77_L3_SEL</B>
\r
28690 <TD width=15% BGCOLOR=#FBF5EF>
\r
28693 <TD width=10% BGCOLOR=#FBF5EF>
\r
28696 <TD width=10% BGCOLOR=#FBF5EF>
\r
28699 <TD width=15% BGCOLOR=#FBF5EF>
\r
28702 <TD width=35% BGCOLOR=#FBF5EF>
\r
28703 <B>Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_out- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used</B>
\r
28706 <TR valign="top">
\r
28707 <TD width=15% BGCOLOR=#C0C0C0>
\r
28708 <B>PSU_IOU_SLCR_MIO_PIN_77@0XFF180134</B>
\r
28710 <TD width=15% BGCOLOR=#C0C0C0>
\r
28713 <TD width=10% BGCOLOR=#C0C0C0>
\r
28716 <TD width=10% BGCOLOR=#C0C0C0>
\r
28719 <TD width=15% BGCOLOR=#C0C0C0>
\r
28722 <TD width=35% BGCOLOR=#C0C0C0>
\r
28723 <B>Configures MIO Pin 77 peripheral interface mapping</B>
\r
28728 <H2><a name="MIO_MST_TRI0">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI0</a></H2>
\r
28729 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28730 <TR valign="top">
\r
28731 <TD width=15% BGCOLOR=#FFFF00>
\r
28732 <B>Register Name</B>
\r
28734 <TD width=15% BGCOLOR=#FFFF00>
\r
28737 <TD width=10% BGCOLOR=#FFFF00>
\r
28740 <TD width=10% BGCOLOR=#FFFF00>
\r
28743 <TD width=15% BGCOLOR=#FFFF00>
\r
28744 <B>Reset Value</B>
\r
28746 <TD width=35% BGCOLOR=#FFFF00>
\r
28747 <B>Description</B>
\r
28750 <TR valign="top">
\r
28751 <TD width=15% BGCOLOR=#FBF5EF>
\r
28752 <B>MIO_MST_TRI0</B>
\r
28754 <TD width=15% BGCOLOR=#FBF5EF>
\r
28755 <B>0XFF180204</B>
\r
28757 <TD width=10% BGCOLOR=#FBF5EF>
\r
28760 <TD width=10% BGCOLOR=#FBF5EF>
\r
28763 <TD width=15% BGCOLOR=#FBF5EF>
\r
28764 <B>0x00000000</B>
\r
28766 <TD width=35% BGCOLOR=#FBF5EF>
\r
28772 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
28773 <TR valign="top">
\r
28774 <TD width=15% BGCOLOR=#C0FFC0>
\r
28775 <B>Field Name</B>
\r
28777 <TD width=15% BGCOLOR=#C0FFC0>
\r
28780 <TD width=10% BGCOLOR=#C0FFC0>
\r
28783 <TD width=10% BGCOLOR=#C0FFC0>
\r
28786 <TD width=15% BGCOLOR=#C0FFC0>
\r
28787 <B>Shifted Value</B>
\r
28789 <TD width=35% BGCOLOR=#C0FFC0>
\r
28790 <B>Description</B>
\r
28793 <TR valign="top">
\r
28794 <TD width=15% BGCOLOR=#FBF5EF>
\r
28795 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI</B>
\r
28797 <TD width=15% BGCOLOR=#FBF5EF>
\r
28800 <TD width=10% BGCOLOR=#FBF5EF>
\r
28803 <TD width=10% BGCOLOR=#FBF5EF>
\r
28806 <TD width=15% BGCOLOR=#FBF5EF>
\r
28809 <TD width=35% BGCOLOR=#FBF5EF>
\r
28810 <B>Master Tri-state Enable for pin 0, active high</B>
\r
28813 <TR valign="top">
\r
28814 <TD width=15% BGCOLOR=#FBF5EF>
\r
28815 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI</B>
\r
28817 <TD width=15% BGCOLOR=#FBF5EF>
\r
28820 <TD width=10% BGCOLOR=#FBF5EF>
\r
28823 <TD width=10% BGCOLOR=#FBF5EF>
\r
28826 <TD width=15% BGCOLOR=#FBF5EF>
\r
28829 <TD width=35% BGCOLOR=#FBF5EF>
\r
28830 <B>Master Tri-state Enable for pin 1, active high</B>
\r
28833 <TR valign="top">
\r
28834 <TD width=15% BGCOLOR=#FBF5EF>
\r
28835 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI</B>
\r
28837 <TD width=15% BGCOLOR=#FBF5EF>
\r
28840 <TD width=10% BGCOLOR=#FBF5EF>
\r
28843 <TD width=10% BGCOLOR=#FBF5EF>
\r
28846 <TD width=15% BGCOLOR=#FBF5EF>
\r
28849 <TD width=35% BGCOLOR=#FBF5EF>
\r
28850 <B>Master Tri-state Enable for pin 2, active high</B>
\r
28853 <TR valign="top">
\r
28854 <TD width=15% BGCOLOR=#FBF5EF>
\r
28855 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI</B>
\r
28857 <TD width=15% BGCOLOR=#FBF5EF>
\r
28860 <TD width=10% BGCOLOR=#FBF5EF>
\r
28863 <TD width=10% BGCOLOR=#FBF5EF>
\r
28866 <TD width=15% BGCOLOR=#FBF5EF>
\r
28869 <TD width=35% BGCOLOR=#FBF5EF>
\r
28870 <B>Master Tri-state Enable for pin 3, active high</B>
\r
28873 <TR valign="top">
\r
28874 <TD width=15% BGCOLOR=#FBF5EF>
\r
28875 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI</B>
\r
28877 <TD width=15% BGCOLOR=#FBF5EF>
\r
28880 <TD width=10% BGCOLOR=#FBF5EF>
\r
28883 <TD width=10% BGCOLOR=#FBF5EF>
\r
28886 <TD width=15% BGCOLOR=#FBF5EF>
\r
28889 <TD width=35% BGCOLOR=#FBF5EF>
\r
28890 <B>Master Tri-state Enable for pin 4, active high</B>
\r
28893 <TR valign="top">
\r
28894 <TD width=15% BGCOLOR=#FBF5EF>
\r
28895 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI</B>
\r
28897 <TD width=15% BGCOLOR=#FBF5EF>
\r
28900 <TD width=10% BGCOLOR=#FBF5EF>
\r
28903 <TD width=10% BGCOLOR=#FBF5EF>
\r
28906 <TD width=15% BGCOLOR=#FBF5EF>
\r
28909 <TD width=35% BGCOLOR=#FBF5EF>
\r
28910 <B>Master Tri-state Enable for pin 5, active high</B>
\r
28913 <TR valign="top">
\r
28914 <TD width=15% BGCOLOR=#FBF5EF>
\r
28915 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI</B>
\r
28917 <TD width=15% BGCOLOR=#FBF5EF>
\r
28920 <TD width=10% BGCOLOR=#FBF5EF>
\r
28923 <TD width=10% BGCOLOR=#FBF5EF>
\r
28926 <TD width=15% BGCOLOR=#FBF5EF>
\r
28929 <TD width=35% BGCOLOR=#FBF5EF>
\r
28930 <B>Master Tri-state Enable for pin 6, active high</B>
\r
28933 <TR valign="top">
\r
28934 <TD width=15% BGCOLOR=#FBF5EF>
\r
28935 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI</B>
\r
28937 <TD width=15% BGCOLOR=#FBF5EF>
\r
28940 <TD width=10% BGCOLOR=#FBF5EF>
\r
28943 <TD width=10% BGCOLOR=#FBF5EF>
\r
28946 <TD width=15% BGCOLOR=#FBF5EF>
\r
28949 <TD width=35% BGCOLOR=#FBF5EF>
\r
28950 <B>Master Tri-state Enable for pin 7, active high</B>
\r
28953 <TR valign="top">
\r
28954 <TD width=15% BGCOLOR=#FBF5EF>
\r
28955 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI</B>
\r
28957 <TD width=15% BGCOLOR=#FBF5EF>
\r
28960 <TD width=10% BGCOLOR=#FBF5EF>
\r
28963 <TD width=10% BGCOLOR=#FBF5EF>
\r
28966 <TD width=15% BGCOLOR=#FBF5EF>
\r
28969 <TD width=35% BGCOLOR=#FBF5EF>
\r
28970 <B>Master Tri-state Enable for pin 8, active high</B>
\r
28973 <TR valign="top">
\r
28974 <TD width=15% BGCOLOR=#FBF5EF>
\r
28975 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI</B>
\r
28977 <TD width=15% BGCOLOR=#FBF5EF>
\r
28980 <TD width=10% BGCOLOR=#FBF5EF>
\r
28983 <TD width=10% BGCOLOR=#FBF5EF>
\r
28986 <TD width=15% BGCOLOR=#FBF5EF>
\r
28989 <TD width=35% BGCOLOR=#FBF5EF>
\r
28990 <B>Master Tri-state Enable for pin 9, active high</B>
\r
28993 <TR valign="top">
\r
28994 <TD width=15% BGCOLOR=#FBF5EF>
\r
28995 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI</B>
\r
28997 <TD width=15% BGCOLOR=#FBF5EF>
\r
29000 <TD width=10% BGCOLOR=#FBF5EF>
\r
29003 <TD width=10% BGCOLOR=#FBF5EF>
\r
29006 <TD width=15% BGCOLOR=#FBF5EF>
\r
29009 <TD width=35% BGCOLOR=#FBF5EF>
\r
29010 <B>Master Tri-state Enable for pin 10, active high</B>
\r
29013 <TR valign="top">
\r
29014 <TD width=15% BGCOLOR=#FBF5EF>
\r
29015 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI</B>
\r
29017 <TD width=15% BGCOLOR=#FBF5EF>
\r
29020 <TD width=10% BGCOLOR=#FBF5EF>
\r
29023 <TD width=10% BGCOLOR=#FBF5EF>
\r
29026 <TD width=15% BGCOLOR=#FBF5EF>
\r
29029 <TD width=35% BGCOLOR=#FBF5EF>
\r
29030 <B>Master Tri-state Enable for pin 11, active high</B>
\r
29033 <TR valign="top">
\r
29034 <TD width=15% BGCOLOR=#FBF5EF>
\r
29035 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI</B>
\r
29037 <TD width=15% BGCOLOR=#FBF5EF>
\r
29040 <TD width=10% BGCOLOR=#FBF5EF>
\r
29043 <TD width=10% BGCOLOR=#FBF5EF>
\r
29046 <TD width=15% BGCOLOR=#FBF5EF>
\r
29049 <TD width=35% BGCOLOR=#FBF5EF>
\r
29050 <B>Master Tri-state Enable for pin 12, active high</B>
\r
29053 <TR valign="top">
\r
29054 <TD width=15% BGCOLOR=#FBF5EF>
\r
29055 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI</B>
\r
29057 <TD width=15% BGCOLOR=#FBF5EF>
\r
29060 <TD width=10% BGCOLOR=#FBF5EF>
\r
29063 <TD width=10% BGCOLOR=#FBF5EF>
\r
29066 <TD width=15% BGCOLOR=#FBF5EF>
\r
29069 <TD width=35% BGCOLOR=#FBF5EF>
\r
29070 <B>Master Tri-state Enable for pin 13, active high</B>
\r
29073 <TR valign="top">
\r
29074 <TD width=15% BGCOLOR=#FBF5EF>
\r
29075 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI</B>
\r
29077 <TD width=15% BGCOLOR=#FBF5EF>
\r
29080 <TD width=10% BGCOLOR=#FBF5EF>
\r
29083 <TD width=10% BGCOLOR=#FBF5EF>
\r
29086 <TD width=15% BGCOLOR=#FBF5EF>
\r
29089 <TD width=35% BGCOLOR=#FBF5EF>
\r
29090 <B>Master Tri-state Enable for pin 14, active high</B>
\r
29093 <TR valign="top">
\r
29094 <TD width=15% BGCOLOR=#FBF5EF>
\r
29095 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI</B>
\r
29097 <TD width=15% BGCOLOR=#FBF5EF>
\r
29100 <TD width=10% BGCOLOR=#FBF5EF>
\r
29103 <TD width=10% BGCOLOR=#FBF5EF>
\r
29106 <TD width=15% BGCOLOR=#FBF5EF>
\r
29109 <TD width=35% BGCOLOR=#FBF5EF>
\r
29110 <B>Master Tri-state Enable for pin 15, active high</B>
\r
29113 <TR valign="top">
\r
29114 <TD width=15% BGCOLOR=#FBF5EF>
\r
29115 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI</B>
\r
29117 <TD width=15% BGCOLOR=#FBF5EF>
\r
29120 <TD width=10% BGCOLOR=#FBF5EF>
\r
29123 <TD width=10% BGCOLOR=#FBF5EF>
\r
29126 <TD width=15% BGCOLOR=#FBF5EF>
\r
29129 <TD width=35% BGCOLOR=#FBF5EF>
\r
29130 <B>Master Tri-state Enable for pin 16, active high</B>
\r
29133 <TR valign="top">
\r
29134 <TD width=15% BGCOLOR=#FBF5EF>
\r
29135 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI</B>
\r
29137 <TD width=15% BGCOLOR=#FBF5EF>
\r
29140 <TD width=10% BGCOLOR=#FBF5EF>
\r
29143 <TD width=10% BGCOLOR=#FBF5EF>
\r
29146 <TD width=15% BGCOLOR=#FBF5EF>
\r
29149 <TD width=35% BGCOLOR=#FBF5EF>
\r
29150 <B>Master Tri-state Enable for pin 17, active high</B>
\r
29153 <TR valign="top">
\r
29154 <TD width=15% BGCOLOR=#FBF5EF>
\r
29155 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI</B>
\r
29157 <TD width=15% BGCOLOR=#FBF5EF>
\r
29160 <TD width=10% BGCOLOR=#FBF5EF>
\r
29163 <TD width=10% BGCOLOR=#FBF5EF>
\r
29166 <TD width=15% BGCOLOR=#FBF5EF>
\r
29169 <TD width=35% BGCOLOR=#FBF5EF>
\r
29170 <B>Master Tri-state Enable for pin 18, active high</B>
\r
29173 <TR valign="top">
\r
29174 <TD width=15% BGCOLOR=#FBF5EF>
\r
29175 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI</B>
\r
29177 <TD width=15% BGCOLOR=#FBF5EF>
\r
29180 <TD width=10% BGCOLOR=#FBF5EF>
\r
29183 <TD width=10% BGCOLOR=#FBF5EF>
\r
29186 <TD width=15% BGCOLOR=#FBF5EF>
\r
29189 <TD width=35% BGCOLOR=#FBF5EF>
\r
29190 <B>Master Tri-state Enable for pin 19, active high</B>
\r
29193 <TR valign="top">
\r
29194 <TD width=15% BGCOLOR=#FBF5EF>
\r
29195 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI</B>
\r
29197 <TD width=15% BGCOLOR=#FBF5EF>
\r
29200 <TD width=10% BGCOLOR=#FBF5EF>
\r
29203 <TD width=10% BGCOLOR=#FBF5EF>
\r
29206 <TD width=15% BGCOLOR=#FBF5EF>
\r
29209 <TD width=35% BGCOLOR=#FBF5EF>
\r
29210 <B>Master Tri-state Enable for pin 20, active high</B>
\r
29213 <TR valign="top">
\r
29214 <TD width=15% BGCOLOR=#FBF5EF>
\r
29215 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI</B>
\r
29217 <TD width=15% BGCOLOR=#FBF5EF>
\r
29220 <TD width=10% BGCOLOR=#FBF5EF>
\r
29223 <TD width=10% BGCOLOR=#FBF5EF>
\r
29226 <TD width=15% BGCOLOR=#FBF5EF>
\r
29229 <TD width=35% BGCOLOR=#FBF5EF>
\r
29230 <B>Master Tri-state Enable for pin 21, active high</B>
\r
29233 <TR valign="top">
\r
29234 <TD width=15% BGCOLOR=#FBF5EF>
\r
29235 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI</B>
\r
29237 <TD width=15% BGCOLOR=#FBF5EF>
\r
29240 <TD width=10% BGCOLOR=#FBF5EF>
\r
29243 <TD width=10% BGCOLOR=#FBF5EF>
\r
29246 <TD width=15% BGCOLOR=#FBF5EF>
\r
29249 <TD width=35% BGCOLOR=#FBF5EF>
\r
29250 <B>Master Tri-state Enable for pin 22, active high</B>
\r
29253 <TR valign="top">
\r
29254 <TD width=15% BGCOLOR=#FBF5EF>
\r
29255 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI</B>
\r
29257 <TD width=15% BGCOLOR=#FBF5EF>
\r
29260 <TD width=10% BGCOLOR=#FBF5EF>
\r
29263 <TD width=10% BGCOLOR=#FBF5EF>
\r
29266 <TD width=15% BGCOLOR=#FBF5EF>
\r
29269 <TD width=35% BGCOLOR=#FBF5EF>
\r
29270 <B>Master Tri-state Enable for pin 23, active high</B>
\r
29273 <TR valign="top">
\r
29274 <TD width=15% BGCOLOR=#FBF5EF>
\r
29275 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI</B>
\r
29277 <TD width=15% BGCOLOR=#FBF5EF>
\r
29280 <TD width=10% BGCOLOR=#FBF5EF>
\r
29283 <TD width=10% BGCOLOR=#FBF5EF>
\r
29286 <TD width=15% BGCOLOR=#FBF5EF>
\r
29289 <TD width=35% BGCOLOR=#FBF5EF>
\r
29290 <B>Master Tri-state Enable for pin 24, active high</B>
\r
29293 <TR valign="top">
\r
29294 <TD width=15% BGCOLOR=#FBF5EF>
\r
29295 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI</B>
\r
29297 <TD width=15% BGCOLOR=#FBF5EF>
\r
29300 <TD width=10% BGCOLOR=#FBF5EF>
\r
29303 <TD width=10% BGCOLOR=#FBF5EF>
\r
29306 <TD width=15% BGCOLOR=#FBF5EF>
\r
29309 <TD width=35% BGCOLOR=#FBF5EF>
\r
29310 <B>Master Tri-state Enable for pin 25, active high</B>
\r
29313 <TR valign="top">
\r
29314 <TD width=15% BGCOLOR=#FBF5EF>
\r
29315 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI</B>
\r
29317 <TD width=15% BGCOLOR=#FBF5EF>
\r
29320 <TD width=10% BGCOLOR=#FBF5EF>
\r
29323 <TD width=10% BGCOLOR=#FBF5EF>
\r
29326 <TD width=15% BGCOLOR=#FBF5EF>
\r
29329 <TD width=35% BGCOLOR=#FBF5EF>
\r
29330 <B>Master Tri-state Enable for pin 26, active high</B>
\r
29333 <TR valign="top">
\r
29334 <TD width=15% BGCOLOR=#FBF5EF>
\r
29335 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI</B>
\r
29337 <TD width=15% BGCOLOR=#FBF5EF>
\r
29340 <TD width=10% BGCOLOR=#FBF5EF>
\r
29343 <TD width=10% BGCOLOR=#FBF5EF>
\r
29346 <TD width=15% BGCOLOR=#FBF5EF>
\r
29349 <TD width=35% BGCOLOR=#FBF5EF>
\r
29350 <B>Master Tri-state Enable for pin 27, active high</B>
\r
29353 <TR valign="top">
\r
29354 <TD width=15% BGCOLOR=#FBF5EF>
\r
29355 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI</B>
\r
29357 <TD width=15% BGCOLOR=#FBF5EF>
\r
29360 <TD width=10% BGCOLOR=#FBF5EF>
\r
29363 <TD width=10% BGCOLOR=#FBF5EF>
\r
29366 <TD width=15% BGCOLOR=#FBF5EF>
\r
29369 <TD width=35% BGCOLOR=#FBF5EF>
\r
29370 <B>Master Tri-state Enable for pin 28, active high</B>
\r
29373 <TR valign="top">
\r
29374 <TD width=15% BGCOLOR=#FBF5EF>
\r
29375 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI</B>
\r
29377 <TD width=15% BGCOLOR=#FBF5EF>
\r
29380 <TD width=10% BGCOLOR=#FBF5EF>
\r
29383 <TD width=10% BGCOLOR=#FBF5EF>
\r
29386 <TD width=15% BGCOLOR=#FBF5EF>
\r
29389 <TD width=35% BGCOLOR=#FBF5EF>
\r
29390 <B>Master Tri-state Enable for pin 29, active high</B>
\r
29393 <TR valign="top">
\r
29394 <TD width=15% BGCOLOR=#FBF5EF>
\r
29395 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI</B>
\r
29397 <TD width=15% BGCOLOR=#FBF5EF>
\r
29400 <TD width=10% BGCOLOR=#FBF5EF>
\r
29403 <TD width=10% BGCOLOR=#FBF5EF>
\r
29406 <TD width=15% BGCOLOR=#FBF5EF>
\r
29409 <TD width=35% BGCOLOR=#FBF5EF>
\r
29410 <B>Master Tri-state Enable for pin 30, active high</B>
\r
29413 <TR valign="top">
\r
29414 <TD width=15% BGCOLOR=#FBF5EF>
\r
29415 <B>PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI</B>
\r
29417 <TD width=15% BGCOLOR=#FBF5EF>
\r
29420 <TD width=10% BGCOLOR=#FBF5EF>
\r
29423 <TD width=10% BGCOLOR=#FBF5EF>
\r
29426 <TD width=15% BGCOLOR=#FBF5EF>
\r
29429 <TD width=35% BGCOLOR=#FBF5EF>
\r
29430 <B>Master Tri-state Enable for pin 31, active high</B>
\r
29433 <TR valign="top">
\r
29434 <TD width=15% BGCOLOR=#C0C0C0>
\r
29435 <B>PSU_IOU_SLCR_MIO_MST_TRI0@0XFF180204</B>
\r
29437 <TD width=15% BGCOLOR=#C0C0C0>
\r
29440 <TD width=10% BGCOLOR=#C0C0C0>
\r
29443 <TD width=10% BGCOLOR=#C0C0C0>
\r
29446 <TD width=15% BGCOLOR=#C0C0C0>
\r
29449 <TD width=35% BGCOLOR=#C0C0C0>
\r
29450 <B>MIO pin Tri-state Enables, 31:0</B>
\r
29455 <H2><a name="MIO_MST_TRI1">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI1</a></H2>
\r
29456 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
29457 <TR valign="top">
\r
29458 <TD width=15% BGCOLOR=#FFFF00>
\r
29459 <B>Register Name</B>
\r
29461 <TD width=15% BGCOLOR=#FFFF00>
\r
29464 <TD width=10% BGCOLOR=#FFFF00>
\r
29467 <TD width=10% BGCOLOR=#FFFF00>
\r
29470 <TD width=15% BGCOLOR=#FFFF00>
\r
29471 <B>Reset Value</B>
\r
29473 <TD width=35% BGCOLOR=#FFFF00>
\r
29474 <B>Description</B>
\r
29477 <TR valign="top">
\r
29478 <TD width=15% BGCOLOR=#FBF5EF>
\r
29479 <B>MIO_MST_TRI1</B>
\r
29481 <TD width=15% BGCOLOR=#FBF5EF>
\r
29482 <B>0XFF180208</B>
\r
29484 <TD width=10% BGCOLOR=#FBF5EF>
\r
29487 <TD width=10% BGCOLOR=#FBF5EF>
\r
29490 <TD width=15% BGCOLOR=#FBF5EF>
\r
29491 <B>0x00000000</B>
\r
29493 <TD width=35% BGCOLOR=#FBF5EF>
\r
29499 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
29500 <TR valign="top">
\r
29501 <TD width=15% BGCOLOR=#C0FFC0>
\r
29502 <B>Field Name</B>
\r
29504 <TD width=15% BGCOLOR=#C0FFC0>
\r
29507 <TD width=10% BGCOLOR=#C0FFC0>
\r
29510 <TD width=10% BGCOLOR=#C0FFC0>
\r
29513 <TD width=15% BGCOLOR=#C0FFC0>
\r
29514 <B>Shifted Value</B>
\r
29516 <TD width=35% BGCOLOR=#C0FFC0>
\r
29517 <B>Description</B>
\r
29520 <TR valign="top">
\r
29521 <TD width=15% BGCOLOR=#FBF5EF>
\r
29522 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI</B>
\r
29524 <TD width=15% BGCOLOR=#FBF5EF>
\r
29527 <TD width=10% BGCOLOR=#FBF5EF>
\r
29530 <TD width=10% BGCOLOR=#FBF5EF>
\r
29533 <TD width=15% BGCOLOR=#FBF5EF>
\r
29536 <TD width=35% BGCOLOR=#FBF5EF>
\r
29537 <B>Master Tri-state Enable for pin 32, active high</B>
\r
29540 <TR valign="top">
\r
29541 <TD width=15% BGCOLOR=#FBF5EF>
\r
29542 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI</B>
\r
29544 <TD width=15% BGCOLOR=#FBF5EF>
\r
29547 <TD width=10% BGCOLOR=#FBF5EF>
\r
29550 <TD width=10% BGCOLOR=#FBF5EF>
\r
29553 <TD width=15% BGCOLOR=#FBF5EF>
\r
29556 <TD width=35% BGCOLOR=#FBF5EF>
\r
29557 <B>Master Tri-state Enable for pin 33, active high</B>
\r
29560 <TR valign="top">
\r
29561 <TD width=15% BGCOLOR=#FBF5EF>
\r
29562 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI</B>
\r
29564 <TD width=15% BGCOLOR=#FBF5EF>
\r
29567 <TD width=10% BGCOLOR=#FBF5EF>
\r
29570 <TD width=10% BGCOLOR=#FBF5EF>
\r
29573 <TD width=15% BGCOLOR=#FBF5EF>
\r
29576 <TD width=35% BGCOLOR=#FBF5EF>
\r
29577 <B>Master Tri-state Enable for pin 34, active high</B>
\r
29580 <TR valign="top">
\r
29581 <TD width=15% BGCOLOR=#FBF5EF>
\r
29582 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI</B>
\r
29584 <TD width=15% BGCOLOR=#FBF5EF>
\r
29587 <TD width=10% BGCOLOR=#FBF5EF>
\r
29590 <TD width=10% BGCOLOR=#FBF5EF>
\r
29593 <TD width=15% BGCOLOR=#FBF5EF>
\r
29596 <TD width=35% BGCOLOR=#FBF5EF>
\r
29597 <B>Master Tri-state Enable for pin 35, active high</B>
\r
29600 <TR valign="top">
\r
29601 <TD width=15% BGCOLOR=#FBF5EF>
\r
29602 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI</B>
\r
29604 <TD width=15% BGCOLOR=#FBF5EF>
\r
29607 <TD width=10% BGCOLOR=#FBF5EF>
\r
29610 <TD width=10% BGCOLOR=#FBF5EF>
\r
29613 <TD width=15% BGCOLOR=#FBF5EF>
\r
29616 <TD width=35% BGCOLOR=#FBF5EF>
\r
29617 <B>Master Tri-state Enable for pin 36, active high</B>
\r
29620 <TR valign="top">
\r
29621 <TD width=15% BGCOLOR=#FBF5EF>
\r
29622 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI</B>
\r
29624 <TD width=15% BGCOLOR=#FBF5EF>
\r
29627 <TD width=10% BGCOLOR=#FBF5EF>
\r
29630 <TD width=10% BGCOLOR=#FBF5EF>
\r
29633 <TD width=15% BGCOLOR=#FBF5EF>
\r
29636 <TD width=35% BGCOLOR=#FBF5EF>
\r
29637 <B>Master Tri-state Enable for pin 37, active high</B>
\r
29640 <TR valign="top">
\r
29641 <TD width=15% BGCOLOR=#FBF5EF>
\r
29642 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI</B>
\r
29644 <TD width=15% BGCOLOR=#FBF5EF>
\r
29647 <TD width=10% BGCOLOR=#FBF5EF>
\r
29650 <TD width=10% BGCOLOR=#FBF5EF>
\r
29653 <TD width=15% BGCOLOR=#FBF5EF>
\r
29656 <TD width=35% BGCOLOR=#FBF5EF>
\r
29657 <B>Master Tri-state Enable for pin 38, active high</B>
\r
29660 <TR valign="top">
\r
29661 <TD width=15% BGCOLOR=#FBF5EF>
\r
29662 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI</B>
\r
29664 <TD width=15% BGCOLOR=#FBF5EF>
\r
29667 <TD width=10% BGCOLOR=#FBF5EF>
\r
29670 <TD width=10% BGCOLOR=#FBF5EF>
\r
29673 <TD width=15% BGCOLOR=#FBF5EF>
\r
29676 <TD width=35% BGCOLOR=#FBF5EF>
\r
29677 <B>Master Tri-state Enable for pin 39, active high</B>
\r
29680 <TR valign="top">
\r
29681 <TD width=15% BGCOLOR=#FBF5EF>
\r
29682 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI</B>
\r
29684 <TD width=15% BGCOLOR=#FBF5EF>
\r
29687 <TD width=10% BGCOLOR=#FBF5EF>
\r
29690 <TD width=10% BGCOLOR=#FBF5EF>
\r
29693 <TD width=15% BGCOLOR=#FBF5EF>
\r
29696 <TD width=35% BGCOLOR=#FBF5EF>
\r
29697 <B>Master Tri-state Enable for pin 40, active high</B>
\r
29700 <TR valign="top">
\r
29701 <TD width=15% BGCOLOR=#FBF5EF>
\r
29702 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI</B>
\r
29704 <TD width=15% BGCOLOR=#FBF5EF>
\r
29707 <TD width=10% BGCOLOR=#FBF5EF>
\r
29710 <TD width=10% BGCOLOR=#FBF5EF>
\r
29713 <TD width=15% BGCOLOR=#FBF5EF>
\r
29716 <TD width=35% BGCOLOR=#FBF5EF>
\r
29717 <B>Master Tri-state Enable for pin 41, active high</B>
\r
29720 <TR valign="top">
\r
29721 <TD width=15% BGCOLOR=#FBF5EF>
\r
29722 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI</B>
\r
29724 <TD width=15% BGCOLOR=#FBF5EF>
\r
29727 <TD width=10% BGCOLOR=#FBF5EF>
\r
29730 <TD width=10% BGCOLOR=#FBF5EF>
\r
29733 <TD width=15% BGCOLOR=#FBF5EF>
\r
29736 <TD width=35% BGCOLOR=#FBF5EF>
\r
29737 <B>Master Tri-state Enable for pin 42, active high</B>
\r
29740 <TR valign="top">
\r
29741 <TD width=15% BGCOLOR=#FBF5EF>
\r
29742 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI</B>
\r
29744 <TD width=15% BGCOLOR=#FBF5EF>
\r
29747 <TD width=10% BGCOLOR=#FBF5EF>
\r
29750 <TD width=10% BGCOLOR=#FBF5EF>
\r
29753 <TD width=15% BGCOLOR=#FBF5EF>
\r
29756 <TD width=35% BGCOLOR=#FBF5EF>
\r
29757 <B>Master Tri-state Enable for pin 43, active high</B>
\r
29760 <TR valign="top">
\r
29761 <TD width=15% BGCOLOR=#FBF5EF>
\r
29762 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI</B>
\r
29764 <TD width=15% BGCOLOR=#FBF5EF>
\r
29767 <TD width=10% BGCOLOR=#FBF5EF>
\r
29770 <TD width=10% BGCOLOR=#FBF5EF>
\r
29773 <TD width=15% BGCOLOR=#FBF5EF>
\r
29776 <TD width=35% BGCOLOR=#FBF5EF>
\r
29777 <B>Master Tri-state Enable for pin 44, active high</B>
\r
29780 <TR valign="top">
\r
29781 <TD width=15% BGCOLOR=#FBF5EF>
\r
29782 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI</B>
\r
29784 <TD width=15% BGCOLOR=#FBF5EF>
\r
29787 <TD width=10% BGCOLOR=#FBF5EF>
\r
29790 <TD width=10% BGCOLOR=#FBF5EF>
\r
29793 <TD width=15% BGCOLOR=#FBF5EF>
\r
29796 <TD width=35% BGCOLOR=#FBF5EF>
\r
29797 <B>Master Tri-state Enable for pin 45, active high</B>
\r
29800 <TR valign="top">
\r
29801 <TD width=15% BGCOLOR=#FBF5EF>
\r
29802 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI</B>
\r
29804 <TD width=15% BGCOLOR=#FBF5EF>
\r
29807 <TD width=10% BGCOLOR=#FBF5EF>
\r
29810 <TD width=10% BGCOLOR=#FBF5EF>
\r
29813 <TD width=15% BGCOLOR=#FBF5EF>
\r
29816 <TD width=35% BGCOLOR=#FBF5EF>
\r
29817 <B>Master Tri-state Enable for pin 46, active high</B>
\r
29820 <TR valign="top">
\r
29821 <TD width=15% BGCOLOR=#FBF5EF>
\r
29822 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI</B>
\r
29824 <TD width=15% BGCOLOR=#FBF5EF>
\r
29827 <TD width=10% BGCOLOR=#FBF5EF>
\r
29830 <TD width=10% BGCOLOR=#FBF5EF>
\r
29833 <TD width=15% BGCOLOR=#FBF5EF>
\r
29836 <TD width=35% BGCOLOR=#FBF5EF>
\r
29837 <B>Master Tri-state Enable for pin 47, active high</B>
\r
29840 <TR valign="top">
\r
29841 <TD width=15% BGCOLOR=#FBF5EF>
\r
29842 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI</B>
\r
29844 <TD width=15% BGCOLOR=#FBF5EF>
\r
29847 <TD width=10% BGCOLOR=#FBF5EF>
\r
29850 <TD width=10% BGCOLOR=#FBF5EF>
\r
29853 <TD width=15% BGCOLOR=#FBF5EF>
\r
29856 <TD width=35% BGCOLOR=#FBF5EF>
\r
29857 <B>Master Tri-state Enable for pin 48, active high</B>
\r
29860 <TR valign="top">
\r
29861 <TD width=15% BGCOLOR=#FBF5EF>
\r
29862 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI</B>
\r
29864 <TD width=15% BGCOLOR=#FBF5EF>
\r
29867 <TD width=10% BGCOLOR=#FBF5EF>
\r
29870 <TD width=10% BGCOLOR=#FBF5EF>
\r
29873 <TD width=15% BGCOLOR=#FBF5EF>
\r
29876 <TD width=35% BGCOLOR=#FBF5EF>
\r
29877 <B>Master Tri-state Enable for pin 49, active high</B>
\r
29880 <TR valign="top">
\r
29881 <TD width=15% BGCOLOR=#FBF5EF>
\r
29882 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI</B>
\r
29884 <TD width=15% BGCOLOR=#FBF5EF>
\r
29887 <TD width=10% BGCOLOR=#FBF5EF>
\r
29890 <TD width=10% BGCOLOR=#FBF5EF>
\r
29893 <TD width=15% BGCOLOR=#FBF5EF>
\r
29896 <TD width=35% BGCOLOR=#FBF5EF>
\r
29897 <B>Master Tri-state Enable for pin 50, active high</B>
\r
29900 <TR valign="top">
\r
29901 <TD width=15% BGCOLOR=#FBF5EF>
\r
29902 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI</B>
\r
29904 <TD width=15% BGCOLOR=#FBF5EF>
\r
29907 <TD width=10% BGCOLOR=#FBF5EF>
\r
29910 <TD width=10% BGCOLOR=#FBF5EF>
\r
29913 <TD width=15% BGCOLOR=#FBF5EF>
\r
29916 <TD width=35% BGCOLOR=#FBF5EF>
\r
29917 <B>Master Tri-state Enable for pin 51, active high</B>
\r
29920 <TR valign="top">
\r
29921 <TD width=15% BGCOLOR=#FBF5EF>
\r
29922 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI</B>
\r
29924 <TD width=15% BGCOLOR=#FBF5EF>
\r
29927 <TD width=10% BGCOLOR=#FBF5EF>
\r
29930 <TD width=10% BGCOLOR=#FBF5EF>
\r
29933 <TD width=15% BGCOLOR=#FBF5EF>
\r
29936 <TD width=35% BGCOLOR=#FBF5EF>
\r
29937 <B>Master Tri-state Enable for pin 52, active high</B>
\r
29940 <TR valign="top">
\r
29941 <TD width=15% BGCOLOR=#FBF5EF>
\r
29942 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI</B>
\r
29944 <TD width=15% BGCOLOR=#FBF5EF>
\r
29947 <TD width=10% BGCOLOR=#FBF5EF>
\r
29950 <TD width=10% BGCOLOR=#FBF5EF>
\r
29953 <TD width=15% BGCOLOR=#FBF5EF>
\r
29956 <TD width=35% BGCOLOR=#FBF5EF>
\r
29957 <B>Master Tri-state Enable for pin 53, active high</B>
\r
29960 <TR valign="top">
\r
29961 <TD width=15% BGCOLOR=#FBF5EF>
\r
29962 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI</B>
\r
29964 <TD width=15% BGCOLOR=#FBF5EF>
\r
29967 <TD width=10% BGCOLOR=#FBF5EF>
\r
29970 <TD width=10% BGCOLOR=#FBF5EF>
\r
29973 <TD width=15% BGCOLOR=#FBF5EF>
\r
29976 <TD width=35% BGCOLOR=#FBF5EF>
\r
29977 <B>Master Tri-state Enable for pin 54, active high</B>
\r
29980 <TR valign="top">
\r
29981 <TD width=15% BGCOLOR=#FBF5EF>
\r
29982 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI</B>
\r
29984 <TD width=15% BGCOLOR=#FBF5EF>
\r
29987 <TD width=10% BGCOLOR=#FBF5EF>
\r
29990 <TD width=10% BGCOLOR=#FBF5EF>
\r
29993 <TD width=15% BGCOLOR=#FBF5EF>
\r
29996 <TD width=35% BGCOLOR=#FBF5EF>
\r
29997 <B>Master Tri-state Enable for pin 55, active high</B>
\r
30000 <TR valign="top">
\r
30001 <TD width=15% BGCOLOR=#FBF5EF>
\r
30002 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI</B>
\r
30004 <TD width=15% BGCOLOR=#FBF5EF>
\r
30007 <TD width=10% BGCOLOR=#FBF5EF>
\r
30010 <TD width=10% BGCOLOR=#FBF5EF>
\r
30013 <TD width=15% BGCOLOR=#FBF5EF>
\r
30016 <TD width=35% BGCOLOR=#FBF5EF>
\r
30017 <B>Master Tri-state Enable for pin 56, active high</B>
\r
30020 <TR valign="top">
\r
30021 <TD width=15% BGCOLOR=#FBF5EF>
\r
30022 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI</B>
\r
30024 <TD width=15% BGCOLOR=#FBF5EF>
\r
30027 <TD width=10% BGCOLOR=#FBF5EF>
\r
30030 <TD width=10% BGCOLOR=#FBF5EF>
\r
30033 <TD width=15% BGCOLOR=#FBF5EF>
\r
30036 <TD width=35% BGCOLOR=#FBF5EF>
\r
30037 <B>Master Tri-state Enable for pin 57, active high</B>
\r
30040 <TR valign="top">
\r
30041 <TD width=15% BGCOLOR=#FBF5EF>
\r
30042 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI</B>
\r
30044 <TD width=15% BGCOLOR=#FBF5EF>
\r
30047 <TD width=10% BGCOLOR=#FBF5EF>
\r
30050 <TD width=10% BGCOLOR=#FBF5EF>
\r
30053 <TD width=15% BGCOLOR=#FBF5EF>
\r
30056 <TD width=35% BGCOLOR=#FBF5EF>
\r
30057 <B>Master Tri-state Enable for pin 58, active high</B>
\r
30060 <TR valign="top">
\r
30061 <TD width=15% BGCOLOR=#FBF5EF>
\r
30062 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI</B>
\r
30064 <TD width=15% BGCOLOR=#FBF5EF>
\r
30067 <TD width=10% BGCOLOR=#FBF5EF>
\r
30070 <TD width=10% BGCOLOR=#FBF5EF>
\r
30073 <TD width=15% BGCOLOR=#FBF5EF>
\r
30076 <TD width=35% BGCOLOR=#FBF5EF>
\r
30077 <B>Master Tri-state Enable for pin 59, active high</B>
\r
30080 <TR valign="top">
\r
30081 <TD width=15% BGCOLOR=#FBF5EF>
\r
30082 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI</B>
\r
30084 <TD width=15% BGCOLOR=#FBF5EF>
\r
30087 <TD width=10% BGCOLOR=#FBF5EF>
\r
30090 <TD width=10% BGCOLOR=#FBF5EF>
\r
30093 <TD width=15% BGCOLOR=#FBF5EF>
\r
30096 <TD width=35% BGCOLOR=#FBF5EF>
\r
30097 <B>Master Tri-state Enable for pin 60, active high</B>
\r
30100 <TR valign="top">
\r
30101 <TD width=15% BGCOLOR=#FBF5EF>
\r
30102 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI</B>
\r
30104 <TD width=15% BGCOLOR=#FBF5EF>
\r
30107 <TD width=10% BGCOLOR=#FBF5EF>
\r
30110 <TD width=10% BGCOLOR=#FBF5EF>
\r
30113 <TD width=15% BGCOLOR=#FBF5EF>
\r
30116 <TD width=35% BGCOLOR=#FBF5EF>
\r
30117 <B>Master Tri-state Enable for pin 61, active high</B>
\r
30120 <TR valign="top">
\r
30121 <TD width=15% BGCOLOR=#FBF5EF>
\r
30122 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI</B>
\r
30124 <TD width=15% BGCOLOR=#FBF5EF>
\r
30127 <TD width=10% BGCOLOR=#FBF5EF>
\r
30130 <TD width=10% BGCOLOR=#FBF5EF>
\r
30133 <TD width=15% BGCOLOR=#FBF5EF>
\r
30136 <TD width=35% BGCOLOR=#FBF5EF>
\r
30137 <B>Master Tri-state Enable for pin 62, active high</B>
\r
30140 <TR valign="top">
\r
30141 <TD width=15% BGCOLOR=#FBF5EF>
\r
30142 <B>PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI</B>
\r
30144 <TD width=15% BGCOLOR=#FBF5EF>
\r
30147 <TD width=10% BGCOLOR=#FBF5EF>
\r
30150 <TD width=10% BGCOLOR=#FBF5EF>
\r
30153 <TD width=15% BGCOLOR=#FBF5EF>
\r
30156 <TD width=35% BGCOLOR=#FBF5EF>
\r
30157 <B>Master Tri-state Enable for pin 63, active high</B>
\r
30160 <TR valign="top">
\r
30161 <TD width=15% BGCOLOR=#C0C0C0>
\r
30162 <B>PSU_IOU_SLCR_MIO_MST_TRI1@0XFF180208</B>
\r
30164 <TD width=15% BGCOLOR=#C0C0C0>
\r
30167 <TD width=10% BGCOLOR=#C0C0C0>
\r
30170 <TD width=10% BGCOLOR=#C0C0C0>
\r
30173 <TD width=15% BGCOLOR=#C0C0C0>
\r
30176 <TD width=35% BGCOLOR=#C0C0C0>
\r
30177 <B>MIO pin Tri-state Enables, 63:32</B>
\r
30182 <H2><a name="MIO_MST_TRI2">Register (<A href=#mod___slcr> slcr </A>)MIO_MST_TRI2</a></H2>
\r
30183 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
30184 <TR valign="top">
\r
30185 <TD width=15% BGCOLOR=#FFFF00>
\r
30186 <B>Register Name</B>
\r
30188 <TD width=15% BGCOLOR=#FFFF00>
\r
30191 <TD width=10% BGCOLOR=#FFFF00>
\r
30194 <TD width=10% BGCOLOR=#FFFF00>
\r
30197 <TD width=15% BGCOLOR=#FFFF00>
\r
30198 <B>Reset Value</B>
\r
30200 <TD width=35% BGCOLOR=#FFFF00>
\r
30201 <B>Description</B>
\r
30204 <TR valign="top">
\r
30205 <TD width=15% BGCOLOR=#FBF5EF>
\r
30206 <B>MIO_MST_TRI2</B>
\r
30208 <TD width=15% BGCOLOR=#FBF5EF>
\r
30209 <B>0XFF18020C</B>
\r
30211 <TD width=10% BGCOLOR=#FBF5EF>
\r
30214 <TD width=10% BGCOLOR=#FBF5EF>
\r
30217 <TD width=15% BGCOLOR=#FBF5EF>
\r
30218 <B>0x00000000</B>
\r
30220 <TD width=35% BGCOLOR=#FBF5EF>
\r
30226 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
30227 <TR valign="top">
\r
30228 <TD width=15% BGCOLOR=#C0FFC0>
\r
30229 <B>Field Name</B>
\r
30231 <TD width=15% BGCOLOR=#C0FFC0>
\r
30234 <TD width=10% BGCOLOR=#C0FFC0>
\r
30237 <TD width=10% BGCOLOR=#C0FFC0>
\r
30240 <TD width=15% BGCOLOR=#C0FFC0>
\r
30241 <B>Shifted Value</B>
\r
30243 <TD width=35% BGCOLOR=#C0FFC0>
\r
30244 <B>Description</B>
\r
30247 <TR valign="top">
\r
30248 <TD width=15% BGCOLOR=#FBF5EF>
\r
30249 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI</B>
\r
30251 <TD width=15% BGCOLOR=#FBF5EF>
\r
30254 <TD width=10% BGCOLOR=#FBF5EF>
\r
30257 <TD width=10% BGCOLOR=#FBF5EF>
\r
30260 <TD width=15% BGCOLOR=#FBF5EF>
\r
30263 <TD width=35% BGCOLOR=#FBF5EF>
\r
30264 <B>Master Tri-state Enable for pin 64, active high</B>
\r
30267 <TR valign="top">
\r
30268 <TD width=15% BGCOLOR=#FBF5EF>
\r
30269 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI</B>
\r
30271 <TD width=15% BGCOLOR=#FBF5EF>
\r
30274 <TD width=10% BGCOLOR=#FBF5EF>
\r
30277 <TD width=10% BGCOLOR=#FBF5EF>
\r
30280 <TD width=15% BGCOLOR=#FBF5EF>
\r
30283 <TD width=35% BGCOLOR=#FBF5EF>
\r
30284 <B>Master Tri-state Enable for pin 65, active high</B>
\r
30287 <TR valign="top">
\r
30288 <TD width=15% BGCOLOR=#FBF5EF>
\r
30289 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI</B>
\r
30291 <TD width=15% BGCOLOR=#FBF5EF>
\r
30294 <TD width=10% BGCOLOR=#FBF5EF>
\r
30297 <TD width=10% BGCOLOR=#FBF5EF>
\r
30300 <TD width=15% BGCOLOR=#FBF5EF>
\r
30303 <TD width=35% BGCOLOR=#FBF5EF>
\r
30304 <B>Master Tri-state Enable for pin 66, active high</B>
\r
30307 <TR valign="top">
\r
30308 <TD width=15% BGCOLOR=#FBF5EF>
\r
30309 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI</B>
\r
30311 <TD width=15% BGCOLOR=#FBF5EF>
\r
30314 <TD width=10% BGCOLOR=#FBF5EF>
\r
30317 <TD width=10% BGCOLOR=#FBF5EF>
\r
30320 <TD width=15% BGCOLOR=#FBF5EF>
\r
30323 <TD width=35% BGCOLOR=#FBF5EF>
\r
30324 <B>Master Tri-state Enable for pin 67, active high</B>
\r
30327 <TR valign="top">
\r
30328 <TD width=15% BGCOLOR=#FBF5EF>
\r
30329 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI</B>
\r
30331 <TD width=15% BGCOLOR=#FBF5EF>
\r
30334 <TD width=10% BGCOLOR=#FBF5EF>
\r
30337 <TD width=10% BGCOLOR=#FBF5EF>
\r
30340 <TD width=15% BGCOLOR=#FBF5EF>
\r
30343 <TD width=35% BGCOLOR=#FBF5EF>
\r
30344 <B>Master Tri-state Enable for pin 68, active high</B>
\r
30347 <TR valign="top">
\r
30348 <TD width=15% BGCOLOR=#FBF5EF>
\r
30349 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI</B>
\r
30351 <TD width=15% BGCOLOR=#FBF5EF>
\r
30354 <TD width=10% BGCOLOR=#FBF5EF>
\r
30357 <TD width=10% BGCOLOR=#FBF5EF>
\r
30360 <TD width=15% BGCOLOR=#FBF5EF>
\r
30363 <TD width=35% BGCOLOR=#FBF5EF>
\r
30364 <B>Master Tri-state Enable for pin 69, active high</B>
\r
30367 <TR valign="top">
\r
30368 <TD width=15% BGCOLOR=#FBF5EF>
\r
30369 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI</B>
\r
30371 <TD width=15% BGCOLOR=#FBF5EF>
\r
30374 <TD width=10% BGCOLOR=#FBF5EF>
\r
30377 <TD width=10% BGCOLOR=#FBF5EF>
\r
30380 <TD width=15% BGCOLOR=#FBF5EF>
\r
30383 <TD width=35% BGCOLOR=#FBF5EF>
\r
30384 <B>Master Tri-state Enable for pin 70, active high</B>
\r
30387 <TR valign="top">
\r
30388 <TD width=15% BGCOLOR=#FBF5EF>
\r
30389 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI</B>
\r
30391 <TD width=15% BGCOLOR=#FBF5EF>
\r
30394 <TD width=10% BGCOLOR=#FBF5EF>
\r
30397 <TD width=10% BGCOLOR=#FBF5EF>
\r
30400 <TD width=15% BGCOLOR=#FBF5EF>
\r
30403 <TD width=35% BGCOLOR=#FBF5EF>
\r
30404 <B>Master Tri-state Enable for pin 71, active high</B>
\r
30407 <TR valign="top">
\r
30408 <TD width=15% BGCOLOR=#FBF5EF>
\r
30409 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI</B>
\r
30411 <TD width=15% BGCOLOR=#FBF5EF>
\r
30414 <TD width=10% BGCOLOR=#FBF5EF>
\r
30417 <TD width=10% BGCOLOR=#FBF5EF>
\r
30420 <TD width=15% BGCOLOR=#FBF5EF>
\r
30423 <TD width=35% BGCOLOR=#FBF5EF>
\r
30424 <B>Master Tri-state Enable for pin 72, active high</B>
\r
30427 <TR valign="top">
\r
30428 <TD width=15% BGCOLOR=#FBF5EF>
\r
30429 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI</B>
\r
30431 <TD width=15% BGCOLOR=#FBF5EF>
\r
30434 <TD width=10% BGCOLOR=#FBF5EF>
\r
30437 <TD width=10% BGCOLOR=#FBF5EF>
\r
30440 <TD width=15% BGCOLOR=#FBF5EF>
\r
30443 <TD width=35% BGCOLOR=#FBF5EF>
\r
30444 <B>Master Tri-state Enable for pin 73, active high</B>
\r
30447 <TR valign="top">
\r
30448 <TD width=15% BGCOLOR=#FBF5EF>
\r
30449 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI</B>
\r
30451 <TD width=15% BGCOLOR=#FBF5EF>
\r
30454 <TD width=10% BGCOLOR=#FBF5EF>
\r
30457 <TD width=10% BGCOLOR=#FBF5EF>
\r
30460 <TD width=15% BGCOLOR=#FBF5EF>
\r
30463 <TD width=35% BGCOLOR=#FBF5EF>
\r
30464 <B>Master Tri-state Enable for pin 74, active high</B>
\r
30467 <TR valign="top">
\r
30468 <TD width=15% BGCOLOR=#FBF5EF>
\r
30469 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI</B>
\r
30471 <TD width=15% BGCOLOR=#FBF5EF>
\r
30474 <TD width=10% BGCOLOR=#FBF5EF>
\r
30477 <TD width=10% BGCOLOR=#FBF5EF>
\r
30480 <TD width=15% BGCOLOR=#FBF5EF>
\r
30483 <TD width=35% BGCOLOR=#FBF5EF>
\r
30484 <B>Master Tri-state Enable for pin 75, active high</B>
\r
30487 <TR valign="top">
\r
30488 <TD width=15% BGCOLOR=#FBF5EF>
\r
30489 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI</B>
\r
30491 <TD width=15% BGCOLOR=#FBF5EF>
\r
30494 <TD width=10% BGCOLOR=#FBF5EF>
\r
30497 <TD width=10% BGCOLOR=#FBF5EF>
\r
30500 <TD width=15% BGCOLOR=#FBF5EF>
\r
30503 <TD width=35% BGCOLOR=#FBF5EF>
\r
30504 <B>Master Tri-state Enable for pin 76, active high</B>
\r
30507 <TR valign="top">
\r
30508 <TD width=15% BGCOLOR=#FBF5EF>
\r
30509 <B>PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI</B>
\r
30511 <TD width=15% BGCOLOR=#FBF5EF>
\r
30514 <TD width=10% BGCOLOR=#FBF5EF>
\r
30517 <TD width=10% BGCOLOR=#FBF5EF>
\r
30520 <TD width=15% BGCOLOR=#FBF5EF>
\r
30523 <TD width=35% BGCOLOR=#FBF5EF>
\r
30524 <B>Master Tri-state Enable for pin 77, active high</B>
\r
30527 <TR valign="top">
\r
30528 <TD width=15% BGCOLOR=#C0C0C0>
\r
30529 <B>PSU_IOU_SLCR_MIO_MST_TRI2@0XFF18020C</B>
\r
30531 <TD width=15% BGCOLOR=#C0C0C0>
\r
30534 <TD width=10% BGCOLOR=#C0C0C0>
\r
30537 <TD width=10% BGCOLOR=#C0C0C0>
\r
30540 <TD width=15% BGCOLOR=#C0C0C0>
\r
30543 <TD width=35% BGCOLOR=#C0C0C0>
\r
30544 <B>MIO pin Tri-state Enables, 77:64</B>
\r
30549 <H1>LOOPBACK</H1>
\r
30550 <H2><a name="MIO_LOOPBACK">Register (<A href=#mod___slcr> slcr </A>)MIO_LOOPBACK</a></H2>
\r
30551 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
30552 <TR valign="top">
\r
30553 <TD width=15% BGCOLOR=#FFFF00>
\r
30554 <B>Register Name</B>
\r
30556 <TD width=15% BGCOLOR=#FFFF00>
\r
30559 <TD width=10% BGCOLOR=#FFFF00>
\r
30562 <TD width=10% BGCOLOR=#FFFF00>
\r
30565 <TD width=15% BGCOLOR=#FFFF00>
\r
30566 <B>Reset Value</B>
\r
30568 <TD width=35% BGCOLOR=#FFFF00>
\r
30569 <B>Description</B>
\r
30572 <TR valign="top">
\r
30573 <TD width=15% BGCOLOR=#FBF5EF>
\r
30574 <B>MIO_LOOPBACK</B>
\r
30576 <TD width=15% BGCOLOR=#FBF5EF>
\r
30577 <B>0XFF180200</B>
\r
30579 <TD width=10% BGCOLOR=#FBF5EF>
\r
30582 <TD width=10% BGCOLOR=#FBF5EF>
\r
30585 <TD width=15% BGCOLOR=#FBF5EF>
\r
30586 <B>0x00000000</B>
\r
30588 <TD width=35% BGCOLOR=#FBF5EF>
\r
30594 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
30595 <TR valign="top">
\r
30596 <TD width=15% BGCOLOR=#C0FFC0>
\r
30597 <B>Field Name</B>
\r
30599 <TD width=15% BGCOLOR=#C0FFC0>
\r
30602 <TD width=10% BGCOLOR=#C0FFC0>
\r
30605 <TD width=10% BGCOLOR=#C0FFC0>
\r
30608 <TD width=15% BGCOLOR=#C0FFC0>
\r
30609 <B>Shifted Value</B>
\r
30611 <TD width=35% BGCOLOR=#C0FFC0>
\r
30612 <B>Description</B>
\r
30615 <TR valign="top">
\r
30616 <TD width=15% BGCOLOR=#FBF5EF>
\r
30617 <B>PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1</B>
\r
30619 <TD width=15% BGCOLOR=#FBF5EF>
\r
30622 <TD width=10% BGCOLOR=#FBF5EF>
\r
30625 <TD width=10% BGCOLOR=#FBF5EF>
\r
30628 <TD width=15% BGCOLOR=#FBF5EF>
\r
30631 <TD width=35% BGCOLOR=#FBF5EF>
\r
30632 <B>I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs.</B>
\r
30635 <TR valign="top">
\r
30636 <TD width=15% BGCOLOR=#FBF5EF>
\r
30637 <B>PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1</B>
\r
30639 <TD width=15% BGCOLOR=#FBF5EF>
\r
30642 <TD width=10% BGCOLOR=#FBF5EF>
\r
30645 <TD width=10% BGCOLOR=#FBF5EF>
\r
30648 <TD width=15% BGCOLOR=#FBF5EF>
\r
30651 <TD width=35% BGCOLOR=#FBF5EF>
\r
30652 <B>CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.</B>
\r
30655 <TR valign="top">
\r
30656 <TD width=15% BGCOLOR=#FBF5EF>
\r
30657 <B>PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1</B>
\r
30659 <TD width=15% BGCOLOR=#FBF5EF>
\r
30662 <TD width=10% BGCOLOR=#FBF5EF>
\r
30665 <TD width=10% BGCOLOR=#FBF5EF>
\r
30668 <TD width=15% BGCOLOR=#FBF5EF>
\r
30671 <TD width=35% BGCOLOR=#FBF5EF>
\r
30672 <B>UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.</B>
\r
30675 <TR valign="top">
\r
30676 <TD width=15% BGCOLOR=#FBF5EF>
\r
30677 <B>PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1</B>
\r
30679 <TD width=15% BGCOLOR=#FBF5EF>
\r
30682 <TD width=10% BGCOLOR=#FBF5EF>
\r
30685 <TD width=10% BGCOLOR=#FBF5EF>
\r
30688 <TD width=15% BGCOLOR=#FBF5EF>
\r
30691 <TD width=35% BGCOLOR=#FBF5EF>
\r
30692 <B>SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.</B>
\r
30695 <TR valign="top">
\r
30696 <TD width=15% BGCOLOR=#C0C0C0>
\r
30697 <B>PSU_IOU_SLCR_MIO_LOOPBACK@0XFF180200</B>
\r
30699 <TD width=15% BGCOLOR=#C0C0C0>
\r
30702 <TD width=10% BGCOLOR=#C0C0C0>
\r
30705 <TD width=10% BGCOLOR=#C0C0C0>
\r
30708 <TD width=15% BGCOLOR=#C0C0C0>
\r
30711 <TD width=35% BGCOLOR=#C0C0C0>
\r
30712 <B>Loopback function within MIO</B>
\r
30719 <H2><a name="psu_peripherals_init_data_3_0">psu_peripherals_init_data_3_0</a></H2>
\r
30720 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
30721 <TR valign="top">
\r
30722 <TD width=15% BGCOLOR=#FFC0FF>
\r
30723 <B>Register Name</B>
\r
30725 <TD width=15% BGCOLOR=#FFC0FF>
\r
30728 <TD width=10% BGCOLOR=#FFC0FF>
\r
30731 <TD width=10% BGCOLOR=#FFC0FF>
\r
30734 <TD width=15% BGCOLOR=#FFC0FF>
\r
30735 <B>Reset Value</B>
\r
30737 <TD width=35% BGCOLOR=#FFC0FF>
\r
30738 <B>Description</B>
\r
30741 <TR valign="top">
\r
30742 <TD width=15% BGCOLOR=#FBF5EF>
\r
30743 <A href="#PSU_CRL_APB_RST_LPD_IOU0">
\r
30744 PSU_CRL_APB_RST_LPD_IOU0
\r
30747 <TD width=15% BGCOLOR=#FBF5EF>
\r
30748 <B>0XFF5E0230</B>
\r
30750 <TD width=10% BGCOLOR=#FBF5EF>
\r
30753 <TD width=10% BGCOLOR=#FBF5EF>
\r
30756 <TD width=15% BGCOLOR=#FBF5EF>
\r
30759 <TD width=35% BGCOLOR=#FBF5EF>
\r
30760 <B>Software controlled reset for the GEMs</B>
\r
30763 <TR valign="top">
\r
30764 <TD width=15% BGCOLOR=#FBF5EF>
\r
30765 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30766 PSU_CRL_APB_RST_LPD_IOU2
\r
30769 <TD width=15% BGCOLOR=#FBF5EF>
\r
30770 <B>0XFF5E0238</B>
\r
30772 <TD width=10% BGCOLOR=#FBF5EF>
\r
30775 <TD width=10% BGCOLOR=#FBF5EF>
\r
30778 <TD width=15% BGCOLOR=#FBF5EF>
\r
30781 <TD width=35% BGCOLOR=#FBF5EF>
\r
30782 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30785 <TR valign="top">
\r
30786 <TD width=15% BGCOLOR=#FBF5EF>
\r
30787 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30788 PSU_CRL_APB_RST_LPD_IOU2
\r
30791 <TD width=15% BGCOLOR=#FBF5EF>
\r
30792 <B>0XFF5E0238</B>
\r
30794 <TD width=10% BGCOLOR=#FBF5EF>
\r
30797 <TD width=10% BGCOLOR=#FBF5EF>
\r
30800 <TD width=15% BGCOLOR=#FBF5EF>
\r
30803 <TD width=35% BGCOLOR=#FBF5EF>
\r
30804 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30807 <TR valign="top">
\r
30808 <TD width=15% BGCOLOR=#FBF5EF>
\r
30809 <A href="#PSU_CRL_APB_RST_LPD_TOP">
\r
30810 PSU_CRL_APB_RST_LPD_TOP
\r
30813 <TD width=15% BGCOLOR=#FBF5EF>
\r
30814 <B>0XFF5E023C</B>
\r
30816 <TD width=10% BGCOLOR=#FBF5EF>
\r
30819 <TD width=10% BGCOLOR=#FBF5EF>
\r
30822 <TD width=15% BGCOLOR=#FBF5EF>
\r
30825 <TD width=35% BGCOLOR=#FBF5EF>
\r
30826 <B>Software control register for the LPD block.</B>
\r
30829 <TR valign="top">
\r
30830 <TD width=15% BGCOLOR=#FBF5EF>
\r
30831 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30832 PSU_CRL_APB_RST_LPD_IOU2
\r
30835 <TD width=15% BGCOLOR=#FBF5EF>
\r
30836 <B>0XFF5E0238</B>
\r
30838 <TD width=10% BGCOLOR=#FBF5EF>
\r
30841 <TD width=10% BGCOLOR=#FBF5EF>
\r
30844 <TD width=15% BGCOLOR=#FBF5EF>
\r
30847 <TD width=35% BGCOLOR=#FBF5EF>
\r
30848 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30851 <TR valign="top">
\r
30852 <TD width=15% BGCOLOR=#FBF5EF>
\r
30853 <A href="#PSU_IOU_SLCR_CTRL_REG_SD">
\r
30854 PSU_IOU_SLCR_CTRL_REG_SD
\r
30857 <TD width=15% BGCOLOR=#FBF5EF>
\r
30858 <B>0XFF180310</B>
\r
30860 <TD width=10% BGCOLOR=#FBF5EF>
\r
30863 <TD width=10% BGCOLOR=#FBF5EF>
\r
30866 <TD width=15% BGCOLOR=#FBF5EF>
\r
30869 <TD width=35% BGCOLOR=#FBF5EF>
\r
30870 <B>SD eMMC selection</B>
\r
30873 <TR valign="top">
\r
30874 <TD width=15% BGCOLOR=#FBF5EF>
\r
30875 <A href="#PSU_IOU_SLCR_SD_CONFIG_REG2">
\r
30876 PSU_IOU_SLCR_SD_CONFIG_REG2
\r
30879 <TD width=15% BGCOLOR=#FBF5EF>
\r
30880 <B>0XFF180320</B>
\r
30882 <TD width=10% BGCOLOR=#FBF5EF>
\r
30885 <TD width=10% BGCOLOR=#FBF5EF>
\r
30888 <TD width=15% BGCOLOR=#FBF5EF>
\r
30891 <TD width=35% BGCOLOR=#FBF5EF>
\r
30892 <B>SD Config Register 2</B>
\r
30895 <TR valign="top">
\r
30896 <TD width=15% BGCOLOR=#FBF5EF>
\r
30897 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30898 PSU_CRL_APB_RST_LPD_IOU2
\r
30901 <TD width=15% BGCOLOR=#FBF5EF>
\r
30902 <B>0XFF5E0238</B>
\r
30904 <TD width=10% BGCOLOR=#FBF5EF>
\r
30907 <TD width=10% BGCOLOR=#FBF5EF>
\r
30910 <TD width=15% BGCOLOR=#FBF5EF>
\r
30913 <TD width=35% BGCOLOR=#FBF5EF>
\r
30914 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30917 <TR valign="top">
\r
30918 <TD width=15% BGCOLOR=#FBF5EF>
\r
30919 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30920 PSU_CRL_APB_RST_LPD_IOU2
\r
30923 <TD width=15% BGCOLOR=#FBF5EF>
\r
30924 <B>0XFF5E0238</B>
\r
30926 <TD width=10% BGCOLOR=#FBF5EF>
\r
30929 <TD width=10% BGCOLOR=#FBF5EF>
\r
30932 <TD width=15% BGCOLOR=#FBF5EF>
\r
30935 <TD width=35% BGCOLOR=#FBF5EF>
\r
30936 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30939 <TR valign="top">
\r
30940 <TD width=15% BGCOLOR=#FBF5EF>
\r
30941 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30942 PSU_CRL_APB_RST_LPD_IOU2
\r
30945 <TD width=15% BGCOLOR=#FBF5EF>
\r
30946 <B>0XFF5E0238</B>
\r
30948 <TD width=10% BGCOLOR=#FBF5EF>
\r
30951 <TD width=10% BGCOLOR=#FBF5EF>
\r
30954 <TD width=15% BGCOLOR=#FBF5EF>
\r
30957 <TD width=35% BGCOLOR=#FBF5EF>
\r
30958 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30961 <TR valign="top">
\r
30962 <TD width=15% BGCOLOR=#FBF5EF>
\r
30963 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30964 PSU_CRL_APB_RST_LPD_IOU2
\r
30967 <TD width=15% BGCOLOR=#FBF5EF>
\r
30968 <B>0XFF5E0238</B>
\r
30970 <TD width=10% BGCOLOR=#FBF5EF>
\r
30973 <TD width=10% BGCOLOR=#FBF5EF>
\r
30976 <TD width=15% BGCOLOR=#FBF5EF>
\r
30979 <TD width=35% BGCOLOR=#FBF5EF>
\r
30980 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
30983 <TR valign="top">
\r
30984 <TD width=15% BGCOLOR=#FBF5EF>
\r
30985 <A href="#PSU_CRL_APB_RST_LPD_IOU2">
\r
30986 PSU_CRL_APB_RST_LPD_IOU2
\r
30989 <TD width=15% BGCOLOR=#FBF5EF>
\r
30990 <B>0XFF5E0238</B>
\r
30992 <TD width=10% BGCOLOR=#FBF5EF>
\r
30995 <TD width=10% BGCOLOR=#FBF5EF>
\r
30998 <TD width=15% BGCOLOR=#FBF5EF>
\r
31001 <TD width=35% BGCOLOR=#FBF5EF>
\r
31002 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
31005 <TR valign="top">
\r
31006 <TD width=15% BGCOLOR=#FBF5EF>
\r
31007 <A href="#PSU_UART0_BAUD_RATE_DIVIDER_REG0">
\r
31008 PSU_UART0_BAUD_RATE_DIVIDER_REG0
\r
31011 <TD width=15% BGCOLOR=#FBF5EF>
\r
31012 <B>0XFF000034</B>
\r
31014 <TD width=10% BGCOLOR=#FBF5EF>
\r
31017 <TD width=10% BGCOLOR=#FBF5EF>
\r
31020 <TD width=15% BGCOLOR=#FBF5EF>
\r
31023 <TD width=35% BGCOLOR=#FBF5EF>
\r
31024 <B>Baud Rate Divider Register</B>
\r
31027 <TR valign="top">
\r
31028 <TD width=15% BGCOLOR=#FBF5EF>
\r
31029 <A href="#PSU_UART0_BAUD_RATE_GEN_REG0">
\r
31030 PSU_UART0_BAUD_RATE_GEN_REG0
\r
31033 <TD width=15% BGCOLOR=#FBF5EF>
\r
31034 <B>0XFF000018</B>
\r
31036 <TD width=10% BGCOLOR=#FBF5EF>
\r
31039 <TD width=10% BGCOLOR=#FBF5EF>
\r
31042 <TD width=15% BGCOLOR=#FBF5EF>
\r
31045 <TD width=35% BGCOLOR=#FBF5EF>
\r
31046 <B>Baud Rate Generator Register.</B>
\r
31049 <TR valign="top">
\r
31050 <TD width=15% BGCOLOR=#FBF5EF>
\r
31051 <A href="#PSU_UART0_CONTROL_REG0">
\r
31052 PSU_UART0_CONTROL_REG0
\r
31055 <TD width=15% BGCOLOR=#FBF5EF>
\r
31056 <B>0XFF000000</B>
\r
31058 <TD width=10% BGCOLOR=#FBF5EF>
\r
31061 <TD width=10% BGCOLOR=#FBF5EF>
\r
31064 <TD width=15% BGCOLOR=#FBF5EF>
\r
31067 <TD width=35% BGCOLOR=#FBF5EF>
\r
31068 <B>UART Control Register</B>
\r
31071 <TR valign="top">
\r
31072 <TD width=15% BGCOLOR=#FBF5EF>
\r
31073 <A href="#PSU_UART0_MODE_REG0">
\r
31074 PSU_UART0_MODE_REG0
\r
31077 <TD width=15% BGCOLOR=#FBF5EF>
\r
31078 <B>0XFF000004</B>
\r
31080 <TD width=10% BGCOLOR=#FBF5EF>
\r
31083 <TD width=10% BGCOLOR=#FBF5EF>
\r
31086 <TD width=15% BGCOLOR=#FBF5EF>
\r
31089 <TD width=35% BGCOLOR=#FBF5EF>
\r
31090 <B>UART Mode Register</B>
\r
31093 <TR valign="top">
\r
31094 <TD width=15% BGCOLOR=#FBF5EF>
\r
31095 <A href="#PSU_UART1_BAUD_RATE_DIVIDER_REG0">
\r
31096 PSU_UART1_BAUD_RATE_DIVIDER_REG0
\r
31099 <TD width=15% BGCOLOR=#FBF5EF>
\r
31100 <B>0XFF010034</B>
\r
31102 <TD width=10% BGCOLOR=#FBF5EF>
\r
31105 <TD width=10% BGCOLOR=#FBF5EF>
\r
31108 <TD width=15% BGCOLOR=#FBF5EF>
\r
31111 <TD width=35% BGCOLOR=#FBF5EF>
\r
31112 <B>Baud Rate Divider Register</B>
\r
31115 <TR valign="top">
\r
31116 <TD width=15% BGCOLOR=#FBF5EF>
\r
31117 <A href="#PSU_UART1_BAUD_RATE_GEN_REG0">
\r
31118 PSU_UART1_BAUD_RATE_GEN_REG0
\r
31121 <TD width=15% BGCOLOR=#FBF5EF>
\r
31122 <B>0XFF010018</B>
\r
31124 <TD width=10% BGCOLOR=#FBF5EF>
\r
31127 <TD width=10% BGCOLOR=#FBF5EF>
\r
31130 <TD width=15% BGCOLOR=#FBF5EF>
\r
31133 <TD width=35% BGCOLOR=#FBF5EF>
\r
31134 <B>Baud Rate Generator Register.</B>
\r
31137 <TR valign="top">
\r
31138 <TD width=15% BGCOLOR=#FBF5EF>
\r
31139 <A href="#PSU_UART1_CONTROL_REG0">
\r
31140 PSU_UART1_CONTROL_REG0
\r
31143 <TD width=15% BGCOLOR=#FBF5EF>
\r
31144 <B>0XFF010000</B>
\r
31146 <TD width=10% BGCOLOR=#FBF5EF>
\r
31149 <TD width=10% BGCOLOR=#FBF5EF>
\r
31152 <TD width=15% BGCOLOR=#FBF5EF>
\r
31155 <TD width=35% BGCOLOR=#FBF5EF>
\r
31156 <B>UART Control Register</B>
\r
31159 <TR valign="top">
\r
31160 <TD width=15% BGCOLOR=#FBF5EF>
\r
31161 <A href="#PSU_UART1_MODE_REG0">
\r
31162 PSU_UART1_MODE_REG0
\r
31165 <TD width=15% BGCOLOR=#FBF5EF>
\r
31166 <B>0XFF010004</B>
\r
31168 <TD width=10% BGCOLOR=#FBF5EF>
\r
31171 <TD width=10% BGCOLOR=#FBF5EF>
\r
31174 <TD width=15% BGCOLOR=#FBF5EF>
\r
31177 <TD width=35% BGCOLOR=#FBF5EF>
\r
31178 <B>UART Mode Register</B>
\r
31181 <TR valign="top">
\r
31182 <TD width=15% BGCOLOR=#FBF5EF>
\r
31183 <A href="#PSU_LPD_SLCR_SECURE_SLCR_ADMA">
\r
31184 PSU_LPD_SLCR_SECURE_SLCR_ADMA
\r
31187 <TD width=15% BGCOLOR=#FBF5EF>
\r
31188 <B>0XFF4B0024</B>
\r
31190 <TD width=10% BGCOLOR=#FBF5EF>
\r
31193 <TD width=10% BGCOLOR=#FBF5EF>
\r
31196 <TD width=15% BGCOLOR=#FBF5EF>
\r
31199 <TD width=35% BGCOLOR=#FBF5EF>
\r
31200 <B>RPU TrustZone settings</B>
\r
31203 <TR valign="top">
\r
31204 <TD width=15% BGCOLOR=#FBF5EF>
\r
31205 <A href="#PSU_CSU_TAMPER_STATUS">
\r
31206 PSU_CSU_TAMPER_STATUS
\r
31209 <TD width=15% BGCOLOR=#FBF5EF>
\r
31210 <B>0XFFCA5000</B>
\r
31212 <TD width=10% BGCOLOR=#FBF5EF>
\r
31215 <TD width=10% BGCOLOR=#FBF5EF>
\r
31218 <TD width=15% BGCOLOR=#FBF5EF>
\r
31221 <TD width=35% BGCOLOR=#FBF5EF>
\r
31222 <B>Tamper Response Status</B>
\r
31227 <H2><a name="psu_peripherals_init_data_3_0">psu_peripherals_init_data_3_0</a></H2>
\r
31228 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31229 <TR valign="top">
\r
31230 <TD width=15% BGCOLOR=#FFC0FF>
\r
31231 <B>Register Name</B>
\r
31233 <TD width=15% BGCOLOR=#FFC0FF>
\r
31236 <TD width=10% BGCOLOR=#FFC0FF>
\r
31239 <TD width=10% BGCOLOR=#FFC0FF>
\r
31242 <TD width=15% BGCOLOR=#FFC0FF>
\r
31243 <B>Reset Value</B>
\r
31245 <TD width=35% BGCOLOR=#FFC0FF>
\r
31246 <B>Description</B>
\r
31250 <H2><a name="RST_LPD_IOU0">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU0</a></H2>
\r
31251 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31252 <TR valign="top">
\r
31253 <TD width=15% BGCOLOR=#FFFF00>
\r
31254 <B>Register Name</B>
\r
31256 <TD width=15% BGCOLOR=#FFFF00>
\r
31259 <TD width=10% BGCOLOR=#FFFF00>
\r
31262 <TD width=10% BGCOLOR=#FFFF00>
\r
31265 <TD width=15% BGCOLOR=#FFFF00>
\r
31266 <B>Reset Value</B>
\r
31268 <TD width=35% BGCOLOR=#FFFF00>
\r
31269 <B>Description</B>
\r
31272 <TR valign="top">
\r
31273 <TD width=15% BGCOLOR=#FBF5EF>
\r
31274 <B>RST_LPD_IOU0</B>
\r
31276 <TD width=15% BGCOLOR=#FBF5EF>
\r
31277 <B>0XFF5E0230</B>
\r
31279 <TD width=10% BGCOLOR=#FBF5EF>
\r
31282 <TD width=10% BGCOLOR=#FBF5EF>
\r
31285 <TD width=15% BGCOLOR=#FBF5EF>
\r
31286 <B>0x00000000</B>
\r
31288 <TD width=35% BGCOLOR=#FBF5EF>
\r
31294 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31295 <TR valign="top">
\r
31296 <TD width=15% BGCOLOR=#C0FFC0>
\r
31297 <B>Field Name</B>
\r
31299 <TD width=15% BGCOLOR=#C0FFC0>
\r
31302 <TD width=10% BGCOLOR=#C0FFC0>
\r
31305 <TD width=10% BGCOLOR=#C0FFC0>
\r
31308 <TD width=15% BGCOLOR=#C0FFC0>
\r
31309 <B>Shifted Value</B>
\r
31311 <TD width=35% BGCOLOR=#C0FFC0>
\r
31312 <B>Description</B>
\r
31315 <TR valign="top">
\r
31316 <TD width=15% BGCOLOR=#FBF5EF>
\r
31317 <B>PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET</B>
\r
31319 <TD width=15% BGCOLOR=#FBF5EF>
\r
31322 <TD width=10% BGCOLOR=#FBF5EF>
\r
31325 <TD width=10% BGCOLOR=#FBF5EF>
\r
31328 <TD width=15% BGCOLOR=#FBF5EF>
\r
31331 <TD width=35% BGCOLOR=#FBF5EF>
\r
31332 <B>GEM 0 reset</B>
\r
31335 <TR valign="top">
\r
31336 <TD width=15% BGCOLOR=#FBF5EF>
\r
31337 <B>PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET</B>
\r
31339 <TD width=15% BGCOLOR=#FBF5EF>
\r
31342 <TD width=10% BGCOLOR=#FBF5EF>
\r
31345 <TD width=10% BGCOLOR=#FBF5EF>
\r
31348 <TD width=15% BGCOLOR=#FBF5EF>
\r
31351 <TD width=35% BGCOLOR=#FBF5EF>
\r
31352 <B>GEM 1 reset</B>
\r
31355 <TR valign="top">
\r
31356 <TD width=15% BGCOLOR=#FBF5EF>
\r
31357 <B>PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET</B>
\r
31359 <TD width=15% BGCOLOR=#FBF5EF>
\r
31362 <TD width=10% BGCOLOR=#FBF5EF>
\r
31365 <TD width=10% BGCOLOR=#FBF5EF>
\r
31368 <TD width=15% BGCOLOR=#FBF5EF>
\r
31371 <TD width=35% BGCOLOR=#FBF5EF>
\r
31372 <B>GEM 2 reset</B>
\r
31375 <TR valign="top">
\r
31376 <TD width=15% BGCOLOR=#FBF5EF>
\r
31377 <B>PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET</B>
\r
31379 <TD width=15% BGCOLOR=#FBF5EF>
\r
31382 <TD width=10% BGCOLOR=#FBF5EF>
\r
31385 <TD width=10% BGCOLOR=#FBF5EF>
\r
31388 <TD width=15% BGCOLOR=#FBF5EF>
\r
31391 <TD width=35% BGCOLOR=#FBF5EF>
\r
31392 <B>GEM 3 reset</B>
\r
31395 <TR valign="top">
\r
31396 <TD width=15% BGCOLOR=#C0C0C0>
\r
31397 <B>PSU_CRL_APB_RST_LPD_IOU0@0XFF5E0230</B>
\r
31399 <TD width=15% BGCOLOR=#C0C0C0>
\r
31402 <TD width=10% BGCOLOR=#C0C0C0>
\r
31405 <TD width=10% BGCOLOR=#C0C0C0>
\r
31408 <TD width=15% BGCOLOR=#C0C0C0>
\r
31411 <TD width=35% BGCOLOR=#C0C0C0>
\r
31412 <B>Software controlled reset for the GEMs</B>
\r
31418 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
31419 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31420 <TR valign="top">
\r
31421 <TD width=15% BGCOLOR=#FFFF00>
\r
31422 <B>Register Name</B>
\r
31424 <TD width=15% BGCOLOR=#FFFF00>
\r
31427 <TD width=10% BGCOLOR=#FFFF00>
\r
31430 <TD width=10% BGCOLOR=#FFFF00>
\r
31433 <TD width=15% BGCOLOR=#FFFF00>
\r
31434 <B>Reset Value</B>
\r
31436 <TD width=35% BGCOLOR=#FFFF00>
\r
31437 <B>Description</B>
\r
31440 <TR valign="top">
\r
31441 <TD width=15% BGCOLOR=#FBF5EF>
\r
31442 <B>RST_LPD_IOU2</B>
\r
31444 <TD width=15% BGCOLOR=#FBF5EF>
\r
31445 <B>0XFF5E0238</B>
\r
31447 <TD width=10% BGCOLOR=#FBF5EF>
\r
31450 <TD width=10% BGCOLOR=#FBF5EF>
\r
31453 <TD width=15% BGCOLOR=#FBF5EF>
\r
31454 <B>0x00000000</B>
\r
31456 <TD width=35% BGCOLOR=#FBF5EF>
\r
31462 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31463 <TR valign="top">
\r
31464 <TD width=15% BGCOLOR=#C0FFC0>
\r
31465 <B>Field Name</B>
\r
31467 <TD width=15% BGCOLOR=#C0FFC0>
\r
31470 <TD width=10% BGCOLOR=#C0FFC0>
\r
31473 <TD width=10% BGCOLOR=#C0FFC0>
\r
31476 <TD width=15% BGCOLOR=#C0FFC0>
\r
31477 <B>Shifted Value</B>
\r
31479 <TD width=35% BGCOLOR=#C0FFC0>
\r
31480 <B>Description</B>
\r
31483 <TR valign="top">
\r
31484 <TD width=15% BGCOLOR=#FBF5EF>
\r
31485 <B>PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET</B>
\r
31487 <TD width=15% BGCOLOR=#FBF5EF>
\r
31490 <TD width=10% BGCOLOR=#FBF5EF>
\r
31493 <TD width=10% BGCOLOR=#FBF5EF>
\r
31496 <TD width=15% BGCOLOR=#FBF5EF>
\r
31499 <TD width=35% BGCOLOR=#FBF5EF>
\r
31500 <B>Block level reset</B>
\r
31503 <TR valign="top">
\r
31504 <TD width=15% BGCOLOR=#C0C0C0>
\r
31505 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
31507 <TD width=15% BGCOLOR=#C0C0C0>
\r
31510 <TD width=10% BGCOLOR=#C0C0C0>
\r
31513 <TD width=10% BGCOLOR=#C0C0C0>
\r
31516 <TD width=15% BGCOLOR=#C0C0C0>
\r
31519 <TD width=35% BGCOLOR=#C0C0C0>
\r
31520 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
31526 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
31527 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31528 <TR valign="top">
\r
31529 <TD width=15% BGCOLOR=#FFFF00>
\r
31530 <B>Register Name</B>
\r
31532 <TD width=15% BGCOLOR=#FFFF00>
\r
31535 <TD width=10% BGCOLOR=#FFFF00>
\r
31538 <TD width=10% BGCOLOR=#FFFF00>
\r
31541 <TD width=15% BGCOLOR=#FFFF00>
\r
31542 <B>Reset Value</B>
\r
31544 <TD width=35% BGCOLOR=#FFFF00>
\r
31545 <B>Description</B>
\r
31548 <TR valign="top">
\r
31549 <TD width=15% BGCOLOR=#FBF5EF>
\r
31550 <B>RST_LPD_IOU2</B>
\r
31552 <TD width=15% BGCOLOR=#FBF5EF>
\r
31553 <B>0XFF5E0238</B>
\r
31555 <TD width=10% BGCOLOR=#FBF5EF>
\r
31558 <TD width=10% BGCOLOR=#FBF5EF>
\r
31561 <TD width=15% BGCOLOR=#FBF5EF>
\r
31562 <B>0x00000000</B>
\r
31564 <TD width=35% BGCOLOR=#FBF5EF>
\r
31570 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31571 <TR valign="top">
\r
31572 <TD width=15% BGCOLOR=#C0FFC0>
\r
31573 <B>Field Name</B>
\r
31575 <TD width=15% BGCOLOR=#C0FFC0>
\r
31578 <TD width=10% BGCOLOR=#C0FFC0>
\r
31581 <TD width=10% BGCOLOR=#C0FFC0>
\r
31584 <TD width=15% BGCOLOR=#C0FFC0>
\r
31585 <B>Shifted Value</B>
\r
31587 <TD width=35% BGCOLOR=#C0FFC0>
\r
31588 <B>Description</B>
\r
31591 <TR valign="top">
\r
31592 <TD width=15% BGCOLOR=#FBF5EF>
\r
31593 <B>PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET</B>
\r
31595 <TD width=15% BGCOLOR=#FBF5EF>
\r
31598 <TD width=10% BGCOLOR=#FBF5EF>
\r
31601 <TD width=10% BGCOLOR=#FBF5EF>
\r
31604 <TD width=15% BGCOLOR=#FBF5EF>
\r
31607 <TD width=35% BGCOLOR=#FBF5EF>
\r
31608 <B>Block level reset</B>
\r
31611 <TR valign="top">
\r
31612 <TD width=15% BGCOLOR=#C0C0C0>
\r
31613 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
31615 <TD width=15% BGCOLOR=#C0C0C0>
\r
31618 <TD width=10% BGCOLOR=#C0C0C0>
\r
31621 <TD width=10% BGCOLOR=#C0C0C0>
\r
31624 <TD width=15% BGCOLOR=#C0C0C0>
\r
31627 <TD width=35% BGCOLOR=#C0C0C0>
\r
31628 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
31634 <H2><a name="RST_LPD_TOP">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_TOP</a></H2>
\r
31635 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31636 <TR valign="top">
\r
31637 <TD width=15% BGCOLOR=#FFFF00>
\r
31638 <B>Register Name</B>
\r
31640 <TD width=15% BGCOLOR=#FFFF00>
\r
31643 <TD width=10% BGCOLOR=#FFFF00>
\r
31646 <TD width=10% BGCOLOR=#FFFF00>
\r
31649 <TD width=15% BGCOLOR=#FFFF00>
\r
31650 <B>Reset Value</B>
\r
31652 <TD width=35% BGCOLOR=#FFFF00>
\r
31653 <B>Description</B>
\r
31656 <TR valign="top">
\r
31657 <TD width=15% BGCOLOR=#FBF5EF>
\r
31658 <B>RST_LPD_TOP</B>
\r
31660 <TD width=15% BGCOLOR=#FBF5EF>
\r
31661 <B>0XFF5E023C</B>
\r
31663 <TD width=10% BGCOLOR=#FBF5EF>
\r
31666 <TD width=10% BGCOLOR=#FBF5EF>
\r
31669 <TD width=15% BGCOLOR=#FBF5EF>
\r
31670 <B>0x00000000</B>
\r
31672 <TD width=35% BGCOLOR=#FBF5EF>
\r
31678 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31679 <TR valign="top">
\r
31680 <TD width=15% BGCOLOR=#C0FFC0>
\r
31681 <B>Field Name</B>
\r
31683 <TD width=15% BGCOLOR=#C0FFC0>
\r
31686 <TD width=10% BGCOLOR=#C0FFC0>
\r
31689 <TD width=10% BGCOLOR=#C0FFC0>
\r
31692 <TD width=15% BGCOLOR=#C0FFC0>
\r
31693 <B>Shifted Value</B>
\r
31695 <TD width=35% BGCOLOR=#C0FFC0>
\r
31696 <B>Description</B>
\r
31699 <TR valign="top">
\r
31700 <TD width=15% BGCOLOR=#FBF5EF>
\r
31701 <B>PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET</B>
\r
31703 <TD width=15% BGCOLOR=#FBF5EF>
\r
31706 <TD width=10% BGCOLOR=#FBF5EF>
\r
31709 <TD width=10% BGCOLOR=#FBF5EF>
\r
31712 <TD width=15% BGCOLOR=#FBF5EF>
\r
31715 <TD width=35% BGCOLOR=#FBF5EF>
\r
31716 <B>USB 0 reset for control registers</B>
\r
31719 <TR valign="top">
\r
31720 <TD width=15% BGCOLOR=#FBF5EF>
\r
31721 <B>PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET</B>
\r
31723 <TD width=15% BGCOLOR=#FBF5EF>
\r
31726 <TD width=10% BGCOLOR=#FBF5EF>
\r
31729 <TD width=10% BGCOLOR=#FBF5EF>
\r
31732 <TD width=15% BGCOLOR=#FBF5EF>
\r
31735 <TD width=35% BGCOLOR=#FBF5EF>
\r
31736 <B>USB 0 sleep circuit reset</B>
\r
31739 <TR valign="top">
\r
31740 <TD width=15% BGCOLOR=#FBF5EF>
\r
31741 <B>PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET</B>
\r
31743 <TD width=15% BGCOLOR=#FBF5EF>
\r
31746 <TD width=10% BGCOLOR=#FBF5EF>
\r
31749 <TD width=10% BGCOLOR=#FBF5EF>
\r
31752 <TD width=15% BGCOLOR=#FBF5EF>
\r
31755 <TD width=35% BGCOLOR=#FBF5EF>
\r
31756 <B>USB 0 reset</B>
\r
31759 <TR valign="top">
\r
31760 <TD width=15% BGCOLOR=#C0C0C0>
\r
31761 <B>PSU_CRL_APB_RST_LPD_TOP@0XFF5E023C</B>
\r
31763 <TD width=15% BGCOLOR=#C0C0C0>
\r
31766 <TD width=10% BGCOLOR=#C0C0C0>
\r
31769 <TD width=10% BGCOLOR=#C0C0C0>
\r
31772 <TD width=15% BGCOLOR=#C0C0C0>
\r
31775 <TD width=35% BGCOLOR=#C0C0C0>
\r
31776 <B>Software control register for the LPD block.</B>
\r
31782 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
31783 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31784 <TR valign="top">
\r
31785 <TD width=15% BGCOLOR=#FFFF00>
\r
31786 <B>Register Name</B>
\r
31788 <TD width=15% BGCOLOR=#FFFF00>
\r
31791 <TD width=10% BGCOLOR=#FFFF00>
\r
31794 <TD width=10% BGCOLOR=#FFFF00>
\r
31797 <TD width=15% BGCOLOR=#FFFF00>
\r
31798 <B>Reset Value</B>
\r
31800 <TD width=35% BGCOLOR=#FFFF00>
\r
31801 <B>Description</B>
\r
31804 <TR valign="top">
\r
31805 <TD width=15% BGCOLOR=#FBF5EF>
\r
31806 <B>RST_LPD_IOU2</B>
\r
31808 <TD width=15% BGCOLOR=#FBF5EF>
\r
31809 <B>0XFF5E0238</B>
\r
31811 <TD width=10% BGCOLOR=#FBF5EF>
\r
31814 <TD width=10% BGCOLOR=#FBF5EF>
\r
31817 <TD width=15% BGCOLOR=#FBF5EF>
\r
31818 <B>0x00000000</B>
\r
31820 <TD width=35% BGCOLOR=#FBF5EF>
\r
31826 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31827 <TR valign="top">
\r
31828 <TD width=15% BGCOLOR=#C0FFC0>
\r
31829 <B>Field Name</B>
\r
31831 <TD width=15% BGCOLOR=#C0FFC0>
\r
31834 <TD width=10% BGCOLOR=#C0FFC0>
\r
31837 <TD width=10% BGCOLOR=#C0FFC0>
\r
31840 <TD width=15% BGCOLOR=#C0FFC0>
\r
31841 <B>Shifted Value</B>
\r
31843 <TD width=35% BGCOLOR=#C0FFC0>
\r
31844 <B>Description</B>
\r
31847 <TR valign="top">
\r
31848 <TD width=15% BGCOLOR=#FBF5EF>
\r
31849 <B>PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET</B>
\r
31851 <TD width=15% BGCOLOR=#FBF5EF>
\r
31854 <TD width=10% BGCOLOR=#FBF5EF>
\r
31857 <TD width=10% BGCOLOR=#FBF5EF>
\r
31860 <TD width=15% BGCOLOR=#FBF5EF>
\r
31863 <TD width=35% BGCOLOR=#FBF5EF>
\r
31864 <B>Block level reset</B>
\r
31867 <TR valign="top">
\r
31868 <TD width=15% BGCOLOR=#FBF5EF>
\r
31869 <B>PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET</B>
\r
31871 <TD width=15% BGCOLOR=#FBF5EF>
\r
31874 <TD width=10% BGCOLOR=#FBF5EF>
\r
31877 <TD width=10% BGCOLOR=#FBF5EF>
\r
31880 <TD width=15% BGCOLOR=#FBF5EF>
\r
31883 <TD width=35% BGCOLOR=#FBF5EF>
\r
31884 <B>Block level reset</B>
\r
31887 <TR valign="top">
\r
31888 <TD width=15% BGCOLOR=#C0C0C0>
\r
31889 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
31891 <TD width=15% BGCOLOR=#C0C0C0>
\r
31894 <TD width=10% BGCOLOR=#C0C0C0>
\r
31897 <TD width=10% BGCOLOR=#C0C0C0>
\r
31900 <TD width=15% BGCOLOR=#C0C0C0>
\r
31903 <TD width=35% BGCOLOR=#C0C0C0>
\r
31904 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
31909 <H2><a name="CTRL_REG_SD">Register (<A href=#mod___slcr> slcr </A>)CTRL_REG_SD</a></H2>
\r
31910 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31911 <TR valign="top">
\r
31912 <TD width=15% BGCOLOR=#FFFF00>
\r
31913 <B>Register Name</B>
\r
31915 <TD width=15% BGCOLOR=#FFFF00>
\r
31918 <TD width=10% BGCOLOR=#FFFF00>
\r
31921 <TD width=10% BGCOLOR=#FFFF00>
\r
31924 <TD width=15% BGCOLOR=#FFFF00>
\r
31925 <B>Reset Value</B>
\r
31927 <TD width=35% BGCOLOR=#FFFF00>
\r
31928 <B>Description</B>
\r
31931 <TR valign="top">
\r
31932 <TD width=15% BGCOLOR=#FBF5EF>
\r
31933 <B>CTRL_REG_SD</B>
\r
31935 <TD width=15% BGCOLOR=#FBF5EF>
\r
31936 <B>0XFF180310</B>
\r
31938 <TD width=10% BGCOLOR=#FBF5EF>
\r
31941 <TD width=10% BGCOLOR=#FBF5EF>
\r
31944 <TD width=15% BGCOLOR=#FBF5EF>
\r
31945 <B>0x00000000</B>
\r
31947 <TD width=35% BGCOLOR=#FBF5EF>
\r
31953 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
31954 <TR valign="top">
\r
31955 <TD width=15% BGCOLOR=#C0FFC0>
\r
31956 <B>Field Name</B>
\r
31958 <TD width=15% BGCOLOR=#C0FFC0>
\r
31961 <TD width=10% BGCOLOR=#C0FFC0>
\r
31964 <TD width=10% BGCOLOR=#C0FFC0>
\r
31967 <TD width=15% BGCOLOR=#C0FFC0>
\r
31968 <B>Shifted Value</B>
\r
31970 <TD width=35% BGCOLOR=#C0FFC0>
\r
31971 <B>Description</B>
\r
31974 <TR valign="top">
\r
31975 <TD width=15% BGCOLOR=#FBF5EF>
\r
31976 <B>PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL</B>
\r
31978 <TD width=15% BGCOLOR=#FBF5EF>
\r
31981 <TD width=10% BGCOLOR=#FBF5EF>
\r
31984 <TD width=10% BGCOLOR=#FBF5EF>
\r
31987 <TD width=15% BGCOLOR=#FBF5EF>
\r
31990 <TD width=35% BGCOLOR=#FBF5EF>
\r
31991 <B>SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled</B>
\r
31994 <TR valign="top">
\r
31995 <TD width=15% BGCOLOR=#FBF5EF>
\r
31996 <B>PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL</B>
\r
31998 <TD width=15% BGCOLOR=#FBF5EF>
\r
32001 <TD width=10% BGCOLOR=#FBF5EF>
\r
32004 <TD width=10% BGCOLOR=#FBF5EF>
\r
32007 <TD width=15% BGCOLOR=#FBF5EF>
\r
32010 <TD width=35% BGCOLOR=#FBF5EF>
\r
32011 <B>SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled</B>
\r
32014 <TR valign="top">
\r
32015 <TD width=15% BGCOLOR=#C0C0C0>
\r
32016 <B>PSU_IOU_SLCR_CTRL_REG_SD@0XFF180310</B>
\r
32018 <TD width=15% BGCOLOR=#C0C0C0>
\r
32021 <TD width=10% BGCOLOR=#C0C0C0>
\r
32024 <TD width=10% BGCOLOR=#C0C0C0>
\r
32027 <TD width=15% BGCOLOR=#C0C0C0>
\r
32030 <TD width=35% BGCOLOR=#C0C0C0>
\r
32031 <B>SD eMMC selection</B>
\r
32036 <H2><a name="SD_CONFIG_REG2">Register (<A href=#mod___slcr> slcr </A>)SD_CONFIG_REG2</a></H2>
\r
32037 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32038 <TR valign="top">
\r
32039 <TD width=15% BGCOLOR=#FFFF00>
\r
32040 <B>Register Name</B>
\r
32042 <TD width=15% BGCOLOR=#FFFF00>
\r
32045 <TD width=10% BGCOLOR=#FFFF00>
\r
32048 <TD width=10% BGCOLOR=#FFFF00>
\r
32051 <TD width=15% BGCOLOR=#FFFF00>
\r
32052 <B>Reset Value</B>
\r
32054 <TD width=35% BGCOLOR=#FFFF00>
\r
32055 <B>Description</B>
\r
32058 <TR valign="top">
\r
32059 <TD width=15% BGCOLOR=#FBF5EF>
\r
32060 <B>SD_CONFIG_REG2</B>
\r
32062 <TD width=15% BGCOLOR=#FBF5EF>
\r
32063 <B>0XFF180320</B>
\r
32065 <TD width=10% BGCOLOR=#FBF5EF>
\r
32068 <TD width=10% BGCOLOR=#FBF5EF>
\r
32071 <TD width=15% BGCOLOR=#FBF5EF>
\r
32072 <B>0x00000000</B>
\r
32074 <TD width=35% BGCOLOR=#FBF5EF>
\r
32080 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32081 <TR valign="top">
\r
32082 <TD width=15% BGCOLOR=#C0FFC0>
\r
32083 <B>Field Name</B>
\r
32085 <TD width=15% BGCOLOR=#C0FFC0>
\r
32088 <TD width=10% BGCOLOR=#C0FFC0>
\r
32091 <TD width=10% BGCOLOR=#C0FFC0>
\r
32094 <TD width=15% BGCOLOR=#C0FFC0>
\r
32095 <B>Shifted Value</B>
\r
32097 <TD width=35% BGCOLOR=#C0FFC0>
\r
32098 <B>Description</B>
\r
32101 <TR valign="top">
\r
32102 <TD width=15% BGCOLOR=#FBF5EF>
\r
32103 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE</B>
\r
32105 <TD width=15% BGCOLOR=#FBF5EF>
\r
32108 <TD width=10% BGCOLOR=#FBF5EF>
\r
32111 <TD width=10% BGCOLOR=#FBF5EF>
\r
32114 <TD width=15% BGCOLOR=#FBF5EF>
\r
32117 <TD width=35% BGCOLOR=#FBF5EF>
\r
32118 <B>Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved</B>
\r
32121 <TR valign="top">
\r
32122 <TD width=15% BGCOLOR=#FBF5EF>
\r
32123 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE</B>
\r
32125 <TD width=15% BGCOLOR=#FBF5EF>
\r
32128 <TD width=10% BGCOLOR=#FBF5EF>
\r
32131 <TD width=10% BGCOLOR=#FBF5EF>
\r
32134 <TD width=15% BGCOLOR=#FBF5EF>
\r
32137 <TD width=35% BGCOLOR=#FBF5EF>
\r
32138 <B>Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved</B>
\r
32141 <TR valign="top">
\r
32142 <TD width=15% BGCOLOR=#FBF5EF>
\r
32143 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V</B>
\r
32145 <TD width=15% BGCOLOR=#FBF5EF>
\r
32148 <TD width=10% BGCOLOR=#FBF5EF>
\r
32151 <TD width=10% BGCOLOR=#FBF5EF>
\r
32154 <TD width=15% BGCOLOR=#FBF5EF>
\r
32157 <TD width=35% BGCOLOR=#FBF5EF>
\r
32158 <B>1.8V Support 1: 1.8V supported 0: 1.8V not supported support</B>
\r
32161 <TR valign="top">
\r
32162 <TD width=15% BGCOLOR=#FBF5EF>
\r
32163 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V</B>
\r
32165 <TD width=15% BGCOLOR=#FBF5EF>
\r
32168 <TD width=10% BGCOLOR=#FBF5EF>
\r
32171 <TD width=10% BGCOLOR=#FBF5EF>
\r
32174 <TD width=15% BGCOLOR=#FBF5EF>
\r
32177 <TD width=35% BGCOLOR=#FBF5EF>
\r
32178 <B>3.0V Support 1: 3.0V supported 0: 3.0V not supported support</B>
\r
32181 <TR valign="top">
\r
32182 <TD width=15% BGCOLOR=#FBF5EF>
\r
32183 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V</B>
\r
32185 <TD width=15% BGCOLOR=#FBF5EF>
\r
32188 <TD width=10% BGCOLOR=#FBF5EF>
\r
32191 <TD width=10% BGCOLOR=#FBF5EF>
\r
32194 <TD width=15% BGCOLOR=#FBF5EF>
\r
32197 <TD width=35% BGCOLOR=#FBF5EF>
\r
32198 <B>3.3V Support 1: 3.3V supported 0: 3.3V not supported support</B>
\r
32201 <TR valign="top">
\r
32202 <TD width=15% BGCOLOR=#FBF5EF>
\r
32203 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V</B>
\r
32205 <TD width=15% BGCOLOR=#FBF5EF>
\r
32208 <TD width=10% BGCOLOR=#FBF5EF>
\r
32211 <TD width=10% BGCOLOR=#FBF5EF>
\r
32214 <TD width=15% BGCOLOR=#FBF5EF>
\r
32217 <TD width=35% BGCOLOR=#FBF5EF>
\r
32218 <B>1.8V Support 1: 1.8V supported 0: 1.8V not supported support</B>
\r
32221 <TR valign="top">
\r
32222 <TD width=15% BGCOLOR=#FBF5EF>
\r
32223 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V</B>
\r
32225 <TD width=15% BGCOLOR=#FBF5EF>
\r
32228 <TD width=10% BGCOLOR=#FBF5EF>
\r
32231 <TD width=10% BGCOLOR=#FBF5EF>
\r
32234 <TD width=15% BGCOLOR=#FBF5EF>
\r
32237 <TD width=35% BGCOLOR=#FBF5EF>
\r
32238 <B>3.0V Support 1: 3.0V supported 0: 3.0V not supported support</B>
\r
32241 <TR valign="top">
\r
32242 <TD width=15% BGCOLOR=#FBF5EF>
\r
32243 <B>PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V</B>
\r
32245 <TD width=15% BGCOLOR=#FBF5EF>
\r
32248 <TD width=10% BGCOLOR=#FBF5EF>
\r
32251 <TD width=10% BGCOLOR=#FBF5EF>
\r
32254 <TD width=15% BGCOLOR=#FBF5EF>
\r
32257 <TD width=35% BGCOLOR=#FBF5EF>
\r
32258 <B>3.3V Support 1: 3.3V supported 0: 3.3V not supported support</B>
\r
32261 <TR valign="top">
\r
32262 <TD width=15% BGCOLOR=#C0C0C0>
\r
32263 <B>PSU_IOU_SLCR_SD_CONFIG_REG2@0XFF180320</B>
\r
32265 <TD width=15% BGCOLOR=#C0C0C0>
\r
32268 <TD width=10% BGCOLOR=#C0C0C0>
\r
32271 <TD width=10% BGCOLOR=#C0C0C0>
\r
32274 <TD width=15% BGCOLOR=#C0C0C0>
\r
32277 <TD width=35% BGCOLOR=#C0C0C0>
\r
32278 <B>SD Config Register 2</B>
\r
32284 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
32285 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32286 <TR valign="top">
\r
32287 <TD width=15% BGCOLOR=#FFFF00>
\r
32288 <B>Register Name</B>
\r
32290 <TD width=15% BGCOLOR=#FFFF00>
\r
32293 <TD width=10% BGCOLOR=#FFFF00>
\r
32296 <TD width=10% BGCOLOR=#FFFF00>
\r
32299 <TD width=15% BGCOLOR=#FFFF00>
\r
32300 <B>Reset Value</B>
\r
32302 <TD width=35% BGCOLOR=#FFFF00>
\r
32303 <B>Description</B>
\r
32306 <TR valign="top">
\r
32307 <TD width=15% BGCOLOR=#FBF5EF>
\r
32308 <B>RST_LPD_IOU2</B>
\r
32310 <TD width=15% BGCOLOR=#FBF5EF>
\r
32311 <B>0XFF5E0238</B>
\r
32313 <TD width=10% BGCOLOR=#FBF5EF>
\r
32316 <TD width=10% BGCOLOR=#FBF5EF>
\r
32319 <TD width=15% BGCOLOR=#FBF5EF>
\r
32320 <B>0x00000000</B>
\r
32322 <TD width=35% BGCOLOR=#FBF5EF>
\r
32328 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32329 <TR valign="top">
\r
32330 <TD width=15% BGCOLOR=#C0FFC0>
\r
32331 <B>Field Name</B>
\r
32333 <TD width=15% BGCOLOR=#C0FFC0>
\r
32336 <TD width=10% BGCOLOR=#C0FFC0>
\r
32339 <TD width=10% BGCOLOR=#C0FFC0>
\r
32342 <TD width=15% BGCOLOR=#C0FFC0>
\r
32343 <B>Shifted Value</B>
\r
32345 <TD width=35% BGCOLOR=#C0FFC0>
\r
32346 <B>Description</B>
\r
32349 <TR valign="top">
\r
32350 <TD width=15% BGCOLOR=#FBF5EF>
\r
32351 <B>PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET</B>
\r
32353 <TD width=15% BGCOLOR=#FBF5EF>
\r
32356 <TD width=10% BGCOLOR=#FBF5EF>
\r
32359 <TD width=10% BGCOLOR=#FBF5EF>
\r
32362 <TD width=15% BGCOLOR=#FBF5EF>
\r
32365 <TD width=35% BGCOLOR=#FBF5EF>
\r
32366 <B>Block level reset</B>
\r
32369 <TR valign="top">
\r
32370 <TD width=15% BGCOLOR=#FBF5EF>
\r
32371 <B>PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET</B>
\r
32373 <TD width=15% BGCOLOR=#FBF5EF>
\r
32376 <TD width=10% BGCOLOR=#FBF5EF>
\r
32379 <TD width=10% BGCOLOR=#FBF5EF>
\r
32382 <TD width=15% BGCOLOR=#FBF5EF>
\r
32385 <TD width=35% BGCOLOR=#FBF5EF>
\r
32386 <B>Block level reset</B>
\r
32389 <TR valign="top">
\r
32390 <TD width=15% BGCOLOR=#C0C0C0>
\r
32391 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
32393 <TD width=15% BGCOLOR=#C0C0C0>
\r
32396 <TD width=10% BGCOLOR=#C0C0C0>
\r
32399 <TD width=10% BGCOLOR=#C0C0C0>
\r
32402 <TD width=15% BGCOLOR=#C0C0C0>
\r
32405 <TD width=35% BGCOLOR=#C0C0C0>
\r
32406 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
32412 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
32413 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32414 <TR valign="top">
\r
32415 <TD width=15% BGCOLOR=#FFFF00>
\r
32416 <B>Register Name</B>
\r
32418 <TD width=15% BGCOLOR=#FFFF00>
\r
32421 <TD width=10% BGCOLOR=#FFFF00>
\r
32424 <TD width=10% BGCOLOR=#FFFF00>
\r
32427 <TD width=15% BGCOLOR=#FFFF00>
\r
32428 <B>Reset Value</B>
\r
32430 <TD width=35% BGCOLOR=#FFFF00>
\r
32431 <B>Description</B>
\r
32434 <TR valign="top">
\r
32435 <TD width=15% BGCOLOR=#FBF5EF>
\r
32436 <B>RST_LPD_IOU2</B>
\r
32438 <TD width=15% BGCOLOR=#FBF5EF>
\r
32439 <B>0XFF5E0238</B>
\r
32441 <TD width=10% BGCOLOR=#FBF5EF>
\r
32444 <TD width=10% BGCOLOR=#FBF5EF>
\r
32447 <TD width=15% BGCOLOR=#FBF5EF>
\r
32448 <B>0x00000000</B>
\r
32450 <TD width=35% BGCOLOR=#FBF5EF>
\r
32456 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32457 <TR valign="top">
\r
32458 <TD width=15% BGCOLOR=#C0FFC0>
\r
32459 <B>Field Name</B>
\r
32461 <TD width=15% BGCOLOR=#C0FFC0>
\r
32464 <TD width=10% BGCOLOR=#C0FFC0>
\r
32467 <TD width=10% BGCOLOR=#C0FFC0>
\r
32470 <TD width=15% BGCOLOR=#C0FFC0>
\r
32471 <B>Shifted Value</B>
\r
32473 <TD width=35% BGCOLOR=#C0FFC0>
\r
32474 <B>Description</B>
\r
32477 <TR valign="top">
\r
32478 <TD width=15% BGCOLOR=#FBF5EF>
\r
32479 <B>PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET</B>
\r
32481 <TD width=15% BGCOLOR=#FBF5EF>
\r
32484 <TD width=10% BGCOLOR=#FBF5EF>
\r
32487 <TD width=10% BGCOLOR=#FBF5EF>
\r
32490 <TD width=15% BGCOLOR=#FBF5EF>
\r
32493 <TD width=35% BGCOLOR=#FBF5EF>
\r
32494 <B>Block level reset</B>
\r
32497 <TR valign="top">
\r
32498 <TD width=15% BGCOLOR=#FBF5EF>
\r
32499 <B>PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET</B>
\r
32501 <TD width=15% BGCOLOR=#FBF5EF>
\r
32504 <TD width=10% BGCOLOR=#FBF5EF>
\r
32507 <TD width=10% BGCOLOR=#FBF5EF>
\r
32510 <TD width=15% BGCOLOR=#FBF5EF>
\r
32513 <TD width=35% BGCOLOR=#FBF5EF>
\r
32514 <B>Block level reset</B>
\r
32517 <TR valign="top">
\r
32518 <TD width=15% BGCOLOR=#C0C0C0>
\r
32519 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
32521 <TD width=15% BGCOLOR=#C0C0C0>
\r
32524 <TD width=10% BGCOLOR=#C0C0C0>
\r
32527 <TD width=10% BGCOLOR=#C0C0C0>
\r
32530 <TD width=15% BGCOLOR=#C0C0C0>
\r
32533 <TD width=35% BGCOLOR=#C0C0C0>
\r
32534 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
32541 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
32542 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32543 <TR valign="top">
\r
32544 <TD width=15% BGCOLOR=#FFFF00>
\r
32545 <B>Register Name</B>
\r
32547 <TD width=15% BGCOLOR=#FFFF00>
\r
32550 <TD width=10% BGCOLOR=#FFFF00>
\r
32553 <TD width=10% BGCOLOR=#FFFF00>
\r
32556 <TD width=15% BGCOLOR=#FFFF00>
\r
32557 <B>Reset Value</B>
\r
32559 <TD width=35% BGCOLOR=#FFFF00>
\r
32560 <B>Description</B>
\r
32563 <TR valign="top">
\r
32564 <TD width=15% BGCOLOR=#FBF5EF>
\r
32565 <B>RST_LPD_IOU2</B>
\r
32567 <TD width=15% BGCOLOR=#FBF5EF>
\r
32568 <B>0XFF5E0238</B>
\r
32570 <TD width=10% BGCOLOR=#FBF5EF>
\r
32573 <TD width=10% BGCOLOR=#FBF5EF>
\r
32576 <TD width=15% BGCOLOR=#FBF5EF>
\r
32577 <B>0x00000000</B>
\r
32579 <TD width=35% BGCOLOR=#FBF5EF>
\r
32585 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32586 <TR valign="top">
\r
32587 <TD width=15% BGCOLOR=#C0FFC0>
\r
32588 <B>Field Name</B>
\r
32590 <TD width=15% BGCOLOR=#C0FFC0>
\r
32593 <TD width=10% BGCOLOR=#C0FFC0>
\r
32596 <TD width=10% BGCOLOR=#C0FFC0>
\r
32599 <TD width=15% BGCOLOR=#C0FFC0>
\r
32600 <B>Shifted Value</B>
\r
32602 <TD width=35% BGCOLOR=#C0FFC0>
\r
32603 <B>Description</B>
\r
32606 <TR valign="top">
\r
32607 <TD width=15% BGCOLOR=#FBF5EF>
\r
32608 <B>PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET</B>
\r
32610 <TD width=15% BGCOLOR=#FBF5EF>
\r
32613 <TD width=10% BGCOLOR=#FBF5EF>
\r
32616 <TD width=10% BGCOLOR=#FBF5EF>
\r
32619 <TD width=15% BGCOLOR=#FBF5EF>
\r
32622 <TD width=35% BGCOLOR=#FBF5EF>
\r
32623 <B>Block level reset</B>
\r
32626 <TR valign="top">
\r
32627 <TD width=15% BGCOLOR=#FBF5EF>
\r
32628 <B>PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET</B>
\r
32630 <TD width=15% BGCOLOR=#FBF5EF>
\r
32633 <TD width=10% BGCOLOR=#FBF5EF>
\r
32636 <TD width=10% BGCOLOR=#FBF5EF>
\r
32639 <TD width=15% BGCOLOR=#FBF5EF>
\r
32642 <TD width=35% BGCOLOR=#FBF5EF>
\r
32643 <B>Block level reset</B>
\r
32646 <TR valign="top">
\r
32647 <TD width=15% BGCOLOR=#C0C0C0>
\r
32648 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
32650 <TD width=15% BGCOLOR=#C0C0C0>
\r
32653 <TD width=10% BGCOLOR=#C0C0C0>
\r
32656 <TD width=10% BGCOLOR=#C0C0C0>
\r
32659 <TD width=15% BGCOLOR=#C0C0C0>
\r
32662 <TD width=35% BGCOLOR=#C0C0C0>
\r
32663 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
32669 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
32670 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32671 <TR valign="top">
\r
32672 <TD width=15% BGCOLOR=#FFFF00>
\r
32673 <B>Register Name</B>
\r
32675 <TD width=15% BGCOLOR=#FFFF00>
\r
32678 <TD width=10% BGCOLOR=#FFFF00>
\r
32681 <TD width=10% BGCOLOR=#FFFF00>
\r
32684 <TD width=15% BGCOLOR=#FFFF00>
\r
32685 <B>Reset Value</B>
\r
32687 <TD width=35% BGCOLOR=#FFFF00>
\r
32688 <B>Description</B>
\r
32691 <TR valign="top">
\r
32692 <TD width=15% BGCOLOR=#FBF5EF>
\r
32693 <B>RST_LPD_IOU2</B>
\r
32695 <TD width=15% BGCOLOR=#FBF5EF>
\r
32696 <B>0XFF5E0238</B>
\r
32698 <TD width=10% BGCOLOR=#FBF5EF>
\r
32701 <TD width=10% BGCOLOR=#FBF5EF>
\r
32704 <TD width=15% BGCOLOR=#FBF5EF>
\r
32705 <B>0x00000000</B>
\r
32707 <TD width=35% BGCOLOR=#FBF5EF>
\r
32713 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32714 <TR valign="top">
\r
32715 <TD width=15% BGCOLOR=#C0FFC0>
\r
32716 <B>Field Name</B>
\r
32718 <TD width=15% BGCOLOR=#C0FFC0>
\r
32721 <TD width=10% BGCOLOR=#C0FFC0>
\r
32724 <TD width=10% BGCOLOR=#C0FFC0>
\r
32727 <TD width=15% BGCOLOR=#C0FFC0>
\r
32728 <B>Shifted Value</B>
\r
32730 <TD width=35% BGCOLOR=#C0FFC0>
\r
32731 <B>Description</B>
\r
32734 <TR valign="top">
\r
32735 <TD width=15% BGCOLOR=#FBF5EF>
\r
32736 <B>PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET</B>
\r
32738 <TD width=15% BGCOLOR=#FBF5EF>
\r
32741 <TD width=10% BGCOLOR=#FBF5EF>
\r
32744 <TD width=10% BGCOLOR=#FBF5EF>
\r
32747 <TD width=15% BGCOLOR=#FBF5EF>
\r
32750 <TD width=35% BGCOLOR=#FBF5EF>
\r
32751 <B>Block level reset</B>
\r
32754 <TR valign="top">
\r
32755 <TD width=15% BGCOLOR=#FBF5EF>
\r
32756 <B>PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET</B>
\r
32758 <TD width=15% BGCOLOR=#FBF5EF>
\r
32761 <TD width=10% BGCOLOR=#FBF5EF>
\r
32764 <TD width=10% BGCOLOR=#FBF5EF>
\r
32767 <TD width=15% BGCOLOR=#FBF5EF>
\r
32770 <TD width=35% BGCOLOR=#FBF5EF>
\r
32771 <B>Block level reset</B>
\r
32774 <TR valign="top">
\r
32775 <TD width=15% BGCOLOR=#FBF5EF>
\r
32776 <B>PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET</B>
\r
32778 <TD width=15% BGCOLOR=#FBF5EF>
\r
32781 <TD width=10% BGCOLOR=#FBF5EF>
\r
32784 <TD width=10% BGCOLOR=#FBF5EF>
\r
32787 <TD width=15% BGCOLOR=#FBF5EF>
\r
32790 <TD width=35% BGCOLOR=#FBF5EF>
\r
32791 <B>Block level reset</B>
\r
32794 <TR valign="top">
\r
32795 <TD width=15% BGCOLOR=#FBF5EF>
\r
32796 <B>PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET</B>
\r
32798 <TD width=15% BGCOLOR=#FBF5EF>
\r
32801 <TD width=10% BGCOLOR=#FBF5EF>
\r
32804 <TD width=10% BGCOLOR=#FBF5EF>
\r
32807 <TD width=15% BGCOLOR=#FBF5EF>
\r
32810 <TD width=35% BGCOLOR=#FBF5EF>
\r
32811 <B>Block level reset</B>
\r
32814 <TR valign="top">
\r
32815 <TD width=15% BGCOLOR=#C0C0C0>
\r
32816 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
32818 <TD width=15% BGCOLOR=#C0C0C0>
\r
32821 <TD width=10% BGCOLOR=#C0C0C0>
\r
32824 <TD width=10% BGCOLOR=#C0C0C0>
\r
32827 <TD width=15% BGCOLOR=#C0C0C0>
\r
32830 <TD width=35% BGCOLOR=#C0C0C0>
\r
32831 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
32837 <H2><a name="RST_LPD_IOU2">Register (<A href=#mod___slcr> slcr </A>)RST_LPD_IOU2</a></H2>
\r
32838 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32839 <TR valign="top">
\r
32840 <TD width=15% BGCOLOR=#FFFF00>
\r
32841 <B>Register Name</B>
\r
32843 <TD width=15% BGCOLOR=#FFFF00>
\r
32846 <TD width=10% BGCOLOR=#FFFF00>
\r
32849 <TD width=10% BGCOLOR=#FFFF00>
\r
32852 <TD width=15% BGCOLOR=#FFFF00>
\r
32853 <B>Reset Value</B>
\r
32855 <TD width=35% BGCOLOR=#FFFF00>
\r
32856 <B>Description</B>
\r
32859 <TR valign="top">
\r
32860 <TD width=15% BGCOLOR=#FBF5EF>
\r
32861 <B>RST_LPD_IOU2</B>
\r
32863 <TD width=15% BGCOLOR=#FBF5EF>
\r
32864 <B>0XFF5E0238</B>
\r
32866 <TD width=10% BGCOLOR=#FBF5EF>
\r
32869 <TD width=10% BGCOLOR=#FBF5EF>
\r
32872 <TD width=15% BGCOLOR=#FBF5EF>
\r
32873 <B>0x00000000</B>
\r
32875 <TD width=35% BGCOLOR=#FBF5EF>
\r
32881 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32882 <TR valign="top">
\r
32883 <TD width=15% BGCOLOR=#C0FFC0>
\r
32884 <B>Field Name</B>
\r
32886 <TD width=15% BGCOLOR=#C0FFC0>
\r
32889 <TD width=10% BGCOLOR=#C0FFC0>
\r
32892 <TD width=10% BGCOLOR=#C0FFC0>
\r
32895 <TD width=15% BGCOLOR=#C0FFC0>
\r
32896 <B>Shifted Value</B>
\r
32898 <TD width=35% BGCOLOR=#C0FFC0>
\r
32899 <B>Description</B>
\r
32902 <TR valign="top">
\r
32903 <TD width=15% BGCOLOR=#FBF5EF>
\r
32904 <B>PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET</B>
\r
32906 <TD width=15% BGCOLOR=#FBF5EF>
\r
32909 <TD width=10% BGCOLOR=#FBF5EF>
\r
32912 <TD width=10% BGCOLOR=#FBF5EF>
\r
32915 <TD width=15% BGCOLOR=#FBF5EF>
\r
32918 <TD width=35% BGCOLOR=#FBF5EF>
\r
32919 <B>Block level reset</B>
\r
32922 <TR valign="top">
\r
32923 <TD width=15% BGCOLOR=#FBF5EF>
\r
32924 <B>PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET</B>
\r
32926 <TD width=15% BGCOLOR=#FBF5EF>
\r
32929 <TD width=10% BGCOLOR=#FBF5EF>
\r
32932 <TD width=10% BGCOLOR=#FBF5EF>
\r
32935 <TD width=15% BGCOLOR=#FBF5EF>
\r
32938 <TD width=35% BGCOLOR=#FBF5EF>
\r
32939 <B>Block level reset</B>
\r
32942 <TR valign="top">
\r
32943 <TD width=15% BGCOLOR=#C0C0C0>
\r
32944 <B>PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238</B>
\r
32946 <TD width=15% BGCOLOR=#C0C0C0>
\r
32949 <TD width=10% BGCOLOR=#C0C0C0>
\r
32952 <TD width=10% BGCOLOR=#C0C0C0>
\r
32955 <TD width=15% BGCOLOR=#C0C0C0>
\r
32958 <TD width=35% BGCOLOR=#C0C0C0>
\r
32959 <B>Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.</B>
\r
32964 <H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
\r
32965 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
32966 <TR valign="top">
\r
32967 <TD width=15% BGCOLOR=#FFFF00>
\r
32968 <B>Register Name</B>
\r
32970 <TD width=15% BGCOLOR=#FFFF00>
\r
32973 <TD width=10% BGCOLOR=#FFFF00>
\r
32976 <TD width=10% BGCOLOR=#FFFF00>
\r
32979 <TD width=15% BGCOLOR=#FFFF00>
\r
32980 <B>Reset Value</B>
\r
32982 <TD width=35% BGCOLOR=#FFFF00>
\r
32983 <B>Description</B>
\r
32986 <TR valign="top">
\r
32987 <TD width=15% BGCOLOR=#FBF5EF>
\r
32988 <B>Baud_rate_divider_reg0</B>
\r
32990 <TD width=15% BGCOLOR=#FBF5EF>
\r
32991 <B>0XFF000034</B>
\r
32993 <TD width=10% BGCOLOR=#FBF5EF>
\r
32996 <TD width=10% BGCOLOR=#FBF5EF>
\r
32999 <TD width=15% BGCOLOR=#FBF5EF>
\r
33000 <B>0x00000000</B>
\r
33002 <TD width=35% BGCOLOR=#FBF5EF>
\r
33008 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33009 <TR valign="top">
\r
33010 <TD width=15% BGCOLOR=#C0FFC0>
\r
33011 <B>Field Name</B>
\r
33013 <TD width=15% BGCOLOR=#C0FFC0>
\r
33016 <TD width=10% BGCOLOR=#C0FFC0>
\r
33019 <TD width=10% BGCOLOR=#C0FFC0>
\r
33022 <TD width=15% BGCOLOR=#C0FFC0>
\r
33023 <B>Shifted Value</B>
\r
33025 <TD width=35% BGCOLOR=#C0FFC0>
\r
33026 <B>Description</B>
\r
33029 <TR valign="top">
\r
33030 <TD width=15% BGCOLOR=#FBF5EF>
\r
33031 <B>PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV</B>
\r
33033 <TD width=15% BGCOLOR=#FBF5EF>
\r
33036 <TD width=10% BGCOLOR=#FBF5EF>
\r
33039 <TD width=10% BGCOLOR=#FBF5EF>
\r
33042 <TD width=15% BGCOLOR=#FBF5EF>
\r
33045 <TD width=35% BGCOLOR=#FBF5EF>
\r
33046 <B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
\r
33049 <TR valign="top">
\r
33050 <TD width=15% BGCOLOR=#C0C0C0>
\r
33051 <B>PSU_UART0_BAUD_RATE_DIVIDER_REG0@0XFF000034</B>
\r
33053 <TD width=15% BGCOLOR=#C0C0C0>
\r
33056 <TD width=10% BGCOLOR=#C0C0C0>
\r
33059 <TD width=10% BGCOLOR=#C0C0C0>
\r
33062 <TD width=15% BGCOLOR=#C0C0C0>
\r
33065 <TD width=35% BGCOLOR=#C0C0C0>
\r
33066 <B>Baud Rate Divider Register</B>
\r
33071 <H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
\r
33072 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33073 <TR valign="top">
\r
33074 <TD width=15% BGCOLOR=#FFFF00>
\r
33075 <B>Register Name</B>
\r
33077 <TD width=15% BGCOLOR=#FFFF00>
\r
33080 <TD width=10% BGCOLOR=#FFFF00>
\r
33083 <TD width=10% BGCOLOR=#FFFF00>
\r
33086 <TD width=15% BGCOLOR=#FFFF00>
\r
33087 <B>Reset Value</B>
\r
33089 <TD width=35% BGCOLOR=#FFFF00>
\r
33090 <B>Description</B>
\r
33093 <TR valign="top">
\r
33094 <TD width=15% BGCOLOR=#FBF5EF>
\r
33095 <B>Baud_rate_gen_reg0</B>
\r
33097 <TD width=15% BGCOLOR=#FBF5EF>
\r
33098 <B>0XFF000018</B>
\r
33100 <TD width=10% BGCOLOR=#FBF5EF>
\r
33103 <TD width=10% BGCOLOR=#FBF5EF>
\r
33106 <TD width=15% BGCOLOR=#FBF5EF>
\r
33107 <B>0x00000000</B>
\r
33109 <TD width=35% BGCOLOR=#FBF5EF>
\r
33115 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33116 <TR valign="top">
\r
33117 <TD width=15% BGCOLOR=#C0FFC0>
\r
33118 <B>Field Name</B>
\r
33120 <TD width=15% BGCOLOR=#C0FFC0>
\r
33123 <TD width=10% BGCOLOR=#C0FFC0>
\r
33126 <TD width=10% BGCOLOR=#C0FFC0>
\r
33129 <TD width=15% BGCOLOR=#C0FFC0>
\r
33130 <B>Shifted Value</B>
\r
33132 <TD width=35% BGCOLOR=#C0FFC0>
\r
33133 <B>Description</B>
\r
33136 <TR valign="top">
\r
33137 <TD width=15% BGCOLOR=#FBF5EF>
\r
33138 <B>PSU_UART0_BAUD_RATE_GEN_REG0_CD</B>
\r
33140 <TD width=15% BGCOLOR=#FBF5EF>
\r
33143 <TD width=10% BGCOLOR=#FBF5EF>
\r
33146 <TD width=10% BGCOLOR=#FBF5EF>
\r
33149 <TD width=15% BGCOLOR=#FBF5EF>
\r
33152 <TD width=35% BGCOLOR=#FBF5EF>
\r
33153 <B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
\r
33156 <TR valign="top">
\r
33157 <TD width=15% BGCOLOR=#C0C0C0>
\r
33158 <B>PSU_UART0_BAUD_RATE_GEN_REG0@0XFF000018</B>
\r
33160 <TD width=15% BGCOLOR=#C0C0C0>
\r
33163 <TD width=10% BGCOLOR=#C0C0C0>
\r
33166 <TD width=10% BGCOLOR=#C0C0C0>
\r
33169 <TD width=15% BGCOLOR=#C0C0C0>
\r
33172 <TD width=35% BGCOLOR=#C0C0C0>
\r
33173 <B>Baud Rate Generator Register.</B>
\r
33178 <H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
\r
33179 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33180 <TR valign="top">
\r
33181 <TD width=15% BGCOLOR=#FFFF00>
\r
33182 <B>Register Name</B>
\r
33184 <TD width=15% BGCOLOR=#FFFF00>
\r
33187 <TD width=10% BGCOLOR=#FFFF00>
\r
33190 <TD width=10% BGCOLOR=#FFFF00>
\r
33193 <TD width=15% BGCOLOR=#FFFF00>
\r
33194 <B>Reset Value</B>
\r
33196 <TD width=35% BGCOLOR=#FFFF00>
\r
33197 <B>Description</B>
\r
33200 <TR valign="top">
\r
33201 <TD width=15% BGCOLOR=#FBF5EF>
\r
33202 <B>Control_reg0</B>
\r
33204 <TD width=15% BGCOLOR=#FBF5EF>
\r
33205 <B>0XFF000000</B>
\r
33207 <TD width=10% BGCOLOR=#FBF5EF>
\r
33210 <TD width=10% BGCOLOR=#FBF5EF>
\r
33213 <TD width=15% BGCOLOR=#FBF5EF>
\r
33214 <B>0x00000000</B>
\r
33216 <TD width=35% BGCOLOR=#FBF5EF>
\r
33222 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33223 <TR valign="top">
\r
33224 <TD width=15% BGCOLOR=#C0FFC0>
\r
33225 <B>Field Name</B>
\r
33227 <TD width=15% BGCOLOR=#C0FFC0>
\r
33230 <TD width=10% BGCOLOR=#C0FFC0>
\r
33233 <TD width=10% BGCOLOR=#C0FFC0>
\r
33236 <TD width=15% BGCOLOR=#C0FFC0>
\r
33237 <B>Shifted Value</B>
\r
33239 <TD width=35% BGCOLOR=#C0FFC0>
\r
33240 <B>Description</B>
\r
33243 <TR valign="top">
\r
33244 <TD width=15% BGCOLOR=#FBF5EF>
\r
33245 <B>PSU_UART0_CONTROL_REG0_STPBRK</B>
\r
33247 <TD width=15% BGCOLOR=#FBF5EF>
\r
33250 <TD width=10% BGCOLOR=#FBF5EF>
\r
33253 <TD width=10% BGCOLOR=#FBF5EF>
\r
33256 <TD width=15% BGCOLOR=#FBF5EF>
\r
33259 <TD width=35% BGCOLOR=#FBF5EF>
\r
33260 <B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
\r
33263 <TR valign="top">
\r
33264 <TD width=15% BGCOLOR=#FBF5EF>
\r
33265 <B>PSU_UART0_CONTROL_REG0_STTBRK</B>
\r
33267 <TD width=15% BGCOLOR=#FBF5EF>
\r
33270 <TD width=10% BGCOLOR=#FBF5EF>
\r
33273 <TD width=10% BGCOLOR=#FBF5EF>
\r
33276 <TD width=15% BGCOLOR=#FBF5EF>
\r
33279 <TD width=35% BGCOLOR=#FBF5EF>
\r
33280 <B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
\r
33283 <TR valign="top">
\r
33284 <TD width=15% BGCOLOR=#FBF5EF>
\r
33285 <B>PSU_UART0_CONTROL_REG0_RSTTO</B>
\r
33287 <TD width=15% BGCOLOR=#FBF5EF>
\r
33290 <TD width=10% BGCOLOR=#FBF5EF>
\r
33293 <TD width=10% BGCOLOR=#FBF5EF>
\r
33296 <TD width=15% BGCOLOR=#FBF5EF>
\r
33299 <TD width=35% BGCOLOR=#FBF5EF>
\r
33300 <B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
\r
33303 <TR valign="top">
\r
33304 <TD width=15% BGCOLOR=#FBF5EF>
\r
33305 <B>PSU_UART0_CONTROL_REG0_TXDIS</B>
\r
33307 <TD width=15% BGCOLOR=#FBF5EF>
\r
33310 <TD width=10% BGCOLOR=#FBF5EF>
\r
33313 <TD width=10% BGCOLOR=#FBF5EF>
\r
33316 <TD width=15% BGCOLOR=#FBF5EF>
\r
33319 <TD width=35% BGCOLOR=#FBF5EF>
\r
33320 <B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
\r
33323 <TR valign="top">
\r
33324 <TD width=15% BGCOLOR=#FBF5EF>
\r
33325 <B>PSU_UART0_CONTROL_REG0_TXEN</B>
\r
33327 <TD width=15% BGCOLOR=#FBF5EF>
\r
33330 <TD width=10% BGCOLOR=#FBF5EF>
\r
33333 <TD width=10% BGCOLOR=#FBF5EF>
\r
33336 <TD width=15% BGCOLOR=#FBF5EF>
\r
33339 <TD width=35% BGCOLOR=#FBF5EF>
\r
33340 <B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
\r
33343 <TR valign="top">
\r
33344 <TD width=15% BGCOLOR=#FBF5EF>
\r
33345 <B>PSU_UART0_CONTROL_REG0_RXDIS</B>
\r
33347 <TD width=15% BGCOLOR=#FBF5EF>
\r
33350 <TD width=10% BGCOLOR=#FBF5EF>
\r
33353 <TD width=10% BGCOLOR=#FBF5EF>
\r
33356 <TD width=15% BGCOLOR=#FBF5EF>
\r
33359 <TD width=35% BGCOLOR=#FBF5EF>
\r
33360 <B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
\r
33363 <TR valign="top">
\r
33364 <TD width=15% BGCOLOR=#FBF5EF>
\r
33365 <B>PSU_UART0_CONTROL_REG0_RXEN</B>
\r
33367 <TD width=15% BGCOLOR=#FBF5EF>
\r
33370 <TD width=10% BGCOLOR=#FBF5EF>
\r
33373 <TD width=10% BGCOLOR=#FBF5EF>
\r
33376 <TD width=15% BGCOLOR=#FBF5EF>
\r
33379 <TD width=35% BGCOLOR=#FBF5EF>
\r
33380 <B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
\r
33383 <TR valign="top">
\r
33384 <TD width=15% BGCOLOR=#FBF5EF>
\r
33385 <B>PSU_UART0_CONTROL_REG0_TXRES</B>
\r
33387 <TD width=15% BGCOLOR=#FBF5EF>
\r
33390 <TD width=10% BGCOLOR=#FBF5EF>
\r
33393 <TD width=10% BGCOLOR=#FBF5EF>
\r
33396 <TD width=15% BGCOLOR=#FBF5EF>
\r
33399 <TD width=35% BGCOLOR=#FBF5EF>
\r
33400 <B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
\r
33403 <TR valign="top">
\r
33404 <TD width=15% BGCOLOR=#FBF5EF>
\r
33405 <B>PSU_UART0_CONTROL_REG0_RXRES</B>
\r
33407 <TD width=15% BGCOLOR=#FBF5EF>
\r
33410 <TD width=10% BGCOLOR=#FBF5EF>
\r
33413 <TD width=10% BGCOLOR=#FBF5EF>
\r
33416 <TD width=15% BGCOLOR=#FBF5EF>
\r
33419 <TD width=35% BGCOLOR=#FBF5EF>
\r
33420 <B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
\r
33423 <TR valign="top">
\r
33424 <TD width=15% BGCOLOR=#C0C0C0>
\r
33425 <B>PSU_UART0_CONTROL_REG0@0XFF000000</B>
\r
33427 <TD width=15% BGCOLOR=#C0C0C0>
\r
33430 <TD width=10% BGCOLOR=#C0C0C0>
\r
33433 <TD width=10% BGCOLOR=#C0C0C0>
\r
33436 <TD width=15% BGCOLOR=#C0C0C0>
\r
33439 <TD width=35% BGCOLOR=#C0C0C0>
\r
33440 <B>UART Control Register</B>
\r
33445 <H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
\r
33446 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33447 <TR valign="top">
\r
33448 <TD width=15% BGCOLOR=#FFFF00>
\r
33449 <B>Register Name</B>
\r
33451 <TD width=15% BGCOLOR=#FFFF00>
\r
33454 <TD width=10% BGCOLOR=#FFFF00>
\r
33457 <TD width=10% BGCOLOR=#FFFF00>
\r
33460 <TD width=15% BGCOLOR=#FFFF00>
\r
33461 <B>Reset Value</B>
\r
33463 <TD width=35% BGCOLOR=#FFFF00>
\r
33464 <B>Description</B>
\r
33467 <TR valign="top">
\r
33468 <TD width=15% BGCOLOR=#FBF5EF>
\r
33471 <TD width=15% BGCOLOR=#FBF5EF>
\r
33472 <B>0XFF000004</B>
\r
33474 <TD width=10% BGCOLOR=#FBF5EF>
\r
33477 <TD width=10% BGCOLOR=#FBF5EF>
\r
33480 <TD width=15% BGCOLOR=#FBF5EF>
\r
33481 <B>0x00000000</B>
\r
33483 <TD width=35% BGCOLOR=#FBF5EF>
\r
33489 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33490 <TR valign="top">
\r
33491 <TD width=15% BGCOLOR=#C0FFC0>
\r
33492 <B>Field Name</B>
\r
33494 <TD width=15% BGCOLOR=#C0FFC0>
\r
33497 <TD width=10% BGCOLOR=#C0FFC0>
\r
33500 <TD width=10% BGCOLOR=#C0FFC0>
\r
33503 <TD width=15% BGCOLOR=#C0FFC0>
\r
33504 <B>Shifted Value</B>
\r
33506 <TD width=35% BGCOLOR=#C0FFC0>
\r
33507 <B>Description</B>
\r
33510 <TR valign="top">
\r
33511 <TD width=15% BGCOLOR=#FBF5EF>
\r
33512 <B>PSU_UART0_MODE_REG0_CHMODE</B>
\r
33514 <TD width=15% BGCOLOR=#FBF5EF>
\r
33517 <TD width=10% BGCOLOR=#FBF5EF>
\r
33520 <TD width=10% BGCOLOR=#FBF5EF>
\r
33523 <TD width=15% BGCOLOR=#FBF5EF>
\r
33526 <TD width=35% BGCOLOR=#FBF5EF>
\r
33527 <B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
\r
33530 <TR valign="top">
\r
33531 <TD width=15% BGCOLOR=#FBF5EF>
\r
33532 <B>PSU_UART0_MODE_REG0_NBSTOP</B>
\r
33534 <TD width=15% BGCOLOR=#FBF5EF>
\r
33537 <TD width=10% BGCOLOR=#FBF5EF>
\r
33540 <TD width=10% BGCOLOR=#FBF5EF>
\r
33543 <TD width=15% BGCOLOR=#FBF5EF>
\r
33546 <TD width=35% BGCOLOR=#FBF5EF>
\r
33547 <B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
\r
33550 <TR valign="top">
\r
33551 <TD width=15% BGCOLOR=#FBF5EF>
\r
33552 <B>PSU_UART0_MODE_REG0_PAR</B>
\r
33554 <TD width=15% BGCOLOR=#FBF5EF>
\r
33557 <TD width=10% BGCOLOR=#FBF5EF>
\r
33560 <TD width=10% BGCOLOR=#FBF5EF>
\r
33563 <TD width=15% BGCOLOR=#FBF5EF>
\r
33566 <TD width=35% BGCOLOR=#FBF5EF>
\r
33567 <B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
\r
33570 <TR valign="top">
\r
33571 <TD width=15% BGCOLOR=#FBF5EF>
\r
33572 <B>PSU_UART0_MODE_REG0_CHRL</B>
\r
33574 <TD width=15% BGCOLOR=#FBF5EF>
\r
33577 <TD width=10% BGCOLOR=#FBF5EF>
\r
33580 <TD width=10% BGCOLOR=#FBF5EF>
\r
33583 <TD width=15% BGCOLOR=#FBF5EF>
\r
33586 <TD width=35% BGCOLOR=#FBF5EF>
\r
33587 <B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
\r
33590 <TR valign="top">
\r
33591 <TD width=15% BGCOLOR=#FBF5EF>
\r
33592 <B>PSU_UART0_MODE_REG0_CLKS</B>
\r
33594 <TD width=15% BGCOLOR=#FBF5EF>
\r
33597 <TD width=10% BGCOLOR=#FBF5EF>
\r
33600 <TD width=10% BGCOLOR=#FBF5EF>
\r
33603 <TD width=15% BGCOLOR=#FBF5EF>
\r
33606 <TD width=35% BGCOLOR=#FBF5EF>
\r
33607 <B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
\r
33610 <TR valign="top">
\r
33611 <TD width=15% BGCOLOR=#C0C0C0>
\r
33612 <B>PSU_UART0_MODE_REG0@0XFF000004</B>
\r
33614 <TD width=15% BGCOLOR=#C0C0C0>
\r
33617 <TD width=10% BGCOLOR=#C0C0C0>
\r
33620 <TD width=10% BGCOLOR=#C0C0C0>
\r
33623 <TD width=15% BGCOLOR=#C0C0C0>
\r
33626 <TD width=35% BGCOLOR=#C0C0C0>
\r
33627 <B>UART Mode Register</B>
\r
33632 <H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
\r
33633 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33634 <TR valign="top">
\r
33635 <TD width=15% BGCOLOR=#FFFF00>
\r
33636 <B>Register Name</B>
\r
33638 <TD width=15% BGCOLOR=#FFFF00>
\r
33641 <TD width=10% BGCOLOR=#FFFF00>
\r
33644 <TD width=10% BGCOLOR=#FFFF00>
\r
33647 <TD width=15% BGCOLOR=#FFFF00>
\r
33648 <B>Reset Value</B>
\r
33650 <TD width=35% BGCOLOR=#FFFF00>
\r
33651 <B>Description</B>
\r
33654 <TR valign="top">
\r
33655 <TD width=15% BGCOLOR=#FBF5EF>
\r
33656 <B>Baud_rate_divider_reg0</B>
\r
33658 <TD width=15% BGCOLOR=#FBF5EF>
\r
33659 <B>0XFF010034</B>
\r
33661 <TD width=10% BGCOLOR=#FBF5EF>
\r
33664 <TD width=10% BGCOLOR=#FBF5EF>
\r
33667 <TD width=15% BGCOLOR=#FBF5EF>
\r
33668 <B>0x00000000</B>
\r
33670 <TD width=35% BGCOLOR=#FBF5EF>
\r
33676 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33677 <TR valign="top">
\r
33678 <TD width=15% BGCOLOR=#C0FFC0>
\r
33679 <B>Field Name</B>
\r
33681 <TD width=15% BGCOLOR=#C0FFC0>
\r
33684 <TD width=10% BGCOLOR=#C0FFC0>
\r
33687 <TD width=10% BGCOLOR=#C0FFC0>
\r
33690 <TD width=15% BGCOLOR=#C0FFC0>
\r
33691 <B>Shifted Value</B>
\r
33693 <TD width=35% BGCOLOR=#C0FFC0>
\r
33694 <B>Description</B>
\r
33697 <TR valign="top">
\r
33698 <TD width=15% BGCOLOR=#FBF5EF>
\r
33699 <B>PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV</B>
\r
33701 <TD width=15% BGCOLOR=#FBF5EF>
\r
33704 <TD width=10% BGCOLOR=#FBF5EF>
\r
33707 <TD width=10% BGCOLOR=#FBF5EF>
\r
33710 <TD width=15% BGCOLOR=#FBF5EF>
\r
33713 <TD width=35% BGCOLOR=#FBF5EF>
\r
33714 <B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
\r
33717 <TR valign="top">
\r
33718 <TD width=15% BGCOLOR=#C0C0C0>
\r
33719 <B>PSU_UART1_BAUD_RATE_DIVIDER_REG0@0XFF010034</B>
\r
33721 <TD width=15% BGCOLOR=#C0C0C0>
\r
33724 <TD width=10% BGCOLOR=#C0C0C0>
\r
33727 <TD width=10% BGCOLOR=#C0C0C0>
\r
33730 <TD width=15% BGCOLOR=#C0C0C0>
\r
33733 <TD width=35% BGCOLOR=#C0C0C0>
\r
33734 <B>Baud Rate Divider Register</B>
\r
33739 <H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
\r
33740 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33741 <TR valign="top">
\r
33742 <TD width=15% BGCOLOR=#FFFF00>
\r
33743 <B>Register Name</B>
\r
33745 <TD width=15% BGCOLOR=#FFFF00>
\r
33748 <TD width=10% BGCOLOR=#FFFF00>
\r
33751 <TD width=10% BGCOLOR=#FFFF00>
\r
33754 <TD width=15% BGCOLOR=#FFFF00>
\r
33755 <B>Reset Value</B>
\r
33757 <TD width=35% BGCOLOR=#FFFF00>
\r
33758 <B>Description</B>
\r
33761 <TR valign="top">
\r
33762 <TD width=15% BGCOLOR=#FBF5EF>
\r
33763 <B>Baud_rate_gen_reg0</B>
\r
33765 <TD width=15% BGCOLOR=#FBF5EF>
\r
33766 <B>0XFF010018</B>
\r
33768 <TD width=10% BGCOLOR=#FBF5EF>
\r
33771 <TD width=10% BGCOLOR=#FBF5EF>
\r
33774 <TD width=15% BGCOLOR=#FBF5EF>
\r
33775 <B>0x00000000</B>
\r
33777 <TD width=35% BGCOLOR=#FBF5EF>
\r
33783 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33784 <TR valign="top">
\r
33785 <TD width=15% BGCOLOR=#C0FFC0>
\r
33786 <B>Field Name</B>
\r
33788 <TD width=15% BGCOLOR=#C0FFC0>
\r
33791 <TD width=10% BGCOLOR=#C0FFC0>
\r
33794 <TD width=10% BGCOLOR=#C0FFC0>
\r
33797 <TD width=15% BGCOLOR=#C0FFC0>
\r
33798 <B>Shifted Value</B>
\r
33800 <TD width=35% BGCOLOR=#C0FFC0>
\r
33801 <B>Description</B>
\r
33804 <TR valign="top">
\r
33805 <TD width=15% BGCOLOR=#FBF5EF>
\r
33806 <B>PSU_UART1_BAUD_RATE_GEN_REG0_CD</B>
\r
33808 <TD width=15% BGCOLOR=#FBF5EF>
\r
33811 <TD width=10% BGCOLOR=#FBF5EF>
\r
33814 <TD width=10% BGCOLOR=#FBF5EF>
\r
33817 <TD width=15% BGCOLOR=#FBF5EF>
\r
33820 <TD width=35% BGCOLOR=#FBF5EF>
\r
33821 <B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
\r
33824 <TR valign="top">
\r
33825 <TD width=15% BGCOLOR=#C0C0C0>
\r
33826 <B>PSU_UART1_BAUD_RATE_GEN_REG0@0XFF010018</B>
\r
33828 <TD width=15% BGCOLOR=#C0C0C0>
\r
33831 <TD width=10% BGCOLOR=#C0C0C0>
\r
33834 <TD width=10% BGCOLOR=#C0C0C0>
\r
33837 <TD width=15% BGCOLOR=#C0C0C0>
\r
33840 <TD width=35% BGCOLOR=#C0C0C0>
\r
33841 <B>Baud Rate Generator Register.</B>
\r
33846 <H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
\r
33847 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33848 <TR valign="top">
\r
33849 <TD width=15% BGCOLOR=#FFFF00>
\r
33850 <B>Register Name</B>
\r
33852 <TD width=15% BGCOLOR=#FFFF00>
\r
33855 <TD width=10% BGCOLOR=#FFFF00>
\r
33858 <TD width=10% BGCOLOR=#FFFF00>
\r
33861 <TD width=15% BGCOLOR=#FFFF00>
\r
33862 <B>Reset Value</B>
\r
33864 <TD width=35% BGCOLOR=#FFFF00>
\r
33865 <B>Description</B>
\r
33868 <TR valign="top">
\r
33869 <TD width=15% BGCOLOR=#FBF5EF>
\r
33870 <B>Control_reg0</B>
\r
33872 <TD width=15% BGCOLOR=#FBF5EF>
\r
33873 <B>0XFF010000</B>
\r
33875 <TD width=10% BGCOLOR=#FBF5EF>
\r
33878 <TD width=10% BGCOLOR=#FBF5EF>
\r
33881 <TD width=15% BGCOLOR=#FBF5EF>
\r
33882 <B>0x00000000</B>
\r
33884 <TD width=35% BGCOLOR=#FBF5EF>
\r
33890 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
33891 <TR valign="top">
\r
33892 <TD width=15% BGCOLOR=#C0FFC0>
\r
33893 <B>Field Name</B>
\r
33895 <TD width=15% BGCOLOR=#C0FFC0>
\r
33898 <TD width=10% BGCOLOR=#C0FFC0>
\r
33901 <TD width=10% BGCOLOR=#C0FFC0>
\r
33904 <TD width=15% BGCOLOR=#C0FFC0>
\r
33905 <B>Shifted Value</B>
\r
33907 <TD width=35% BGCOLOR=#C0FFC0>
\r
33908 <B>Description</B>
\r
33911 <TR valign="top">
\r
33912 <TD width=15% BGCOLOR=#FBF5EF>
\r
33913 <B>PSU_UART1_CONTROL_REG0_STPBRK</B>
\r
33915 <TD width=15% BGCOLOR=#FBF5EF>
\r
33918 <TD width=10% BGCOLOR=#FBF5EF>
\r
33921 <TD width=10% BGCOLOR=#FBF5EF>
\r
33924 <TD width=15% BGCOLOR=#FBF5EF>
\r
33927 <TD width=35% BGCOLOR=#FBF5EF>
\r
33928 <B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
\r
33931 <TR valign="top">
\r
33932 <TD width=15% BGCOLOR=#FBF5EF>
\r
33933 <B>PSU_UART1_CONTROL_REG0_STTBRK</B>
\r
33935 <TD width=15% BGCOLOR=#FBF5EF>
\r
33938 <TD width=10% BGCOLOR=#FBF5EF>
\r
33941 <TD width=10% BGCOLOR=#FBF5EF>
\r
33944 <TD width=15% BGCOLOR=#FBF5EF>
\r
33947 <TD width=35% BGCOLOR=#FBF5EF>
\r
33948 <B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
\r
33951 <TR valign="top">
\r
33952 <TD width=15% BGCOLOR=#FBF5EF>
\r
33953 <B>PSU_UART1_CONTROL_REG0_RSTTO</B>
\r
33955 <TD width=15% BGCOLOR=#FBF5EF>
\r
33958 <TD width=10% BGCOLOR=#FBF5EF>
\r
33961 <TD width=10% BGCOLOR=#FBF5EF>
\r
33964 <TD width=15% BGCOLOR=#FBF5EF>
\r
33967 <TD width=35% BGCOLOR=#FBF5EF>
\r
33968 <B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
\r
33971 <TR valign="top">
\r
33972 <TD width=15% BGCOLOR=#FBF5EF>
\r
33973 <B>PSU_UART1_CONTROL_REG0_TXDIS</B>
\r
33975 <TD width=15% BGCOLOR=#FBF5EF>
\r
33978 <TD width=10% BGCOLOR=#FBF5EF>
\r
33981 <TD width=10% BGCOLOR=#FBF5EF>
\r
33984 <TD width=15% BGCOLOR=#FBF5EF>
\r
33987 <TD width=35% BGCOLOR=#FBF5EF>
\r
33988 <B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
\r
33991 <TR valign="top">
\r
33992 <TD width=15% BGCOLOR=#FBF5EF>
\r
33993 <B>PSU_UART1_CONTROL_REG0_TXEN</B>
\r
33995 <TD width=15% BGCOLOR=#FBF5EF>
\r
33998 <TD width=10% BGCOLOR=#FBF5EF>
\r
34001 <TD width=10% BGCOLOR=#FBF5EF>
\r
34004 <TD width=15% BGCOLOR=#FBF5EF>
\r
34007 <TD width=35% BGCOLOR=#FBF5EF>
\r
34008 <B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
\r
34011 <TR valign="top">
\r
34012 <TD width=15% BGCOLOR=#FBF5EF>
\r
34013 <B>PSU_UART1_CONTROL_REG0_RXDIS</B>
\r
34015 <TD width=15% BGCOLOR=#FBF5EF>
\r
34018 <TD width=10% BGCOLOR=#FBF5EF>
\r
34021 <TD width=10% BGCOLOR=#FBF5EF>
\r
34024 <TD width=15% BGCOLOR=#FBF5EF>
\r
34027 <TD width=35% BGCOLOR=#FBF5EF>
\r
34028 <B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
\r
34031 <TR valign="top">
\r
34032 <TD width=15% BGCOLOR=#FBF5EF>
\r
34033 <B>PSU_UART1_CONTROL_REG0_RXEN</B>
\r
34035 <TD width=15% BGCOLOR=#FBF5EF>
\r
34038 <TD width=10% BGCOLOR=#FBF5EF>
\r
34041 <TD width=10% BGCOLOR=#FBF5EF>
\r
34044 <TD width=15% BGCOLOR=#FBF5EF>
\r
34047 <TD width=35% BGCOLOR=#FBF5EF>
\r
34048 <B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
\r
34051 <TR valign="top">
\r
34052 <TD width=15% BGCOLOR=#FBF5EF>
\r
34053 <B>PSU_UART1_CONTROL_REG0_TXRES</B>
\r
34055 <TD width=15% BGCOLOR=#FBF5EF>
\r
34058 <TD width=10% BGCOLOR=#FBF5EF>
\r
34061 <TD width=10% BGCOLOR=#FBF5EF>
\r
34064 <TD width=15% BGCOLOR=#FBF5EF>
\r
34067 <TD width=35% BGCOLOR=#FBF5EF>
\r
34068 <B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
\r
34071 <TR valign="top">
\r
34072 <TD width=15% BGCOLOR=#FBF5EF>
\r
34073 <B>PSU_UART1_CONTROL_REG0_RXRES</B>
\r
34075 <TD width=15% BGCOLOR=#FBF5EF>
\r
34078 <TD width=10% BGCOLOR=#FBF5EF>
\r
34081 <TD width=10% BGCOLOR=#FBF5EF>
\r
34084 <TD width=15% BGCOLOR=#FBF5EF>
\r
34087 <TD width=35% BGCOLOR=#FBF5EF>
\r
34088 <B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
\r
34091 <TR valign="top">
\r
34092 <TD width=15% BGCOLOR=#C0C0C0>
\r
34093 <B>PSU_UART1_CONTROL_REG0@0XFF010000</B>
\r
34095 <TD width=15% BGCOLOR=#C0C0C0>
\r
34098 <TD width=10% BGCOLOR=#C0C0C0>
\r
34101 <TD width=10% BGCOLOR=#C0C0C0>
\r
34104 <TD width=15% BGCOLOR=#C0C0C0>
\r
34107 <TD width=35% BGCOLOR=#C0C0C0>
\r
34108 <B>UART Control Register</B>
\r
34113 <H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
\r
34114 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34115 <TR valign="top">
\r
34116 <TD width=15% BGCOLOR=#FFFF00>
\r
34117 <B>Register Name</B>
\r
34119 <TD width=15% BGCOLOR=#FFFF00>
\r
34122 <TD width=10% BGCOLOR=#FFFF00>
\r
34125 <TD width=10% BGCOLOR=#FFFF00>
\r
34128 <TD width=15% BGCOLOR=#FFFF00>
\r
34129 <B>Reset Value</B>
\r
34131 <TD width=35% BGCOLOR=#FFFF00>
\r
34132 <B>Description</B>
\r
34135 <TR valign="top">
\r
34136 <TD width=15% BGCOLOR=#FBF5EF>
\r
34139 <TD width=15% BGCOLOR=#FBF5EF>
\r
34140 <B>0XFF010004</B>
\r
34142 <TD width=10% BGCOLOR=#FBF5EF>
\r
34145 <TD width=10% BGCOLOR=#FBF5EF>
\r
34148 <TD width=15% BGCOLOR=#FBF5EF>
\r
34149 <B>0x00000000</B>
\r
34151 <TD width=35% BGCOLOR=#FBF5EF>
\r
34157 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34158 <TR valign="top">
\r
34159 <TD width=15% BGCOLOR=#C0FFC0>
\r
34160 <B>Field Name</B>
\r
34162 <TD width=15% BGCOLOR=#C0FFC0>
\r
34165 <TD width=10% BGCOLOR=#C0FFC0>
\r
34168 <TD width=10% BGCOLOR=#C0FFC0>
\r
34171 <TD width=15% BGCOLOR=#C0FFC0>
\r
34172 <B>Shifted Value</B>
\r
34174 <TD width=35% BGCOLOR=#C0FFC0>
\r
34175 <B>Description</B>
\r
34178 <TR valign="top">
\r
34179 <TD width=15% BGCOLOR=#FBF5EF>
\r
34180 <B>PSU_UART1_MODE_REG0_CHMODE</B>
\r
34182 <TD width=15% BGCOLOR=#FBF5EF>
\r
34185 <TD width=10% BGCOLOR=#FBF5EF>
\r
34188 <TD width=10% BGCOLOR=#FBF5EF>
\r
34191 <TD width=15% BGCOLOR=#FBF5EF>
\r
34194 <TD width=35% BGCOLOR=#FBF5EF>
\r
34195 <B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
\r
34198 <TR valign="top">
\r
34199 <TD width=15% BGCOLOR=#FBF5EF>
\r
34200 <B>PSU_UART1_MODE_REG0_NBSTOP</B>
\r
34202 <TD width=15% BGCOLOR=#FBF5EF>
\r
34205 <TD width=10% BGCOLOR=#FBF5EF>
\r
34208 <TD width=10% BGCOLOR=#FBF5EF>
\r
34211 <TD width=15% BGCOLOR=#FBF5EF>
\r
34214 <TD width=35% BGCOLOR=#FBF5EF>
\r
34215 <B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
\r
34218 <TR valign="top">
\r
34219 <TD width=15% BGCOLOR=#FBF5EF>
\r
34220 <B>PSU_UART1_MODE_REG0_PAR</B>
\r
34222 <TD width=15% BGCOLOR=#FBF5EF>
\r
34225 <TD width=10% BGCOLOR=#FBF5EF>
\r
34228 <TD width=10% BGCOLOR=#FBF5EF>
\r
34231 <TD width=15% BGCOLOR=#FBF5EF>
\r
34234 <TD width=35% BGCOLOR=#FBF5EF>
\r
34235 <B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
\r
34238 <TR valign="top">
\r
34239 <TD width=15% BGCOLOR=#FBF5EF>
\r
34240 <B>PSU_UART1_MODE_REG0_CHRL</B>
\r
34242 <TD width=15% BGCOLOR=#FBF5EF>
\r
34245 <TD width=10% BGCOLOR=#FBF5EF>
\r
34248 <TD width=10% BGCOLOR=#FBF5EF>
\r
34251 <TD width=15% BGCOLOR=#FBF5EF>
\r
34254 <TD width=35% BGCOLOR=#FBF5EF>
\r
34255 <B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
\r
34258 <TR valign="top">
\r
34259 <TD width=15% BGCOLOR=#FBF5EF>
\r
34260 <B>PSU_UART1_MODE_REG0_CLKS</B>
\r
34262 <TD width=15% BGCOLOR=#FBF5EF>
\r
34265 <TD width=10% BGCOLOR=#FBF5EF>
\r
34268 <TD width=10% BGCOLOR=#FBF5EF>
\r
34271 <TD width=15% BGCOLOR=#FBF5EF>
\r
34274 <TD width=35% BGCOLOR=#FBF5EF>
\r
34275 <B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
\r
34278 <TR valign="top">
\r
34279 <TD width=15% BGCOLOR=#C0C0C0>
\r
34280 <B>PSU_UART1_MODE_REG0@0XFF010004</B>
\r
34282 <TD width=15% BGCOLOR=#C0C0C0>
\r
34285 <TD width=10% BGCOLOR=#C0C0C0>
\r
34288 <TD width=10% BGCOLOR=#C0C0C0>
\r
34291 <TD width=15% BGCOLOR=#C0C0C0>
\r
34294 <TD width=35% BGCOLOR=#C0C0C0>
\r
34295 <B>UART Mode Register</B>
\r
34302 <H2><a name="slcr_adma">Register (<A href=#mod___slcr> slcr </A>)slcr_adma</a></H2>
\r
34303 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34304 <TR valign="top">
\r
34305 <TD width=15% BGCOLOR=#FFFF00>
\r
34306 <B>Register Name</B>
\r
34308 <TD width=15% BGCOLOR=#FFFF00>
\r
34311 <TD width=10% BGCOLOR=#FFFF00>
\r
34314 <TD width=10% BGCOLOR=#FFFF00>
\r
34317 <TD width=15% BGCOLOR=#FFFF00>
\r
34318 <B>Reset Value</B>
\r
34320 <TD width=35% BGCOLOR=#FFFF00>
\r
34321 <B>Description</B>
\r
34324 <TR valign="top">
\r
34325 <TD width=15% BGCOLOR=#FBF5EF>
\r
34328 <TD width=15% BGCOLOR=#FBF5EF>
\r
34329 <B>0XFF4B0024</B>
\r
34331 <TD width=10% BGCOLOR=#FBF5EF>
\r
34334 <TD width=10% BGCOLOR=#FBF5EF>
\r
34337 <TD width=15% BGCOLOR=#FBF5EF>
\r
34338 <B>0x00000000</B>
\r
34340 <TD width=35% BGCOLOR=#FBF5EF>
\r
34346 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34347 <TR valign="top">
\r
34348 <TD width=15% BGCOLOR=#C0FFC0>
\r
34349 <B>Field Name</B>
\r
34351 <TD width=15% BGCOLOR=#C0FFC0>
\r
34354 <TD width=10% BGCOLOR=#C0FFC0>
\r
34357 <TD width=10% BGCOLOR=#C0FFC0>
\r
34360 <TD width=15% BGCOLOR=#C0FFC0>
\r
34361 <B>Shifted Value</B>
\r
34363 <TD width=35% BGCOLOR=#C0FFC0>
\r
34364 <B>Description</B>
\r
34367 <TR valign="top">
\r
34368 <TD width=15% BGCOLOR=#FBF5EF>
\r
34369 <B>PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ</B>
\r
34371 <TD width=15% BGCOLOR=#FBF5EF>
\r
34374 <TD width=10% BGCOLOR=#FBF5EF>
\r
34377 <TD width=10% BGCOLOR=#FBF5EF>
\r
34380 <TD width=15% BGCOLOR=#FBF5EF>
\r
34383 <TD width=35% BGCOLOR=#FBF5EF>
\r
34384 <B>TrustZone Classification for ADMA</B>
\r
34387 <TR valign="top">
\r
34388 <TD width=15% BGCOLOR=#C0C0C0>
\r
34389 <B>PSU_LPD_SLCR_SECURE_SLCR_ADMA@0XFF4B0024</B>
\r
34391 <TD width=15% BGCOLOR=#C0C0C0>
\r
34394 <TD width=10% BGCOLOR=#C0C0C0>
\r
34397 <TD width=10% BGCOLOR=#C0C0C0>
\r
34400 <TD width=15% BGCOLOR=#C0C0C0>
\r
34403 <TD width=35% BGCOLOR=#C0C0C0>
\r
34404 <B>RPU TrustZone settings</B>
\r
34409 <H1>CSU TAMPERING</H1>
\r
34410 <H1>CSU TAMPER STATUS</H1>
\r
34411 <H2><a name="tamper_status">Register (<A href=#mod___slcr> slcr </A>)tamper_status</a></H2>
\r
34412 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34413 <TR valign="top">
\r
34414 <TD width=15% BGCOLOR=#FFFF00>
\r
34415 <B>Register Name</B>
\r
34417 <TD width=15% BGCOLOR=#FFFF00>
\r
34420 <TD width=10% BGCOLOR=#FFFF00>
\r
34423 <TD width=10% BGCOLOR=#FFFF00>
\r
34426 <TD width=15% BGCOLOR=#FFFF00>
\r
34427 <B>Reset Value</B>
\r
34429 <TD width=35% BGCOLOR=#FFFF00>
\r
34430 <B>Description</B>
\r
34433 <TR valign="top">
\r
34434 <TD width=15% BGCOLOR=#FBF5EF>
\r
34435 <B>tamper_status</B>
\r
34437 <TD width=15% BGCOLOR=#FBF5EF>
\r
34438 <B>0XFFCA5000</B>
\r
34440 <TD width=10% BGCOLOR=#FBF5EF>
\r
34443 <TD width=10% BGCOLOR=#FBF5EF>
\r
34446 <TD width=15% BGCOLOR=#FBF5EF>
\r
34447 <B>0x00000000</B>
\r
34449 <TD width=35% BGCOLOR=#FBF5EF>
\r
34455 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34456 <TR valign="top">
\r
34457 <TD width=15% BGCOLOR=#C0FFC0>
\r
34458 <B>Field Name</B>
\r
34460 <TD width=15% BGCOLOR=#C0FFC0>
\r
34463 <TD width=10% BGCOLOR=#C0FFC0>
\r
34466 <TD width=10% BGCOLOR=#C0FFC0>
\r
34469 <TD width=15% BGCOLOR=#C0FFC0>
\r
34470 <B>Shifted Value</B>
\r
34472 <TD width=35% BGCOLOR=#C0FFC0>
\r
34473 <B>Description</B>
\r
34476 <TR valign="top">
\r
34477 <TD width=15% BGCOLOR=#FBF5EF>
\r
34478 <B>PSU_CSU_TAMPER_STATUS_TAMPER_0</B>
\r
34480 <TD width=15% BGCOLOR=#FBF5EF>
\r
34483 <TD width=10% BGCOLOR=#FBF5EF>
\r
34486 <TD width=10% BGCOLOR=#FBF5EF>
\r
34489 <TD width=15% BGCOLOR=#FBF5EF>
\r
34492 <TD width=35% BGCOLOR=#FBF5EF>
\r
34493 <B>CSU regsiter</B>
\r
34496 <TR valign="top">
\r
34497 <TD width=15% BGCOLOR=#FBF5EF>
\r
34498 <B>PSU_CSU_TAMPER_STATUS_TAMPER_1</B>
\r
34500 <TD width=15% BGCOLOR=#FBF5EF>
\r
34503 <TD width=10% BGCOLOR=#FBF5EF>
\r
34506 <TD width=10% BGCOLOR=#FBF5EF>
\r
34509 <TD width=15% BGCOLOR=#FBF5EF>
\r
34512 <TD width=35% BGCOLOR=#FBF5EF>
\r
34513 <B>External MIO</B>
\r
34516 <TR valign="top">
\r
34517 <TD width=15% BGCOLOR=#FBF5EF>
\r
34518 <B>PSU_CSU_TAMPER_STATUS_TAMPER_2</B>
\r
34520 <TD width=15% BGCOLOR=#FBF5EF>
\r
34523 <TD width=10% BGCOLOR=#FBF5EF>
\r
34526 <TD width=10% BGCOLOR=#FBF5EF>
\r
34529 <TD width=15% BGCOLOR=#FBF5EF>
\r
34532 <TD width=35% BGCOLOR=#FBF5EF>
\r
34533 <B>JTAG toggle detect</B>
\r
34536 <TR valign="top">
\r
34537 <TD width=15% BGCOLOR=#FBF5EF>
\r
34538 <B>PSU_CSU_TAMPER_STATUS_TAMPER_3</B>
\r
34540 <TD width=15% BGCOLOR=#FBF5EF>
\r
34543 <TD width=10% BGCOLOR=#FBF5EF>
\r
34546 <TD width=10% BGCOLOR=#FBF5EF>
\r
34549 <TD width=15% BGCOLOR=#FBF5EF>
\r
34552 <TD width=35% BGCOLOR=#FBF5EF>
\r
34553 <B>PL SEU error</B>
\r
34556 <TR valign="top">
\r
34557 <TD width=15% BGCOLOR=#FBF5EF>
\r
34558 <B>PSU_CSU_TAMPER_STATUS_TAMPER_4</B>
\r
34560 <TD width=15% BGCOLOR=#FBF5EF>
\r
34563 <TD width=10% BGCOLOR=#FBF5EF>
\r
34566 <TD width=10% BGCOLOR=#FBF5EF>
\r
34569 <TD width=15% BGCOLOR=#FBF5EF>
\r
34572 <TD width=35% BGCOLOR=#FBF5EF>
\r
34573 <B>AMS over temperature alarm for LPD</B>
\r
34576 <TR valign="top">
\r
34577 <TD width=15% BGCOLOR=#FBF5EF>
\r
34578 <B>PSU_CSU_TAMPER_STATUS_TAMPER_5</B>
\r
34580 <TD width=15% BGCOLOR=#FBF5EF>
\r
34583 <TD width=10% BGCOLOR=#FBF5EF>
\r
34586 <TD width=10% BGCOLOR=#FBF5EF>
\r
34589 <TD width=15% BGCOLOR=#FBF5EF>
\r
34592 <TD width=35% BGCOLOR=#FBF5EF>
\r
34593 <B>AMS over temperature alarm for APU</B>
\r
34596 <TR valign="top">
\r
34597 <TD width=15% BGCOLOR=#FBF5EF>
\r
34598 <B>PSU_CSU_TAMPER_STATUS_TAMPER_6</B>
\r
34600 <TD width=15% BGCOLOR=#FBF5EF>
\r
34603 <TD width=10% BGCOLOR=#FBF5EF>
\r
34606 <TD width=10% BGCOLOR=#FBF5EF>
\r
34609 <TD width=15% BGCOLOR=#FBF5EF>
\r
34612 <TD width=35% BGCOLOR=#FBF5EF>
\r
34613 <B>AMS voltage alarm for VCCPINT_FPD</B>
\r
34616 <TR valign="top">
\r
34617 <TD width=15% BGCOLOR=#FBF5EF>
\r
34618 <B>PSU_CSU_TAMPER_STATUS_TAMPER_7</B>
\r
34620 <TD width=15% BGCOLOR=#FBF5EF>
\r
34623 <TD width=10% BGCOLOR=#FBF5EF>
\r
34626 <TD width=10% BGCOLOR=#FBF5EF>
\r
34629 <TD width=15% BGCOLOR=#FBF5EF>
\r
34632 <TD width=35% BGCOLOR=#FBF5EF>
\r
34633 <B>AMS voltage alarm for VCCPINT_LPD</B>
\r
34636 <TR valign="top">
\r
34637 <TD width=15% BGCOLOR=#FBF5EF>
\r
34638 <B>PSU_CSU_TAMPER_STATUS_TAMPER_8</B>
\r
34640 <TD width=15% BGCOLOR=#FBF5EF>
\r
34643 <TD width=10% BGCOLOR=#FBF5EF>
\r
34646 <TD width=10% BGCOLOR=#FBF5EF>
\r
34649 <TD width=15% BGCOLOR=#FBF5EF>
\r
34652 <TD width=35% BGCOLOR=#FBF5EF>
\r
34653 <B>AMS voltage alarm for VCCPAUX</B>
\r
34656 <TR valign="top">
\r
34657 <TD width=15% BGCOLOR=#FBF5EF>
\r
34658 <B>PSU_CSU_TAMPER_STATUS_TAMPER_9</B>
\r
34660 <TD width=15% BGCOLOR=#FBF5EF>
\r
34663 <TD width=10% BGCOLOR=#FBF5EF>
\r
34666 <TD width=10% BGCOLOR=#FBF5EF>
\r
34669 <TD width=15% BGCOLOR=#FBF5EF>
\r
34672 <TD width=35% BGCOLOR=#FBF5EF>
\r
34673 <B>AMS voltage alarm for DDRPHY</B>
\r
34676 <TR valign="top">
\r
34677 <TD width=15% BGCOLOR=#FBF5EF>
\r
34678 <B>PSU_CSU_TAMPER_STATUS_TAMPER_10</B>
\r
34680 <TD width=15% BGCOLOR=#FBF5EF>
\r
34683 <TD width=10% BGCOLOR=#FBF5EF>
\r
34686 <TD width=10% BGCOLOR=#FBF5EF>
\r
34689 <TD width=15% BGCOLOR=#FBF5EF>
\r
34692 <TD width=35% BGCOLOR=#FBF5EF>
\r
34693 <B>AMS voltage alarm for PSIO bank 0/1/2</B>
\r
34696 <TR valign="top">
\r
34697 <TD width=15% BGCOLOR=#FBF5EF>
\r
34698 <B>PSU_CSU_TAMPER_STATUS_TAMPER_11</B>
\r
34700 <TD width=15% BGCOLOR=#FBF5EF>
\r
34703 <TD width=10% BGCOLOR=#FBF5EF>
\r
34706 <TD width=10% BGCOLOR=#FBF5EF>
\r
34709 <TD width=15% BGCOLOR=#FBF5EF>
\r
34712 <TD width=35% BGCOLOR=#FBF5EF>
\r
34713 <B>AMS voltage alarm for PSIO bank 3 (dedicated pins)</B>
\r
34716 <TR valign="top">
\r
34717 <TD width=15% BGCOLOR=#FBF5EF>
\r
34718 <B>PSU_CSU_TAMPER_STATUS_TAMPER_12</B>
\r
34720 <TD width=15% BGCOLOR=#FBF5EF>
\r
34723 <TD width=10% BGCOLOR=#FBF5EF>
\r
34726 <TD width=10% BGCOLOR=#FBF5EF>
\r
34729 <TD width=15% BGCOLOR=#FBF5EF>
\r
34732 <TD width=35% BGCOLOR=#FBF5EF>
\r
34733 <B>AMS voltaage alarm for GT</B>
\r
34736 <TR valign="top">
\r
34737 <TD width=15% BGCOLOR=#C0C0C0>
\r
34738 <B>PSU_CSU_TAMPER_STATUS@0XFFCA5000</B>
\r
34740 <TD width=15% BGCOLOR=#C0C0C0>
\r
34743 <TD width=10% BGCOLOR=#C0C0C0>
\r
34746 <TD width=10% BGCOLOR=#C0C0C0>
\r
34749 <TD width=15% BGCOLOR=#C0C0C0>
\r
34752 <TD width=35% BGCOLOR=#C0C0C0>
\r
34753 <B>Tamper Response Status</B>
\r
34758 <H1>CSU TAMPER RESPONSE</H1>
\r
34761 <H2><a name="psu_post_config">psu_post_config</a></H2>
\r
34762 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34763 <TR valign="top">
\r
34764 <TD width=15% BGCOLOR=#FFC0FF>
\r
34765 <B>Register Name</B>
\r
34767 <TD width=15% BGCOLOR=#FFC0FF>
\r
34770 <TD width=10% BGCOLOR=#FFC0FF>
\r
34773 <TD width=10% BGCOLOR=#FFC0FF>
\r
34776 <TD width=15% BGCOLOR=#FFC0FF>
\r
34777 <B>Reset Value</B>
\r
34779 <TD width=35% BGCOLOR=#FFC0FF>
\r
34780 <B>Description</B>
\r
34785 <H2><a name="psu_post_config">psu_post_config</a></H2>
\r
34786 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34787 <TR valign="top">
\r
34788 <TD width=15% BGCOLOR=#FFC0FF>
\r
34789 <B>Register Name</B>
\r
34791 <TD width=15% BGCOLOR=#FFC0FF>
\r
34794 <TD width=10% BGCOLOR=#FFC0FF>
\r
34797 <TD width=10% BGCOLOR=#FFC0FF>
\r
34800 <TD width=15% BGCOLOR=#FFC0FF>
\r
34801 <B>Reset Value</B>
\r
34803 <TD width=35% BGCOLOR=#FFC0FF>
\r
34804 <B>Description</B>
\r
34809 <H2><a name="psu_peripherals_powerdwn_data_3_0">psu_peripherals_powerdwn_data_3_0</a></H2>
\r
34810 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34811 <TR valign="top">
\r
34812 <TD width=15% BGCOLOR=#FFC0FF>
\r
34813 <B>Register Name</B>
\r
34815 <TD width=15% BGCOLOR=#FFC0FF>
\r
34818 <TD width=10% BGCOLOR=#FFC0FF>
\r
34821 <TD width=10% BGCOLOR=#FFC0FF>
\r
34824 <TD width=15% BGCOLOR=#FFC0FF>
\r
34825 <B>Reset Value</B>
\r
34827 <TD width=35% BGCOLOR=#FFC0FF>
\r
34828 <B>Description</B>
\r
34833 <H2><a name="psu_peripherals_powerdwn_data_3_0">psu_peripherals_powerdwn_data_3_0</a></H2>
\r
34834 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34835 <TR valign="top">
\r
34836 <TD width=15% BGCOLOR=#FFC0FF>
\r
34837 <B>Register Name</B>
\r
34839 <TD width=15% BGCOLOR=#FFC0FF>
\r
34842 <TD width=10% BGCOLOR=#FFC0FF>
\r
34845 <TD width=10% BGCOLOR=#FFC0FF>
\r
34848 <TD width=15% BGCOLOR=#FFC0FF>
\r
34849 <B>Reset Value</B>
\r
34851 <TD width=35% BGCOLOR=#FFC0FF>
\r
34852 <B>Description</B>
\r
34855 <H1>POWER DOWN REQUEST INTERRUPT ENABLE</H1>
\r
34856 <H1>POWER DOWN TRIGGER</H1>
\r
34859 <H2><a name="psu_security_data_3_0">psu_security_data_3_0</a></H2>
\r
34860 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
34861 <TR valign="top">
\r
34862 <TD width=15% BGCOLOR=#FFC0FF>
\r
34863 <B>Register Name</B>
\r
34865 <TD width=15% BGCOLOR=#FFC0FF>
\r
34868 <TD width=10% BGCOLOR=#FFC0FF>
\r
34871 <TD width=10% BGCOLOR=#FFC0FF>
\r
34874 <TD width=15% BGCOLOR=#FFC0FF>
\r
34875 <B>Reset Value</B>
\r
34877 <TD width=35% BGCOLOR=#FFC0FF>
\r
34878 <B>Description</B>
\r
34881 <TR valign="top">
\r
34882 <TD width=15% BGCOLOR=#FBF5EF>
\r
34883 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID00">
\r
34884 PSU_LPD_XPPU_CFG_MASTER_ID00
\r
34887 <TD width=15% BGCOLOR=#FBF5EF>
\r
34888 <B>0XFF980100</B>
\r
34890 <TD width=10% BGCOLOR=#FBF5EF>
\r
34893 <TD width=10% BGCOLOR=#FBF5EF>
\r
34896 <TD width=15% BGCOLOR=#FBF5EF>
\r
34899 <TD width=35% BGCOLOR=#FBF5EF>
\r
34900 <B>Master ID 00 Register</B>
\r
34903 <TR valign="top">
\r
34904 <TD width=15% BGCOLOR=#FBF5EF>
\r
34905 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID01">
\r
34906 PSU_LPD_XPPU_CFG_MASTER_ID01
\r
34909 <TD width=15% BGCOLOR=#FBF5EF>
\r
34910 <B>0XFF980104</B>
\r
34912 <TD width=10% BGCOLOR=#FBF5EF>
\r
34915 <TD width=10% BGCOLOR=#FBF5EF>
\r
34918 <TD width=15% BGCOLOR=#FBF5EF>
\r
34921 <TD width=35% BGCOLOR=#FBF5EF>
\r
34922 <B>Master ID 01 Register</B>
\r
34925 <TR valign="top">
\r
34926 <TD width=15% BGCOLOR=#FBF5EF>
\r
34927 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID02">
\r
34928 PSU_LPD_XPPU_CFG_MASTER_ID02
\r
34931 <TD width=15% BGCOLOR=#FBF5EF>
\r
34932 <B>0XFF980108</B>
\r
34934 <TD width=10% BGCOLOR=#FBF5EF>
\r
34937 <TD width=10% BGCOLOR=#FBF5EF>
\r
34940 <TD width=15% BGCOLOR=#FBF5EF>
\r
34943 <TD width=35% BGCOLOR=#FBF5EF>
\r
34944 <B>Master ID 02 Register</B>
\r
34947 <TR valign="top">
\r
34948 <TD width=15% BGCOLOR=#FBF5EF>
\r
34949 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID03">
\r
34950 PSU_LPD_XPPU_CFG_MASTER_ID03
\r
34953 <TD width=15% BGCOLOR=#FBF5EF>
\r
34954 <B>0XFF98010C</B>
\r
34956 <TD width=10% BGCOLOR=#FBF5EF>
\r
34959 <TD width=10% BGCOLOR=#FBF5EF>
\r
34962 <TD width=15% BGCOLOR=#FBF5EF>
\r
34965 <TD width=35% BGCOLOR=#FBF5EF>
\r
34966 <B>Master ID 03 Register</B>
\r
34969 <TR valign="top">
\r
34970 <TD width=15% BGCOLOR=#FBF5EF>
\r
34971 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID04">
\r
34972 PSU_LPD_XPPU_CFG_MASTER_ID04
\r
34975 <TD width=15% BGCOLOR=#FBF5EF>
\r
34976 <B>0XFF980110</B>
\r
34978 <TD width=10% BGCOLOR=#FBF5EF>
\r
34981 <TD width=10% BGCOLOR=#FBF5EF>
\r
34984 <TD width=15% BGCOLOR=#FBF5EF>
\r
34987 <TD width=35% BGCOLOR=#FBF5EF>
\r
34988 <B>Master ID 04 Register</B>
\r
34991 <TR valign="top">
\r
34992 <TD width=15% BGCOLOR=#FBF5EF>
\r
34993 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID05">
\r
34994 PSU_LPD_XPPU_CFG_MASTER_ID05
\r
34997 <TD width=15% BGCOLOR=#FBF5EF>
\r
34998 <B>0XFF980114</B>
\r
35000 <TD width=10% BGCOLOR=#FBF5EF>
\r
35003 <TD width=10% BGCOLOR=#FBF5EF>
\r
35006 <TD width=15% BGCOLOR=#FBF5EF>
\r
35009 <TD width=35% BGCOLOR=#FBF5EF>
\r
35010 <B>Master ID 05 Register</B>
\r
35013 <TR valign="top">
\r
35014 <TD width=15% BGCOLOR=#FBF5EF>
\r
35015 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID06">
\r
35016 PSU_LPD_XPPU_CFG_MASTER_ID06
\r
35019 <TD width=15% BGCOLOR=#FBF5EF>
\r
35020 <B>0XFF980118</B>
\r
35022 <TD width=10% BGCOLOR=#FBF5EF>
\r
35025 <TD width=10% BGCOLOR=#FBF5EF>
\r
35028 <TD width=15% BGCOLOR=#FBF5EF>
\r
35031 <TD width=35% BGCOLOR=#FBF5EF>
\r
35032 <B>Master ID 06 Register</B>
\r
35035 <TR valign="top">
\r
35036 <TD width=15% BGCOLOR=#FBF5EF>
\r
35037 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID07">
\r
35038 PSU_LPD_XPPU_CFG_MASTER_ID07
\r
35041 <TD width=15% BGCOLOR=#FBF5EF>
\r
35042 <B>0XFF98011C</B>
\r
35044 <TD width=10% BGCOLOR=#FBF5EF>
\r
35047 <TD width=10% BGCOLOR=#FBF5EF>
\r
35050 <TD width=15% BGCOLOR=#FBF5EF>
\r
35053 <TD width=35% BGCOLOR=#FBF5EF>
\r
35054 <B>Master ID 07 Register</B>
\r
35057 <TR valign="top">
\r
35058 <TD width=15% BGCOLOR=#FBF5EF>
\r
35059 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID08">
\r
35060 PSU_LPD_XPPU_CFG_MASTER_ID08
\r
35063 <TD width=15% BGCOLOR=#FBF5EF>
\r
35064 <B>0XFF980120</B>
\r
35066 <TD width=10% BGCOLOR=#FBF5EF>
\r
35069 <TD width=10% BGCOLOR=#FBF5EF>
\r
35072 <TD width=15% BGCOLOR=#FBF5EF>
\r
35075 <TD width=35% BGCOLOR=#FBF5EF>
\r
35076 <B>Master ID 08 Register</B>
\r
35079 <TR valign="top">
\r
35080 <TD width=15% BGCOLOR=#FBF5EF>
\r
35081 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID09">
\r
35082 PSU_LPD_XPPU_CFG_MASTER_ID09
\r
35085 <TD width=15% BGCOLOR=#FBF5EF>
\r
35086 <B>0XFF980124</B>
\r
35088 <TD width=10% BGCOLOR=#FBF5EF>
\r
35091 <TD width=10% BGCOLOR=#FBF5EF>
\r
35094 <TD width=15% BGCOLOR=#FBF5EF>
\r
35097 <TD width=35% BGCOLOR=#FBF5EF>
\r
35098 <B>Master ID 09 Register</B>
\r
35101 <TR valign="top">
\r
35102 <TD width=15% BGCOLOR=#FBF5EF>
\r
35103 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID10">
\r
35104 PSU_LPD_XPPU_CFG_MASTER_ID10
\r
35107 <TD width=15% BGCOLOR=#FBF5EF>
\r
35108 <B>0XFF980128</B>
\r
35110 <TD width=10% BGCOLOR=#FBF5EF>
\r
35113 <TD width=10% BGCOLOR=#FBF5EF>
\r
35116 <TD width=15% BGCOLOR=#FBF5EF>
\r
35119 <TD width=35% BGCOLOR=#FBF5EF>
\r
35120 <B>Master ID 10 Register</B>
\r
35123 <TR valign="top">
\r
35124 <TD width=15% BGCOLOR=#FBF5EF>
\r
35125 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID11">
\r
35126 PSU_LPD_XPPU_CFG_MASTER_ID11
\r
35129 <TD width=15% BGCOLOR=#FBF5EF>
\r
35130 <B>0XFF98012C</B>
\r
35132 <TD width=10% BGCOLOR=#FBF5EF>
\r
35135 <TD width=10% BGCOLOR=#FBF5EF>
\r
35138 <TD width=15% BGCOLOR=#FBF5EF>
\r
35141 <TD width=35% BGCOLOR=#FBF5EF>
\r
35142 <B>Master ID 11 Register</B>
\r
35145 <TR valign="top">
\r
35146 <TD width=15% BGCOLOR=#FBF5EF>
\r
35147 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID12">
\r
35148 PSU_LPD_XPPU_CFG_MASTER_ID12
\r
35151 <TD width=15% BGCOLOR=#FBF5EF>
\r
35152 <B>0XFF980130</B>
\r
35154 <TD width=10% BGCOLOR=#FBF5EF>
\r
35157 <TD width=10% BGCOLOR=#FBF5EF>
\r
35160 <TD width=15% BGCOLOR=#FBF5EF>
\r
35163 <TD width=35% BGCOLOR=#FBF5EF>
\r
35164 <B>Master ID 12 Register</B>
\r
35167 <TR valign="top">
\r
35168 <TD width=15% BGCOLOR=#FBF5EF>
\r
35169 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID13">
\r
35170 PSU_LPD_XPPU_CFG_MASTER_ID13
\r
35173 <TD width=15% BGCOLOR=#FBF5EF>
\r
35174 <B>0XFF980134</B>
\r
35176 <TD width=10% BGCOLOR=#FBF5EF>
\r
35179 <TD width=10% BGCOLOR=#FBF5EF>
\r
35182 <TD width=15% BGCOLOR=#FBF5EF>
\r
35185 <TD width=35% BGCOLOR=#FBF5EF>
\r
35186 <B>Master ID 13 Register</B>
\r
35189 <TR valign="top">
\r
35190 <TD width=15% BGCOLOR=#FBF5EF>
\r
35191 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID14">
\r
35192 PSU_LPD_XPPU_CFG_MASTER_ID14
\r
35195 <TD width=15% BGCOLOR=#FBF5EF>
\r
35196 <B>0XFF980138</B>
\r
35198 <TD width=10% BGCOLOR=#FBF5EF>
\r
35201 <TD width=10% BGCOLOR=#FBF5EF>
\r
35204 <TD width=15% BGCOLOR=#FBF5EF>
\r
35207 <TD width=35% BGCOLOR=#FBF5EF>
\r
35208 <B>Master ID 14 Register</B>
\r
35211 <TR valign="top">
\r
35212 <TD width=15% BGCOLOR=#FBF5EF>
\r
35213 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID15">
\r
35214 PSU_LPD_XPPU_CFG_MASTER_ID15
\r
35217 <TD width=15% BGCOLOR=#FBF5EF>
\r
35218 <B>0XFF98013C</B>
\r
35220 <TD width=10% BGCOLOR=#FBF5EF>
\r
35223 <TD width=10% BGCOLOR=#FBF5EF>
\r
35226 <TD width=15% BGCOLOR=#FBF5EF>
\r
35229 <TD width=35% BGCOLOR=#FBF5EF>
\r
35230 <B>Master ID 15 Register</B>
\r
35233 <TR valign="top">
\r
35234 <TD width=15% BGCOLOR=#FBF5EF>
\r
35235 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID16">
\r
35236 PSU_LPD_XPPU_CFG_MASTER_ID16
\r
35239 <TD width=15% BGCOLOR=#FBF5EF>
\r
35240 <B>0XFF980140</B>
\r
35242 <TD width=10% BGCOLOR=#FBF5EF>
\r
35245 <TD width=10% BGCOLOR=#FBF5EF>
\r
35248 <TD width=15% BGCOLOR=#FBF5EF>
\r
35251 <TD width=35% BGCOLOR=#FBF5EF>
\r
35252 <B>Master ID 16 Register</B>
\r
35255 <TR valign="top">
\r
35256 <TD width=15% BGCOLOR=#FBF5EF>
\r
35257 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID17">
\r
35258 PSU_LPD_XPPU_CFG_MASTER_ID17
\r
35261 <TD width=15% BGCOLOR=#FBF5EF>
\r
35262 <B>0XFF980144</B>
\r
35264 <TD width=10% BGCOLOR=#FBF5EF>
\r
35267 <TD width=10% BGCOLOR=#FBF5EF>
\r
35270 <TD width=15% BGCOLOR=#FBF5EF>
\r
35273 <TD width=35% BGCOLOR=#FBF5EF>
\r
35274 <B>Master ID 17 Register</B>
\r
35277 <TR valign="top">
\r
35278 <TD width=15% BGCOLOR=#FBF5EF>
\r
35279 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID18">
\r
35280 PSU_LPD_XPPU_CFG_MASTER_ID18
\r
35283 <TD width=15% BGCOLOR=#FBF5EF>
\r
35284 <B>0XFF980148</B>
\r
35286 <TD width=10% BGCOLOR=#FBF5EF>
\r
35289 <TD width=10% BGCOLOR=#FBF5EF>
\r
35292 <TD width=15% BGCOLOR=#FBF5EF>
\r
35295 <TD width=35% BGCOLOR=#FBF5EF>
\r
35296 <B>Master ID 18 Register</B>
\r
35299 <TR valign="top">
\r
35300 <TD width=15% BGCOLOR=#FBF5EF>
\r
35301 <A href="#PSU_LPD_XPPU_CFG_MASTER_ID19">
\r
35302 PSU_LPD_XPPU_CFG_MASTER_ID19
\r
35305 <TD width=15% BGCOLOR=#FBF5EF>
\r
35306 <B>0XFF98014C</B>
\r
35308 <TD width=10% BGCOLOR=#FBF5EF>
\r
35311 <TD width=10% BGCOLOR=#FBF5EF>
\r
35314 <TD width=15% BGCOLOR=#FBF5EF>
\r
35317 <TD width=35% BGCOLOR=#FBF5EF>
\r
35318 <B>Master ID 19 Register</B>
\r
35323 <H2><a name="psu_security_data_3_0">psu_security_data_3_0</a></H2>
\r
35324 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35325 <TR valign="top">
\r
35326 <TD width=15% BGCOLOR=#FFC0FF>
\r
35327 <B>Register Name</B>
\r
35329 <TD width=15% BGCOLOR=#FFC0FF>
\r
35332 <TD width=10% BGCOLOR=#FFC0FF>
\r
35335 <TD width=10% BGCOLOR=#FFC0FF>
\r
35338 <TD width=15% BGCOLOR=#FFC0FF>
\r
35339 <B>Reset Value</B>
\r
35341 <TD width=35% BGCOLOR=#FFC0FF>
\r
35342 <B>Description</B>
\r
35345 <H1>DDR XMPU0</H1>
\r
35346 <H1>DDR XMPU1</H1>
\r
35347 <H1>DDR XMPU2</H1>
\r
35348 <H1>DDR XMPU3</H1>
\r
35349 <H1>DDR XMPU4</H1>
\r
35350 <H1>DDR XMPU5</H1>
\r
35351 <H1>FPD XMPU</H1>
\r
35352 <H1>OCM XMPU</H1>
\r
35354 <H1>MASTER ID LIST</H1>
\r
35355 <H2><a name="MASTER_ID00">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID00</a></H2>
\r
35356 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35357 <TR valign="top">
\r
35358 <TD width=15% BGCOLOR=#FFFF00>
\r
35359 <B>Register Name</B>
\r
35361 <TD width=15% BGCOLOR=#FFFF00>
\r
35364 <TD width=10% BGCOLOR=#FFFF00>
\r
35367 <TD width=10% BGCOLOR=#FFFF00>
\r
35370 <TD width=15% BGCOLOR=#FFFF00>
\r
35371 <B>Reset Value</B>
\r
35373 <TD width=35% BGCOLOR=#FFFF00>
\r
35374 <B>Description</B>
\r
35377 <TR valign="top">
\r
35378 <TD width=15% BGCOLOR=#FBF5EF>
\r
35379 <B>MASTER_ID00</B>
\r
35381 <TD width=15% BGCOLOR=#FBF5EF>
\r
35382 <B>0XFF980100</B>
\r
35384 <TD width=10% BGCOLOR=#FBF5EF>
\r
35387 <TD width=10% BGCOLOR=#FBF5EF>
\r
35390 <TD width=15% BGCOLOR=#FBF5EF>
\r
35391 <B>0x00000000</B>
\r
35393 <TD width=35% BGCOLOR=#FBF5EF>
\r
35399 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35400 <TR valign="top">
\r
35401 <TD width=15% BGCOLOR=#C0FFC0>
\r
35402 <B>Field Name</B>
\r
35404 <TD width=15% BGCOLOR=#C0FFC0>
\r
35407 <TD width=10% BGCOLOR=#C0FFC0>
\r
35410 <TD width=10% BGCOLOR=#C0FFC0>
\r
35413 <TD width=15% BGCOLOR=#C0FFC0>
\r
35414 <B>Shifted Value</B>
\r
35416 <TD width=35% BGCOLOR=#C0FFC0>
\r
35417 <B>Description</B>
\r
35420 <TR valign="top">
\r
35421 <TD width=15% BGCOLOR=#FBF5EF>
\r
35422 <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP</B>
\r
35424 <TD width=15% BGCOLOR=#FBF5EF>
\r
35427 <TD width=10% BGCOLOR=#FBF5EF>
\r
35430 <TD width=10% BGCOLOR=#FBF5EF>
\r
35433 <TD width=15% BGCOLOR=#FBF5EF>
\r
35436 <TD width=35% BGCOLOR=#FBF5EF>
\r
35437 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
35440 <TR valign="top">
\r
35441 <TD width=15% BGCOLOR=#FBF5EF>
\r
35442 <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR</B>
\r
35444 <TD width=15% BGCOLOR=#FBF5EF>
\r
35447 <TD width=10% BGCOLOR=#FBF5EF>
\r
35450 <TD width=10% BGCOLOR=#FBF5EF>
\r
35453 <TD width=15% BGCOLOR=#FBF5EF>
\r
35456 <TD width=35% BGCOLOR=#FBF5EF>
\r
35457 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
35460 <TR valign="top">
\r
35461 <TD width=15% BGCOLOR=#FBF5EF>
\r
35462 <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM</B>
\r
35464 <TD width=15% BGCOLOR=#FBF5EF>
\r
35467 <TD width=10% BGCOLOR=#FBF5EF>
\r
35470 <TD width=10% BGCOLOR=#FBF5EF>
\r
35473 <TD width=15% BGCOLOR=#FBF5EF>
\r
35476 <TD width=35% BGCOLOR=#FBF5EF>
\r
35477 <B>Mask to be applied before comparing</B>
\r
35480 <TR valign="top">
\r
35481 <TD width=15% BGCOLOR=#FBF5EF>
\r
35482 <B>PSU_LPD_XPPU_CFG_MASTER_ID00_MID</B>
\r
35484 <TD width=15% BGCOLOR=#FBF5EF>
\r
35487 <TD width=10% BGCOLOR=#FBF5EF>
\r
35490 <TD width=10% BGCOLOR=#FBF5EF>
\r
35493 <TD width=15% BGCOLOR=#FBF5EF>
\r
35496 <TD width=35% BGCOLOR=#FBF5EF>
\r
35497 <B>Predefined Master ID for PMU</B>
\r
35500 <TR valign="top">
\r
35501 <TD width=15% BGCOLOR=#C0C0C0>
\r
35502 <B>PSU_LPD_XPPU_CFG_MASTER_ID00@0XFF980100</B>
\r
35504 <TD width=15% BGCOLOR=#C0C0C0>
\r
35507 <TD width=10% BGCOLOR=#C0C0C0>
\r
35510 <TD width=10% BGCOLOR=#C0C0C0>
\r
35513 <TD width=15% BGCOLOR=#C0C0C0>
\r
35516 <TD width=35% BGCOLOR=#C0C0C0>
\r
35517 <B>Master ID 00 Register</B>
\r
35522 <H2><a name="MASTER_ID01">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID01</a></H2>
\r
35523 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35524 <TR valign="top">
\r
35525 <TD width=15% BGCOLOR=#FFFF00>
\r
35526 <B>Register Name</B>
\r
35528 <TD width=15% BGCOLOR=#FFFF00>
\r
35531 <TD width=10% BGCOLOR=#FFFF00>
\r
35534 <TD width=10% BGCOLOR=#FFFF00>
\r
35537 <TD width=15% BGCOLOR=#FFFF00>
\r
35538 <B>Reset Value</B>
\r
35540 <TD width=35% BGCOLOR=#FFFF00>
\r
35541 <B>Description</B>
\r
35544 <TR valign="top">
\r
35545 <TD width=15% BGCOLOR=#FBF5EF>
\r
35546 <B>MASTER_ID01</B>
\r
35548 <TD width=15% BGCOLOR=#FBF5EF>
\r
35549 <B>0XFF980104</B>
\r
35551 <TD width=10% BGCOLOR=#FBF5EF>
\r
35554 <TD width=10% BGCOLOR=#FBF5EF>
\r
35557 <TD width=15% BGCOLOR=#FBF5EF>
\r
35558 <B>0x00000000</B>
\r
35560 <TD width=35% BGCOLOR=#FBF5EF>
\r
35566 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35567 <TR valign="top">
\r
35568 <TD width=15% BGCOLOR=#C0FFC0>
\r
35569 <B>Field Name</B>
\r
35571 <TD width=15% BGCOLOR=#C0FFC0>
\r
35574 <TD width=10% BGCOLOR=#C0FFC0>
\r
35577 <TD width=10% BGCOLOR=#C0FFC0>
\r
35580 <TD width=15% BGCOLOR=#C0FFC0>
\r
35581 <B>Shifted Value</B>
\r
35583 <TD width=35% BGCOLOR=#C0FFC0>
\r
35584 <B>Description</B>
\r
35587 <TR valign="top">
\r
35588 <TD width=15% BGCOLOR=#FBF5EF>
\r
35589 <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP</B>
\r
35591 <TD width=15% BGCOLOR=#FBF5EF>
\r
35594 <TD width=10% BGCOLOR=#FBF5EF>
\r
35597 <TD width=10% BGCOLOR=#FBF5EF>
\r
35600 <TD width=15% BGCOLOR=#FBF5EF>
\r
35603 <TD width=35% BGCOLOR=#FBF5EF>
\r
35604 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
35607 <TR valign="top">
\r
35608 <TD width=15% BGCOLOR=#FBF5EF>
\r
35609 <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR</B>
\r
35611 <TD width=15% BGCOLOR=#FBF5EF>
\r
35614 <TD width=10% BGCOLOR=#FBF5EF>
\r
35617 <TD width=10% BGCOLOR=#FBF5EF>
\r
35620 <TD width=15% BGCOLOR=#FBF5EF>
\r
35623 <TD width=35% BGCOLOR=#FBF5EF>
\r
35624 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
35627 <TR valign="top">
\r
35628 <TD width=15% BGCOLOR=#FBF5EF>
\r
35629 <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM</B>
\r
35631 <TD width=15% BGCOLOR=#FBF5EF>
\r
35634 <TD width=10% BGCOLOR=#FBF5EF>
\r
35637 <TD width=10% BGCOLOR=#FBF5EF>
\r
35640 <TD width=15% BGCOLOR=#FBF5EF>
\r
35643 <TD width=35% BGCOLOR=#FBF5EF>
\r
35644 <B>Mask to be applied before comparing</B>
\r
35647 <TR valign="top">
\r
35648 <TD width=15% BGCOLOR=#FBF5EF>
\r
35649 <B>PSU_LPD_XPPU_CFG_MASTER_ID01_MID</B>
\r
35651 <TD width=15% BGCOLOR=#FBF5EF>
\r
35654 <TD width=10% BGCOLOR=#FBF5EF>
\r
35657 <TD width=10% BGCOLOR=#FBF5EF>
\r
35660 <TD width=15% BGCOLOR=#FBF5EF>
\r
35663 <TD width=35% BGCOLOR=#FBF5EF>
\r
35664 <B>Predefined Master ID for RPU0</B>
\r
35667 <TR valign="top">
\r
35668 <TD width=15% BGCOLOR=#C0C0C0>
\r
35669 <B>PSU_LPD_XPPU_CFG_MASTER_ID01@0XFF980104</B>
\r
35671 <TD width=15% BGCOLOR=#C0C0C0>
\r
35674 <TD width=10% BGCOLOR=#C0C0C0>
\r
35677 <TD width=10% BGCOLOR=#C0C0C0>
\r
35680 <TD width=15% BGCOLOR=#C0C0C0>
\r
35683 <TD width=35% BGCOLOR=#C0C0C0>
\r
35684 <B>Master ID 01 Register</B>
\r
35689 <H2><a name="MASTER_ID02">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID02</a></H2>
\r
35690 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35691 <TR valign="top">
\r
35692 <TD width=15% BGCOLOR=#FFFF00>
\r
35693 <B>Register Name</B>
\r
35695 <TD width=15% BGCOLOR=#FFFF00>
\r
35698 <TD width=10% BGCOLOR=#FFFF00>
\r
35701 <TD width=10% BGCOLOR=#FFFF00>
\r
35704 <TD width=15% BGCOLOR=#FFFF00>
\r
35705 <B>Reset Value</B>
\r
35707 <TD width=35% BGCOLOR=#FFFF00>
\r
35708 <B>Description</B>
\r
35711 <TR valign="top">
\r
35712 <TD width=15% BGCOLOR=#FBF5EF>
\r
35713 <B>MASTER_ID02</B>
\r
35715 <TD width=15% BGCOLOR=#FBF5EF>
\r
35716 <B>0XFF980108</B>
\r
35718 <TD width=10% BGCOLOR=#FBF5EF>
\r
35721 <TD width=10% BGCOLOR=#FBF5EF>
\r
35724 <TD width=15% BGCOLOR=#FBF5EF>
\r
35725 <B>0x00000000</B>
\r
35727 <TD width=35% BGCOLOR=#FBF5EF>
\r
35733 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35734 <TR valign="top">
\r
35735 <TD width=15% BGCOLOR=#C0FFC0>
\r
35736 <B>Field Name</B>
\r
35738 <TD width=15% BGCOLOR=#C0FFC0>
\r
35741 <TD width=10% BGCOLOR=#C0FFC0>
\r
35744 <TD width=10% BGCOLOR=#C0FFC0>
\r
35747 <TD width=15% BGCOLOR=#C0FFC0>
\r
35748 <B>Shifted Value</B>
\r
35750 <TD width=35% BGCOLOR=#C0FFC0>
\r
35751 <B>Description</B>
\r
35754 <TR valign="top">
\r
35755 <TD width=15% BGCOLOR=#FBF5EF>
\r
35756 <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP</B>
\r
35758 <TD width=15% BGCOLOR=#FBF5EF>
\r
35761 <TD width=10% BGCOLOR=#FBF5EF>
\r
35764 <TD width=10% BGCOLOR=#FBF5EF>
\r
35767 <TD width=15% BGCOLOR=#FBF5EF>
\r
35770 <TD width=35% BGCOLOR=#FBF5EF>
\r
35771 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
35774 <TR valign="top">
\r
35775 <TD width=15% BGCOLOR=#FBF5EF>
\r
35776 <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR</B>
\r
35778 <TD width=15% BGCOLOR=#FBF5EF>
\r
35781 <TD width=10% BGCOLOR=#FBF5EF>
\r
35784 <TD width=10% BGCOLOR=#FBF5EF>
\r
35787 <TD width=15% BGCOLOR=#FBF5EF>
\r
35790 <TD width=35% BGCOLOR=#FBF5EF>
\r
35791 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
35794 <TR valign="top">
\r
35795 <TD width=15% BGCOLOR=#FBF5EF>
\r
35796 <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM</B>
\r
35798 <TD width=15% BGCOLOR=#FBF5EF>
\r
35801 <TD width=10% BGCOLOR=#FBF5EF>
\r
35804 <TD width=10% BGCOLOR=#FBF5EF>
\r
35807 <TD width=15% BGCOLOR=#FBF5EF>
\r
35810 <TD width=35% BGCOLOR=#FBF5EF>
\r
35811 <B>Mask to be applied before comparing</B>
\r
35814 <TR valign="top">
\r
35815 <TD width=15% BGCOLOR=#FBF5EF>
\r
35816 <B>PSU_LPD_XPPU_CFG_MASTER_ID02_MID</B>
\r
35818 <TD width=15% BGCOLOR=#FBF5EF>
\r
35821 <TD width=10% BGCOLOR=#FBF5EF>
\r
35824 <TD width=10% BGCOLOR=#FBF5EF>
\r
35827 <TD width=15% BGCOLOR=#FBF5EF>
\r
35830 <TD width=35% BGCOLOR=#FBF5EF>
\r
35831 <B>Predefined Master ID for RPU1</B>
\r
35834 <TR valign="top">
\r
35835 <TD width=15% BGCOLOR=#C0C0C0>
\r
35836 <B>PSU_LPD_XPPU_CFG_MASTER_ID02@0XFF980108</B>
\r
35838 <TD width=15% BGCOLOR=#C0C0C0>
\r
35841 <TD width=10% BGCOLOR=#C0C0C0>
\r
35844 <TD width=10% BGCOLOR=#C0C0C0>
\r
35847 <TD width=15% BGCOLOR=#C0C0C0>
\r
35850 <TD width=35% BGCOLOR=#C0C0C0>
\r
35851 <B>Master ID 02 Register</B>
\r
35856 <H2><a name="MASTER_ID03">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID03</a></H2>
\r
35857 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35858 <TR valign="top">
\r
35859 <TD width=15% BGCOLOR=#FFFF00>
\r
35860 <B>Register Name</B>
\r
35862 <TD width=15% BGCOLOR=#FFFF00>
\r
35865 <TD width=10% BGCOLOR=#FFFF00>
\r
35868 <TD width=10% BGCOLOR=#FFFF00>
\r
35871 <TD width=15% BGCOLOR=#FFFF00>
\r
35872 <B>Reset Value</B>
\r
35874 <TD width=35% BGCOLOR=#FFFF00>
\r
35875 <B>Description</B>
\r
35878 <TR valign="top">
\r
35879 <TD width=15% BGCOLOR=#FBF5EF>
\r
35880 <B>MASTER_ID03</B>
\r
35882 <TD width=15% BGCOLOR=#FBF5EF>
\r
35883 <B>0XFF98010C</B>
\r
35885 <TD width=10% BGCOLOR=#FBF5EF>
\r
35888 <TD width=10% BGCOLOR=#FBF5EF>
\r
35891 <TD width=15% BGCOLOR=#FBF5EF>
\r
35892 <B>0x00000000</B>
\r
35894 <TD width=35% BGCOLOR=#FBF5EF>
\r
35900 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
35901 <TR valign="top">
\r
35902 <TD width=15% BGCOLOR=#C0FFC0>
\r
35903 <B>Field Name</B>
\r
35905 <TD width=15% BGCOLOR=#C0FFC0>
\r
35908 <TD width=10% BGCOLOR=#C0FFC0>
\r
35911 <TD width=10% BGCOLOR=#C0FFC0>
\r
35914 <TD width=15% BGCOLOR=#C0FFC0>
\r
35915 <B>Shifted Value</B>
\r
35917 <TD width=35% BGCOLOR=#C0FFC0>
\r
35918 <B>Description</B>
\r
35921 <TR valign="top">
\r
35922 <TD width=15% BGCOLOR=#FBF5EF>
\r
35923 <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP</B>
\r
35925 <TD width=15% BGCOLOR=#FBF5EF>
\r
35928 <TD width=10% BGCOLOR=#FBF5EF>
\r
35931 <TD width=10% BGCOLOR=#FBF5EF>
\r
35934 <TD width=15% BGCOLOR=#FBF5EF>
\r
35937 <TD width=35% BGCOLOR=#FBF5EF>
\r
35938 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
35941 <TR valign="top">
\r
35942 <TD width=15% BGCOLOR=#FBF5EF>
\r
35943 <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR</B>
\r
35945 <TD width=15% BGCOLOR=#FBF5EF>
\r
35948 <TD width=10% BGCOLOR=#FBF5EF>
\r
35951 <TD width=10% BGCOLOR=#FBF5EF>
\r
35954 <TD width=15% BGCOLOR=#FBF5EF>
\r
35957 <TD width=35% BGCOLOR=#FBF5EF>
\r
35958 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
35961 <TR valign="top">
\r
35962 <TD width=15% BGCOLOR=#FBF5EF>
\r
35963 <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM</B>
\r
35965 <TD width=15% BGCOLOR=#FBF5EF>
\r
35968 <TD width=10% BGCOLOR=#FBF5EF>
\r
35971 <TD width=10% BGCOLOR=#FBF5EF>
\r
35974 <TD width=15% BGCOLOR=#FBF5EF>
\r
35977 <TD width=35% BGCOLOR=#FBF5EF>
\r
35978 <B>Mask to be applied before comparing</B>
\r
35981 <TR valign="top">
\r
35982 <TD width=15% BGCOLOR=#FBF5EF>
\r
35983 <B>PSU_LPD_XPPU_CFG_MASTER_ID03_MID</B>
\r
35985 <TD width=15% BGCOLOR=#FBF5EF>
\r
35988 <TD width=10% BGCOLOR=#FBF5EF>
\r
35991 <TD width=10% BGCOLOR=#FBF5EF>
\r
35994 <TD width=15% BGCOLOR=#FBF5EF>
\r
35997 <TD width=35% BGCOLOR=#FBF5EF>
\r
35998 <B>Predefined Master ID for APU</B>
\r
36001 <TR valign="top">
\r
36002 <TD width=15% BGCOLOR=#C0C0C0>
\r
36003 <B>PSU_LPD_XPPU_CFG_MASTER_ID03@0XFF98010C</B>
\r
36005 <TD width=15% BGCOLOR=#C0C0C0>
\r
36008 <TD width=10% BGCOLOR=#C0C0C0>
\r
36011 <TD width=10% BGCOLOR=#C0C0C0>
\r
36014 <TD width=15% BGCOLOR=#C0C0C0>
\r
36017 <TD width=35% BGCOLOR=#C0C0C0>
\r
36018 <B>Master ID 03 Register</B>
\r
36023 <H2><a name="MASTER_ID04">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID04</a></H2>
\r
36024 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36025 <TR valign="top">
\r
36026 <TD width=15% BGCOLOR=#FFFF00>
\r
36027 <B>Register Name</B>
\r
36029 <TD width=15% BGCOLOR=#FFFF00>
\r
36032 <TD width=10% BGCOLOR=#FFFF00>
\r
36035 <TD width=10% BGCOLOR=#FFFF00>
\r
36038 <TD width=15% BGCOLOR=#FFFF00>
\r
36039 <B>Reset Value</B>
\r
36041 <TD width=35% BGCOLOR=#FFFF00>
\r
36042 <B>Description</B>
\r
36045 <TR valign="top">
\r
36046 <TD width=15% BGCOLOR=#FBF5EF>
\r
36047 <B>MASTER_ID04</B>
\r
36049 <TD width=15% BGCOLOR=#FBF5EF>
\r
36050 <B>0XFF980110</B>
\r
36052 <TD width=10% BGCOLOR=#FBF5EF>
\r
36055 <TD width=10% BGCOLOR=#FBF5EF>
\r
36058 <TD width=15% BGCOLOR=#FBF5EF>
\r
36059 <B>0x00000000</B>
\r
36061 <TD width=35% BGCOLOR=#FBF5EF>
\r
36067 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36068 <TR valign="top">
\r
36069 <TD width=15% BGCOLOR=#C0FFC0>
\r
36070 <B>Field Name</B>
\r
36072 <TD width=15% BGCOLOR=#C0FFC0>
\r
36075 <TD width=10% BGCOLOR=#C0FFC0>
\r
36078 <TD width=10% BGCOLOR=#C0FFC0>
\r
36081 <TD width=15% BGCOLOR=#C0FFC0>
\r
36082 <B>Shifted Value</B>
\r
36084 <TD width=35% BGCOLOR=#C0FFC0>
\r
36085 <B>Description</B>
\r
36088 <TR valign="top">
\r
36089 <TD width=15% BGCOLOR=#FBF5EF>
\r
36090 <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP</B>
\r
36092 <TD width=15% BGCOLOR=#FBF5EF>
\r
36095 <TD width=10% BGCOLOR=#FBF5EF>
\r
36098 <TD width=10% BGCOLOR=#FBF5EF>
\r
36101 <TD width=15% BGCOLOR=#FBF5EF>
\r
36104 <TD width=35% BGCOLOR=#FBF5EF>
\r
36105 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36108 <TR valign="top">
\r
36109 <TD width=15% BGCOLOR=#FBF5EF>
\r
36110 <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR</B>
\r
36112 <TD width=15% BGCOLOR=#FBF5EF>
\r
36115 <TD width=10% BGCOLOR=#FBF5EF>
\r
36118 <TD width=10% BGCOLOR=#FBF5EF>
\r
36121 <TD width=15% BGCOLOR=#FBF5EF>
\r
36124 <TD width=35% BGCOLOR=#FBF5EF>
\r
36125 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36128 <TR valign="top">
\r
36129 <TD width=15% BGCOLOR=#FBF5EF>
\r
36130 <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM</B>
\r
36132 <TD width=15% BGCOLOR=#FBF5EF>
\r
36135 <TD width=10% BGCOLOR=#FBF5EF>
\r
36138 <TD width=10% BGCOLOR=#FBF5EF>
\r
36141 <TD width=15% BGCOLOR=#FBF5EF>
\r
36144 <TD width=35% BGCOLOR=#FBF5EF>
\r
36145 <B>Mask to be applied before comparing</B>
\r
36148 <TR valign="top">
\r
36149 <TD width=15% BGCOLOR=#FBF5EF>
\r
36150 <B>PSU_LPD_XPPU_CFG_MASTER_ID04_MID</B>
\r
36152 <TD width=15% BGCOLOR=#FBF5EF>
\r
36155 <TD width=10% BGCOLOR=#FBF5EF>
\r
36158 <TD width=10% BGCOLOR=#FBF5EF>
\r
36161 <TD width=15% BGCOLOR=#FBF5EF>
\r
36164 <TD width=35% BGCOLOR=#FBF5EF>
\r
36165 <B>Predefined Master ID for A53 Core 0</B>
\r
36168 <TR valign="top">
\r
36169 <TD width=15% BGCOLOR=#C0C0C0>
\r
36170 <B>PSU_LPD_XPPU_CFG_MASTER_ID04@0XFF980110</B>
\r
36172 <TD width=15% BGCOLOR=#C0C0C0>
\r
36175 <TD width=10% BGCOLOR=#C0C0C0>
\r
36178 <TD width=10% BGCOLOR=#C0C0C0>
\r
36181 <TD width=15% BGCOLOR=#C0C0C0>
\r
36184 <TD width=35% BGCOLOR=#C0C0C0>
\r
36185 <B>Master ID 04 Register</B>
\r
36190 <H2><a name="MASTER_ID05">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID05</a></H2>
\r
36191 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36192 <TR valign="top">
\r
36193 <TD width=15% BGCOLOR=#FFFF00>
\r
36194 <B>Register Name</B>
\r
36196 <TD width=15% BGCOLOR=#FFFF00>
\r
36199 <TD width=10% BGCOLOR=#FFFF00>
\r
36202 <TD width=10% BGCOLOR=#FFFF00>
\r
36205 <TD width=15% BGCOLOR=#FFFF00>
\r
36206 <B>Reset Value</B>
\r
36208 <TD width=35% BGCOLOR=#FFFF00>
\r
36209 <B>Description</B>
\r
36212 <TR valign="top">
\r
36213 <TD width=15% BGCOLOR=#FBF5EF>
\r
36214 <B>MASTER_ID05</B>
\r
36216 <TD width=15% BGCOLOR=#FBF5EF>
\r
36217 <B>0XFF980114</B>
\r
36219 <TD width=10% BGCOLOR=#FBF5EF>
\r
36222 <TD width=10% BGCOLOR=#FBF5EF>
\r
36225 <TD width=15% BGCOLOR=#FBF5EF>
\r
36226 <B>0x00000000</B>
\r
36228 <TD width=35% BGCOLOR=#FBF5EF>
\r
36234 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36235 <TR valign="top">
\r
36236 <TD width=15% BGCOLOR=#C0FFC0>
\r
36237 <B>Field Name</B>
\r
36239 <TD width=15% BGCOLOR=#C0FFC0>
\r
36242 <TD width=10% BGCOLOR=#C0FFC0>
\r
36245 <TD width=10% BGCOLOR=#C0FFC0>
\r
36248 <TD width=15% BGCOLOR=#C0FFC0>
\r
36249 <B>Shifted Value</B>
\r
36251 <TD width=35% BGCOLOR=#C0FFC0>
\r
36252 <B>Description</B>
\r
36255 <TR valign="top">
\r
36256 <TD width=15% BGCOLOR=#FBF5EF>
\r
36257 <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP</B>
\r
36259 <TD width=15% BGCOLOR=#FBF5EF>
\r
36262 <TD width=10% BGCOLOR=#FBF5EF>
\r
36265 <TD width=10% BGCOLOR=#FBF5EF>
\r
36268 <TD width=15% BGCOLOR=#FBF5EF>
\r
36271 <TD width=35% BGCOLOR=#FBF5EF>
\r
36272 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36275 <TR valign="top">
\r
36276 <TD width=15% BGCOLOR=#FBF5EF>
\r
36277 <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR</B>
\r
36279 <TD width=15% BGCOLOR=#FBF5EF>
\r
36282 <TD width=10% BGCOLOR=#FBF5EF>
\r
36285 <TD width=10% BGCOLOR=#FBF5EF>
\r
36288 <TD width=15% BGCOLOR=#FBF5EF>
\r
36291 <TD width=35% BGCOLOR=#FBF5EF>
\r
36292 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36295 <TR valign="top">
\r
36296 <TD width=15% BGCOLOR=#FBF5EF>
\r
36297 <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM</B>
\r
36299 <TD width=15% BGCOLOR=#FBF5EF>
\r
36302 <TD width=10% BGCOLOR=#FBF5EF>
\r
36305 <TD width=10% BGCOLOR=#FBF5EF>
\r
36308 <TD width=15% BGCOLOR=#FBF5EF>
\r
36311 <TD width=35% BGCOLOR=#FBF5EF>
\r
36312 <B>Mask to be applied before comparing</B>
\r
36315 <TR valign="top">
\r
36316 <TD width=15% BGCOLOR=#FBF5EF>
\r
36317 <B>PSU_LPD_XPPU_CFG_MASTER_ID05_MID</B>
\r
36319 <TD width=15% BGCOLOR=#FBF5EF>
\r
36322 <TD width=10% BGCOLOR=#FBF5EF>
\r
36325 <TD width=10% BGCOLOR=#FBF5EF>
\r
36328 <TD width=15% BGCOLOR=#FBF5EF>
\r
36331 <TD width=35% BGCOLOR=#FBF5EF>
\r
36332 <B>Predefined Master ID for A53 Core 1</B>
\r
36335 <TR valign="top">
\r
36336 <TD width=15% BGCOLOR=#C0C0C0>
\r
36337 <B>PSU_LPD_XPPU_CFG_MASTER_ID05@0XFF980114</B>
\r
36339 <TD width=15% BGCOLOR=#C0C0C0>
\r
36342 <TD width=10% BGCOLOR=#C0C0C0>
\r
36345 <TD width=10% BGCOLOR=#C0C0C0>
\r
36348 <TD width=15% BGCOLOR=#C0C0C0>
\r
36351 <TD width=35% BGCOLOR=#C0C0C0>
\r
36352 <B>Master ID 05 Register</B>
\r
36357 <H2><a name="MASTER_ID06">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID06</a></H2>
\r
36358 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36359 <TR valign="top">
\r
36360 <TD width=15% BGCOLOR=#FFFF00>
\r
36361 <B>Register Name</B>
\r
36363 <TD width=15% BGCOLOR=#FFFF00>
\r
36366 <TD width=10% BGCOLOR=#FFFF00>
\r
36369 <TD width=10% BGCOLOR=#FFFF00>
\r
36372 <TD width=15% BGCOLOR=#FFFF00>
\r
36373 <B>Reset Value</B>
\r
36375 <TD width=35% BGCOLOR=#FFFF00>
\r
36376 <B>Description</B>
\r
36379 <TR valign="top">
\r
36380 <TD width=15% BGCOLOR=#FBF5EF>
\r
36381 <B>MASTER_ID06</B>
\r
36383 <TD width=15% BGCOLOR=#FBF5EF>
\r
36384 <B>0XFF980118</B>
\r
36386 <TD width=10% BGCOLOR=#FBF5EF>
\r
36389 <TD width=10% BGCOLOR=#FBF5EF>
\r
36392 <TD width=15% BGCOLOR=#FBF5EF>
\r
36393 <B>0x00000000</B>
\r
36395 <TD width=35% BGCOLOR=#FBF5EF>
\r
36401 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36402 <TR valign="top">
\r
36403 <TD width=15% BGCOLOR=#C0FFC0>
\r
36404 <B>Field Name</B>
\r
36406 <TD width=15% BGCOLOR=#C0FFC0>
\r
36409 <TD width=10% BGCOLOR=#C0FFC0>
\r
36412 <TD width=10% BGCOLOR=#C0FFC0>
\r
36415 <TD width=15% BGCOLOR=#C0FFC0>
\r
36416 <B>Shifted Value</B>
\r
36418 <TD width=35% BGCOLOR=#C0FFC0>
\r
36419 <B>Description</B>
\r
36422 <TR valign="top">
\r
36423 <TD width=15% BGCOLOR=#FBF5EF>
\r
36424 <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP</B>
\r
36426 <TD width=15% BGCOLOR=#FBF5EF>
\r
36429 <TD width=10% BGCOLOR=#FBF5EF>
\r
36432 <TD width=10% BGCOLOR=#FBF5EF>
\r
36435 <TD width=15% BGCOLOR=#FBF5EF>
\r
36438 <TD width=35% BGCOLOR=#FBF5EF>
\r
36439 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36442 <TR valign="top">
\r
36443 <TD width=15% BGCOLOR=#FBF5EF>
\r
36444 <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR</B>
\r
36446 <TD width=15% BGCOLOR=#FBF5EF>
\r
36449 <TD width=10% BGCOLOR=#FBF5EF>
\r
36452 <TD width=10% BGCOLOR=#FBF5EF>
\r
36455 <TD width=15% BGCOLOR=#FBF5EF>
\r
36458 <TD width=35% BGCOLOR=#FBF5EF>
\r
36459 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36462 <TR valign="top">
\r
36463 <TD width=15% BGCOLOR=#FBF5EF>
\r
36464 <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM</B>
\r
36466 <TD width=15% BGCOLOR=#FBF5EF>
\r
36469 <TD width=10% BGCOLOR=#FBF5EF>
\r
36472 <TD width=10% BGCOLOR=#FBF5EF>
\r
36475 <TD width=15% BGCOLOR=#FBF5EF>
\r
36478 <TD width=35% BGCOLOR=#FBF5EF>
\r
36479 <B>Mask to be applied before comparing</B>
\r
36482 <TR valign="top">
\r
36483 <TD width=15% BGCOLOR=#FBF5EF>
\r
36484 <B>PSU_LPD_XPPU_CFG_MASTER_ID06_MID</B>
\r
36486 <TD width=15% BGCOLOR=#FBF5EF>
\r
36489 <TD width=10% BGCOLOR=#FBF5EF>
\r
36492 <TD width=10% BGCOLOR=#FBF5EF>
\r
36495 <TD width=15% BGCOLOR=#FBF5EF>
\r
36498 <TD width=35% BGCOLOR=#FBF5EF>
\r
36499 <B>Predefined Master ID for A53 Core 2</B>
\r
36502 <TR valign="top">
\r
36503 <TD width=15% BGCOLOR=#C0C0C0>
\r
36504 <B>PSU_LPD_XPPU_CFG_MASTER_ID06@0XFF980118</B>
\r
36506 <TD width=15% BGCOLOR=#C0C0C0>
\r
36509 <TD width=10% BGCOLOR=#C0C0C0>
\r
36512 <TD width=10% BGCOLOR=#C0C0C0>
\r
36515 <TD width=15% BGCOLOR=#C0C0C0>
\r
36518 <TD width=35% BGCOLOR=#C0C0C0>
\r
36519 <B>Master ID 06 Register</B>
\r
36524 <H2><a name="MASTER_ID07">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID07</a></H2>
\r
36525 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36526 <TR valign="top">
\r
36527 <TD width=15% BGCOLOR=#FFFF00>
\r
36528 <B>Register Name</B>
\r
36530 <TD width=15% BGCOLOR=#FFFF00>
\r
36533 <TD width=10% BGCOLOR=#FFFF00>
\r
36536 <TD width=10% BGCOLOR=#FFFF00>
\r
36539 <TD width=15% BGCOLOR=#FFFF00>
\r
36540 <B>Reset Value</B>
\r
36542 <TD width=35% BGCOLOR=#FFFF00>
\r
36543 <B>Description</B>
\r
36546 <TR valign="top">
\r
36547 <TD width=15% BGCOLOR=#FBF5EF>
\r
36548 <B>MASTER_ID07</B>
\r
36550 <TD width=15% BGCOLOR=#FBF5EF>
\r
36551 <B>0XFF98011C</B>
\r
36553 <TD width=10% BGCOLOR=#FBF5EF>
\r
36556 <TD width=10% BGCOLOR=#FBF5EF>
\r
36559 <TD width=15% BGCOLOR=#FBF5EF>
\r
36560 <B>0x00000000</B>
\r
36562 <TD width=35% BGCOLOR=#FBF5EF>
\r
36568 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36569 <TR valign="top">
\r
36570 <TD width=15% BGCOLOR=#C0FFC0>
\r
36571 <B>Field Name</B>
\r
36573 <TD width=15% BGCOLOR=#C0FFC0>
\r
36576 <TD width=10% BGCOLOR=#C0FFC0>
\r
36579 <TD width=10% BGCOLOR=#C0FFC0>
\r
36582 <TD width=15% BGCOLOR=#C0FFC0>
\r
36583 <B>Shifted Value</B>
\r
36585 <TD width=35% BGCOLOR=#C0FFC0>
\r
36586 <B>Description</B>
\r
36589 <TR valign="top">
\r
36590 <TD width=15% BGCOLOR=#FBF5EF>
\r
36591 <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP</B>
\r
36593 <TD width=15% BGCOLOR=#FBF5EF>
\r
36596 <TD width=10% BGCOLOR=#FBF5EF>
\r
36599 <TD width=10% BGCOLOR=#FBF5EF>
\r
36602 <TD width=15% BGCOLOR=#FBF5EF>
\r
36605 <TD width=35% BGCOLOR=#FBF5EF>
\r
36606 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36609 <TR valign="top">
\r
36610 <TD width=15% BGCOLOR=#FBF5EF>
\r
36611 <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR</B>
\r
36613 <TD width=15% BGCOLOR=#FBF5EF>
\r
36616 <TD width=10% BGCOLOR=#FBF5EF>
\r
36619 <TD width=10% BGCOLOR=#FBF5EF>
\r
36622 <TD width=15% BGCOLOR=#FBF5EF>
\r
36625 <TD width=35% BGCOLOR=#FBF5EF>
\r
36626 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36629 <TR valign="top">
\r
36630 <TD width=15% BGCOLOR=#FBF5EF>
\r
36631 <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM</B>
\r
36633 <TD width=15% BGCOLOR=#FBF5EF>
\r
36636 <TD width=10% BGCOLOR=#FBF5EF>
\r
36639 <TD width=10% BGCOLOR=#FBF5EF>
\r
36642 <TD width=15% BGCOLOR=#FBF5EF>
\r
36645 <TD width=35% BGCOLOR=#FBF5EF>
\r
36646 <B>Mask to be applied before comparing</B>
\r
36649 <TR valign="top">
\r
36650 <TD width=15% BGCOLOR=#FBF5EF>
\r
36651 <B>PSU_LPD_XPPU_CFG_MASTER_ID07_MID</B>
\r
36653 <TD width=15% BGCOLOR=#FBF5EF>
\r
36656 <TD width=10% BGCOLOR=#FBF5EF>
\r
36659 <TD width=10% BGCOLOR=#FBF5EF>
\r
36662 <TD width=15% BGCOLOR=#FBF5EF>
\r
36665 <TD width=35% BGCOLOR=#FBF5EF>
\r
36666 <B>Predefined Master ID for A53 Core 3</B>
\r
36669 <TR valign="top">
\r
36670 <TD width=15% BGCOLOR=#C0C0C0>
\r
36671 <B>PSU_LPD_XPPU_CFG_MASTER_ID07@0XFF98011C</B>
\r
36673 <TD width=15% BGCOLOR=#C0C0C0>
\r
36676 <TD width=10% BGCOLOR=#C0C0C0>
\r
36679 <TD width=10% BGCOLOR=#C0C0C0>
\r
36682 <TD width=15% BGCOLOR=#C0C0C0>
\r
36685 <TD width=35% BGCOLOR=#C0C0C0>
\r
36686 <B>Master ID 07 Register</B>
\r
36691 <H2><a name="MASTER_ID08">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID08</a></H2>
\r
36692 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36693 <TR valign="top">
\r
36694 <TD width=15% BGCOLOR=#FFFF00>
\r
36695 <B>Register Name</B>
\r
36697 <TD width=15% BGCOLOR=#FFFF00>
\r
36700 <TD width=10% BGCOLOR=#FFFF00>
\r
36703 <TD width=10% BGCOLOR=#FFFF00>
\r
36706 <TD width=15% BGCOLOR=#FFFF00>
\r
36707 <B>Reset Value</B>
\r
36709 <TD width=35% BGCOLOR=#FFFF00>
\r
36710 <B>Description</B>
\r
36713 <TR valign="top">
\r
36714 <TD width=15% BGCOLOR=#FBF5EF>
\r
36715 <B>MASTER_ID08</B>
\r
36717 <TD width=15% BGCOLOR=#FBF5EF>
\r
36718 <B>0XFF980120</B>
\r
36720 <TD width=10% BGCOLOR=#FBF5EF>
\r
36723 <TD width=10% BGCOLOR=#FBF5EF>
\r
36726 <TD width=15% BGCOLOR=#FBF5EF>
\r
36727 <B>0x00000000</B>
\r
36729 <TD width=35% BGCOLOR=#FBF5EF>
\r
36735 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36736 <TR valign="top">
\r
36737 <TD width=15% BGCOLOR=#C0FFC0>
\r
36738 <B>Field Name</B>
\r
36740 <TD width=15% BGCOLOR=#C0FFC0>
\r
36743 <TD width=10% BGCOLOR=#C0FFC0>
\r
36746 <TD width=10% BGCOLOR=#C0FFC0>
\r
36749 <TD width=15% BGCOLOR=#C0FFC0>
\r
36750 <B>Shifted Value</B>
\r
36752 <TD width=35% BGCOLOR=#C0FFC0>
\r
36753 <B>Description</B>
\r
36756 <TR valign="top">
\r
36757 <TD width=15% BGCOLOR=#FBF5EF>
\r
36758 <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP</B>
\r
36760 <TD width=15% BGCOLOR=#FBF5EF>
\r
36763 <TD width=10% BGCOLOR=#FBF5EF>
\r
36766 <TD width=10% BGCOLOR=#FBF5EF>
\r
36769 <TD width=15% BGCOLOR=#FBF5EF>
\r
36772 <TD width=35% BGCOLOR=#FBF5EF>
\r
36773 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36776 <TR valign="top">
\r
36777 <TD width=15% BGCOLOR=#FBF5EF>
\r
36778 <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR</B>
\r
36780 <TD width=15% BGCOLOR=#FBF5EF>
\r
36783 <TD width=10% BGCOLOR=#FBF5EF>
\r
36786 <TD width=10% BGCOLOR=#FBF5EF>
\r
36789 <TD width=15% BGCOLOR=#FBF5EF>
\r
36792 <TD width=35% BGCOLOR=#FBF5EF>
\r
36793 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36796 <TR valign="top">
\r
36797 <TD width=15% BGCOLOR=#FBF5EF>
\r
36798 <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM</B>
\r
36800 <TD width=15% BGCOLOR=#FBF5EF>
\r
36803 <TD width=10% BGCOLOR=#FBF5EF>
\r
36806 <TD width=10% BGCOLOR=#FBF5EF>
\r
36809 <TD width=15% BGCOLOR=#FBF5EF>
\r
36812 <TD width=35% BGCOLOR=#FBF5EF>
\r
36813 <B>Mask to be applied before comparing</B>
\r
36816 <TR valign="top">
\r
36817 <TD width=15% BGCOLOR=#FBF5EF>
\r
36818 <B>PSU_LPD_XPPU_CFG_MASTER_ID08_MID</B>
\r
36820 <TD width=15% BGCOLOR=#FBF5EF>
\r
36823 <TD width=10% BGCOLOR=#FBF5EF>
\r
36826 <TD width=10% BGCOLOR=#FBF5EF>
\r
36829 <TD width=15% BGCOLOR=#FBF5EF>
\r
36832 <TD width=35% BGCOLOR=#FBF5EF>
\r
36833 <B>Programmable Master ID</B>
\r
36836 <TR valign="top">
\r
36837 <TD width=15% BGCOLOR=#C0C0C0>
\r
36838 <B>PSU_LPD_XPPU_CFG_MASTER_ID08@0XFF980120</B>
\r
36840 <TD width=15% BGCOLOR=#C0C0C0>
\r
36843 <TD width=10% BGCOLOR=#C0C0C0>
\r
36846 <TD width=10% BGCOLOR=#C0C0C0>
\r
36849 <TD width=15% BGCOLOR=#C0C0C0>
\r
36852 <TD width=35% BGCOLOR=#C0C0C0>
\r
36853 <B>Master ID 08 Register</B>
\r
36858 <H2><a name="MASTER_ID09">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID09</a></H2>
\r
36859 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36860 <TR valign="top">
\r
36861 <TD width=15% BGCOLOR=#FFFF00>
\r
36862 <B>Register Name</B>
\r
36864 <TD width=15% BGCOLOR=#FFFF00>
\r
36867 <TD width=10% BGCOLOR=#FFFF00>
\r
36870 <TD width=10% BGCOLOR=#FFFF00>
\r
36873 <TD width=15% BGCOLOR=#FFFF00>
\r
36874 <B>Reset Value</B>
\r
36876 <TD width=35% BGCOLOR=#FFFF00>
\r
36877 <B>Description</B>
\r
36880 <TR valign="top">
\r
36881 <TD width=15% BGCOLOR=#FBF5EF>
\r
36882 <B>MASTER_ID09</B>
\r
36884 <TD width=15% BGCOLOR=#FBF5EF>
\r
36885 <B>0XFF980124</B>
\r
36887 <TD width=10% BGCOLOR=#FBF5EF>
\r
36890 <TD width=10% BGCOLOR=#FBF5EF>
\r
36893 <TD width=15% BGCOLOR=#FBF5EF>
\r
36894 <B>0x00000000</B>
\r
36896 <TD width=35% BGCOLOR=#FBF5EF>
\r
36902 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
36903 <TR valign="top">
\r
36904 <TD width=15% BGCOLOR=#C0FFC0>
\r
36905 <B>Field Name</B>
\r
36907 <TD width=15% BGCOLOR=#C0FFC0>
\r
36910 <TD width=10% BGCOLOR=#C0FFC0>
\r
36913 <TD width=10% BGCOLOR=#C0FFC0>
\r
36916 <TD width=15% BGCOLOR=#C0FFC0>
\r
36917 <B>Shifted Value</B>
\r
36919 <TD width=35% BGCOLOR=#C0FFC0>
\r
36920 <B>Description</B>
\r
36923 <TR valign="top">
\r
36924 <TD width=15% BGCOLOR=#FBF5EF>
\r
36925 <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP</B>
\r
36927 <TD width=15% BGCOLOR=#FBF5EF>
\r
36930 <TD width=10% BGCOLOR=#FBF5EF>
\r
36933 <TD width=10% BGCOLOR=#FBF5EF>
\r
36936 <TD width=15% BGCOLOR=#FBF5EF>
\r
36939 <TD width=35% BGCOLOR=#FBF5EF>
\r
36940 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
36943 <TR valign="top">
\r
36944 <TD width=15% BGCOLOR=#FBF5EF>
\r
36945 <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR</B>
\r
36947 <TD width=15% BGCOLOR=#FBF5EF>
\r
36950 <TD width=10% BGCOLOR=#FBF5EF>
\r
36953 <TD width=10% BGCOLOR=#FBF5EF>
\r
36956 <TD width=15% BGCOLOR=#FBF5EF>
\r
36959 <TD width=35% BGCOLOR=#FBF5EF>
\r
36960 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
36963 <TR valign="top">
\r
36964 <TD width=15% BGCOLOR=#FBF5EF>
\r
36965 <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM</B>
\r
36967 <TD width=15% BGCOLOR=#FBF5EF>
\r
36970 <TD width=10% BGCOLOR=#FBF5EF>
\r
36973 <TD width=10% BGCOLOR=#FBF5EF>
\r
36976 <TD width=15% BGCOLOR=#FBF5EF>
\r
36979 <TD width=35% BGCOLOR=#FBF5EF>
\r
36980 <B>Mask to be applied before comparing</B>
\r
36983 <TR valign="top">
\r
36984 <TD width=15% BGCOLOR=#FBF5EF>
\r
36985 <B>PSU_LPD_XPPU_CFG_MASTER_ID09_MID</B>
\r
36987 <TD width=15% BGCOLOR=#FBF5EF>
\r
36990 <TD width=10% BGCOLOR=#FBF5EF>
\r
36993 <TD width=10% BGCOLOR=#FBF5EF>
\r
36996 <TD width=15% BGCOLOR=#FBF5EF>
\r
36999 <TD width=35% BGCOLOR=#FBF5EF>
\r
37000 <B>Programmable Master ID</B>
\r
37003 <TR valign="top">
\r
37004 <TD width=15% BGCOLOR=#C0C0C0>
\r
37005 <B>PSU_LPD_XPPU_CFG_MASTER_ID09@0XFF980124</B>
\r
37007 <TD width=15% BGCOLOR=#C0C0C0>
\r
37010 <TD width=10% BGCOLOR=#C0C0C0>
\r
37013 <TD width=10% BGCOLOR=#C0C0C0>
\r
37016 <TD width=15% BGCOLOR=#C0C0C0>
\r
37019 <TD width=35% BGCOLOR=#C0C0C0>
\r
37020 <B>Master ID 09 Register</B>
\r
37025 <H2><a name="MASTER_ID10">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID10</a></H2>
\r
37026 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37027 <TR valign="top">
\r
37028 <TD width=15% BGCOLOR=#FFFF00>
\r
37029 <B>Register Name</B>
\r
37031 <TD width=15% BGCOLOR=#FFFF00>
\r
37034 <TD width=10% BGCOLOR=#FFFF00>
\r
37037 <TD width=10% BGCOLOR=#FFFF00>
\r
37040 <TD width=15% BGCOLOR=#FFFF00>
\r
37041 <B>Reset Value</B>
\r
37043 <TD width=35% BGCOLOR=#FFFF00>
\r
37044 <B>Description</B>
\r
37047 <TR valign="top">
\r
37048 <TD width=15% BGCOLOR=#FBF5EF>
\r
37049 <B>MASTER_ID10</B>
\r
37051 <TD width=15% BGCOLOR=#FBF5EF>
\r
37052 <B>0XFF980128</B>
\r
37054 <TD width=10% BGCOLOR=#FBF5EF>
\r
37057 <TD width=10% BGCOLOR=#FBF5EF>
\r
37060 <TD width=15% BGCOLOR=#FBF5EF>
\r
37061 <B>0x00000000</B>
\r
37063 <TD width=35% BGCOLOR=#FBF5EF>
\r
37069 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37070 <TR valign="top">
\r
37071 <TD width=15% BGCOLOR=#C0FFC0>
\r
37072 <B>Field Name</B>
\r
37074 <TD width=15% BGCOLOR=#C0FFC0>
\r
37077 <TD width=10% BGCOLOR=#C0FFC0>
\r
37080 <TD width=10% BGCOLOR=#C0FFC0>
\r
37083 <TD width=15% BGCOLOR=#C0FFC0>
\r
37084 <B>Shifted Value</B>
\r
37086 <TD width=35% BGCOLOR=#C0FFC0>
\r
37087 <B>Description</B>
\r
37090 <TR valign="top">
\r
37091 <TD width=15% BGCOLOR=#FBF5EF>
\r
37092 <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP</B>
\r
37094 <TD width=15% BGCOLOR=#FBF5EF>
\r
37097 <TD width=10% BGCOLOR=#FBF5EF>
\r
37100 <TD width=10% BGCOLOR=#FBF5EF>
\r
37103 <TD width=15% BGCOLOR=#FBF5EF>
\r
37106 <TD width=35% BGCOLOR=#FBF5EF>
\r
37107 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37110 <TR valign="top">
\r
37111 <TD width=15% BGCOLOR=#FBF5EF>
\r
37112 <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR</B>
\r
37114 <TD width=15% BGCOLOR=#FBF5EF>
\r
37117 <TD width=10% BGCOLOR=#FBF5EF>
\r
37120 <TD width=10% BGCOLOR=#FBF5EF>
\r
37123 <TD width=15% BGCOLOR=#FBF5EF>
\r
37126 <TD width=35% BGCOLOR=#FBF5EF>
\r
37127 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37130 <TR valign="top">
\r
37131 <TD width=15% BGCOLOR=#FBF5EF>
\r
37132 <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM</B>
\r
37134 <TD width=15% BGCOLOR=#FBF5EF>
\r
37137 <TD width=10% BGCOLOR=#FBF5EF>
\r
37140 <TD width=10% BGCOLOR=#FBF5EF>
\r
37143 <TD width=15% BGCOLOR=#FBF5EF>
\r
37146 <TD width=35% BGCOLOR=#FBF5EF>
\r
37147 <B>Mask to be applied before comparing</B>
\r
37150 <TR valign="top">
\r
37151 <TD width=15% BGCOLOR=#FBF5EF>
\r
37152 <B>PSU_LPD_XPPU_CFG_MASTER_ID10_MID</B>
\r
37154 <TD width=15% BGCOLOR=#FBF5EF>
\r
37157 <TD width=10% BGCOLOR=#FBF5EF>
\r
37160 <TD width=10% BGCOLOR=#FBF5EF>
\r
37163 <TD width=15% BGCOLOR=#FBF5EF>
\r
37166 <TD width=35% BGCOLOR=#FBF5EF>
\r
37167 <B>Programmable Master ID</B>
\r
37170 <TR valign="top">
\r
37171 <TD width=15% BGCOLOR=#C0C0C0>
\r
37172 <B>PSU_LPD_XPPU_CFG_MASTER_ID10@0XFF980128</B>
\r
37174 <TD width=15% BGCOLOR=#C0C0C0>
\r
37177 <TD width=10% BGCOLOR=#C0C0C0>
\r
37180 <TD width=10% BGCOLOR=#C0C0C0>
\r
37183 <TD width=15% BGCOLOR=#C0C0C0>
\r
37186 <TD width=35% BGCOLOR=#C0C0C0>
\r
37187 <B>Master ID 10 Register</B>
\r
37192 <H2><a name="MASTER_ID11">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID11</a></H2>
\r
37193 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37194 <TR valign="top">
\r
37195 <TD width=15% BGCOLOR=#FFFF00>
\r
37196 <B>Register Name</B>
\r
37198 <TD width=15% BGCOLOR=#FFFF00>
\r
37201 <TD width=10% BGCOLOR=#FFFF00>
\r
37204 <TD width=10% BGCOLOR=#FFFF00>
\r
37207 <TD width=15% BGCOLOR=#FFFF00>
\r
37208 <B>Reset Value</B>
\r
37210 <TD width=35% BGCOLOR=#FFFF00>
\r
37211 <B>Description</B>
\r
37214 <TR valign="top">
\r
37215 <TD width=15% BGCOLOR=#FBF5EF>
\r
37216 <B>MASTER_ID11</B>
\r
37218 <TD width=15% BGCOLOR=#FBF5EF>
\r
37219 <B>0XFF98012C</B>
\r
37221 <TD width=10% BGCOLOR=#FBF5EF>
\r
37224 <TD width=10% BGCOLOR=#FBF5EF>
\r
37227 <TD width=15% BGCOLOR=#FBF5EF>
\r
37228 <B>0x00000000</B>
\r
37230 <TD width=35% BGCOLOR=#FBF5EF>
\r
37236 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37237 <TR valign="top">
\r
37238 <TD width=15% BGCOLOR=#C0FFC0>
\r
37239 <B>Field Name</B>
\r
37241 <TD width=15% BGCOLOR=#C0FFC0>
\r
37244 <TD width=10% BGCOLOR=#C0FFC0>
\r
37247 <TD width=10% BGCOLOR=#C0FFC0>
\r
37250 <TD width=15% BGCOLOR=#C0FFC0>
\r
37251 <B>Shifted Value</B>
\r
37253 <TD width=35% BGCOLOR=#C0FFC0>
\r
37254 <B>Description</B>
\r
37257 <TR valign="top">
\r
37258 <TD width=15% BGCOLOR=#FBF5EF>
\r
37259 <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP</B>
\r
37261 <TD width=15% BGCOLOR=#FBF5EF>
\r
37264 <TD width=10% BGCOLOR=#FBF5EF>
\r
37267 <TD width=10% BGCOLOR=#FBF5EF>
\r
37270 <TD width=15% BGCOLOR=#FBF5EF>
\r
37273 <TD width=35% BGCOLOR=#FBF5EF>
\r
37274 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37277 <TR valign="top">
\r
37278 <TD width=15% BGCOLOR=#FBF5EF>
\r
37279 <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR</B>
\r
37281 <TD width=15% BGCOLOR=#FBF5EF>
\r
37284 <TD width=10% BGCOLOR=#FBF5EF>
\r
37287 <TD width=10% BGCOLOR=#FBF5EF>
\r
37290 <TD width=15% BGCOLOR=#FBF5EF>
\r
37293 <TD width=35% BGCOLOR=#FBF5EF>
\r
37294 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37297 <TR valign="top">
\r
37298 <TD width=15% BGCOLOR=#FBF5EF>
\r
37299 <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM</B>
\r
37301 <TD width=15% BGCOLOR=#FBF5EF>
\r
37304 <TD width=10% BGCOLOR=#FBF5EF>
\r
37307 <TD width=10% BGCOLOR=#FBF5EF>
\r
37310 <TD width=15% BGCOLOR=#FBF5EF>
\r
37313 <TD width=35% BGCOLOR=#FBF5EF>
\r
37314 <B>Mask to be applied before comparing</B>
\r
37317 <TR valign="top">
\r
37318 <TD width=15% BGCOLOR=#FBF5EF>
\r
37319 <B>PSU_LPD_XPPU_CFG_MASTER_ID11_MID</B>
\r
37321 <TD width=15% BGCOLOR=#FBF5EF>
\r
37324 <TD width=10% BGCOLOR=#FBF5EF>
\r
37327 <TD width=10% BGCOLOR=#FBF5EF>
\r
37330 <TD width=15% BGCOLOR=#FBF5EF>
\r
37333 <TD width=35% BGCOLOR=#FBF5EF>
\r
37334 <B>Programmable Master ID</B>
\r
37337 <TR valign="top">
\r
37338 <TD width=15% BGCOLOR=#C0C0C0>
\r
37339 <B>PSU_LPD_XPPU_CFG_MASTER_ID11@0XFF98012C</B>
\r
37341 <TD width=15% BGCOLOR=#C0C0C0>
\r
37344 <TD width=10% BGCOLOR=#C0C0C0>
\r
37347 <TD width=10% BGCOLOR=#C0C0C0>
\r
37350 <TD width=15% BGCOLOR=#C0C0C0>
\r
37353 <TD width=35% BGCOLOR=#C0C0C0>
\r
37354 <B>Master ID 11 Register</B>
\r
37359 <H2><a name="MASTER_ID12">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID12</a></H2>
\r
37360 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37361 <TR valign="top">
\r
37362 <TD width=15% BGCOLOR=#FFFF00>
\r
37363 <B>Register Name</B>
\r
37365 <TD width=15% BGCOLOR=#FFFF00>
\r
37368 <TD width=10% BGCOLOR=#FFFF00>
\r
37371 <TD width=10% BGCOLOR=#FFFF00>
\r
37374 <TD width=15% BGCOLOR=#FFFF00>
\r
37375 <B>Reset Value</B>
\r
37377 <TD width=35% BGCOLOR=#FFFF00>
\r
37378 <B>Description</B>
\r
37381 <TR valign="top">
\r
37382 <TD width=15% BGCOLOR=#FBF5EF>
\r
37383 <B>MASTER_ID12</B>
\r
37385 <TD width=15% BGCOLOR=#FBF5EF>
\r
37386 <B>0XFF980130</B>
\r
37388 <TD width=10% BGCOLOR=#FBF5EF>
\r
37391 <TD width=10% BGCOLOR=#FBF5EF>
\r
37394 <TD width=15% BGCOLOR=#FBF5EF>
\r
37395 <B>0x00000000</B>
\r
37397 <TD width=35% BGCOLOR=#FBF5EF>
\r
37403 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37404 <TR valign="top">
\r
37405 <TD width=15% BGCOLOR=#C0FFC0>
\r
37406 <B>Field Name</B>
\r
37408 <TD width=15% BGCOLOR=#C0FFC0>
\r
37411 <TD width=10% BGCOLOR=#C0FFC0>
\r
37414 <TD width=10% BGCOLOR=#C0FFC0>
\r
37417 <TD width=15% BGCOLOR=#C0FFC0>
\r
37418 <B>Shifted Value</B>
\r
37420 <TD width=35% BGCOLOR=#C0FFC0>
\r
37421 <B>Description</B>
\r
37424 <TR valign="top">
\r
37425 <TD width=15% BGCOLOR=#FBF5EF>
\r
37426 <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP</B>
\r
37428 <TD width=15% BGCOLOR=#FBF5EF>
\r
37431 <TD width=10% BGCOLOR=#FBF5EF>
\r
37434 <TD width=10% BGCOLOR=#FBF5EF>
\r
37437 <TD width=15% BGCOLOR=#FBF5EF>
\r
37440 <TD width=35% BGCOLOR=#FBF5EF>
\r
37441 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37444 <TR valign="top">
\r
37445 <TD width=15% BGCOLOR=#FBF5EF>
\r
37446 <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR</B>
\r
37448 <TD width=15% BGCOLOR=#FBF5EF>
\r
37451 <TD width=10% BGCOLOR=#FBF5EF>
\r
37454 <TD width=10% BGCOLOR=#FBF5EF>
\r
37457 <TD width=15% BGCOLOR=#FBF5EF>
\r
37460 <TD width=35% BGCOLOR=#FBF5EF>
\r
37461 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37464 <TR valign="top">
\r
37465 <TD width=15% BGCOLOR=#FBF5EF>
\r
37466 <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM</B>
\r
37468 <TD width=15% BGCOLOR=#FBF5EF>
\r
37471 <TD width=10% BGCOLOR=#FBF5EF>
\r
37474 <TD width=10% BGCOLOR=#FBF5EF>
\r
37477 <TD width=15% BGCOLOR=#FBF5EF>
\r
37480 <TD width=35% BGCOLOR=#FBF5EF>
\r
37481 <B>Mask to be applied before comparing</B>
\r
37484 <TR valign="top">
\r
37485 <TD width=15% BGCOLOR=#FBF5EF>
\r
37486 <B>PSU_LPD_XPPU_CFG_MASTER_ID12_MID</B>
\r
37488 <TD width=15% BGCOLOR=#FBF5EF>
\r
37491 <TD width=10% BGCOLOR=#FBF5EF>
\r
37494 <TD width=10% BGCOLOR=#FBF5EF>
\r
37497 <TD width=15% BGCOLOR=#FBF5EF>
\r
37500 <TD width=35% BGCOLOR=#FBF5EF>
\r
37501 <B>Programmable Master ID</B>
\r
37504 <TR valign="top">
\r
37505 <TD width=15% BGCOLOR=#C0C0C0>
\r
37506 <B>PSU_LPD_XPPU_CFG_MASTER_ID12@0XFF980130</B>
\r
37508 <TD width=15% BGCOLOR=#C0C0C0>
\r
37511 <TD width=10% BGCOLOR=#C0C0C0>
\r
37514 <TD width=10% BGCOLOR=#C0C0C0>
\r
37517 <TD width=15% BGCOLOR=#C0C0C0>
\r
37520 <TD width=35% BGCOLOR=#C0C0C0>
\r
37521 <B>Master ID 12 Register</B>
\r
37526 <H2><a name="MASTER_ID13">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID13</a></H2>
\r
37527 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37528 <TR valign="top">
\r
37529 <TD width=15% BGCOLOR=#FFFF00>
\r
37530 <B>Register Name</B>
\r
37532 <TD width=15% BGCOLOR=#FFFF00>
\r
37535 <TD width=10% BGCOLOR=#FFFF00>
\r
37538 <TD width=10% BGCOLOR=#FFFF00>
\r
37541 <TD width=15% BGCOLOR=#FFFF00>
\r
37542 <B>Reset Value</B>
\r
37544 <TD width=35% BGCOLOR=#FFFF00>
\r
37545 <B>Description</B>
\r
37548 <TR valign="top">
\r
37549 <TD width=15% BGCOLOR=#FBF5EF>
\r
37550 <B>MASTER_ID13</B>
\r
37552 <TD width=15% BGCOLOR=#FBF5EF>
\r
37553 <B>0XFF980134</B>
\r
37555 <TD width=10% BGCOLOR=#FBF5EF>
\r
37558 <TD width=10% BGCOLOR=#FBF5EF>
\r
37561 <TD width=15% BGCOLOR=#FBF5EF>
\r
37562 <B>0x00000000</B>
\r
37564 <TD width=35% BGCOLOR=#FBF5EF>
\r
37570 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37571 <TR valign="top">
\r
37572 <TD width=15% BGCOLOR=#C0FFC0>
\r
37573 <B>Field Name</B>
\r
37575 <TD width=15% BGCOLOR=#C0FFC0>
\r
37578 <TD width=10% BGCOLOR=#C0FFC0>
\r
37581 <TD width=10% BGCOLOR=#C0FFC0>
\r
37584 <TD width=15% BGCOLOR=#C0FFC0>
\r
37585 <B>Shifted Value</B>
\r
37587 <TD width=35% BGCOLOR=#C0FFC0>
\r
37588 <B>Description</B>
\r
37591 <TR valign="top">
\r
37592 <TD width=15% BGCOLOR=#FBF5EF>
\r
37593 <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP</B>
\r
37595 <TD width=15% BGCOLOR=#FBF5EF>
\r
37598 <TD width=10% BGCOLOR=#FBF5EF>
\r
37601 <TD width=10% BGCOLOR=#FBF5EF>
\r
37604 <TD width=15% BGCOLOR=#FBF5EF>
\r
37607 <TD width=35% BGCOLOR=#FBF5EF>
\r
37608 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37611 <TR valign="top">
\r
37612 <TD width=15% BGCOLOR=#FBF5EF>
\r
37613 <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR</B>
\r
37615 <TD width=15% BGCOLOR=#FBF5EF>
\r
37618 <TD width=10% BGCOLOR=#FBF5EF>
\r
37621 <TD width=10% BGCOLOR=#FBF5EF>
\r
37624 <TD width=15% BGCOLOR=#FBF5EF>
\r
37627 <TD width=35% BGCOLOR=#FBF5EF>
\r
37628 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37631 <TR valign="top">
\r
37632 <TD width=15% BGCOLOR=#FBF5EF>
\r
37633 <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM</B>
\r
37635 <TD width=15% BGCOLOR=#FBF5EF>
\r
37638 <TD width=10% BGCOLOR=#FBF5EF>
\r
37641 <TD width=10% BGCOLOR=#FBF5EF>
\r
37644 <TD width=15% BGCOLOR=#FBF5EF>
\r
37647 <TD width=35% BGCOLOR=#FBF5EF>
\r
37648 <B>Mask to be applied before comparing</B>
\r
37651 <TR valign="top">
\r
37652 <TD width=15% BGCOLOR=#FBF5EF>
\r
37653 <B>PSU_LPD_XPPU_CFG_MASTER_ID13_MID</B>
\r
37655 <TD width=15% BGCOLOR=#FBF5EF>
\r
37658 <TD width=10% BGCOLOR=#FBF5EF>
\r
37661 <TD width=10% BGCOLOR=#FBF5EF>
\r
37664 <TD width=15% BGCOLOR=#FBF5EF>
\r
37667 <TD width=35% BGCOLOR=#FBF5EF>
\r
37668 <B>Programmable Master ID</B>
\r
37671 <TR valign="top">
\r
37672 <TD width=15% BGCOLOR=#C0C0C0>
\r
37673 <B>PSU_LPD_XPPU_CFG_MASTER_ID13@0XFF980134</B>
\r
37675 <TD width=15% BGCOLOR=#C0C0C0>
\r
37678 <TD width=10% BGCOLOR=#C0C0C0>
\r
37681 <TD width=10% BGCOLOR=#C0C0C0>
\r
37684 <TD width=15% BGCOLOR=#C0C0C0>
\r
37687 <TD width=35% BGCOLOR=#C0C0C0>
\r
37688 <B>Master ID 13 Register</B>
\r
37693 <H2><a name="MASTER_ID14">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID14</a></H2>
\r
37694 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37695 <TR valign="top">
\r
37696 <TD width=15% BGCOLOR=#FFFF00>
\r
37697 <B>Register Name</B>
\r
37699 <TD width=15% BGCOLOR=#FFFF00>
\r
37702 <TD width=10% BGCOLOR=#FFFF00>
\r
37705 <TD width=10% BGCOLOR=#FFFF00>
\r
37708 <TD width=15% BGCOLOR=#FFFF00>
\r
37709 <B>Reset Value</B>
\r
37711 <TD width=35% BGCOLOR=#FFFF00>
\r
37712 <B>Description</B>
\r
37715 <TR valign="top">
\r
37716 <TD width=15% BGCOLOR=#FBF5EF>
\r
37717 <B>MASTER_ID14</B>
\r
37719 <TD width=15% BGCOLOR=#FBF5EF>
\r
37720 <B>0XFF980138</B>
\r
37722 <TD width=10% BGCOLOR=#FBF5EF>
\r
37725 <TD width=10% BGCOLOR=#FBF5EF>
\r
37728 <TD width=15% BGCOLOR=#FBF5EF>
\r
37729 <B>0x00000000</B>
\r
37731 <TD width=35% BGCOLOR=#FBF5EF>
\r
37737 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37738 <TR valign="top">
\r
37739 <TD width=15% BGCOLOR=#C0FFC0>
\r
37740 <B>Field Name</B>
\r
37742 <TD width=15% BGCOLOR=#C0FFC0>
\r
37745 <TD width=10% BGCOLOR=#C0FFC0>
\r
37748 <TD width=10% BGCOLOR=#C0FFC0>
\r
37751 <TD width=15% BGCOLOR=#C0FFC0>
\r
37752 <B>Shifted Value</B>
\r
37754 <TD width=35% BGCOLOR=#C0FFC0>
\r
37755 <B>Description</B>
\r
37758 <TR valign="top">
\r
37759 <TD width=15% BGCOLOR=#FBF5EF>
\r
37760 <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP</B>
\r
37762 <TD width=15% BGCOLOR=#FBF5EF>
\r
37765 <TD width=10% BGCOLOR=#FBF5EF>
\r
37768 <TD width=10% BGCOLOR=#FBF5EF>
\r
37771 <TD width=15% BGCOLOR=#FBF5EF>
\r
37774 <TD width=35% BGCOLOR=#FBF5EF>
\r
37775 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37778 <TR valign="top">
\r
37779 <TD width=15% BGCOLOR=#FBF5EF>
\r
37780 <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR</B>
\r
37782 <TD width=15% BGCOLOR=#FBF5EF>
\r
37785 <TD width=10% BGCOLOR=#FBF5EF>
\r
37788 <TD width=10% BGCOLOR=#FBF5EF>
\r
37791 <TD width=15% BGCOLOR=#FBF5EF>
\r
37794 <TD width=35% BGCOLOR=#FBF5EF>
\r
37795 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37798 <TR valign="top">
\r
37799 <TD width=15% BGCOLOR=#FBF5EF>
\r
37800 <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM</B>
\r
37802 <TD width=15% BGCOLOR=#FBF5EF>
\r
37805 <TD width=10% BGCOLOR=#FBF5EF>
\r
37808 <TD width=10% BGCOLOR=#FBF5EF>
\r
37811 <TD width=15% BGCOLOR=#FBF5EF>
\r
37814 <TD width=35% BGCOLOR=#FBF5EF>
\r
37815 <B>Mask to be applied before comparing</B>
\r
37818 <TR valign="top">
\r
37819 <TD width=15% BGCOLOR=#FBF5EF>
\r
37820 <B>PSU_LPD_XPPU_CFG_MASTER_ID14_MID</B>
\r
37822 <TD width=15% BGCOLOR=#FBF5EF>
\r
37825 <TD width=10% BGCOLOR=#FBF5EF>
\r
37828 <TD width=10% BGCOLOR=#FBF5EF>
\r
37831 <TD width=15% BGCOLOR=#FBF5EF>
\r
37834 <TD width=35% BGCOLOR=#FBF5EF>
\r
37835 <B>Programmable Master ID</B>
\r
37838 <TR valign="top">
\r
37839 <TD width=15% BGCOLOR=#C0C0C0>
\r
37840 <B>PSU_LPD_XPPU_CFG_MASTER_ID14@0XFF980138</B>
\r
37842 <TD width=15% BGCOLOR=#C0C0C0>
\r
37845 <TD width=10% BGCOLOR=#C0C0C0>
\r
37848 <TD width=10% BGCOLOR=#C0C0C0>
\r
37851 <TD width=15% BGCOLOR=#C0C0C0>
\r
37854 <TD width=35% BGCOLOR=#C0C0C0>
\r
37855 <B>Master ID 14 Register</B>
\r
37860 <H2><a name="MASTER_ID15">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID15</a></H2>
\r
37861 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37862 <TR valign="top">
\r
37863 <TD width=15% BGCOLOR=#FFFF00>
\r
37864 <B>Register Name</B>
\r
37866 <TD width=15% BGCOLOR=#FFFF00>
\r
37869 <TD width=10% BGCOLOR=#FFFF00>
\r
37872 <TD width=10% BGCOLOR=#FFFF00>
\r
37875 <TD width=15% BGCOLOR=#FFFF00>
\r
37876 <B>Reset Value</B>
\r
37878 <TD width=35% BGCOLOR=#FFFF00>
\r
37879 <B>Description</B>
\r
37882 <TR valign="top">
\r
37883 <TD width=15% BGCOLOR=#FBF5EF>
\r
37884 <B>MASTER_ID15</B>
\r
37886 <TD width=15% BGCOLOR=#FBF5EF>
\r
37887 <B>0XFF98013C</B>
\r
37889 <TD width=10% BGCOLOR=#FBF5EF>
\r
37892 <TD width=10% BGCOLOR=#FBF5EF>
\r
37895 <TD width=15% BGCOLOR=#FBF5EF>
\r
37896 <B>0x00000000</B>
\r
37898 <TD width=35% BGCOLOR=#FBF5EF>
\r
37904 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
37905 <TR valign="top">
\r
37906 <TD width=15% BGCOLOR=#C0FFC0>
\r
37907 <B>Field Name</B>
\r
37909 <TD width=15% BGCOLOR=#C0FFC0>
\r
37912 <TD width=10% BGCOLOR=#C0FFC0>
\r
37915 <TD width=10% BGCOLOR=#C0FFC0>
\r
37918 <TD width=15% BGCOLOR=#C0FFC0>
\r
37919 <B>Shifted Value</B>
\r
37921 <TD width=35% BGCOLOR=#C0FFC0>
\r
37922 <B>Description</B>
\r
37925 <TR valign="top">
\r
37926 <TD width=15% BGCOLOR=#FBF5EF>
\r
37927 <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP</B>
\r
37929 <TD width=15% BGCOLOR=#FBF5EF>
\r
37932 <TD width=10% BGCOLOR=#FBF5EF>
\r
37935 <TD width=10% BGCOLOR=#FBF5EF>
\r
37938 <TD width=15% BGCOLOR=#FBF5EF>
\r
37941 <TD width=35% BGCOLOR=#FBF5EF>
\r
37942 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
37945 <TR valign="top">
\r
37946 <TD width=15% BGCOLOR=#FBF5EF>
\r
37947 <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR</B>
\r
37949 <TD width=15% BGCOLOR=#FBF5EF>
\r
37952 <TD width=10% BGCOLOR=#FBF5EF>
\r
37955 <TD width=10% BGCOLOR=#FBF5EF>
\r
37958 <TD width=15% BGCOLOR=#FBF5EF>
\r
37961 <TD width=35% BGCOLOR=#FBF5EF>
\r
37962 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
37965 <TR valign="top">
\r
37966 <TD width=15% BGCOLOR=#FBF5EF>
\r
37967 <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM</B>
\r
37969 <TD width=15% BGCOLOR=#FBF5EF>
\r
37972 <TD width=10% BGCOLOR=#FBF5EF>
\r
37975 <TD width=10% BGCOLOR=#FBF5EF>
\r
37978 <TD width=15% BGCOLOR=#FBF5EF>
\r
37981 <TD width=35% BGCOLOR=#FBF5EF>
\r
37982 <B>Mask to be applied before comparing</B>
\r
37985 <TR valign="top">
\r
37986 <TD width=15% BGCOLOR=#FBF5EF>
\r
37987 <B>PSU_LPD_XPPU_CFG_MASTER_ID15_MID</B>
\r
37989 <TD width=15% BGCOLOR=#FBF5EF>
\r
37992 <TD width=10% BGCOLOR=#FBF5EF>
\r
37995 <TD width=10% BGCOLOR=#FBF5EF>
\r
37998 <TD width=15% BGCOLOR=#FBF5EF>
\r
38001 <TD width=35% BGCOLOR=#FBF5EF>
\r
38002 <B>Programmable Master ID</B>
\r
38005 <TR valign="top">
\r
38006 <TD width=15% BGCOLOR=#C0C0C0>
\r
38007 <B>PSU_LPD_XPPU_CFG_MASTER_ID15@0XFF98013C</B>
\r
38009 <TD width=15% BGCOLOR=#C0C0C0>
\r
38012 <TD width=10% BGCOLOR=#C0C0C0>
\r
38015 <TD width=10% BGCOLOR=#C0C0C0>
\r
38018 <TD width=15% BGCOLOR=#C0C0C0>
\r
38021 <TD width=35% BGCOLOR=#C0C0C0>
\r
38022 <B>Master ID 15 Register</B>
\r
38027 <H2><a name="MASTER_ID16">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID16</a></H2>
\r
38028 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38029 <TR valign="top">
\r
38030 <TD width=15% BGCOLOR=#FFFF00>
\r
38031 <B>Register Name</B>
\r
38033 <TD width=15% BGCOLOR=#FFFF00>
\r
38036 <TD width=10% BGCOLOR=#FFFF00>
\r
38039 <TD width=10% BGCOLOR=#FFFF00>
\r
38042 <TD width=15% BGCOLOR=#FFFF00>
\r
38043 <B>Reset Value</B>
\r
38045 <TD width=35% BGCOLOR=#FFFF00>
\r
38046 <B>Description</B>
\r
38049 <TR valign="top">
\r
38050 <TD width=15% BGCOLOR=#FBF5EF>
\r
38051 <B>MASTER_ID16</B>
\r
38053 <TD width=15% BGCOLOR=#FBF5EF>
\r
38054 <B>0XFF980140</B>
\r
38056 <TD width=10% BGCOLOR=#FBF5EF>
\r
38059 <TD width=10% BGCOLOR=#FBF5EF>
\r
38062 <TD width=15% BGCOLOR=#FBF5EF>
\r
38063 <B>0x00000000</B>
\r
38065 <TD width=35% BGCOLOR=#FBF5EF>
\r
38071 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38072 <TR valign="top">
\r
38073 <TD width=15% BGCOLOR=#C0FFC0>
\r
38074 <B>Field Name</B>
\r
38076 <TD width=15% BGCOLOR=#C0FFC0>
\r
38079 <TD width=10% BGCOLOR=#C0FFC0>
\r
38082 <TD width=10% BGCOLOR=#C0FFC0>
\r
38085 <TD width=15% BGCOLOR=#C0FFC0>
\r
38086 <B>Shifted Value</B>
\r
38088 <TD width=35% BGCOLOR=#C0FFC0>
\r
38089 <B>Description</B>
\r
38092 <TR valign="top">
\r
38093 <TD width=15% BGCOLOR=#FBF5EF>
\r
38094 <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP</B>
\r
38096 <TD width=15% BGCOLOR=#FBF5EF>
\r
38099 <TD width=10% BGCOLOR=#FBF5EF>
\r
38102 <TD width=10% BGCOLOR=#FBF5EF>
\r
38105 <TD width=15% BGCOLOR=#FBF5EF>
\r
38108 <TD width=35% BGCOLOR=#FBF5EF>
\r
38109 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
38112 <TR valign="top">
\r
38113 <TD width=15% BGCOLOR=#FBF5EF>
\r
38114 <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR</B>
\r
38116 <TD width=15% BGCOLOR=#FBF5EF>
\r
38119 <TD width=10% BGCOLOR=#FBF5EF>
\r
38122 <TD width=10% BGCOLOR=#FBF5EF>
\r
38125 <TD width=15% BGCOLOR=#FBF5EF>
\r
38128 <TD width=35% BGCOLOR=#FBF5EF>
\r
38129 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
38132 <TR valign="top">
\r
38133 <TD width=15% BGCOLOR=#FBF5EF>
\r
38134 <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM</B>
\r
38136 <TD width=15% BGCOLOR=#FBF5EF>
\r
38139 <TD width=10% BGCOLOR=#FBF5EF>
\r
38142 <TD width=10% BGCOLOR=#FBF5EF>
\r
38145 <TD width=15% BGCOLOR=#FBF5EF>
\r
38148 <TD width=35% BGCOLOR=#FBF5EF>
\r
38149 <B>Mask to be applied before comparing</B>
\r
38152 <TR valign="top">
\r
38153 <TD width=15% BGCOLOR=#FBF5EF>
\r
38154 <B>PSU_LPD_XPPU_CFG_MASTER_ID16_MID</B>
\r
38156 <TD width=15% BGCOLOR=#FBF5EF>
\r
38159 <TD width=10% BGCOLOR=#FBF5EF>
\r
38162 <TD width=10% BGCOLOR=#FBF5EF>
\r
38165 <TD width=15% BGCOLOR=#FBF5EF>
\r
38168 <TD width=35% BGCOLOR=#FBF5EF>
\r
38169 <B>Programmable Master ID</B>
\r
38172 <TR valign="top">
\r
38173 <TD width=15% BGCOLOR=#C0C0C0>
\r
38174 <B>PSU_LPD_XPPU_CFG_MASTER_ID16@0XFF980140</B>
\r
38176 <TD width=15% BGCOLOR=#C0C0C0>
\r
38179 <TD width=10% BGCOLOR=#C0C0C0>
\r
38182 <TD width=10% BGCOLOR=#C0C0C0>
\r
38185 <TD width=15% BGCOLOR=#C0C0C0>
\r
38188 <TD width=35% BGCOLOR=#C0C0C0>
\r
38189 <B>Master ID 16 Register</B>
\r
38194 <H2><a name="MASTER_ID17">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID17</a></H2>
\r
38195 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38196 <TR valign="top">
\r
38197 <TD width=15% BGCOLOR=#FFFF00>
\r
38198 <B>Register Name</B>
\r
38200 <TD width=15% BGCOLOR=#FFFF00>
\r
38203 <TD width=10% BGCOLOR=#FFFF00>
\r
38206 <TD width=10% BGCOLOR=#FFFF00>
\r
38209 <TD width=15% BGCOLOR=#FFFF00>
\r
38210 <B>Reset Value</B>
\r
38212 <TD width=35% BGCOLOR=#FFFF00>
\r
38213 <B>Description</B>
\r
38216 <TR valign="top">
\r
38217 <TD width=15% BGCOLOR=#FBF5EF>
\r
38218 <B>MASTER_ID17</B>
\r
38220 <TD width=15% BGCOLOR=#FBF5EF>
\r
38221 <B>0XFF980144</B>
\r
38223 <TD width=10% BGCOLOR=#FBF5EF>
\r
38226 <TD width=10% BGCOLOR=#FBF5EF>
\r
38229 <TD width=15% BGCOLOR=#FBF5EF>
\r
38230 <B>0x00000000</B>
\r
38232 <TD width=35% BGCOLOR=#FBF5EF>
\r
38238 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38239 <TR valign="top">
\r
38240 <TD width=15% BGCOLOR=#C0FFC0>
\r
38241 <B>Field Name</B>
\r
38243 <TD width=15% BGCOLOR=#C0FFC0>
\r
38246 <TD width=10% BGCOLOR=#C0FFC0>
\r
38249 <TD width=10% BGCOLOR=#C0FFC0>
\r
38252 <TD width=15% BGCOLOR=#C0FFC0>
\r
38253 <B>Shifted Value</B>
\r
38255 <TD width=35% BGCOLOR=#C0FFC0>
\r
38256 <B>Description</B>
\r
38259 <TR valign="top">
\r
38260 <TD width=15% BGCOLOR=#FBF5EF>
\r
38261 <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP</B>
\r
38263 <TD width=15% BGCOLOR=#FBF5EF>
\r
38266 <TD width=10% BGCOLOR=#FBF5EF>
\r
38269 <TD width=10% BGCOLOR=#FBF5EF>
\r
38272 <TD width=15% BGCOLOR=#FBF5EF>
\r
38275 <TD width=35% BGCOLOR=#FBF5EF>
\r
38276 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
38279 <TR valign="top">
\r
38280 <TD width=15% BGCOLOR=#FBF5EF>
\r
38281 <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR</B>
\r
38283 <TD width=15% BGCOLOR=#FBF5EF>
\r
38286 <TD width=10% BGCOLOR=#FBF5EF>
\r
38289 <TD width=10% BGCOLOR=#FBF5EF>
\r
38292 <TD width=15% BGCOLOR=#FBF5EF>
\r
38295 <TD width=35% BGCOLOR=#FBF5EF>
\r
38296 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
38299 <TR valign="top">
\r
38300 <TD width=15% BGCOLOR=#FBF5EF>
\r
38301 <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM</B>
\r
38303 <TD width=15% BGCOLOR=#FBF5EF>
\r
38306 <TD width=10% BGCOLOR=#FBF5EF>
\r
38309 <TD width=10% BGCOLOR=#FBF5EF>
\r
38312 <TD width=15% BGCOLOR=#FBF5EF>
\r
38315 <TD width=35% BGCOLOR=#FBF5EF>
\r
38316 <B>Mask to be applied before comparing</B>
\r
38319 <TR valign="top">
\r
38320 <TD width=15% BGCOLOR=#FBF5EF>
\r
38321 <B>PSU_LPD_XPPU_CFG_MASTER_ID17_MID</B>
\r
38323 <TD width=15% BGCOLOR=#FBF5EF>
\r
38326 <TD width=10% BGCOLOR=#FBF5EF>
\r
38329 <TD width=10% BGCOLOR=#FBF5EF>
\r
38332 <TD width=15% BGCOLOR=#FBF5EF>
\r
38335 <TD width=35% BGCOLOR=#FBF5EF>
\r
38336 <B>Programmable Master ID</B>
\r
38339 <TR valign="top">
\r
38340 <TD width=15% BGCOLOR=#C0C0C0>
\r
38341 <B>PSU_LPD_XPPU_CFG_MASTER_ID17@0XFF980144</B>
\r
38343 <TD width=15% BGCOLOR=#C0C0C0>
\r
38346 <TD width=10% BGCOLOR=#C0C0C0>
\r
38349 <TD width=10% BGCOLOR=#C0C0C0>
\r
38352 <TD width=15% BGCOLOR=#C0C0C0>
\r
38355 <TD width=35% BGCOLOR=#C0C0C0>
\r
38356 <B>Master ID 17 Register</B>
\r
38361 <H2><a name="MASTER_ID18">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID18</a></H2>
\r
38362 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38363 <TR valign="top">
\r
38364 <TD width=15% BGCOLOR=#FFFF00>
\r
38365 <B>Register Name</B>
\r
38367 <TD width=15% BGCOLOR=#FFFF00>
\r
38370 <TD width=10% BGCOLOR=#FFFF00>
\r
38373 <TD width=10% BGCOLOR=#FFFF00>
\r
38376 <TD width=15% BGCOLOR=#FFFF00>
\r
38377 <B>Reset Value</B>
\r
38379 <TD width=35% BGCOLOR=#FFFF00>
\r
38380 <B>Description</B>
\r
38383 <TR valign="top">
\r
38384 <TD width=15% BGCOLOR=#FBF5EF>
\r
38385 <B>MASTER_ID18</B>
\r
38387 <TD width=15% BGCOLOR=#FBF5EF>
\r
38388 <B>0XFF980148</B>
\r
38390 <TD width=10% BGCOLOR=#FBF5EF>
\r
38393 <TD width=10% BGCOLOR=#FBF5EF>
\r
38396 <TD width=15% BGCOLOR=#FBF5EF>
\r
38397 <B>0x00000000</B>
\r
38399 <TD width=35% BGCOLOR=#FBF5EF>
\r
38405 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38406 <TR valign="top">
\r
38407 <TD width=15% BGCOLOR=#C0FFC0>
\r
38408 <B>Field Name</B>
\r
38410 <TD width=15% BGCOLOR=#C0FFC0>
\r
38413 <TD width=10% BGCOLOR=#C0FFC0>
\r
38416 <TD width=10% BGCOLOR=#C0FFC0>
\r
38419 <TD width=15% BGCOLOR=#C0FFC0>
\r
38420 <B>Shifted Value</B>
\r
38422 <TD width=35% BGCOLOR=#C0FFC0>
\r
38423 <B>Description</B>
\r
38426 <TR valign="top">
\r
38427 <TD width=15% BGCOLOR=#FBF5EF>
\r
38428 <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP</B>
\r
38430 <TD width=15% BGCOLOR=#FBF5EF>
\r
38433 <TD width=10% BGCOLOR=#FBF5EF>
\r
38436 <TD width=10% BGCOLOR=#FBF5EF>
\r
38439 <TD width=15% BGCOLOR=#FBF5EF>
\r
38442 <TD width=35% BGCOLOR=#FBF5EF>
\r
38443 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
38446 <TR valign="top">
\r
38447 <TD width=15% BGCOLOR=#FBF5EF>
\r
38448 <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR</B>
\r
38450 <TD width=15% BGCOLOR=#FBF5EF>
\r
38453 <TD width=10% BGCOLOR=#FBF5EF>
\r
38456 <TD width=10% BGCOLOR=#FBF5EF>
\r
38459 <TD width=15% BGCOLOR=#FBF5EF>
\r
38462 <TD width=35% BGCOLOR=#FBF5EF>
\r
38463 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
38466 <TR valign="top">
\r
38467 <TD width=15% BGCOLOR=#FBF5EF>
\r
38468 <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM</B>
\r
38470 <TD width=15% BGCOLOR=#FBF5EF>
\r
38473 <TD width=10% BGCOLOR=#FBF5EF>
\r
38476 <TD width=10% BGCOLOR=#FBF5EF>
\r
38479 <TD width=15% BGCOLOR=#FBF5EF>
\r
38482 <TD width=35% BGCOLOR=#FBF5EF>
\r
38483 <B>Mask to be applied before comparing</B>
\r
38486 <TR valign="top">
\r
38487 <TD width=15% BGCOLOR=#FBF5EF>
\r
38488 <B>PSU_LPD_XPPU_CFG_MASTER_ID18_MID</B>
\r
38490 <TD width=15% BGCOLOR=#FBF5EF>
\r
38493 <TD width=10% BGCOLOR=#FBF5EF>
\r
38496 <TD width=10% BGCOLOR=#FBF5EF>
\r
38499 <TD width=15% BGCOLOR=#FBF5EF>
\r
38502 <TD width=35% BGCOLOR=#FBF5EF>
\r
38503 <B>Programmable Master ID</B>
\r
38506 <TR valign="top">
\r
38507 <TD width=15% BGCOLOR=#C0C0C0>
\r
38508 <B>PSU_LPD_XPPU_CFG_MASTER_ID18@0XFF980148</B>
\r
38510 <TD width=15% BGCOLOR=#C0C0C0>
\r
38513 <TD width=10% BGCOLOR=#C0C0C0>
\r
38516 <TD width=10% BGCOLOR=#C0C0C0>
\r
38519 <TD width=15% BGCOLOR=#C0C0C0>
\r
38522 <TD width=35% BGCOLOR=#C0C0C0>
\r
38523 <B>Master ID 18 Register</B>
\r
38528 <H2><a name="MASTER_ID19">Register (<A href=#mod___slcr> slcr </A>)MASTER_ID19</a></H2>
\r
38529 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38530 <TR valign="top">
\r
38531 <TD width=15% BGCOLOR=#FFFF00>
\r
38532 <B>Register Name</B>
\r
38534 <TD width=15% BGCOLOR=#FFFF00>
\r
38537 <TD width=10% BGCOLOR=#FFFF00>
\r
38540 <TD width=10% BGCOLOR=#FFFF00>
\r
38543 <TD width=15% BGCOLOR=#FFFF00>
\r
38544 <B>Reset Value</B>
\r
38546 <TD width=35% BGCOLOR=#FFFF00>
\r
38547 <B>Description</B>
\r
38550 <TR valign="top">
\r
38551 <TD width=15% BGCOLOR=#FBF5EF>
\r
38552 <B>MASTER_ID19</B>
\r
38554 <TD width=15% BGCOLOR=#FBF5EF>
\r
38555 <B>0XFF98014C</B>
\r
38557 <TD width=10% BGCOLOR=#FBF5EF>
\r
38560 <TD width=10% BGCOLOR=#FBF5EF>
\r
38563 <TD width=15% BGCOLOR=#FBF5EF>
\r
38564 <B>0x00000000</B>
\r
38566 <TD width=35% BGCOLOR=#FBF5EF>
\r
38572 <TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
\r
38573 <TR valign="top">
\r
38574 <TD width=15% BGCOLOR=#C0FFC0>
\r
38575 <B>Field Name</B>
\r
38577 <TD width=15% BGCOLOR=#C0FFC0>
\r
38580 <TD width=10% BGCOLOR=#C0FFC0>
\r
38583 <TD width=10% BGCOLOR=#C0FFC0>
\r
38586 <TD width=15% BGCOLOR=#C0FFC0>
\r
38587 <B>Shifted Value</B>
\r
38589 <TD width=35% BGCOLOR=#C0FFC0>
\r
38590 <B>Description</B>
\r
38593 <TR valign="top">
\r
38594 <TD width=15% BGCOLOR=#FBF5EF>
\r
38595 <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP</B>
\r
38597 <TD width=15% BGCOLOR=#FBF5EF>
\r
38600 <TD width=10% BGCOLOR=#FBF5EF>
\r
38603 <TD width=10% BGCOLOR=#FBF5EF>
\r
38606 <TD width=15% BGCOLOR=#FBF5EF>
\r
38609 <TD width=35% BGCOLOR=#FBF5EF>
\r
38610 <B>Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)</B>
\r
38613 <TR valign="top">
\r
38614 <TD width=15% BGCOLOR=#FBF5EF>
\r
38615 <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR</B>
\r
38617 <TD width=15% BGCOLOR=#FBF5EF>
\r
38620 <TD width=10% BGCOLOR=#FBF5EF>
\r
38623 <TD width=10% BGCOLOR=#FBF5EF>
\r
38626 <TD width=15% BGCOLOR=#FBF5EF>
\r
38629 <TD width=35% BGCOLOR=#FBF5EF>
\r
38630 <B>If set, only read transactions are allowed for the masters matching this register</B>
\r
38633 <TR valign="top">
\r
38634 <TD width=15% BGCOLOR=#FBF5EF>
\r
38635 <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM</B>
\r
38637 <TD width=15% BGCOLOR=#FBF5EF>
\r
38640 <TD width=10% BGCOLOR=#FBF5EF>
\r
38643 <TD width=10% BGCOLOR=#FBF5EF>
\r
38646 <TD width=15% BGCOLOR=#FBF5EF>
\r
38649 <TD width=35% BGCOLOR=#FBF5EF>
\r
38650 <B>Mask to be applied before comparing</B>
\r
38653 <TR valign="top">
\r
38654 <TD width=15% BGCOLOR=#FBF5EF>
\r
38655 <B>PSU_LPD_XPPU_CFG_MASTER_ID19_MID</B>
\r
38657 <TD width=15% BGCOLOR=#FBF5EF>
\r
38660 <TD width=10% BGCOLOR=#FBF5EF>
\r
38663 <TD width=10% BGCOLOR=#FBF5EF>
\r
38666 <TD width=15% BGCOLOR=#FBF5EF>
\r
38669 <TD width=35% BGCOLOR=#FBF5EF>
\r
38670 <B>Programmable Master ID</B>
\r
38673 <TR valign="top">
\r
38674 <TD width=15% BGCOLOR=#C0C0C0>
\r
38675 <B>PSU_LPD_XPPU_CFG_MASTER_ID19@0XFF98014C</B>
\r
38677 <TD width=15% BGCOLOR=#C0C0C0>
\r
38680 <TD width=10% BGCOLOR=#C0C0C0>
\r
38683 <TD width=10% BGCOLOR=#C0C0C0>
\r
38686 <TD width=15% BGCOLOR=#C0C0C0>
\r
38689 <TD width=35% BGCOLOR=#C0C0C0>
\r
38690 <B>Master ID 19 Register</B>
\r
38695 <H1>APERTURE PERMISIION LIST</H1>
\r