1 #****************************************************************************
6 # This file is automatically generated
8 #****************************************************************************
9 set psu_pll_init_data {
11 # Register : RPLL_CFG @ 0XFF5E0034</p>
13 # PLL loop filter resistor control
14 # PSU_CRL_APB_RPLL_CFG_RES 0x2
16 # PLL charge pump control
17 # PSU_CRL_APB_RPLL_CFG_CP 0x3
19 # PLL loop filter high frequency capacitor control
20 # PSU_CRL_APB_RPLL_CFG_LFHF 0x3
22 # Lock circuit counter setting
23 # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258
25 # Lock circuit configuration settings for lock windowsize
26 # PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
28 # Helper data. Values are to be looked up in a table from Data Sheet
29 #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) */
30 mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62
32 # Register : RPLL_CTRL @ 0XFF5E0030</p>
34 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
35 # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
36 # PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
38 # The integer portion of the feedback divider to the PLL
39 # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48
41 # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
42 # PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
45 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) */
46 mask_write 0XFF5E0030 0x00717F00 0x00014800
48 # Register : RPLL_CTRL @ 0XFF5E0030</p>
50 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
51 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
52 # PSU_CRL_APB_RPLL_CTRL_BYPASS 1
55 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) */
56 mask_write 0XFF5E0030 0x00000008 0x00000008
58 # Register : RPLL_CTRL @ 0XFF5E0030</p>
60 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
61 # PSU_CRL_APB_RPLL_CTRL_RESET 1
64 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) */
65 mask_write 0XFF5E0030 0x00000001 0x00000001
67 # Register : RPLL_CTRL @ 0XFF5E0030</p>
69 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
70 # PSU_CRL_APB_RPLL_CTRL_RESET 0
73 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) */
74 mask_write 0XFF5E0030 0x00000001 0x00000000
76 # Register : PLL_STATUS @ 0XFF5E0040</p>
79 # PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
80 mask_poll 0XFF5E0040 0x00000002
81 # : REMOVE PLL BY PASS
82 # Register : RPLL_CTRL @ 0XFF5E0030</p>
84 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
85 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
86 # PSU_CRL_APB_RPLL_CTRL_BYPASS 0
89 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) */
90 mask_write 0XFF5E0030 0x00000008 0x00000000
91 # Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
93 # Divisor value for this clock.
94 # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3
96 # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
97 #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */
98 mask_write 0XFF5E0048 0x00003F00 0x00000300
100 # Register : RPLL_FRAC_CFG @ 0XFF5E0038</p>
102 # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
103 # mode and uses DATA of this register for the fractional portion of the feedback divider.
104 # PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0
106 # Fractional value for the Feedback value.
107 # PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0
109 # Fractional control for the PLL
110 #(OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) */
111 mask_write 0XFF5E0038 0x8000FFFF 0x00000000
113 # Register : IOPLL_CFG @ 0XFF5E0024</p>
115 # PLL loop filter resistor control
116 # PSU_CRL_APB_IOPLL_CFG_RES 0xc
118 # PLL charge pump control
119 # PSU_CRL_APB_IOPLL_CFG_CP 0x3
121 # PLL loop filter high frequency capacitor control
122 # PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
124 # Lock circuit counter setting
125 # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339
127 # Lock circuit configuration settings for lock windowsize
128 # PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
130 # Helper data. Values are to be looked up in a table from Data Sheet
131 #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) */
132 mask_write 0XFF5E0024 0xFE7FEDEF 0x7E672C6C
134 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
136 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
137 # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
138 # PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
140 # The integer portion of the feedback divider to the PLL
141 # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d
143 # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
144 # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0
147 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) */
148 mask_write 0XFF5E0020 0x00717F00 0x00002D00
150 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
152 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
153 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
154 # PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
157 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) */
158 mask_write 0XFF5E0020 0x00000008 0x00000008
160 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
162 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
163 # PSU_CRL_APB_IOPLL_CTRL_RESET 1
166 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) */
167 mask_write 0XFF5E0020 0x00000001 0x00000001
169 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
171 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
172 # PSU_CRL_APB_IOPLL_CTRL_RESET 0
175 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) */
176 mask_write 0XFF5E0020 0x00000001 0x00000000
178 # Register : PLL_STATUS @ 0XFF5E0040</p>
181 # PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
182 mask_poll 0XFF5E0040 0x00000001
183 # : REMOVE PLL BY PASS
184 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
186 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
187 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
188 # PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
191 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) */
192 mask_write 0XFF5E0020 0x00000008 0x00000000
193 # Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
195 # Divisor value for this clock.
196 # PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
198 # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
199 #(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */
200 mask_write 0XFF5E0044 0x00003F00 0x00000300
202 # Register : IOPLL_FRAC_CFG @ 0XFF5E0028</p>
204 # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
205 # mode and uses DATA of this register for the fractional portion of the feedback divider.
206 # PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0
208 # Fractional value for the Feedback value.
209 # PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0
211 # Fractional control for the PLL
212 #(OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) */
213 mask_write 0XFF5E0028 0x8000FFFF 0x00000000
215 # Register : APLL_CFG @ 0XFD1A0024</p>
217 # PLL loop filter resistor control
218 # PSU_CRF_APB_APLL_CFG_RES 0x2
220 # PLL charge pump control
221 # PSU_CRF_APB_APLL_CFG_CP 0x3
223 # PLL loop filter high frequency capacitor control
224 # PSU_CRF_APB_APLL_CFG_LFHF 0x3
226 # Lock circuit counter setting
227 # PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
229 # Lock circuit configuration settings for lock windowsize
230 # PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
232 # Helper data. Values are to be looked up in a table from Data Sheet
233 #(OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) */
234 mask_write 0XFD1A0024 0xFE7FEDEF 0x7E4B0C62
236 # Register : APLL_CTRL @ 0XFD1A0020</p>
238 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
239 # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
240 # PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
242 # The integer portion of the feedback divider to the PLL
243 # PSU_CRF_APB_APLL_CTRL_FBDIV 0x42
245 # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
246 # PSU_CRF_APB_APLL_CTRL_DIV2 0x1
249 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) */
250 mask_write 0XFD1A0020 0x00717F00 0x00014200
252 # Register : APLL_CTRL @ 0XFD1A0020</p>
254 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
255 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
256 # PSU_CRF_APB_APLL_CTRL_BYPASS 1
259 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) */
260 mask_write 0XFD1A0020 0x00000008 0x00000008
262 # Register : APLL_CTRL @ 0XFD1A0020</p>
264 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
265 # PSU_CRF_APB_APLL_CTRL_RESET 1
268 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) */
269 mask_write 0XFD1A0020 0x00000001 0x00000001
271 # Register : APLL_CTRL @ 0XFD1A0020</p>
273 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
274 # PSU_CRF_APB_APLL_CTRL_RESET 0
277 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) */
278 mask_write 0XFD1A0020 0x00000001 0x00000000
280 # Register : PLL_STATUS @ 0XFD1A0044</p>
283 # PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
284 mask_poll 0XFD1A0044 0x00000001
285 # : REMOVE PLL BY PASS
286 # Register : APLL_CTRL @ 0XFD1A0020</p>
288 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
289 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
290 # PSU_CRF_APB_APLL_CTRL_BYPASS 0
293 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) */
294 mask_write 0XFD1A0020 0x00000008 0x00000000
295 # Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
297 # Divisor value for this clock.
298 # PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
300 # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
301 #(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */
302 mask_write 0XFD1A0048 0x00003F00 0x00000300
304 # Register : APLL_FRAC_CFG @ 0XFD1A0028</p>
306 # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
307 # mode and uses DATA of this register for the fractional portion of the feedback divider.
308 # PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0
310 # Fractional value for the Feedback value.
311 # PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0
313 # Fractional control for the PLL
314 #(OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) */
315 mask_write 0XFD1A0028 0x8000FFFF 0x00000000
317 # Register : DPLL_CFG @ 0XFD1A0030</p>
319 # PLL loop filter resistor control
320 # PSU_CRF_APB_DPLL_CFG_RES 0x2
322 # PLL charge pump control
323 # PSU_CRF_APB_DPLL_CFG_CP 0x3
325 # PLL loop filter high frequency capacitor control
326 # PSU_CRF_APB_DPLL_CFG_LFHF 0x3
328 # Lock circuit counter setting
329 # PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
331 # Lock circuit configuration settings for lock windowsize
332 # PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
334 # Helper data. Values are to be looked up in a table from Data Sheet
335 #(OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) */
336 mask_write 0XFD1A0030 0xFE7FEDEF 0x7E4B0C62
338 # Register : DPLL_CTRL @ 0XFD1A002C</p>
340 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
341 # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
342 # PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
344 # The integer portion of the feedback divider to the PLL
345 # PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
347 # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
348 # PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
351 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) */
352 mask_write 0XFD1A002C 0x00717F00 0x00014000
354 # Register : DPLL_CTRL @ 0XFD1A002C</p>
356 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
357 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
358 # PSU_CRF_APB_DPLL_CTRL_BYPASS 1
361 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) */
362 mask_write 0XFD1A002C 0x00000008 0x00000008
364 # Register : DPLL_CTRL @ 0XFD1A002C</p>
366 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
367 # PSU_CRF_APB_DPLL_CTRL_RESET 1
370 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) */
371 mask_write 0XFD1A002C 0x00000001 0x00000001
373 # Register : DPLL_CTRL @ 0XFD1A002C</p>
375 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
376 # PSU_CRF_APB_DPLL_CTRL_RESET 0
379 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) */
380 mask_write 0XFD1A002C 0x00000001 0x00000000
382 # Register : PLL_STATUS @ 0XFD1A0044</p>
385 # PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
386 mask_poll 0XFD1A0044 0x00000002
387 # : REMOVE PLL BY PASS
388 # Register : DPLL_CTRL @ 0XFD1A002C</p>
390 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
391 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
392 # PSU_CRF_APB_DPLL_CTRL_BYPASS 0
395 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) */
396 mask_write 0XFD1A002C 0x00000008 0x00000000
397 # Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
399 # Divisor value for this clock.
400 # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3
402 # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
403 #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) */
404 mask_write 0XFD1A004C 0x00003F00 0x00000300
406 # Register : DPLL_FRAC_CFG @ 0XFD1A0034</p>
408 # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
409 # mode and uses DATA of this register for the fractional portion of the feedback divider.
410 # PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0
412 # Fractional value for the Feedback value.
413 # PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0
415 # Fractional control for the PLL
416 #(OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) */
417 mask_write 0XFD1A0034 0x8000FFFF 0x00000000
419 # Register : VPLL_CFG @ 0XFD1A003C</p>
421 # PLL loop filter resistor control
422 # PSU_CRF_APB_VPLL_CFG_RES 0x2
424 # PLL charge pump control
425 # PSU_CRF_APB_VPLL_CFG_CP 0x3
427 # PLL loop filter high frequency capacitor control
428 # PSU_CRF_APB_VPLL_CFG_LFHF 0x3
430 # Lock circuit counter setting
431 # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a
433 # Lock circuit configuration settings for lock windowsize
434 # PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
436 # Helper data. Values are to be looked up in a table from Data Sheet
437 #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) */
438 mask_write 0XFD1A003C 0xFE7FEDEF 0x7E514C62
440 # Register : VPLL_CTRL @ 0XFD1A0038</p>
442 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
443 # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
444 # PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
446 # The integer portion of the feedback divider to the PLL
447 # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39
449 # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
450 # PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
453 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) */
454 mask_write 0XFD1A0038 0x00717F00 0x00013900
456 # Register : VPLL_CTRL @ 0XFD1A0038</p>
458 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
459 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
460 # PSU_CRF_APB_VPLL_CTRL_BYPASS 1
463 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) */
464 mask_write 0XFD1A0038 0x00000008 0x00000008
466 # Register : VPLL_CTRL @ 0XFD1A0038</p>
468 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
469 # PSU_CRF_APB_VPLL_CTRL_RESET 1
472 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) */
473 mask_write 0XFD1A0038 0x00000001 0x00000001
475 # Register : VPLL_CTRL @ 0XFD1A0038</p>
477 # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
478 # PSU_CRF_APB_VPLL_CTRL_RESET 0
481 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) */
482 mask_write 0XFD1A0038 0x00000001 0x00000000
484 # Register : PLL_STATUS @ 0XFD1A0044</p>
487 # PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
488 mask_poll 0XFD1A0044 0x00000004
489 # : REMOVE PLL BY PASS
490 # Register : VPLL_CTRL @ 0XFD1A0038</p>
492 # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
493 # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
494 # PSU_CRF_APB_VPLL_CTRL_BYPASS 0
497 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) */
498 mask_write 0XFD1A0038 0x00000008 0x00000000
499 # Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
501 # Divisor value for this clock.
502 # PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
504 # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
505 #(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */
506 mask_write 0XFD1A0050 0x00003F00 0x00000300
508 # Register : VPLL_FRAC_CFG @ 0XFD1A0040</p>
510 # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
511 # mode and uses DATA of this register for the fractional portion of the feedback divider.
512 # PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1
514 # Fractional value for the Feedback value.
515 # PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c
517 # Fractional control for the PLL
518 #(OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) */
519 mask_write 0XFD1A0040 0x8000FFFF 0x8000820C
522 set psu_clock_init_data {
523 # : CLOCK CONTROL SLCR REGISTER
524 # Register : GEM0_REF_CTRL @ 0XFF5E0050</p>
526 # Clock active for the RX channel
527 # PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT 0x1
529 # Clock active signal. Switch to 0 to disable the clock
530 # PSU_CRL_APB_GEM0_REF_CTRL_CLKACT 0x1
533 # PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1 0x1
536 # PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0 0x8
538 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
539 # clock. This is not usually an issue, but designers must be aware.)
540 # PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL 0x0
542 # This register controls this reference clock
543 #(OFFSET, MASK, VALUE) (0XFF5E0050, 0x063F3F07U ,0x06010800U) */
544 mask_write 0XFF5E0050 0x063F3F07 0x06010800
545 # Register : GEM1_REF_CTRL @ 0XFF5E0054</p>
547 # Clock active for the RX channel
548 # PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT 0x1
550 # Clock active signal. Switch to 0 to disable the clock
551 # PSU_CRL_APB_GEM1_REF_CTRL_CLKACT 0x1
554 # PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1 0x1
557 # PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0 0x8
559 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
560 # clock. This is not usually an issue, but designers must be aware.)
561 # PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL 0x0
563 # This register controls this reference clock
564 #(OFFSET, MASK, VALUE) (0XFF5E0054, 0x063F3F07U ,0x06010800U) */
565 mask_write 0XFF5E0054 0x063F3F07 0x06010800
566 # Register : GEM2_REF_CTRL @ 0XFF5E0058</p>
568 # Clock active for the RX channel
569 # PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT 0x1
571 # Clock active signal. Switch to 0 to disable the clock
572 # PSU_CRL_APB_GEM2_REF_CTRL_CLKACT 0x1
575 # PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1 0x1
578 # PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0 0x8
580 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
581 # clock. This is not usually an issue, but designers must be aware.)
582 # PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL 0x0
584 # This register controls this reference clock
585 #(OFFSET, MASK, VALUE) (0XFF5E0058, 0x063F3F07U ,0x06010800U) */
586 mask_write 0XFF5E0058 0x063F3F07 0x06010800
587 # Register : GEM3_REF_CTRL @ 0XFF5E005C</p>
589 # Clock active for the RX channel
590 # PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1
592 # Clock active signal. Switch to 0 to disable the clock
593 # PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1
596 # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
599 # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
601 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
602 # clock. This is not usually an issue, but designers must be aware.)
603 # PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
605 # This register controls this reference clock
606 #(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */
607 mask_write 0XFF5E005C 0x063F3F07 0x06010C00
608 # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100</p>
611 # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
613 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
614 # clock. This is not usually an issue, but designers must be aware.)
615 # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x2
618 # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
620 # Clock active signal. Switch to 0 to disable the clock
621 # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
623 # This register controls this reference clock
624 #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010602U) */
625 mask_write 0XFF5E0100 0x013F3F07 0x01010602
626 # Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
628 # Clock active signal. Switch to 0 to disable the clock
629 # PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
632 # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
635 # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
637 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
638 # clock. This is not usually an issue, but designers must be aware.)
639 # PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
641 # This register controls this reference clock
642 #(OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) */
643 mask_write 0XFF5E0060 0x023F3F07 0x02010600
644 # Register : USB1_BUS_REF_CTRL @ 0XFF5E0064</p>
646 # Clock active signal. Switch to 0 to disable the clock
647 # PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT 0x1
650 # PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1 0x1
653 # PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0 0x4
655 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
656 # clock. This is not usually an issue, but designers must be aware.)
657 # PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL 0x0
659 # This register controls this reference clock
660 #(OFFSET, MASK, VALUE) (0XFF5E0064, 0x023F3F07U ,0x02010400U) */
661 mask_write 0XFF5E0064 0x023F3F07 0x02010400
662 # Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
664 # Clock active signal. Switch to 0 to disable the clock
665 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
668 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf
671 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5
673 # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
674 # clock. This is not usually an issue, but designers must be aware.)
675 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
677 # This register controls this reference clock
678 #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) */
679 mask_write 0XFF5E004C 0x023F3F07 0x020F0500
680 # Register : QSPI_REF_CTRL @ 0XFF5E0068</p>
682 # Clock active signal. Switch to 0 to disable the clock
683 # PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1
686 # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
689 # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
691 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
692 # clock. This is not usually an issue, but designers must be aware.)
693 # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
695 # This register controls this reference clock
696 #(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) */
697 mask_write 0XFF5E0068 0x013F3F07 0x01010C00
698 # Register : SDIO0_REF_CTRL @ 0XFF5E006C</p>
700 # Clock active signal. Switch to 0 to disable the clock
701 # PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT 0x1
704 # PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 0x1
707 # PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 0x7
709 # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
710 # clock. This is not usually an issue, but designers must be aware.)
711 # PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL 0x2
713 # This register controls this reference clock
714 #(OFFSET, MASK, VALUE) (0XFF5E006C, 0x013F3F07U ,0x01010702U) */
715 mask_write 0XFF5E006C 0x013F3F07 0x01010702
716 # Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
718 # Clock active signal. Switch to 0 to disable the clock
719 # PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
722 # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
725 # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6
727 # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
728 # clock. This is not usually an issue, but designers must be aware.)
729 # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2
731 # This register controls this reference clock
732 #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) */
733 mask_write 0XFF5E0070 0x013F3F07 0x01010602
734 # Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
736 # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
737 # PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
739 # SoC Debug Clock Control
740 #(OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) */
741 mask_write 0XFF18030C 0x00020000 0x00000000
742 # Register : UART0_REF_CTRL @ 0XFF5E0074</p>
744 # Clock active signal. Switch to 0 to disable the clock
745 # PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
748 # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
751 # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
753 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
754 # clock. This is not usually an issue, but designers must be aware.)
755 # PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
757 # This register controls this reference clock
758 #(OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) */
759 mask_write 0XFF5E0074 0x013F3F07 0x01010F00
760 # Register : UART1_REF_CTRL @ 0XFF5E0078</p>
762 # Clock active signal. Switch to 0 to disable the clock
763 # PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
766 # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
769 # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
771 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
772 # clock. This is not usually an issue, but designers must be aware.)
773 # PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
775 # This register controls this reference clock
776 #(OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) */
777 mask_write 0XFF5E0078 0x013F3F07 0x01010F00
778 # Register : I2C0_REF_CTRL @ 0XFF5E0120</p>
780 # Clock active signal. Switch to 0 to disable the clock
781 # PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1
784 # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
787 # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
789 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
790 # clock. This is not usually an issue, but designers must be aware.)
791 # PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
793 # This register controls this reference clock
794 #(OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) */
795 mask_write 0XFF5E0120 0x013F3F07 0x01010F00
796 # Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
798 # Clock active signal. Switch to 0 to disable the clock
799 # PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
802 # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
805 # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
807 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
808 # clock. This is not usually an issue, but designers must be aware.)
809 # PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
811 # This register controls this reference clock
812 #(OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) */
813 mask_write 0XFF5E0124 0x013F3F07 0x01010F00
814 # Register : SPI0_REF_CTRL @ 0XFF5E007C</p>
816 # Clock active signal. Switch to 0 to disable the clock
817 # PSU_CRL_APB_SPI0_REF_CTRL_CLKACT 0x1
820 # PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
823 # PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x7
825 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
826 # clock. This is not usually an issue, but designers must be aware.)
827 # PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x2
829 # This register controls this reference clock
830 #(OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010702U) */
831 mask_write 0XFF5E007C 0x013F3F07 0x01010702
832 # Register : SPI1_REF_CTRL @ 0XFF5E0080</p>
834 # Clock active signal. Switch to 0 to disable the clock
835 # PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
838 # PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
841 # PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0x7
843 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
844 # clock. This is not usually an issue, but designers must be aware.)
845 # PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x2
847 # This register controls this reference clock
848 #(OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010702U) */
849 mask_write 0XFF5E0080 0x013F3F07 0x01010702
850 # Register : CAN0_REF_CTRL @ 0XFF5E0084</p>
852 # Clock active signal. Switch to 0 to disable the clock
853 # PSU_CRL_APB_CAN0_REF_CTRL_CLKACT 0x1
856 # PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1 0x1
859 # PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0 0xa
861 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
862 # clock. This is not usually an issue, but designers must be aware.)
863 # PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL 0x0
865 # This register controls this reference clock
866 #(OFFSET, MASK, VALUE) (0XFF5E0084, 0x013F3F07U ,0x01010A00U) */
867 mask_write 0XFF5E0084 0x013F3F07 0x01010A00
868 # Register : CAN1_REF_CTRL @ 0XFF5E0088</p>
870 # Clock active signal. Switch to 0 to disable the clock
871 # PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
874 # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
877 # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
879 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
880 # clock. This is not usually an issue, but designers must be aware.)
881 # PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
883 # This register controls this reference clock
884 #(OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) */
885 mask_write 0XFF5E0088 0x013F3F07 0x01010F00
886 # Register : CPU_R5_CTRL @ 0XFF5E0090</p>
888 # Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
889 # d lead to system hang
890 # PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
893 # PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
895 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
896 # clock. This is not usually an issue, but designers must be aware.)
897 # PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
899 # This register controls this reference clock
900 #(OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) */
901 mask_write 0XFF5E0090 0x01003F07 0x01000302
902 # Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
904 # Clock active signal. Switch to 0 to disable the clock
905 # PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
908 # PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
910 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
911 # clock. This is not usually an issue, but designers must be aware.)
912 # PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
914 # This register controls this reference clock
915 #(OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) */
916 mask_write 0XFF5E009C 0x01003F07 0x01000602
917 # Register : CSU_PLL_CTRL @ 0XFF5E00A0</p>
919 # Clock active signal. Switch to 0 to disable the clock
920 # PSU_CRL_APB_CSU_PLL_CTRL_CLKACT 0x1
923 # PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0 0x3
925 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
926 # clock. This is not usually an issue, but designers must be aware.)
927 # PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL 0x2
929 # This register controls this reference clock
930 #(OFFSET, MASK, VALUE) (0XFF5E00A0, 0x01003F07U ,0x01000302U) */
931 mask_write 0XFF5E00A0 0x01003F07 0x01000302
932 # Register : PCAP_CTRL @ 0XFF5E00A4</p>
934 # Clock active signal. Switch to 0 to disable the clock
935 # PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
938 # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6
940 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
941 # clock. This is not usually an issue, but designers must be aware.)
942 # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2
944 # This register controls this reference clock
945 #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) */
946 mask_write 0XFF5E00A4 0x01003F07 0x01000602
947 # Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
949 # Clock active signal. Switch to 0 to disable the clock
950 # PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
953 # PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
955 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
956 # clock. This is not usually an issue, but designers must be aware.)
957 # PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
959 # This register controls this reference clock
960 #(OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) */
961 mask_write 0XFF5E00A8 0x01003F07 0x01000302
962 # Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
964 # Clock active signal. Switch to 0 to disable the clock
965 # PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
968 # PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
970 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
971 # clock. This is not usually an issue, but designers must be aware.)
972 # PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
974 # This register controls this reference clock
975 #(OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) */
976 mask_write 0XFF5E00AC 0x01003F07 0x01000F02
977 # Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
979 # Clock active signal. Switch to 0 to disable the clock
980 # PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
983 # PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
985 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
986 # clock. This is not usually an issue, but designers must be aware.)
987 # PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
989 # This register controls this reference clock
990 #(OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) */
991 mask_write 0XFF5E00B0 0x01003F07 0x01000602
992 # Register : NAND_REF_CTRL @ 0XFF5E00B4</p>
994 # Clock active signal. Switch to 0 to disable the clock
995 # PSU_CRL_APB_NAND_REF_CTRL_CLKACT 0x1
998 # PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1 0x1
1001 # PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0 0xa
1003 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1004 # clock. This is not usually an issue, but designers must be aware.)
1005 # PSU_CRL_APB_NAND_REF_CTRL_SRCSEL 0x0
1007 # This register controls this reference clock
1008 #(OFFSET, MASK, VALUE) (0XFF5E00B4, 0x013F3F07U ,0x01010A00U) */
1009 mask_write 0XFF5E00B4 0x013F3F07 0x01010A00
1010 # Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
1012 # Clock active signal. Switch to 0 to disable the clock
1013 # PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
1016 # PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
1018 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1019 # clock. This is not usually an issue, but designers must be aware.)
1020 # PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
1022 # This register controls this reference clock
1023 #(OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) */
1024 mask_write 0XFF5E00B8 0x01003F07 0x01000302
1025 # Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
1027 # Clock active signal. Switch to 0 to disable the clock
1028 # PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
1031 # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
1034 # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
1036 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1037 # clock. This is not usually an issue, but designers must be aware.)
1038 # PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
1040 # This register controls this reference clock
1041 #(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) */
1042 mask_write 0XFF5E00C0 0x013F3F07 0x01010F00
1043 # Register : PL1_REF_CTRL @ 0XFF5E00C4</p>
1045 # Clock active signal. Switch to 0 to disable the clock
1046 # PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1
1049 # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4
1052 # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf
1054 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1055 # clock. This is not usually an issue, but designers must be aware.)
1056 # PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0
1058 # This register controls this reference clock
1059 #(OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) */
1060 mask_write 0XFF5E00C4 0x013F3F07 0x01040F00
1061 # Register : PL2_REF_CTRL @ 0XFF5E00C8</p>
1063 # Clock active signal. Switch to 0 to disable the clock
1064 # PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1
1067 # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1
1070 # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4
1072 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1073 # clock. This is not usually an issue, but designers must be aware.)
1074 # PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2
1076 # This register controls this reference clock
1077 #(OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) */
1078 mask_write 0XFF5E00C8 0x013F3F07 0x01010402
1079 # Register : PL3_REF_CTRL @ 0XFF5E00CC</p>
1081 # Clock active signal. Switch to 0 to disable the clock
1082 # PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1
1085 # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1
1088 # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3
1090 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1091 # clock. This is not usually an issue, but designers must be aware.)
1092 # PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2
1094 # This register controls this reference clock
1095 #(OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) */
1096 mask_write 0XFF5E00CC 0x013F3F07 0x01010302
1097 # Register : AMS_REF_CTRL @ 0XFF5E0108</p>
1100 # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
1103 # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d
1105 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1106 # clock. This is not usually an issue, but designers must be aware.)
1107 # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
1109 # Clock active signal. Switch to 0 to disable the clock
1110 # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
1112 # This register controls this reference clock
1113 #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) */
1114 mask_write 0XFF5E0108 0x013F3F07 0x01011D02
1115 # Register : DLL_REF_CTRL @ 0XFF5E0104</p>
1117 # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1118 # is not usually an issue, but designers must be aware.)
1119 # PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
1121 # This register controls this reference clock
1122 #(OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) */
1123 mask_write 0XFF5E0104 0x00000007 0x00000000
1124 # Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
1127 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
1129 # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1130 # cycles of the new clock. This is not usually an issue, but designers must be aware.)
1131 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
1133 # Clock active signal. Switch to 0 to disable the clock
1134 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
1136 # This register controls this reference clock
1137 #(OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) */
1138 mask_write 0XFF5E0128 0x01003F07 0x01000F00
1139 # Register : SATA_REF_CTRL @ 0XFD1A00A0</p>
1141 # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1142 # he new clock. This is not usually an issue, but designers must be aware.)
1143 # PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0
1145 # Clock active signal. Switch to 0 to disable the clock
1146 # PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1
1149 # PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2
1151 # This register controls this reference clock
1152 #(OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) */
1153 mask_write 0XFD1A00A0 0x01003F07 0x01000200
1154 # Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>
1156 # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
1157 # es of the new clock. This is not usually an issue, but designers must be aware.)
1158 # PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
1160 # Clock active signal. Switch to 0 to disable the clock
1161 # PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
1164 # PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
1166 # This register controls this reference clock
1167 #(OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) */
1168 mask_write 0XFD1A00B4 0x01003F07 0x01000200
1169 # Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
1172 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
1175 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3
1177 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1178 # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1179 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3
1181 # Clock active signal. Switch to 0 to disable the clock
1182 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
1184 # This register controls this reference clock
1185 #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) */
1186 mask_write 0XFD1A0070 0x013F3F07 0x01010303
1187 # Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
1190 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
1193 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27
1195 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1196 # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1197 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0
1199 # Clock active signal. Switch to 0 to disable the clock
1200 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1
1202 # This register controls this reference clock
1203 #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) */
1204 mask_write 0XFD1A0074 0x013F3F07 0x01012700
1205 # Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>
1208 # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1
1211 # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11
1213 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1214 # e new clock. This is not usually an issue, but designers must be aware.)
1215 # PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3
1217 # Clock active signal. Switch to 0 to disable the clock
1218 # PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1
1220 # This register controls this reference clock
1221 #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) */
1222 mask_write 0XFD1A007C 0x013F3F07 0x01011103
1223 # Register : ACPU_CTRL @ 0XFD1A0060</p>
1226 # PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1
1228 # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1229 # lock. This is not usually an issue, but designers must be aware.)
1230 # PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0
1232 # Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
1233 # PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1
1235 # Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1237 # PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1
1239 # This register controls this reference clock
1240 #(OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) */
1241 mask_write 0XFD1A0060 0x03003F07 0x03000100
1242 # Register : DBG_TRACE_CTRL @ 0XFD1A0064</p>
1245 # PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2
1247 # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1248 # he new clock. This is not usually an issue, but designers must be aware.)
1249 # PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0
1251 # Clock active signal. Switch to 0 to disable the clock
1252 # PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1
1254 # This register controls this reference clock
1255 #(OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) */
1256 mask_write 0XFD1A0064 0x01003F07 0x01000200
1257 # Register : DBG_FPD_CTRL @ 0XFD1A0068</p>
1260 # PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2
1262 # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1263 # he new clock. This is not usually an issue, but designers must be aware.)
1264 # PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0
1266 # Clock active signal. Switch to 0 to disable the clock
1267 # PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1
1269 # This register controls this reference clock
1270 #(OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) */
1271 mask_write 0XFD1A0068 0x01003F07 0x01000200
1272 # Register : DDR_CTRL @ 0XFD1A0080</p>
1275 # PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2
1277 # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1278 # s not usually an issue, but designers must be aware.)
1279 # PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0
1281 # This register controls this reference clock
1282 #(OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) */
1283 mask_write 0XFD1A0080 0x00003F07 0x00000200
1284 # Register : GPU_REF_CTRL @ 0XFD1A0084</p>
1287 # PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1
1289 # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1290 # he new clock. This is not usually an issue, but designers must be aware.)
1291 # PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0
1293 # Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
1294 # PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1
1296 # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1297 # PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1
1299 # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1300 # PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1
1302 # This register controls this reference clock
1303 #(OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) */
1304 mask_write 0XFD1A0084 0x07003F07 0x07000100
1305 # Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>
1308 # PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2
1310 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1311 # lock. This is not usually an issue, but designers must be aware.)
1312 # PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0
1314 # Clock active signal. Switch to 0 to disable the clock
1315 # PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1
1317 # This register controls this reference clock
1318 #(OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) */
1319 mask_write 0XFD1A00B8 0x01003F07 0x01000200
1320 # Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>
1323 # PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2
1325 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1326 # lock. This is not usually an issue, but designers must be aware.)
1327 # PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0
1329 # Clock active signal. Switch to 0 to disable the clock
1330 # PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1
1332 # This register controls this reference clock
1333 #(OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) */
1334 mask_write 0XFD1A00BC 0x01003F07 0x01000200
1335 # Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>
1338 # PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2
1340 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1341 # lock. This is not usually an issue, but designers must be aware.)
1342 # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2
1344 # Clock active signal. Switch to 0 to disable the clock
1345 # PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1
1347 # This register controls this reference clock
1348 #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) */
1349 mask_write 0XFD1A00C0 0x01003F07 0x01000202
1350 # Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>
1353 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5
1355 # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1356 # he new clock. This is not usually an issue, but designers must be aware.)
1357 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2
1359 # Clock active signal. Switch to 0 to disable the clock
1360 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1
1362 # This register controls this reference clock
1363 #(OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) */
1364 mask_write 0XFD1A00C4 0x01003F07 0x01000502
1365 # Register : GTGREF0_REF_CTRL @ 0XFD1A00C8</p>
1368 # PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0 0x4
1370 # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1371 # he new clock. This is not usually an issue, but designers must be aware.)
1372 # PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL 0x0
1374 # Clock active signal. Switch to 0 to disable the clock
1375 # PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT 0x1
1377 # This register controls this reference clock
1378 #(OFFSET, MASK, VALUE) (0XFD1A00C8, 0x01003F07U ,0x01000400U) */
1379 mask_write 0XFD1A00C8 0x01003F07 0x01000400
1380 # Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>
1383 # PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2
1385 # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1386 # he new clock. This is not usually an issue, but designers must be aware.)
1387 # PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0
1389 # This register controls this reference clock
1390 #(OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) */
1391 mask_write 0XFD1A00F8 0x00003F07 0x00000200
1392 # Register : IOU_TTC_APB_CLK @ 0XFF180380</p>
1394 # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
1395 # 0" = Select the R5 clock for the APB interface of TTC0
1396 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0
1398 # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
1399 # 0" = Select the R5 clock for the APB interface of TTC1
1400 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0
1402 # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
1403 # 0" = Select the R5 clock for the APB interface of TTC2
1404 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0
1406 # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
1407 # 0" = Select the R5 clock for the APB interface of TTC3
1408 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0
1410 # TTC APB clock select
1411 #(OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) */
1412 mask_write 0XFF180380 0x000000FF 0x00000000
1413 # Register : WDT_CLK_SEL @ 0XFD610100</p>
1415 # System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
1416 # PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0
1418 # SWDT clock source select
1419 #(OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) */
1420 mask_write 0XFD610100 0x00000001 0x00000000
1421 # Register : WDT_CLK_SEL @ 0XFF180300</p>
1423 # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
1425 # PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0
1427 # SWDT clock source select
1428 #(OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) */
1429 mask_write 0XFF180300 0x00000001 0x00000000
1430 # Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050</p>
1432 # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
1433 # PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0
1435 # SWDT clock source select
1436 #(OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) */
1437 mask_write 0XFF410050 0x00000001 0x00000000
1440 set psu_ddr_init_data {
1441 # : DDR INITIALIZATION
1442 # : DDR CONTROLLER RESET
1443 # Register : RST_DDR_SS @ 0XFD1A0108</p>
1445 # DDR block level reset inside of the DDR Sub System
1446 # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1
1448 # DDR sub system block level reset
1449 #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) */
1450 mask_write 0XFD1A0108 0x00000008 0x00000008
1451 # Register : MSTR @ 0XFD070000</p>
1453 # Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
1455 # PSU_DDRC_MSTR_DEVICE_CONFIG 0x1
1457 # Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
1458 # PSU_DDRC_MSTR_FREQUENCY_MODE 0x0
1460 # Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
1461 # esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
1462 # ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
1463 # ks - 1111 - Four ranks
1464 # PSU_DDRC_MSTR_ACTIVE_RANKS 0x1
1466 # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
1467 # of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
1468 # he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
1469 # -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
1470 # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1471 # PSU_DDRC_MSTR_BURST_RDWR 0x4
1473 # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
1474 # n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
1475 # l_off_mode is not supported, and this bit must be set to '0'.
1476 # PSU_DDRC_MSTR_DLL_OFF_MODE 0x0
1478 # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
1479 # AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
1480 # dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
1481 # figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
1482 # PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0
1484 # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
1485 # only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
1486 # s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
1487 # PSU_DDRC_MSTR_GEARDOWN_MODE 0x0
1489 # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
1490 # or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
1491 # PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
1492 # ing is not supported in DDR4 geardown mode.
1493 # PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0
1495 # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
1496 # t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
1497 # (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
1498 # _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
1499 # PSU_DDRC_MSTR_BURSTCHOP 0x0
1501 # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
1503 # PSU_DDRC_MSTR_LPDDR4 0x0
1505 # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
1507 # PSU_DDRC_MSTR_DDR4 0x1
1509 # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
1511 # PSU_DDRC_MSTR_LPDDR3 0x0
1513 # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
1515 # PSU_DDRC_MSTR_LPDDR2 0x0
1517 # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
1519 # PSU_DDRC_MSTR_DDR3 0x0
1522 #(OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) */
1523 mask_write 0XFD070000 0xE30FBE3D 0x41040010
1524 # Register : MRCTRL0 @ 0XFD070010</p>
1526 # Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
1527 # automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
1528 # re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
1529 # PSU_DDRC_MRCTRL0_MR_WR 0x0
1531 # Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
1532 # - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
1533 # R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
1534 # dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
1535 # s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
1536 # put Inversion of RDIMMs.
1537 # PSU_DDRC_MRCTRL0_MR_ADDR 0x0
1539 # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
1540 # However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
1541 # amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
1542 # and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
1543 # PSU_DDRC_MRCTRL0_MR_RANK 0x3
1545 # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
1546 # or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
1547 # be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
1548 # o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
1549 # n is not allowed - 1 - Software intervention is allowed
1550 # PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0
1552 # Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
1553 # PSU_DDRC_MRCTRL0_PDA_EN 0x0
1555 # Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
1556 # PSU_DDRC_MRCTRL0_MPR_EN 0x0
1558 # Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
1560 # PSU_DDRC_MRCTRL0_MR_TYPE 0x0
1562 # Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
1563 # it_int - pda_en - mpr_en
1564 #(OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) */
1565 mask_write 0XFD070010 0x8000F03F 0x00000030
1566 # Register : DERATEEN @ 0XFD070020</p>
1568 # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
1569 # Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
1570 # g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
1571 # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3
1573 # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
1574 # r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
1575 # PSU_DDRC_DERATEEN_DERATE_BYTE 0x0
1577 # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
1578 # 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
1579 # for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
1580 # PSU_DDRC_DERATEEN_DERATE_VALUE 0x0
1582 # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
1583 # Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
1585 # PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0
1587 # Temperature Derate Enable Register
1588 #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) */
1589 mask_write 0XFD070020 0x000003F3 0x00000300
1590 # Register : DERATEINT @ 0XFD070024</p>
1592 # Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
1593 # DR3/LPDDR4. This register must not be set to zero
1594 # PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000
1596 # Temperature Derate Interval Register
1597 #(OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) */
1598 mask_write 0XFD070024 0xFFFFFFFF 0x00800000
1599 # Register : PWRCTL @ 0XFD070030</p>
1601 # Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
1602 # r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
1603 # - Allow transition from Self refresh state
1604 # PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0
1606 # A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
1607 # M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
1608 # are Exit from Self Refresh
1609 # PSU_DDRC_PWRCTL_SELFREF_SW 0x0
1611 # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
1612 # st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
1613 # on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
1614 # DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
1615 # PSU_DDRC_PWRCTL_MPSM_EN 0x0
1617 # Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
1618 # is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
1619 # 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
1620 # ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
1621 # rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
1622 # PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0
1624 # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
1625 # et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
1626 # xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
1627 # should not be set to 1. FOR PERFORMANCE ONLY.
1628 # PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0
1630 # If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
1631 # RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
1632 # PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0
1634 # If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
1635 # f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
1636 # PSU_DDRC_PWRCTL_SELFREF_EN 0x0
1638 # Low Power Control Register
1639 #(OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) */
1640 mask_write 0XFD070030 0x0000007F 0x00000000
1641 # Register : PWRTMG @ 0XFD070034</p>
1643 # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
1644 # he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
1645 # PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40
1647 # Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
1648 # ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
1649 # iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
1650 # PSU_DDRC_PWRTMG_T_DPD_X4096 0x84
1652 # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
1653 # PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
1654 # PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10
1656 # Low Power Timing Register
1657 #(OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) */
1658 mask_write 0XFD070034 0x00FFFF1F 0x00408410
1659 # Register : RFSHCTL0 @ 0XFD070050</p>
1661 # Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
1662 # d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
1663 # It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
1664 # may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
1665 # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
1666 # PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2
1668 # If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
1669 # 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
1670 # would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
1671 # HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
1672 # formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
1673 # ued to the uMCTL2. FOR PERFORMANCE ONLY.
1674 # PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10
1676 # The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
1677 # reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
1678 # reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
1679 # RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
1680 # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
1681 # tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
1682 # fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
1683 # ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
1684 # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
1685 # d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
1686 # initiated update is complete.
1687 # PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0
1689 # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
1690 # t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
1691 # support LPDDR2/LPDDR3/LPDDR4
1692 # PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0
1694 # Refresh Control Register 0
1695 #(OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) */
1696 mask_write 0XFD070050 0x00F1F1F4 0x00210000
1697 # Register : RFSHCTL3 @ 0XFD070060</p>
1699 # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
1700 # ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
1701 # orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
1702 # self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
1703 # uture version of the uMCTL2.
1704 # PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0
1706 # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
1707 # s automatically updated when exiting reset, so it does not need to be toggled initially.
1708 # PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0
1710 # When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
1711 # ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
1712 # auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
1713 # is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
1714 # his register field is changeable on the fly.
1715 # PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1
1717 # Refresh Control Register 3
1718 #(OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) */
1719 mask_write 0XFD070060 0x00000073 0x00000001
1720 # Register : RFSHTMG @ 0XFD070064</p>
1722 # tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
1723 # for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
1724 # , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
1725 # e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
1726 # ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
1727 # programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
1728 # TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
1729 # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82
1731 # Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
1732 # REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
1733 # - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
1734 # PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1
1736 # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
1737 # RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
1738 # DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
1739 # per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
1740 # equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
1741 # opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
1742 # PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b
1744 # Refresh Timing Register
1745 #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) */
1746 mask_write 0XFD070064 0x0FFF83FF 0x0082808B
1747 # Register : ECCCFG0 @ 0XFD070070</p>
1749 # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
1750 # PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1
1752 # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
1754 # PSU_DDRC_ECCCFG0_ECC_MODE 0x0
1756 # ECC Configuration Register 0
1757 #(OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) */
1758 mask_write 0XFD070070 0x00000017 0x00000010
1759 # Register : ECCCFG1 @ 0XFD070074</p>
1761 # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
1762 # ng, if ECCCFG1.data_poison_en=1
1763 # PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0
1765 # Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
1766 # PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0
1768 # ECC Configuration Register 1
1769 #(OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) */
1770 mask_write 0XFD070074 0x00000003 0x00000000
1771 # Register : CRCPARCTL1 @ 0XFD0700C4</p>
1773 # The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
1774 # the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
1775 # pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
1776 # L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
1777 # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
1778 # e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
1779 # PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10
1781 # After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
1782 # M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
1783 # the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
1784 # the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
1785 # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
1786 # handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
1787 # rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
1788 # ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
1789 # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
1790 # one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
1791 # PR Page 1 should be treated as 'Don't care'.
1792 # PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1
1794 # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
1795 # CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
1796 # disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
1797 # PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0
1799 # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
1800 # d to support DDR4.
1801 # PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0
1803 # CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
1804 # CRC mode register setting in the DRAM.
1805 # PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0
1807 # C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
1808 # /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
1809 # is register should be 1.
1810 # PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0
1812 # CRC Parity Control Register1
1813 #(OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) */
1814 mask_write 0XFD0700C4 0x3F000391 0x10000200
1815 # Register : CRCPARCTL2 @ 0XFD0700C8</p>
1817 # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
1818 # - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
1819 # er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
1820 # PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40
1822 # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
1823 # tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
1824 # value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
1825 # PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5
1827 # Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
1828 # ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
1829 # er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
1830 # les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
1831 # or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
1832 # ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
1833 # max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
1834 # bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
1835 # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
1836 # ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
1837 # ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
1838 # to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
1839 # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
1840 # PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
1841 # _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
1842 # C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
1843 # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
1844 # bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
1845 # H-6 Values of 0, 1 and 2 are illegal.
1846 # PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f
1848 # CRC Parity Control Register2
1849 #(OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) */
1850 mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F
1851 # Register : INIT0 @ 0XFD0700D0</p>
1853 # If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
1854 # in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
1855 # ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
1856 # r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
1857 # or LPDDR4 in this version of the uMCTL2.
1858 # PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0
1860 # Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
1861 # 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
1862 # grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
1863 # MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
1864 # PSU_DDRC_INIT0_POST_CKE_X1024 0x2
1866 # Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
1867 # pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
1868 # tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
1869 # to next integer value.
1870 # PSU_DDRC_INIT0_PRE_CKE_X1024 0x106
1872 # SDRAM Initialization Register 0
1873 #(OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) */
1874 mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106
1875 # Register : INIT1 @ 0XFD0700D4</p>
1877 # Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
1878 # LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
1879 # PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2
1881 # Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
1882 # bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
1883 # PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0
1885 # Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
1886 # . There is no known specific requirement for this; it may be set to zero.
1887 # PSU_DDRC_INIT1_PRE_OCD_X32 0x0
1889 # SDRAM Initialization Register 1
1890 #(OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) */
1891 mask_write 0XFD0700D4 0x01FF7F0F 0x00020000
1892 # Register : INIT2 @ 0XFD0700D8</p>
1894 # Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
1895 # PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23
1897 # Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
1898 # e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
1899 # PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5
1901 # SDRAM Initialization Register 2
1902 #(OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) */
1903 mask_write 0XFD0700D8 0x0000FF0F 0x00002305
1904 # Register : INIT3 @ 0XFD0700DC</p>
1906 # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
1907 # DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
1909 # PSU_DDRC_INIT3_MR 0x930
1911 # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
1912 # bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
1913 # bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
1914 # lue to write to MR2 register
1915 # PSU_DDRC_INIT3_EMR 0x301
1917 # SDRAM Initialization Register 3
1918 #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) */
1919 mask_write 0XFD0700DC 0xFFFFFFFF 0x09300301
1920 # Register : INIT4 @ 0XFD0700E0</p>
1922 # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
1923 # egister mDDR: Unused
1924 # PSU_DDRC_INIT4_EMR2 0x20
1926 # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
1927 # rite to MR13 register
1928 # PSU_DDRC_INIT4_EMR3 0x200
1930 # SDRAM Initialization Register 4
1931 #(OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) */
1932 mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200
1933 # Register : INIT5 @ 0XFD0700E4</p>
1935 # ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
1936 # ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
1937 # PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21
1939 # Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
1940 # 3 typically requires 10 us.
1941 # PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4
1943 # SDRAM Initialization Register 5
1944 #(OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) */
1945 mask_write 0XFD0700E4 0x00FF03FF 0x00210004
1946 # Register : INIT6 @ 0XFD0700E8</p>
1948 # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
1949 # PSU_DDRC_INIT6_MR4 0x0
1951 # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
1952 # PSU_DDRC_INIT6_MR5 0x6c0
1954 # SDRAM Initialization Register 6
1955 #(OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) */
1956 mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0
1957 # Register : INIT7 @ 0XFD0700EC</p>
1959 # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
1960 # PSU_DDRC_INIT7_MR6 0x819
1962 # SDRAM Initialization Register 7
1963 #(OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) */
1964 mask_write 0XFD0700EC 0xFFFF0000 0x08190000
1965 # Register : DIMMCTL @ 0XFD0700F0</p>
1967 # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
1968 # ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
1969 # address mirroring is enabled.
1970 # PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0
1972 # Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
1973 # be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
1974 # nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
1975 # effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
1976 # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
1977 # PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1
1979 # Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
1980 # be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
1981 # his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
1982 # f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
1983 # PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0
1985 # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
1986 # which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
1987 # A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
1988 # lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
1989 # or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
1990 # has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
1991 # ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
1992 # PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0
1994 # Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
1995 # 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
1996 # re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
1997 # at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
1998 # sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
1999 # swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
2000 # ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
2001 # or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2002 # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
2003 # ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
2004 # not implement address mirroring
2005 # PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0
2007 # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
2008 # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
2009 # CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
2010 # each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
2011 # PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0
2013 # DIMM Control Register
2014 #(OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) */
2015 mask_write 0XFD0700F0 0x0000003F 0x00000010
2016 # Register : RANKCTL @ 0XFD0700F4</p>
2018 # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2019 # e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
2020 # nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
2021 # ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
2022 # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
2023 # n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
2024 # ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
2025 # or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
2026 # to the next integer.
2027 # PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6
2029 # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2030 # e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
2031 # sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
2032 # p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
2033 # ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
2034 # requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
2035 # quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
2036 # ound it up to the next integer.
2037 # PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6
2039 # Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
2040 # nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
2041 # on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
2042 # -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
2043 # _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
2044 # om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
2045 # ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
2046 # llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
2047 # ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
2048 # ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
2049 # . FOR PERFORMANCE ONLY.
2050 # PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf
2052 # Rank Control Register
2053 #(OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) */
2054 mask_write 0XFD0700F4 0x00000FFF 0x0000066F
2055 # Register : DRAMTMG0 @ 0XFD070100</p>
2057 # Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
2058 # 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
2059 # value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
2060 # Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
2061 # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
2062 # with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
2063 # PSU_DDRC_DRAMTMG0_WR2PRE 0x11
2065 # tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
2066 # in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
2067 # nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
2068 # PSU_DDRC_DRAMTMG0_T_FAW 0xc
2070 # tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
2071 # imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
2072 # No rounding up. Unit: Multiples of 1024 clocks.
2073 # PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24
2075 # tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
2076 # rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
2077 # (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
2078 # PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
2080 # SDRAM Timing Register 0
2081 #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) */
2082 mask_write 0XFD070100 0x7F3F7F3F 0x110C2412
2083 # Register : DRAMTMG1 @ 0XFD070104</p>
2085 # tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
2086 # is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
2087 # rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
2088 # PSU_DDRC_DRAMTMG1_T_XP 0x4
2090 # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
2091 # R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
2092 # S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
2093 # 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
2094 # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
2096 # PSU_DDRC_DRAMTMG1_RD2PRE 0x4
2098 # tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
2099 # up to next integer value. Unit: Clocks.
2100 # PSU_DDRC_DRAMTMG1_T_RC 0x19
2102 # SDRAM Timing Register 1
2103 #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) */
2104 mask_write 0XFD070104 0x001F1F7F 0x00040419
2105 # Register : DRAMTMG2 @ 0XFD070108</p>
2107 # Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
2108 # t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
2109 # tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
2110 # equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
2111 # is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2112 # PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7
2114 # Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
2115 # using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
2116 # onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
2117 # er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
2118 # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2119 # PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8
2121 # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
2122 # PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
2123 # /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
2124 # time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
2125 # urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
2126 # tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
2127 # DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
2128 # gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2129 # PSU_DDRC_DRAMTMG2_RD2WR 0x6
2131 # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
2132 # k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
2133 # per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
2134 # length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
2135 # d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
2136 # delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
2137 # ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2138 # PSU_DDRC_DRAMTMG2_WR2RD 0xe
2140 # SDRAM Timing Register 2
2141 #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) */
2142 mask_write 0XFD070108 0x3F3F3F3F 0x0708060E
2143 # Register : DRAMTMG3 @ 0XFD07010C</p>
2145 # Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
2146 # LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
2147 # nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
2148 # used for the time from a MRW/MRR to a MRW/MRR.
2149 # PSU_DDRC_DRAMTMG3_T_MRW 0x5
2151 # tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
2152 # rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
2153 # nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
2154 # 4 is used, set to tMRD_PAR(tMOD+PL) instead.
2155 # PSU_DDRC_DRAMTMG3_T_MRD 0x4
2157 # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
2158 # y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
2159 # if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
2160 # + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
2161 # PSU_DDRC_DRAMTMG3_T_MOD 0xc
2163 # SDRAM Timing Register 3
2164 #(OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) */
2165 mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C
2166 # Register : DRAMTMG4 @ 0XFD070110</p>
2168 # tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
2169 # am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
2170 # lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2171 # PSU_DDRC_DRAMTMG4_T_RCD 0x8
2173 # DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
2174 # time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
2175 # d it up to the next integer value. Unit: clocks.
2176 # PSU_DDRC_DRAMTMG4_T_CCD 0x3
2178 # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
2179 # activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
2180 # it up to the next integer value. Unit: Clocks.
2181 # PSU_DDRC_DRAMTMG4_T_RRD 0x3
2183 # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
2184 # (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
2185 # 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2186 # PSU_DDRC_DRAMTMG4_T_RP 0x9
2188 # SDRAM Timing Register 4
2189 #(OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) */
2190 mask_write 0XFD070110 0x1F0F0F1F 0x08030309
2191 # Register : DRAMTMG5 @ 0XFD070114</p>
2193 # This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
2194 # e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
2195 # tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
2197 # PSU_DDRC_DRAMTMG5_T_CKSRX 0x6
2199 # This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
2200 # SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
2201 # ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
2203 # PSU_DDRC_DRAMTMG5_T_CKSRE 0x6
2205 # Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
2206 # tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
2207 # 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
2209 # PSU_DDRC_DRAMTMG5_T_CKESR 0x4
2211 # Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
2212 # CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
2213 # his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
2214 # next integer value. Unit: Clocks.
2215 # PSU_DDRC_DRAMTMG5_T_CKE 0x3
2217 # SDRAM Timing Register 5
2218 #(OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) */
2219 mask_write 0XFD070114 0x0F0F3F1F 0x06060403
2220 # Register : DRAMTMG6 @ 0XFD070118</p>
2222 # This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
2223 # PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
2224 # ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
2226 # PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1
2228 # This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
2229 # table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
2230 # gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
2231 # R or LPDDR2 devices.
2232 # PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1
2234 # This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
2235 # lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
2236 # 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
2237 # p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2238 # PSU_DDRC_DRAMTMG6_T_CKCSX 0x4
2240 # SDRAM Timing Register 6
2241 #(OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) */
2242 mask_write 0XFD070118 0x0F0F000F 0x01010004
2243 # Register : DRAMTMG7 @ 0XFD07011C</p>
2245 # This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
2246 # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
2247 # is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
2248 # DDR2/LPDDR3/LPDDR4 devices.
2249 # PSU_DDRC_DRAMTMG7_T_CKPDE 0x1
2251 # This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
2252 # time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
2253 # , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
2254 # g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2255 # PSU_DDRC_DRAMTMG7_T_CKPDX 0x1
2257 # SDRAM Timing Register 7
2258 #(OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000101U) */
2259 mask_write 0XFD07011C 0x00000F0F 0x00000101
2260 # Register : DRAMTMG8 @ 0XFD070120</p>
2262 # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
2263 # O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
2264 # is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
2265 # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4
2267 # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
2268 # ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
2269 # nsure this is less than or equal to t_xs_x32.
2270 # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4
2272 # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
2273 # bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
2275 # PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd
2277 # tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
2278 # above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
2280 # PSU_DDRC_DRAMTMG8_T_XS_X32 0x6
2282 # SDRAM Timing Register 8
2283 #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) */
2284 mask_write 0XFD070120 0x7F7F7F7F 0x04040D06
2285 # Register : DRAMTMG9 @ 0XFD070124</p>
2287 # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
2288 # PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0
2290 # tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
2291 # o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
2292 # nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
2293 # PSU_DDRC_DRAMTMG9_T_CCD_S 0x2
2295 # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
2296 # ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
2298 # PSU_DDRC_DRAMTMG9_T_RRD_S 0x2
2300 # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
2301 # round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
2302 # Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
2303 # d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
2304 # is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
2305 # he above equation by 2, and round it up to next integer.
2306 # PSU_DDRC_DRAMTMG9_WR2RD_S 0xb
2308 # SDRAM Timing Register 9
2309 #(OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) */
2310 mask_write 0XFD070124 0x40070F3F 0x0002020B
2311 # Register : DRAMTMG11 @ 0XFD07012C</p>
2313 # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
2314 # this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
2315 # ples of 32 clocks.
2316 # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f
2318 # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
2319 # RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
2320 # PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7
2322 # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
2323 # up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
2324 # PSU_DDRC_DRAMTMG11_T_MPX_S 0x1
2326 # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
2327 # r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
2329 # PSU_DDRC_DRAMTMG11_T_CKMPE 0xe
2331 # SDRAM Timing Register 11
2332 #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) */
2333 mask_write 0XFD07012C 0x7F1F031F 0x6F07010E
2334 # Register : DRAMTMG12 @ 0XFD070130</p>
2336 # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
2337 # REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
2338 # PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2
2340 # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
2341 # /2) and round it up to next integer value.
2342 # PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6
2344 # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
2345 # s to (tMRD_PDA/2) and round it up to next integer value.
2346 # PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8
2348 # SDRAM Timing Register 12
2349 #(OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) */
2350 mask_write 0XFD070130 0x00030F1F 0x00020608
2351 # Register : ZQCTL0 @ 0XFD070180</p>
2353 # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
2354 # ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
2355 # ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2356 # PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1
2358 # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
2359 # or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
2360 # own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
2361 # ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2362 # PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0
2364 # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
2365 # nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
2366 # rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2367 # PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0
2369 # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
2370 # ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
2371 # gns supporting DDR4 devices.
2372 # PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0
2374 # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
2375 # on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
2376 # er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
2377 # ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
2378 # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2379 # PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100
2381 # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
2382 # ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
2383 # e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
2385 # PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40
2387 # ZQ Control Register 0
2388 #(OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) */
2389 mask_write 0XFD070180 0xF7FF03FF 0x81000040
2390 # Register : ZQCTL1 @ 0XFD070184</p>
2392 # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
2393 # ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
2394 # nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
2395 # PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20
2397 # Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
2398 # PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
2399 # upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2400 # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707
2402 # ZQ Control Register 1
2403 #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) */
2404 mask_write 0XFD070184 0x3FFFFFFF 0x02019707
2405 # Register : DFITMG0 @ 0XFD070190</p>
2407 # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
2408 # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
2409 # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
2410 # this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
2411 # PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4
2413 # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
2414 # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
2415 # fer to PHY specification for correct value.
2416 # PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1
2418 # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
2419 # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
2420 # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
2421 # latency through the RDIMM. Unit: Clocks
2422 # PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb
2424 # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
2425 # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
2426 # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
2428 # PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1
2430 # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
2431 # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
2432 # te, max supported value is 8. Unit: Clocks
2433 # PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2
2435 # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
2436 # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
2437 # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
2439 # PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb
2441 # DFI Timing Register 0
2442 #(OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) */
2443 mask_write 0XFD070190 0x1FBFBF3F 0x048B820B
2444 # Register : DFITMG1 @ 0XFD070194</p>
2446 # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
2447 # his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
2448 # the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
2449 # PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0
2451 # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
2453 # PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0
2455 # Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
2456 # nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
2457 # correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
2458 # phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
2459 # RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
2461 # PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3
2463 # Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
2464 # he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
2465 # ligned, this timing parameter should be rounded up to the next integer value.
2466 # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3
2468 # Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
2469 # alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
2470 # not phase aligned, this timing parameter should be rounded up to the next integer value.
2471 # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4
2473 # DFI Timing Register 1
2474 #(OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) */
2475 mask_write 0XFD070194 0xF31F0F0F 0x00030304
2476 # Register : DFILPCFG0 @ 0XFD070198</p>
2478 # Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
2479 # g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
2480 # PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7
2482 # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
2483 # cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
2484 # - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
2485 # 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
2487 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0
2489 # Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
2490 # nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
2491 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0
2493 # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
2494 # les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
2495 # 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
2496 # 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
2497 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0
2499 # Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
2500 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1
2502 # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
2503 # s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
2504 # 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
2505 # cycles - 0xE - 262144 cycles - 0xF - Unlimited
2506 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x4
2508 # Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
2509 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
2511 # DFI Low Power Configuration Register 0
2512 #(OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000141U) */
2513 mask_write 0XFD070198 0x0FF1F1F1 0x07000141
2514 # Register : DFILPCFG1 @ 0XFD07019C</p>
2516 # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
2517 # - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
2518 # 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
2519 # D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
2520 # PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2
2522 # Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
2523 # only present for designs supporting DDR4 devices.
2524 # PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1
2526 # DFI Low Power Configuration Register 1
2527 #(OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) */
2528 mask_write 0XFD07019C 0x000000F1 0x00000021
2529 # Register : DFIUPD1 @ 0XFD0701A4</p>
2531 # This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
2532 # ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
2533 # t read request when the uMCTL2 is idle. Unit: 1024 clocks
2534 # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41
2536 # This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
2537 # hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
2538 # idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
2539 # e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
2540 # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
2541 # 024. Unit: 1024 clocks
2542 # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2
2544 # DFI Update Register 1
2545 #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) */
2546 mask_write 0XFD0701A4 0x00FF00FF 0x004100E2
2547 # Register : DFIMISC @ 0XFD0701B0</p>
2549 # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
2550 # PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0
2552 # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
2553 # in designs configured to support DDR4 and LPDDR4.
2554 # PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0
2556 # PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
2558 # PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0
2560 # DFI Miscellaneous Control Register
2561 #(OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) */
2562 mask_write 0XFD0701B0 0x00000007 0x00000000
2563 # Register : DFITMG2 @ 0XFD0701B4</p>
2565 # >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
2566 # l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
2567 # PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9
2569 # Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
2570 # l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
2571 # PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6
2573 # DFI Timing Register 2
2574 #(OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) */
2575 mask_write 0XFD0701B4 0x00003F3F 0x00000906
2576 # Register : DBICTL @ 0XFD0701C0</p>
2578 # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
2579 # as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
2580 # PSU_DDRC_DBICTL_RD_DBI_EN 0x0
2582 # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
2583 # ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
2584 # PSU_DDRC_DBICTL_WR_DBI_EN 0x0
2586 # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
2587 # mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
2588 # : Set this to inverted value of MR13[5] which is opposite polarity from this signal
2589 # PSU_DDRC_DBICTL_DM_EN 0x1
2591 # DM/DBI Control Register
2592 #(OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) */
2593 mask_write 0XFD0701C0 0x00000007 0x00000001
2594 # Register : ADDRMAP0 @ 0XFD070200</p>
2596 # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
2597 # bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
2598 # PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f
2600 # Address Map Register 0
2601 #(OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) */
2602 mask_write 0XFD070200 0x0000001F 0x0000001F
2603 # Register : ADDRMAP1 @ 0XFD070204</p>
2605 # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
2606 # bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
2607 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f
2609 # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
2610 # r each of the bank address bits is determined by adding the internal base to the value of this field.
2611 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa
2613 # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
2614 # r each of the bank address bits is determined by adding the internal base to the value of this field.
2615 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa
2617 # Address Map Register 1
2618 #(OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) */
2619 mask_write 0XFD070204 0x001F1F1F 0x001F0A0A
2620 # Register : ADDRMAP2 @ 0XFD070208</p>
2622 # - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
2623 # s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
2624 # Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
2625 # this field. If set to 15, this column address bit is set to 0.
2626 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
2628 # - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
2629 # s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
2630 # Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
2631 # this field. If set to 15, this column address bit is set to 0.
2632 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
2634 # - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
2635 # s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
2636 # Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
2637 # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
2639 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
2641 # - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
2642 # s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
2643 # Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
2644 # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
2645 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
2647 # Address Map Register 2
2648 #(OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) */
2649 mask_write 0XFD070208 0x0F0F0F0F 0x00000000
2650 # Register : ADDRMAP3 @ 0XFD07020C</p>
2652 # - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
2653 # s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
2654 # column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
2655 # determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
2656 # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
2657 # ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
2658 # hence column bit 10 is used.
2659 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0
2661 # - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
2662 # s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
2663 # LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
2664 # ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
2665 # cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
2666 # mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
2668 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0
2670 # - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
2671 # s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
2672 # Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
2673 # this field. If set to 15, this column address bit is set to 0.
2674 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0
2676 # - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
2677 # s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
2678 # Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
2679 # this field. If set to 15, this column address bit is set to 0.
2680 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0
2682 # Address Map Register 3
2683 #(OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) */
2684 mask_write 0XFD07020C 0x0F0F0F0F 0x00000000
2685 # Register : ADDRMAP4 @ 0XFD070210</p>
2687 # - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
2688 # mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
2689 # e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
2690 # l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
2691 # n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
2692 # dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
2693 # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf
2695 # - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
2696 # mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
2697 # To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
2698 # termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
2699 # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
2700 # bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
2701 # nce column bit 10 is used.
2702 # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf
2704 # Address Map Register 4
2705 #(OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) */
2706 mask_write 0XFD070210 0x00000F0F 0x00000F0F
2707 # Register : ADDRMAP5 @ 0XFD070214</p>
2709 # Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
2710 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
2711 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8
2713 # Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
2714 # bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
2715 # ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
2716 # 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
2717 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf
2719 # Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
2720 # each of the row address bits is determined by adding the internal base to the value of this field.
2721 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8
2723 # Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
2724 # each of the row address bits is determined by adding the internal base to the value of this field.
2725 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8
2727 # Address Map Register 5
2728 #(OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) */
2729 mask_write 0XFD070214 0x0F0F0F0F 0x080F0808
2730 # Register : ADDRMAP6 @ 0XFD070218</p>
2732 # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
2733 # having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
2734 # y in designs configured to support LPDDR3.
2735 # PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0
2737 # Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
2738 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
2739 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf
2741 # Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
2742 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
2743 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8
2745 # Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
2746 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
2747 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8
2749 # Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
2750 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
2751 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8
2753 # Address Map Register 6
2754 #(OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) */
2755 mask_write 0XFD070218 0x8F0F0F0F 0x0F080808
2756 # Register : ADDRMAP7 @ 0XFD07021C</p>
2758 # Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
2759 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
2760 # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf
2762 # Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
2763 # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
2764 # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf
2766 # Address Map Register 7
2767 #(OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) */
2768 mask_write 0XFD07021C 0x00000F0F 0x00000F0F
2769 # Register : ADDRMAP8 @ 0XFD070220</p>
2771 # Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
2772 # address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
2773 # et to 31, bank group address bit 1 is set to 0.
2774 # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8
2776 # Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
2777 # bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
2778 # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8
2780 # Address Map Register 8
2781 #(OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) */
2782 mask_write 0XFD070220 0x00001F1F 0x00000808
2783 # Register : ADDRMAP9 @ 0XFD070224</p>
2785 # Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
2786 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2787 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2788 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8
2790 # Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
2791 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2792 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2793 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8
2795 # Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
2796 # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
2797 # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2798 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8
2800 # Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
2801 # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
2802 # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2803 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8
2805 # Address Map Register 9
2806 #(OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) */
2807 mask_write 0XFD070224 0x0F0F0F0F 0x08080808
2808 # Register : ADDRMAP10 @ 0XFD070228</p>
2810 # Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
2811 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2812 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2813 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8
2815 # Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
2816 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2817 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2818 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8
2820 # Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
2821 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2822 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2823 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8
2825 # Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
2826 # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
2827 # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2828 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8
2830 # Address Map Register 10
2831 #(OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) */
2832 mask_write 0XFD070228 0x0F0F0F0F 0x08080808
2833 # Register : ADDRMAP11 @ 0XFD07022C</p>
2835 # Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
2836 # or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
2837 # sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
2838 # PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8
2840 # Address Map Register 11
2841 #(OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) */
2842 mask_write 0XFD07022C 0x0000000F 0x00000008
2843 # Register : ODTCFG @ 0XFD070240</p>
2845 # Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
2846 # 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
2847 # L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
2848 # CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
2849 # PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6
2851 # The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
2852 # remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
2853 # 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
2854 # DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
2855 # PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0
2857 # Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
2858 # 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
2859 # tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
2861 # PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6
2863 # The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
2864 # emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
2865 # CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
2866 # L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
2867 # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
2868 # uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
2869 # PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0
2871 # ODT Configuration Register
2872 #(OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) */
2873 mask_write 0XFD070240 0x0F1F0F7C 0x06000600
2874 # Register : ODTMAP @ 0XFD070244</p>
2876 # Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
2877 # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
2878 # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
2879 # PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0
2881 # Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
2882 # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
2883 # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
2884 # PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0
2886 # Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
2887 # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
2888 # etc. For each rank, set its bit to 1 to enable its ODT.
2889 # PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0
2891 # Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
2892 # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
2893 # etc. For each rank, set its bit to 1 to enable its ODT.
2894 # PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1
2896 # ODT/Rank Map Register
2897 #(OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) */
2898 mask_write 0XFD070244 0x00003333 0x00000001
2899 # Register : SCHED @ 0XFD070250</p>
2901 # When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
2902 # non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
2903 # ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
2904 # egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
2905 # OR PERFORMANCE ONLY
2906 # PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1
2909 # PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0
2911 # Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
2912 # the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
2913 # to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
2914 # priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
2915 # than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
2916 # sing out of single bit error correction RMW operation.
2917 # PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20
2919 # If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
2920 # e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
2921 # egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
2922 # es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
2923 # s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
2924 # ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
2925 # age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
2926 # ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
2927 # PSU_DDRC_SCHED_PAGECLOSE 0x0
2929 # If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
2930 # PSU_DDRC_SCHED_PREFER_WRITE 0x0
2932 # Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
2933 # ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
2934 # e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
2935 # ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
2936 # PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1
2938 # Scheduler Control Register
2939 #(OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) */
2940 mask_write 0XFD070250 0x7FFF3F07 0x01002001
2941 # Register : PERFLPR1 @ 0XFD070264</p>
2943 # Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
2944 # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
2945 # PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8
2947 # Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
2948 # er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
2949 # be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
2950 # PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40
2952 # Low Priority Read CAM Register 1
2953 #(OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) */
2954 mask_write 0XFD070264 0xFF00FFFF 0x08000040
2955 # Register : PERFWR1 @ 0XFD07026C</p>
2957 # Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
2958 # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
2959 # PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8
2961 # Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
2962 # r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
2963 # e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
2964 # PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40
2966 # Write CAM Register 1
2967 #(OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) */
2968 mask_write 0XFD07026C 0xFF00FFFF 0x08000040
2969 # Register : DQMAP5 @ 0XFD070294</p>
2971 # All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
2972 # all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
2973 # wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
2975 # PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1
2978 #(OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) */
2979 mask_write 0XFD070294 0x00000001 0x00000001
2980 # Register : DBG0 @ 0XFD070300</p>
2982 # When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
2983 # lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
2984 # s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
2985 # PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0
2987 # When 1, disable write combine. FOR DEBUG ONLY
2988 # PSU_DDRC_DBG0_DIS_WC 0x0
2991 #(OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) */
2992 mask_write 0XFD070300 0x00000011 0x00000000
2993 # Register : DBGCMD @ 0XFD07030C</p>
2995 # Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
2996 # the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
2997 # register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
2998 # _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
2999 # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
3000 # PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0
3002 # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
3003 # he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
3004 # PSU_DDRC_DBGCMD_CTRLUPD 0x0
3006 # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
3007 # he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
3008 # en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
3009 # d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
3011 # PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0
3013 # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
3014 # refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
3015 # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
3016 # wn operating modes or Maximum Power Saving Mode.
3017 # PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0
3019 # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
3020 # refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
3021 # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
3022 # wn operating modes or Maximum Power Saving Mode.
3023 # PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0
3025 # Command Debug Register
3026 #(OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) */
3027 mask_write 0XFD07030C 0x80000033 0x00000000
3028 # Register : SWCTL @ 0XFD070320</p>
3030 # Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
3031 # egister to 1 once programming is done.
3032 # PSU_DDRC_SWCTL_SW_DONE 0x0
3034 # Software register programming control enable
3035 #(OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) */
3036 mask_write 0XFD070320 0x00000001 0x00000000
3037 # Register : PCCFG @ 0XFD070400</p>
3039 # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
3040 # e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
3041 # h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
3042 # ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
3043 # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
3044 # ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
3045 # DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
3046 # only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
3048 # PSU_DDRC_PCCFG_BL_EXP_MODE 0x0
3050 # Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
3051 # rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
3052 # ge DDRC transactions.
3053 # PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0
3055 # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
3056 # n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
3057 # _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
3058 # PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1
3060 # Port Common Configuration Register
3061 #(OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) */
3062 mask_write 0XFD070400 0x00000111 0x00000001
3063 # Register : PCFGR_0 @ 0XFD070404</p>
3065 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3066 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3068 # PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0
3070 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3071 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3072 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3073 # ess handshaking (it is not associated with any particular command).
3074 # PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1
3076 # If set to 1, enables aging function for the read channel of the port.
3077 # PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0
3079 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3080 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3081 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3082 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3083 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3084 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3085 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3086 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3087 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3088 # he two LSBs of this register field are tied internally to 2'b00.
3089 # PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf
3091 # Port n Configuration Read Register
3092 #(OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) */
3093 mask_write 0XFD070404 0x000073FF 0x0000200F
3094 # Register : PCFGW_0 @ 0XFD070408</p>
3096 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3097 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3099 # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1
3101 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3102 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3103 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3104 # not associated with any particular command).
3105 # PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1
3107 # If set to 1, enables aging function for the write channel of the port.
3108 # PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0
3110 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3111 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3112 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3113 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3114 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3115 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3116 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3117 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3118 # PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf
3120 # Port n Configuration Write Register
3121 #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) */
3122 mask_write 0XFD070408 0x000073FF 0x0000600F
3123 # Register : PCTRL_0 @ 0XFD070490</p>
3126 # PSU_DDRC_PCTRL_0_PORT_EN 0x1
3128 # Port n Control Register
3129 #(OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) */
3130 mask_write 0XFD070490 0x00000001 0x00000001
3131 # Register : PCFGQOS0_0 @ 0XFD070494</p>
3133 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3134 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3135 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3136 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2
3138 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3139 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3140 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3141 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0
3143 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3144 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3145 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3147 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb
3149 # Port n Read QoS Configuration Register 0
3150 #(OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) */
3151 mask_write 0XFD070494 0x0033000F 0x0020000B
3152 # Register : PCFGQOS1_0 @ 0XFD070498</p>
3154 # Specifies the timeout value for transactions mapped to the red address queue.
3155 # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0
3157 # Specifies the timeout value for transactions mapped to the blue address queue.
3158 # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0
3160 # Port n Read QoS Configuration Register 1
3161 #(OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) */
3162 mask_write 0XFD070498 0x07FF07FF 0x00000000
3163 # Register : PCFGR_1 @ 0XFD0704B4</p>
3165 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3166 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3168 # PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0
3170 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3171 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3172 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3173 # ess handshaking (it is not associated with any particular command).
3174 # PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1
3176 # If set to 1, enables aging function for the read channel of the port.
3177 # PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0
3179 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3180 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3181 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3182 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3183 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3184 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3185 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3186 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3187 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3188 # he two LSBs of this register field are tied internally to 2'b00.
3189 # PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf
3191 # Port n Configuration Read Register
3192 #(OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) */
3193 mask_write 0XFD0704B4 0x000073FF 0x0000200F
3194 # Register : PCFGW_1 @ 0XFD0704B8</p>
3196 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3197 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3199 # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1
3201 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3202 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3203 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3204 # not associated with any particular command).
3205 # PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1
3207 # If set to 1, enables aging function for the write channel of the port.
3208 # PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0
3210 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3211 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3212 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3213 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3214 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3215 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3216 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3217 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3218 # PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf
3220 # Port n Configuration Write Register
3221 #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) */
3222 mask_write 0XFD0704B8 0x000073FF 0x0000600F
3223 # Register : PCTRL_1 @ 0XFD070540</p>
3226 # PSU_DDRC_PCTRL_1_PORT_EN 0x1
3228 # Port n Control Register
3229 #(OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) */
3230 mask_write 0XFD070540 0x00000001 0x00000001
3231 # Register : PCFGQOS0_1 @ 0XFD070544</p>
3233 # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
3234 # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
3235 # s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3236 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2
3238 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3239 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3240 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3241 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0
3243 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3244 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3245 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3246 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0
3248 # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
3249 # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
3250 # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
3251 # ust be set to distinct values.
3252 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb
3254 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3255 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3256 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3258 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3
3260 # Port n Read QoS Configuration Register 0
3261 #(OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) */
3262 mask_write 0XFD070544 0x03330F0F 0x02000B03
3263 # Register : PCFGQOS1_1 @ 0XFD070548</p>
3265 # Specifies the timeout value for transactions mapped to the red address queue.
3266 # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0
3268 # Specifies the timeout value for transactions mapped to the blue address queue.
3269 # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0
3271 # Port n Read QoS Configuration Register 1
3272 #(OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) */
3273 mask_write 0XFD070548 0x07FF07FF 0x00000000
3274 # Register : PCFGR_2 @ 0XFD070564</p>
3276 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3277 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3279 # PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0
3281 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3282 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3283 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3284 # ess handshaking (it is not associated with any particular command).
3285 # PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1
3287 # If set to 1, enables aging function for the read channel of the port.
3288 # PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0
3290 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3291 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3292 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3293 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3294 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3295 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3296 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3297 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3298 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3299 # he two LSBs of this register field are tied internally to 2'b00.
3300 # PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf
3302 # Port n Configuration Read Register
3303 #(OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) */
3304 mask_write 0XFD070564 0x000073FF 0x0000200F
3305 # Register : PCFGW_2 @ 0XFD070568</p>
3307 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3308 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3310 # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1
3312 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3313 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3314 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3315 # not associated with any particular command).
3316 # PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1
3318 # If set to 1, enables aging function for the write channel of the port.
3319 # PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0
3321 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3322 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3323 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3324 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3325 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3326 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3327 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3328 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3329 # PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf
3331 # Port n Configuration Write Register
3332 #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) */
3333 mask_write 0XFD070568 0x000073FF 0x0000600F
3334 # Register : PCTRL_2 @ 0XFD0705F0</p>
3337 # PSU_DDRC_PCTRL_2_PORT_EN 0x1
3339 # Port n Control Register
3340 #(OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) */
3341 mask_write 0XFD0705F0 0x00000001 0x00000001
3342 # Register : PCFGQOS0_2 @ 0XFD0705F4</p>
3344 # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
3345 # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
3346 # s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3347 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2
3349 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3350 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3351 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3352 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0
3354 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3355 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3356 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3357 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0
3359 # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
3360 # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
3361 # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
3362 # ust be set to distinct values.
3363 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb
3365 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3366 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3367 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3369 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3
3371 # Port n Read QoS Configuration Register 0
3372 #(OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) */
3373 mask_write 0XFD0705F4 0x03330F0F 0x02000B03
3374 # Register : PCFGQOS1_2 @ 0XFD0705F8</p>
3376 # Specifies the timeout value for transactions mapped to the red address queue.
3377 # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0
3379 # Specifies the timeout value for transactions mapped to the blue address queue.
3380 # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0
3382 # Port n Read QoS Configuration Register 1
3383 #(OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) */
3384 mask_write 0XFD0705F8 0x07FF07FF 0x00000000
3385 # Register : PCFGR_3 @ 0XFD070614</p>
3387 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3388 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3390 # PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0
3392 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3393 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3394 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3395 # ess handshaking (it is not associated with any particular command).
3396 # PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1
3398 # If set to 1, enables aging function for the read channel of the port.
3399 # PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0
3401 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3402 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3403 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3404 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3405 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3406 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3407 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3408 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3409 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3410 # he two LSBs of this register field are tied internally to 2'b00.
3411 # PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf
3413 # Port n Configuration Read Register
3414 #(OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) */
3415 mask_write 0XFD070614 0x000073FF 0x0000200F
3416 # Register : PCFGW_3 @ 0XFD070618</p>
3418 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3419 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3421 # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1
3423 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3424 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3425 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3426 # not associated with any particular command).
3427 # PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1
3429 # If set to 1, enables aging function for the write channel of the port.
3430 # PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0
3432 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3433 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3434 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3435 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3436 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3437 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3438 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3439 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3440 # PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf
3442 # Port n Configuration Write Register
3443 #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) */
3444 mask_write 0XFD070618 0x000073FF 0x0000600F
3445 # Register : PCTRL_3 @ 0XFD0706A0</p>
3448 # PSU_DDRC_PCTRL_3_PORT_EN 0x1
3450 # Port n Control Register
3451 #(OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) */
3452 mask_write 0XFD0706A0 0x00000001 0x00000001
3453 # Register : PCFGQOS0_3 @ 0XFD0706A4</p>
3455 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3456 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3457 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3458 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1
3460 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3461 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3462 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3463 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0
3465 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3466 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3467 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3469 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3
3471 # Port n Read QoS Configuration Register 0
3472 #(OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) */
3473 mask_write 0XFD0706A4 0x0033000F 0x00100003
3474 # Register : PCFGQOS1_3 @ 0XFD0706A8</p>
3476 # Specifies the timeout value for transactions mapped to the red address queue.
3477 # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0
3479 # Specifies the timeout value for transactions mapped to the blue address queue.
3480 # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f
3482 # Port n Read QoS Configuration Register 1
3483 #(OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) */
3484 mask_write 0XFD0706A8 0x07FF07FF 0x0000004F
3485 # Register : PCFGWQOS0_3 @ 0XFD0706AC</p>
3487 # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3488 # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
3489 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1
3491 # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3492 # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
3493 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0
3495 # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
3496 # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
3497 # s to higher port priority.
3498 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3
3500 # Port n Write QoS Configuration Register 0
3501 #(OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) */
3502 mask_write 0XFD0706AC 0x0033000F 0x00100003
3503 # Register : PCFGWQOS1_3 @ 0XFD0706B0</p>
3505 # Specifies the timeout value for write transactions.
3506 # PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f
3508 # Port n Write QoS Configuration Register 1
3509 #(OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) */
3510 mask_write 0XFD0706B0 0x000007FF 0x0000004F
3511 # Register : PCFGR_4 @ 0XFD0706C4</p>
3513 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3514 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3516 # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1
3518 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3519 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3520 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3521 # ess handshaking (it is not associated with any particular command).
3522 # PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1
3524 # If set to 1, enables aging function for the read channel of the port.
3525 # PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0
3527 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3528 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3529 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3530 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3531 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3532 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3533 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3534 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3535 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3536 # he two LSBs of this register field are tied internally to 2'b00.
3537 # PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf
3539 # Port n Configuration Read Register
3540 #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) */
3541 mask_write 0XFD0706C4 0x000073FF 0x0000600F
3542 # Register : PCFGW_4 @ 0XFD0706C8</p>
3544 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3545 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3547 # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1
3549 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3550 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3551 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3552 # not associated with any particular command).
3553 # PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1
3555 # If set to 1, enables aging function for the write channel of the port.
3556 # PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0
3558 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3559 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3560 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3561 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3562 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3563 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3564 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3565 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3566 # PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf
3568 # Port n Configuration Write Register
3569 #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) */
3570 mask_write 0XFD0706C8 0x000073FF 0x0000600F
3571 # Register : PCTRL_4 @ 0XFD070750</p>
3574 # PSU_DDRC_PCTRL_4_PORT_EN 0x1
3576 # Port n Control Register
3577 #(OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) */
3578 mask_write 0XFD070750 0x00000001 0x00000001
3579 # Register : PCFGQOS0_4 @ 0XFD070754</p>
3581 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3582 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3583 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3584 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1
3586 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3587 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3588 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3589 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0
3591 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3592 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3593 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3595 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3
3597 # Port n Read QoS Configuration Register 0
3598 #(OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) */
3599 mask_write 0XFD070754 0x0033000F 0x00100003
3600 # Register : PCFGQOS1_4 @ 0XFD070758</p>
3602 # Specifies the timeout value for transactions mapped to the red address queue.
3603 # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0
3605 # Specifies the timeout value for transactions mapped to the blue address queue.
3606 # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f
3608 # Port n Read QoS Configuration Register 1
3609 #(OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) */
3610 mask_write 0XFD070758 0x07FF07FF 0x0000004F
3611 # Register : PCFGWQOS0_4 @ 0XFD07075C</p>
3613 # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3614 # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
3615 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1
3617 # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3618 # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
3619 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0
3621 # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
3622 # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
3623 # s to higher port priority.
3624 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3
3626 # Port n Write QoS Configuration Register 0
3627 #(OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) */
3628 mask_write 0XFD07075C 0x0033000F 0x00100003
3629 # Register : PCFGWQOS1_4 @ 0XFD070760</p>
3631 # Specifies the timeout value for write transactions.
3632 # PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f
3634 # Port n Write QoS Configuration Register 1
3635 #(OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) */
3636 mask_write 0XFD070760 0x000007FF 0x0000004F
3637 # Register : PCFGR_5 @ 0XFD070774</p>
3639 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3640 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3642 # PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0
3644 # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
3645 # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
3646 # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
3647 # ess handshaking (it is not associated with any particular command).
3648 # PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1
3650 # If set to 1, enables aging function for the read channel of the port.
3651 # PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0
3653 # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
3654 # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3655 # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
3656 # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
3657 # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
3658 # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
3659 # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
3660 # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
3661 # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
3662 # he two LSBs of this register field are tied internally to 2'b00.
3663 # PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf
3665 # Port n Configuration Read Register
3666 #(OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) */
3667 mask_write 0XFD070774 0x000073FF 0x0000200F
3668 # Register : PCFGW_5 @ 0XFD070778</p>
3670 # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
3671 # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
3673 # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1
3675 # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
3676 # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
3677 # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
3678 # not associated with any particular command).
3679 # PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1
3681 # If set to 1, enables aging function for the write channel of the port.
3682 # PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0
3684 # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
3685 # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
3686 # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
3687 # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
3688 # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
3689 # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
3690 # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
3691 # ng. Note: The two LSBs of this register field are tied internally to 2'b00.
3692 # PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf
3694 # Port n Configuration Write Register
3695 #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) */
3696 mask_write 0XFD070778 0x000073FF 0x0000600F
3697 # Register : PCTRL_5 @ 0XFD070800</p>
3700 # PSU_DDRC_PCTRL_5_PORT_EN 0x1
3702 # Port n Control Register
3703 #(OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) */
3704 mask_write 0XFD070800 0x00000001 0x00000001
3705 # Register : PCFGQOS0_5 @ 0XFD070804</p>
3707 # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
3708 # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
3709 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3710 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1
3712 # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
3713 # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
3714 # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
3715 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0
3717 # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
3718 # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
3719 # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
3721 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3
3723 # Port n Read QoS Configuration Register 0
3724 #(OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) */
3725 mask_write 0XFD070804 0x0033000F 0x00100003
3726 # Register : PCFGQOS1_5 @ 0XFD070808</p>
3728 # Specifies the timeout value for transactions mapped to the red address queue.
3729 # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0
3731 # Specifies the timeout value for transactions mapped to the blue address queue.
3732 # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f
3734 # Port n Read QoS Configuration Register 1
3735 #(OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) */
3736 mask_write 0XFD070808 0x07FF07FF 0x0000004F
3737 # Register : PCFGWQOS0_5 @ 0XFD07080C</p>
3739 # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3740 # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
3741 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1
3743 # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
3744 # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
3745 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0
3747 # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
3748 # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
3749 # s to higher port priority.
3750 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3
3752 # Port n Write QoS Configuration Register 0
3753 #(OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) */
3754 mask_write 0XFD07080C 0x0033000F 0x00100003
3755 # Register : PCFGWQOS1_5 @ 0XFD070810</p>
3757 # Specifies the timeout value for write transactions.
3758 # PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f
3760 # Port n Write QoS Configuration Register 1
3761 #(OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) */
3762 mask_write 0XFD070810 0x000007FF 0x0000004F
3763 # Register : SARBASE0 @ 0XFD070F04</p>
3765 # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
3766 # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
3767 # PSU_DDRC_SARBASE0_BASE_ADDR 0x0
3769 # SAR Base Address Register n
3770 #(OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) */
3771 mask_write 0XFD070F04 0x000001FF 0x00000000
3772 # Register : SARSIZE0 @ 0XFD070F08</p>
3774 # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
3775 # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
3776 # or example, if register is programmed to 0, region will have 1 block.
3777 # PSU_DDRC_SARSIZE0_NBLOCKS 0x0
3779 # SAR Size Register n
3780 #(OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) */
3781 mask_write 0XFD070F08 0x000000FF 0x00000000
3782 # Register : SARBASE1 @ 0XFD070F0C</p>
3784 # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
3785 # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
3786 # PSU_DDRC_SARBASE1_BASE_ADDR 0x10
3788 # SAR Base Address Register n
3789 #(OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) */
3790 mask_write 0XFD070F0C 0x000001FF 0x00000010
3791 # Register : SARSIZE1 @ 0XFD070F10</p>
3793 # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
3794 # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
3795 # or example, if register is programmed to 0, region will have 1 block.
3796 # PSU_DDRC_SARSIZE1_NBLOCKS 0xf
3798 # SAR Size Register n
3799 #(OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) */
3800 mask_write 0XFD070F10 0x000000FF 0x0000000F
3801 # Register : DFITMG0_SHADOW @ 0XFD072190</p>
3803 # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
3804 # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
3805 # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
3806 # this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
3807 # PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7
3809 # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
3810 # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
3811 # fer to PHY specification for correct value.
3812 # PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1
3814 # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
3815 # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
3816 # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
3817 # latency through the RDIMM. Unit: Clocks
3818 # PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2
3820 # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
3821 # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
3822 # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
3824 # PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1
3826 # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
3827 # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
3828 # te, max supported value is 8. Unit: Clocks
3829 # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0
3831 # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
3832 # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
3833 # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
3835 # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2
3837 # DFI Timing Shadow Register 0
3838 #(OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) */
3839 mask_write 0XFD072190 0x1FBFBF3F 0x07828002
3840 # : DDR CONTROLLER RESET
3841 # Register : RST_DDR_SS @ 0XFD1A0108</p>
3843 # DDR block level reset inside of the DDR Sub System
3844 # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0
3846 # DDR sub system block level reset
3847 #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) */
3848 mask_write 0XFD1A0108 0x00000008 0x00000000
3850 # Register : PGCR0 @ 0XFD080010</p>
3853 # PSU_DDR_PHY_PGCR0_ADCP 0x0
3855 # Reserved. Returns zeroes on reads.
3856 # PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0
3859 # PSU_DDR_PHY_PGCR0_PHYFRST 0x1
3861 # Oscillator Mode Address/Command Delay Line Select
3862 # PSU_DDR_PHY_PGCR0_OSCACDL 0x3
3864 # Reserved. Returns zeroes on reads.
3865 # PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0
3867 # Digital Test Output Select
3868 # PSU_DDR_PHY_PGCR0_DTOSEL 0x0
3870 # Reserved. Returns zeroes on reads.
3871 # PSU_DDR_PHY_PGCR0_RESERVED_13 0x0
3873 # Oscillator Mode Division
3874 # PSU_DDR_PHY_PGCR0_OSCDIV 0xf
3877 # PSU_DDR_PHY_PGCR0_OSCEN 0x0
3879 # Reserved. Returns zeroes on reads.
3880 # PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0
3882 # PHY General Configuration Register 0
3883 #(OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) */
3884 mask_write 0XFD080010 0xFFFFFFFF 0x07001E00
3885 # Register : PGCR2 @ 0XFD080018</p>
3887 # Clear Training Status Registers
3888 # PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0
3890 # Clear Impedance Calibration
3891 # PSU_DDR_PHY_PGCR2_CLRZCAL 0x0
3893 # Clear Parity Error
3894 # PSU_DDR_PHY_PGCR2_CLRPERR 0x0
3896 # Initialization Complete Pin Configuration
3897 # PSU_DDR_PHY_PGCR2_ICPC 0x0
3899 # Data Training PUB Mode Exit Timer
3900 # PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf
3902 # Initialization Bypass
3903 # PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0
3906 # PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
3909 # PSU_DDR_PHY_PGCR2_TREFPRD 0x12302
3911 # PHY General Configuration Register 2
3912 #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F12302U) */
3913 mask_write 0XFD080018 0xFFFFFFFF 0x00F12302
3914 # Register : PGCR5 @ 0XFD080024</p>
3916 # Frequency B Ratio Term
3917 # PSU_DDR_PHY_PGCR5_FRQBT 0x1
3919 # Frequency A Ratio Term
3920 # PSU_DDR_PHY_PGCR5_FRQAT 0x1
3922 # DFI Disconnect Time Period
3923 # PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0
3925 # Receiver bias core side control
3926 # PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf
3928 # Reserved. Return zeroes on reads.
3929 # PSU_DDR_PHY_PGCR5_RESERVED_3 0x0
3931 # Internal VREF generator REFSEL ragne select
3932 # PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1
3934 # DDL Page Read Write select
3935 # PSU_DDR_PHY_PGCR5_DDLPGACT 0x0
3937 # DDL Page Read Write select
3938 # PSU_DDR_PHY_PGCR5_DDLPGRW 0x0
3940 # PHY General Configuration Register 5
3941 #(OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) */
3942 mask_write 0XFD080024 0xFFFFFFFF 0x010100F4
3943 # Register : PTR0 @ 0XFD080040</p>
3945 # PLL Power-Down Time
3946 # PSU_DDR_PHY_PTR0_TPLLPD 0x2f0
3948 # PLL Gear Shift Time
3949 # PSU_DDR_PHY_PTR0_TPLLGS 0x60
3952 # PSU_DDR_PHY_PTR0_TPHYRST 0x10
3954 # PHY Timing Register 0
3955 #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) */
3956 mask_write 0XFD080040 0xFFFFFFFF 0x5E001810
3957 # Register : PTR1 @ 0XFD080044</p>
3960 # PSU_DDR_PHY_PTR1_TPLLLOCK 0x80
3962 # Reserved. Returns zeroes on reads.
3963 # PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0
3966 # PSU_DDR_PHY_PTR1_TPLLRST 0x5f0
3968 # PHY Timing Register 1
3969 #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) */
3970 mask_write 0XFD080044 0xFFFFFFFF 0x008005F0
3971 # Register : DSGCR @ 0XFD080090</p>
3973 # Reserved. Return zeroes on reads.
3974 # PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0
3976 # When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
3977 # fault calculation.
3978 # PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0
3980 # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
3981 # PSU_DDR_PHY_DSGCR_RDBICL 0x2
3983 # PHY Impedance Update Enable
3984 # PSU_DDR_PHY_DSGCR_PHYZUEN 0x1
3986 # Reserved. Return zeroes on reads.
3987 # PSU_DDR_PHY_DSGCR_RESERVED_22 0x0
3989 # SDRAM Reset Output Enable
3990 # PSU_DDR_PHY_DSGCR_RSTOE 0x1
3992 # Single Data Rate Mode
3993 # PSU_DDR_PHY_DSGCR_SDRMODE 0x0
3995 # Reserved. Return zeroes on reads.
3996 # PSU_DDR_PHY_DSGCR_RESERVED_18 0x0
3998 # ATO Analog Test Enable
3999 # PSU_DDR_PHY_DSGCR_ATOAE 0x0
4002 # PSU_DDR_PHY_DSGCR_DTOOE 0x0
4005 # PSU_DDR_PHY_DSGCR_DTOIOM 0x0
4007 # DTO Power Down Receiver
4008 # PSU_DDR_PHY_DSGCR_DTOPDR 0x1
4010 # Reserved. Return zeroes on reads
4011 # PSU_DDR_PHY_DSGCR_RESERVED_13 0x0
4013 # DTO On-Die Termination
4014 # PSU_DDR_PHY_DSGCR_DTOODT 0x0
4016 # PHY Update Acknowledge Delay
4017 # PSU_DDR_PHY_DSGCR_PUAD 0x4
4019 # Controller Update Acknowledge Enable
4020 # PSU_DDR_PHY_DSGCR_CUAEN 0x1
4022 # Reserved. Return zeroes on reads
4023 # PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0
4025 # Controller Impedance Update Enable
4026 # PSU_DDR_PHY_DSGCR_CTLZUEN 0x0
4028 # Reserved. Return zeroes on reads
4029 # PSU_DDR_PHY_DSGCR_RESERVED_1 0x0
4031 # PHY Update Request Enable
4032 # PSU_DDR_PHY_DSGCR_PUREN 0x1
4034 # DDR System General Configuration Register
4035 #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) */
4036 mask_write 0XFD080090 0xFFFFFFFF 0x02A04121
4037 # Register : DCR @ 0XFD080100</p>
4039 # DDR4 Gear Down Timing.
4040 # PSU_DDR_PHY_DCR_GEARDN 0x0
4042 # Un-used Bank Group
4043 # PSU_DDR_PHY_DCR_UBG 0x0
4045 # Un-buffered DIMM Address Mirroring
4046 # PSU_DDR_PHY_DCR_UDIMM 0x0
4049 # PSU_DDR_PHY_DCR_DDR2T 0x0
4051 # No Simultaneous Rank Access
4052 # PSU_DDR_PHY_DCR_NOSRA 0x1
4054 # Reserved. Return zeroes on reads.
4055 # PSU_DDR_PHY_DCR_RESERVED_26_18 0x0
4058 # PSU_DDR_PHY_DCR_BYTEMASK 0x1
4061 # PSU_DDR_PHY_DCR_DDRTYPE 0x0
4063 # Multi-Purpose Register (MPR) DQ (DDR3 Only)
4064 # PSU_DDR_PHY_DCR_MPRDQ 0x0
4066 # Primary DQ (DDR3 Only)
4067 # PSU_DDR_PHY_DCR_PDQ 0x0
4070 # PSU_DDR_PHY_DCR_DDR8BNK 0x1
4073 # PSU_DDR_PHY_DCR_DDRMD 0x4
4075 # DRAM Configuration Register
4076 #(OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) */
4077 mask_write 0XFD080100 0xFFFFFFFF 0x0800040C
4078 # Register : DTPR0 @ 0XFD080110</p>
4080 # Reserved. Return zeroes on reads.
4081 # PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0
4083 # Activate to activate command delay (different banks)
4084 # PSU_DDR_PHY_DTPR0_TRRD 0x6
4086 # Reserved. Return zeroes on reads.
4087 # PSU_DDR_PHY_DTPR0_RESERVED_23 0x0
4089 # Activate to precharge command delay
4090 # PSU_DDR_PHY_DTPR0_TRAS 0x24
4092 # Reserved. Return zeroes on reads.
4093 # PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
4095 # Precharge command period
4096 # PSU_DDR_PHY_DTPR0_TRP 0x12
4098 # Reserved. Return zeroes on reads.
4099 # PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
4101 # Internal read to precharge command delay
4102 # PSU_DDR_PHY_DTPR0_TRTP 0x8
4104 # DRAM Timing Parameters Register 0
4105 #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06241208U) */
4106 mask_write 0XFD080110 0xFFFFFFFF 0x06241208
4107 # Register : DTPR1 @ 0XFD080114</p>
4109 # Reserved. Return zeroes on reads.
4110 # PSU_DDR_PHY_DTPR1_RESERVED_31 0x0
4112 # Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
4113 # PSU_DDR_PHY_DTPR1_TWLMRD 0x28
4115 # Reserved. Return zeroes on reads.
4116 # PSU_DDR_PHY_DTPR1_RESERVED_23 0x0
4118 # 4-bank activate period
4119 # PSU_DDR_PHY_DTPR1_TFAW 0x18
4121 # Reserved. Return zeroes on reads.
4122 # PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0
4124 # Load mode update delay (DDR4 and DDR3 only)
4125 # PSU_DDR_PHY_DTPR1_TMOD 0x7
4127 # Reserved. Return zeroes on reads.
4128 # PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0
4130 # Load mode cycle time
4131 # PSU_DDR_PHY_DTPR1_TMRD 0x8
4133 # DRAM Timing Parameters Register 1
4134 #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) */
4135 mask_write 0XFD080114 0xFFFFFFFF 0x28180708
4136 # Register : DTPR2 @ 0XFD080118</p>
4138 # Reserved. Return zeroes on reads.
4139 # PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0
4141 # Read to Write command delay. Valid values are
4142 # PSU_DDR_PHY_DTPR2_TRTW 0x0
4144 # Reserved. Return zeroes on reads.
4145 # PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0
4147 # Read to ODT delay (DDR3 only)
4148 # PSU_DDR_PHY_DTPR2_TRTODT 0x0
4150 # Reserved. Return zeroes on reads.
4151 # PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0
4153 # CKE minimum pulse width
4154 # PSU_DDR_PHY_DTPR2_TCKE 0x8
4156 # Reserved. Return zeroes on reads.
4157 # PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0
4159 # Self refresh exit delay
4160 # PSU_DDR_PHY_DTPR2_TXS 0x200
4162 # DRAM Timing Parameters Register 2
4163 #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) */
4164 mask_write 0XFD080118 0xFFFFFFFF 0x00080200
4165 # Register : DTPR3 @ 0XFD08011C</p>
4167 # ODT turn-off delay extension
4168 # PSU_DDR_PHY_DTPR3_TOFDX 0x4
4170 # Read to read and write to write command delay
4171 # PSU_DDR_PHY_DTPR3_TCCD 0x0
4174 # PSU_DDR_PHY_DTPR3_TDLLK 0x300
4176 # Reserved. Return zeroes on reads.
4177 # PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0
4179 # Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
4180 # PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8
4182 # Reserved. Return zeroes on reads.
4183 # PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
4185 # DQS output access time from CK/CK# (LPDDR2/3 only)
4186 # PSU_DDR_PHY_DTPR3_TDQSCK 0x4
4188 # DRAM Timing Parameters Register 3
4189 #(OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000804U) */
4190 mask_write 0XFD08011C 0xFFFFFFFF 0x83000804
4191 # Register : DTPR4 @ 0XFD080120</p>
4193 # Reserved. Return zeroes on reads.
4194 # PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0
4196 # ODT turn-on/turn-off delays (DDR2 only)
4197 # PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0
4199 # Reserved. Return zeroes on reads.
4200 # PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0
4202 # Refresh-to-Refresh
4203 # PSU_DDR_PHY_DTPR4_TRFC 0x116
4205 # Reserved. Return zeroes on reads.
4206 # PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0
4208 # Write leveling output delay
4209 # PSU_DDR_PHY_DTPR4_TWLO 0x2b
4211 # Reserved. Return zeroes on reads.
4212 # PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0
4214 # Power down exit delay
4215 # PSU_DDR_PHY_DTPR4_TXP 0x8
4217 # DRAM Timing Parameters Register 4
4218 #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) */
4219 mask_write 0XFD080120 0xFFFFFFFF 0x01162B08
4220 # Register : DTPR5 @ 0XFD080124</p>
4222 # Reserved. Return zeroes on reads.
4223 # PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0
4225 # Activate to activate command delay (same bank)
4226 # PSU_DDR_PHY_DTPR5_TRC 0x32
4228 # Reserved. Return zeroes on reads.
4229 # PSU_DDR_PHY_DTPR5_RESERVED_15 0x0
4231 # Activate to read or write delay
4232 # PSU_DDR_PHY_DTPR5_TRCD 0xf
4234 # Reserved. Return zeroes on reads.
4235 # PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0
4237 # Internal write to read command delay
4238 # PSU_DDR_PHY_DTPR5_TWTR 0x9
4240 # DRAM Timing Parameters Register 5
4241 #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) */
4242 mask_write 0XFD080124 0xFFFFFFFF 0x00320F09
4243 # Register : DTPR6 @ 0XFD080128</p>
4245 # PUB Write Latency Enable
4246 # PSU_DDR_PHY_DTPR6_PUBWLEN 0x0
4248 # PUB Read Latency Enable
4249 # PSU_DDR_PHY_DTPR6_PUBRLEN 0x0
4251 # Reserved. Return zeroes on reads.
4252 # PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0
4255 # PSU_DDR_PHY_DTPR6_PUBWL 0xe
4257 # Reserved. Return zeroes on reads.
4258 # PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0
4261 # PSU_DDR_PHY_DTPR6_PUBRL 0xf
4263 # DRAM Timing Parameters Register 6
4264 #(OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) */
4265 mask_write 0XFD080128 0xFFFFFFFF 0x00000E0F
4266 # Register : RDIMMGCR0 @ 0XFD080140</p>
4268 # Reserved. Return zeroes on reads.
4269 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0
4271 # RDMIMM Quad CS Enable
4272 # PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0
4274 # Reserved. Return zeroes on reads.
4275 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0
4277 # RDIMM Outputs I/O Mode
4278 # PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1
4280 # Reserved. Return zeroes on reads.
4281 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0
4283 # ERROUT# Output Enable
4284 # PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0
4287 # PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1
4289 # ERROUT# Power Down Receiver
4290 # PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0
4292 # Reserved. Return zeroes on reads.
4293 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0
4295 # ERROUT# On-Die Termination
4296 # PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0
4299 # PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0
4302 # PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0
4304 # Reserved. Return zeroes on reads.
4305 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0
4307 # Reserved. Return zeroes on reads.
4308 # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0
4310 # Rank Mirror Enable.
4311 # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2
4313 # Reserved. Return zeroes on reads.
4314 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0
4316 # Stop on Parity Error
4317 # PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0
4319 # Parity Error No Registering
4320 # PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0
4323 # PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0
4325 # RDIMM General Configuration Register 0
4326 #(OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) */
4327 mask_write 0XFD080140 0xFFFFFFFF 0x08400020
4328 # Register : RDIMMGCR1 @ 0XFD080144</p>
4330 # Reserved. Return zeroes on reads.
4331 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0
4333 # Address [17] B-side Inversion Disable
4334 # PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0
4336 # Reserved. Return zeroes on reads.
4337 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0
4339 # Command word to command word programming delay
4340 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0
4342 # Reserved. Return zeroes on reads.
4343 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0
4345 # Command word to command word programming delay
4346 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0
4348 # Reserved. Return zeroes on reads.
4349 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0
4351 # Command word to command word programming delay
4352 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0
4354 # Reserved. Return zeroes on reads.
4355 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0
4357 # Stabilization time
4358 # PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80
4360 # RDIMM General Configuration Register 1
4361 #(OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) */
4362 mask_write 0XFD080144 0xFFFFFFFF 0x00000C80
4363 # Register : RDIMMCR1 @ 0XFD080154</p>
4366 # PSU_DDR_PHY_RDIMMCR1_RC15 0x0
4368 # DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
4369 # PSU_DDR_PHY_RDIMMCR1_RC14 0x0
4371 # DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
4372 # PSU_DDR_PHY_RDIMMCR1_RC13 0x0
4374 # DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
4375 # PSU_DDR_PHY_RDIMMCR1_RC12 0x0
4377 # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
4379 # PSU_DDR_PHY_RDIMMCR1_RC11 0x0
4381 # DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
4382 # PSU_DDR_PHY_RDIMMCR1_RC10 0x2
4384 # DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
4385 # PSU_DDR_PHY_RDIMMCR1_RC9 0x0
4387 # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
4389 # PSU_DDR_PHY_RDIMMCR1_RC8 0x0
4391 # RDIMM Control Register 1
4392 #(OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) */
4393 mask_write 0XFD080154 0xFFFFFFFF 0x00000200
4394 # Register : MR0 @ 0XFD080180</p>
4396 # Reserved. Return zeroes on reads.
4397 # PSU_DDR_PHY_MR0_RESERVED_31_8 0x8
4399 # CA Terminating Rank
4400 # PSU_DDR_PHY_MR0_CATR 0x0
4402 # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4403 # PSU_DDR_PHY_MR0_RSVD_6_5 0x1
4405 # Built-in Self-Test for RZQ
4406 # PSU_DDR_PHY_MR0_RZQI 0x2
4408 # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4409 # PSU_DDR_PHY_MR0_RSVD_2_0 0x0
4411 # LPDDR4 Mode Register 0
4412 #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) */
4413 mask_write 0XFD080180 0xFFFFFFFF 0x00000830
4414 # Register : MR1 @ 0XFD080184</p>
4416 # Reserved. Return zeroes on reads.
4417 # PSU_DDR_PHY_MR1_RESERVED_31_8 0x3
4419 # Read Postamble Length
4420 # PSU_DDR_PHY_MR1_RDPST 0x0
4422 # Write-recovery for auto-precharge command
4423 # PSU_DDR_PHY_MR1_NWR 0x0
4425 # Read Preamble Length
4426 # PSU_DDR_PHY_MR1_RDPRE 0x0
4428 # Write Preamble Length
4429 # PSU_DDR_PHY_MR1_WRPRE 0x0
4432 # PSU_DDR_PHY_MR1_BL 0x1
4434 # LPDDR4 Mode Register 1
4435 #(OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) */
4436 mask_write 0XFD080184 0xFFFFFFFF 0x00000301
4437 # Register : MR2 @ 0XFD080188</p>
4439 # Reserved. Return zeroes on reads.
4440 # PSU_DDR_PHY_MR2_RESERVED_31_8 0x0
4443 # PSU_DDR_PHY_MR2_WRL 0x0
4446 # PSU_DDR_PHY_MR2_WLS 0x0
4449 # PSU_DDR_PHY_MR2_WL 0x4
4452 # PSU_DDR_PHY_MR2_RL 0x0
4454 # LPDDR4 Mode Register 2
4455 #(OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) */
4456 mask_write 0XFD080188 0xFFFFFFFF 0x00000020
4457 # Register : MR3 @ 0XFD08018C</p>
4459 # Reserved. Return zeroes on reads.
4460 # PSU_DDR_PHY_MR3_RESERVED_31_8 0x2
4463 # PSU_DDR_PHY_MR3_DBIWR 0x0
4466 # PSU_DDR_PHY_MR3_DBIRD 0x0
4468 # Pull-down Drive Strength
4469 # PSU_DDR_PHY_MR3_PDDS 0x0
4471 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4472 # PSU_DDR_PHY_MR3_RSVD 0x0
4474 # Write Postamble Length
4475 # PSU_DDR_PHY_MR3_WRPST 0x0
4477 # Pull-up Calibration Point
4478 # PSU_DDR_PHY_MR3_PUCAL 0x0
4480 # LPDDR4 Mode Register 3
4481 #(OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) */
4482 mask_write 0XFD08018C 0xFFFFFFFF 0x00000200
4483 # Register : MR4 @ 0XFD080190</p>
4485 # Reserved. Return zeroes on reads.
4486 # PSU_DDR_PHY_MR4_RESERVED_31_16 0x0
4488 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4489 # PSU_DDR_PHY_MR4_RSVD_15_13 0x0
4492 # PSU_DDR_PHY_MR4_WRP 0x0
4495 # PSU_DDR_PHY_MR4_RDP 0x0
4497 # Read Preamble Training Mode
4498 # PSU_DDR_PHY_MR4_RPTM 0x0
4500 # Self Refresh Abort
4501 # PSU_DDR_PHY_MR4_SRA 0x0
4503 # CS to Command Latency Mode
4504 # PSU_DDR_PHY_MR4_CS2CMDL 0x0
4506 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4507 # PSU_DDR_PHY_MR4_RSVD1 0x0
4509 # Internal VREF Monitor
4510 # PSU_DDR_PHY_MR4_IVM 0x0
4512 # Temperature Controlled Refresh Mode
4513 # PSU_DDR_PHY_MR4_TCRM 0x0
4515 # Temperature Controlled Refresh Range
4516 # PSU_DDR_PHY_MR4_TCRR 0x0
4518 # Maximum Power Down Mode
4519 # PSU_DDR_PHY_MR4_MPDM 0x0
4521 # This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
4522 # PSU_DDR_PHY_MR4_RSVD_0 0x0
4524 # DDR4 Mode Register 4
4525 #(OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) */
4526 mask_write 0XFD080190 0xFFFFFFFF 0x00000000
4527 # Register : MR5 @ 0XFD080194</p>
4529 # Reserved. Return zeroes on reads.
4530 # PSU_DDR_PHY_MR5_RESERVED_31_16 0x0
4532 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4533 # PSU_DDR_PHY_MR5_RSVD 0x0
4536 # PSU_DDR_PHY_MR5_RDBI 0x0
4539 # PSU_DDR_PHY_MR5_WDBI 0x0
4542 # PSU_DDR_PHY_MR5_DM 0x1
4544 # CA Parity Persistent Error
4545 # PSU_DDR_PHY_MR5_CAPPE 0x1
4548 # PSU_DDR_PHY_MR5_RTTPARK 0x3
4550 # ODT Input Buffer during Power Down mode
4551 # PSU_DDR_PHY_MR5_ODTIBPD 0x0
4553 # C/A Parity Error Status
4554 # PSU_DDR_PHY_MR5_CAPES 0x0
4557 # PSU_DDR_PHY_MR5_CRCEC 0x0
4559 # C/A Parity Latency Mode
4560 # PSU_DDR_PHY_MR5_CAPM 0x0
4562 # DDR4 Mode Register 5
4563 #(OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) */
4564 mask_write 0XFD080194 0xFFFFFFFF 0x000006C0
4565 # Register : MR6 @ 0XFD080198</p>
4567 # Reserved. Return zeroes on reads.
4568 # PSU_DDR_PHY_MR6_RESERVED_31_16 0x0
4570 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4571 # PSU_DDR_PHY_MR6_RSVD_15_13 0x0
4573 # CAS_n to CAS_n command delay for same bank group (tCCD_L)
4574 # PSU_DDR_PHY_MR6_TCCDL 0x2
4576 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4577 # PSU_DDR_PHY_MR6_RSVD_9_8 0x0
4579 # VrefDQ Training Enable
4580 # PSU_DDR_PHY_MR6_VDDQTEN 0x0
4582 # VrefDQ Training Range
4583 # PSU_DDR_PHY_MR6_VDQTRG 0x0
4585 # VrefDQ Training Values
4586 # PSU_DDR_PHY_MR6_VDQTVAL 0x19
4588 # DDR4 Mode Register 6
4589 #(OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) */
4590 mask_write 0XFD080198 0xFFFFFFFF 0x00000819
4591 # Register : MR11 @ 0XFD0801AC</p>
4593 # Reserved. Return zeroes on reads.
4594 # PSU_DDR_PHY_MR11_RESERVED_31_8 0x0
4596 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4597 # PSU_DDR_PHY_MR11_RSVD 0x0
4599 # Power Down Control
4600 # PSU_DDR_PHY_MR11_PDCTL 0x0
4602 # DQ Bus Receiver On-Die-Termination
4603 # PSU_DDR_PHY_MR11_DQODT 0x0
4605 # LPDDR4 Mode Register 11
4606 #(OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) */
4607 mask_write 0XFD0801AC 0xFFFFFFFF 0x00000000
4608 # Register : MR12 @ 0XFD0801B0</p>
4610 # Reserved. Return zeroes on reads.
4611 # PSU_DDR_PHY_MR12_RESERVED_31_8 0x0
4613 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4614 # PSU_DDR_PHY_MR12_RSVD 0x0
4616 # VREF_CA Range Select.
4617 # PSU_DDR_PHY_MR12_VR_CA 0x1
4619 # Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
4620 # PSU_DDR_PHY_MR12_VREF_CA 0xd
4622 # LPDDR4 Mode Register 12
4623 #(OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) */
4624 mask_write 0XFD0801B0 0xFFFFFFFF 0x0000004D
4625 # Register : MR13 @ 0XFD0801B4</p>
4627 # Reserved. Return zeroes on reads.
4628 # PSU_DDR_PHY_MR13_RESERVED_31_8 0x0
4630 # Frequency Set Point Operation Mode
4631 # PSU_DDR_PHY_MR13_FSPOP 0x0
4633 # Frequency Set Point Write Enable
4634 # PSU_DDR_PHY_MR13_FSPWR 0x0
4637 # PSU_DDR_PHY_MR13_DMD 0x0
4639 # Refresh Rate Option
4640 # PSU_DDR_PHY_MR13_RRO 0x0
4642 # VREF Current Generator
4643 # PSU_DDR_PHY_MR13_VRCG 0x1
4646 # PSU_DDR_PHY_MR13_VRO 0x0
4648 # Read Preamble Training Mode
4649 # PSU_DDR_PHY_MR13_RPT 0x0
4651 # Command Bus Training
4652 # PSU_DDR_PHY_MR13_CBT 0x0
4654 # LPDDR4 Mode Register 13
4655 #(OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) */
4656 mask_write 0XFD0801B4 0xFFFFFFFF 0x00000008
4657 # Register : MR14 @ 0XFD0801B8</p>
4659 # Reserved. Return zeroes on reads.
4660 # PSU_DDR_PHY_MR14_RESERVED_31_8 0x0
4662 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4663 # PSU_DDR_PHY_MR14_RSVD 0x0
4665 # VREFDQ Range Selects.
4666 # PSU_DDR_PHY_MR14_VR_DQ 0x1
4668 # Reserved. Return zeroes on reads.
4669 # PSU_DDR_PHY_MR14_VREF_DQ 0xd
4671 # LPDDR4 Mode Register 14
4672 #(OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) */
4673 mask_write 0XFD0801B8 0xFFFFFFFF 0x0000004D
4674 # Register : MR22 @ 0XFD0801D8</p>
4676 # Reserved. Return zeroes on reads.
4677 # PSU_DDR_PHY_MR22_RESERVED_31_8 0x0
4679 # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
4680 # PSU_DDR_PHY_MR22_RSVD 0x0
4682 # CA ODT termination disable.
4683 # PSU_DDR_PHY_MR22_ODTD_CA 0x0
4686 # PSU_DDR_PHY_MR22_ODTE_CS 0x0
4689 # PSU_DDR_PHY_MR22_ODTE_CK 0x0
4691 # Controller ODT value for VOH calibration.
4692 # PSU_DDR_PHY_MR22_CODT 0x0
4694 # LPDDR4 Mode Register 22
4695 #(OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) */
4696 mask_write 0XFD0801D8 0xFFFFFFFF 0x00000000
4697 # Register : DTCR0 @ 0XFD080200</p>
4699 # Refresh During Training
4700 # PSU_DDR_PHY_DTCR0_RFSHDT 0x8
4702 # Reserved. Return zeroes on reads.
4703 # PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
4705 # Data Training Debug Rank Select
4706 # PSU_DDR_PHY_DTCR0_DTDRS 0x1
4708 # Data Training with Early/Extended Gate
4709 # PSU_DDR_PHY_DTCR0_DTEXG 0x0
4711 # Data Training Extended Write DQS
4712 # PSU_DDR_PHY_DTCR0_DTEXD 0x0
4714 # Data Training Debug Step
4715 # PSU_DDR_PHY_DTCR0_DTDSTP 0x0
4717 # Data Training Debug Enable
4718 # PSU_DDR_PHY_DTCR0_DTDEN 0x0
4720 # Data Training Debug Byte Select
4721 # PSU_DDR_PHY_DTCR0_DTDBS 0x0
4723 # Data Training read DBI deskewing configuration
4724 # PSU_DDR_PHY_DTCR0_DTRDBITR 0x0
4726 # Reserved. Return zeroes on reads.
4727 # PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
4729 # Data Training Write Bit Deskew Data Mask
4730 # PSU_DDR_PHY_DTCR0_DTWBDDM 0x1
4732 # Refreshes Issued During Entry to Training
4733 # PSU_DDR_PHY_DTCR0_RFSHEN 0x1
4735 # Data Training Compare Data
4736 # PSU_DDR_PHY_DTCR0_DTCMPD 0x1
4738 # Data Training Using MPR
4739 # PSU_DDR_PHY_DTCR0_DTMPR 0x1
4741 # Reserved. Return zeroes on reads.
4742 # PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0
4744 # Data Training Repeat Number
4745 # PSU_DDR_PHY_DTCR0_DTRPTN 0x7
4747 # Data Training Configuration Register 0
4748 #(OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x810011C7U) */
4749 mask_write 0XFD080200 0xFFFFFFFF 0x810011C7
4750 # Register : DTCR1 @ 0XFD080204</p>
4753 # PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0
4756 # PSU_DDR_PHY_DTCR1_RANKEN 0x1
4758 # Reserved. Return zeroes on reads.
4759 # PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0
4761 # Data Training Rank
4762 # PSU_DDR_PHY_DTCR1_DTRANK 0x0
4764 # Reserved. Return zeroes on reads.
4765 # PSU_DDR_PHY_DTCR1_RESERVED_11 0x0
4767 # Read Leveling Gate Sampling Difference
4768 # PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2
4770 # Reserved. Return zeroes on reads.
4771 # PSU_DDR_PHY_DTCR1_RESERVED_7 0x0
4773 # Read Leveling Gate Shift
4774 # PSU_DDR_PHY_DTCR1_RDLVLGS 0x3
4776 # Reserved. Return zeroes on reads.
4777 # PSU_DDR_PHY_DTCR1_RESERVED_3 0x0
4779 # Read Preamble Training enable
4780 # PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1
4782 # Read Leveling Enable
4783 # PSU_DDR_PHY_DTCR1_RDLVLEN 0x1
4785 # Basic Gate Training Enable
4786 # PSU_DDR_PHY_DTCR1_BSTEN 0x0
4788 # Data Training Configuration Register 1
4789 #(OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) */
4790 mask_write 0XFD080204 0xFFFFFFFF 0x00010236
4791 # Register : CATR0 @ 0XFD080240</p>
4793 # Reserved. Return zeroes on reads.
4794 # PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0
4796 # Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
4797 # PSU_DDR_PHY_CATR0_CACD 0x14
4799 # Reserved. Return zeroes on reads.
4800 # PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0
4802 # Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
4803 # been sent to the memory
4804 # PSU_DDR_PHY_CATR0_CAADR 0x10
4806 # CA_1 Response Byte Lane 1
4807 # PSU_DDR_PHY_CATR0_CA1BYTE1 0x5
4809 # CA_1 Response Byte Lane 0
4810 # PSU_DDR_PHY_CATR0_CA1BYTE0 0x4
4812 # CA Training Register 0
4813 #(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */
4814 mask_write 0XFD080240 0xFFFFFFFF 0x00141054
4815 # Register : RIOCR5 @ 0XFD0804F4</p>
4817 # Reserved. Return zeroes on reads.
4818 # PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0
4820 # Reserved. Return zeros on reads.
4821 # PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0
4823 # SDRAM On-die Termination Output Enable (OE) Mode Selection.
4824 # PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5
4826 # Rank I/O Configuration Register 5
4827 #(OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) */
4828 mask_write 0XFD0804F4 0xFFFFFFFF 0x00000005
4829 # Register : ACIOCR0 @ 0XFD080500</p>
4831 # Address/Command Slew Rate (D3F I/O Only)
4832 # PSU_DDR_PHY_ACIOCR0_ACSR 0x0
4834 # SDRAM Reset I/O Mode
4835 # PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1
4837 # SDRAM Reset Power Down Receiver
4838 # PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1
4840 # Reserved. Return zeroes on reads.
4841 # PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0
4843 # SDRAM Reset On-Die Termination
4844 # PSU_DDR_PHY_ACIOCR0_RSTODT 0x0
4846 # Reserved. Return zeroes on reads.
4847 # PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0
4849 # CK Duty Cycle Correction
4850 # PSU_DDR_PHY_ACIOCR0_CKDCC 0x0
4852 # AC Power Down Receiver Mode
4853 # PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2
4855 # AC On-die Termination Mode
4856 # PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2
4858 # Reserved. Return zeroes on reads.
4859 # PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0
4861 # Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
4862 # PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0
4864 # AC I/O Configuration Register 0
4865 #(OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) */
4866 mask_write 0XFD080500 0xFFFFFFFF 0x30000028
4867 # Register : ACIOCR2 @ 0XFD080508</p>
4869 # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
4870 # PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0
4872 # Clock gating for Output Enable D slices [0]
4873 # PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0
4875 # Clock gating for Power Down Receiver D slices [0]
4876 # PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0
4878 # Clock gating for Termination Enable D slices [0]
4879 # PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0
4881 # Clock gating for CK# D slices [1:0]
4882 # PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2
4884 # Clock gating for CK D slices [1:0]
4885 # PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2
4887 # Clock gating for AC D slices [23:0]
4888 # PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0
4890 # AC I/O Configuration Register 2
4891 #(OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) */
4892 mask_write 0XFD080508 0xFFFFFFFF 0x0A000000
4893 # Register : ACIOCR3 @ 0XFD08050C</p>
4895 # SDRAM Parity Output Enable (OE) Mode Selection
4896 # PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0
4898 # SDRAM Bank Group Output Enable (OE) Mode Selection
4899 # PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0
4901 # SDRAM Bank Address Output Enable (OE) Mode Selection
4902 # PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0
4904 # SDRAM A[17] Output Enable (OE) Mode Selection
4905 # PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0
4907 # SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
4908 # PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0
4910 # SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
4911 # PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0
4913 # Reserved. Return zeroes on reads.
4914 # PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0
4916 # Reserved. Return zeros on reads.
4917 # PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0
4919 # SDRAM CK Output Enable (OE) Mode Selection.
4920 # PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9
4922 # AC I/O Configuration Register 3
4923 #(OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) */
4924 mask_write 0XFD08050C 0xFFFFFFFF 0x00000009
4925 # Register : ACIOCR4 @ 0XFD080510</p>
4927 # Clock gating for AC LB slices and loopback read valid slices
4928 # PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0
4930 # Clock gating for Output Enable D slices [1]
4931 # PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0
4933 # Clock gating for Power Down Receiver D slices [1]
4934 # PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0
4936 # Clock gating for Termination Enable D slices [1]
4937 # PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0
4939 # Clock gating for CK# D slices [3:2]
4940 # PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2
4942 # Clock gating for CK D slices [3:2]
4943 # PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2
4945 # Clock gating for AC D slices [47:24]
4946 # PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0
4948 # AC I/O Configuration Register 4
4949 #(OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) */
4950 mask_write 0XFD080510 0xFFFFFFFF 0x0A000000
4951 # Register : IOVCR0 @ 0XFD080520</p>
4953 # Reserved. Return zeroes on reads.
4954 # PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0
4956 # Address/command lane VREF Pad Enable
4957 # PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0
4959 # Address/command lane Internal VREF Enable
4960 # PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0
4962 # Address/command lane Single-End VREF Enable
4963 # PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1
4965 # Address/command lane Internal VREF Enable
4966 # PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1
4968 # External VREF generato REFSEL range select
4969 # PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0
4971 # Address/command lane External VREF Select
4972 # PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0
4974 # Single ended VREF generator REFSEL range select
4975 # PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1
4977 # Address/command lane Single-End VREF Select
4978 # PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30
4980 # Internal VREF generator REFSEL ragne select
4981 # PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1
4983 # REFSEL Control for internal AC IOs
4984 # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30
4986 # IO VREF Control Register 0
4987 #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) */
4988 mask_write 0XFD080520 0xFFFFFFFF 0x0300B0B0
4989 # Register : VTCR0 @ 0XFD080528</p>
4991 # Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
4992 # PSU_DDR_PHY_VTCR0_TVREF 0x7
4994 # DRM DQ VREF training Enable
4995 # PSU_DDR_PHY_VTCR0_DVEN 0x1
4997 # Per Device Addressability Enable
4998 # PSU_DDR_PHY_VTCR0_PDAEN 0x1
5000 # Reserved. Returns zeroes on reads.
5001 # PSU_DDR_PHY_VTCR0_RESERVED_26 0x0
5004 # PSU_DDR_PHY_VTCR0_VWCR 0x4
5006 # DRAM DQ VREF step size used during DRAM VREF training
5007 # PSU_DDR_PHY_VTCR0_DVSS 0x0
5009 # Maximum VREF limit value used during DRAM VREF training
5010 # PSU_DDR_PHY_VTCR0_DVMAX 0x32
5012 # Minimum VREF limit value used during DRAM VREF training
5013 # PSU_DDR_PHY_VTCR0_DVMIN 0x0
5015 # Initial DRAM DQ VREF value used during DRAM VREF training
5016 # PSU_DDR_PHY_VTCR0_DVINIT 0x19
5018 # VREF Training Control Register 0
5019 #(OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) */
5020 mask_write 0XFD080528 0xFFFFFFFF 0xF9032019
5021 # Register : VTCR1 @ 0XFD08052C</p>
5023 # Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
5024 # PSU_DDR_PHY_VTCR1_HVSS 0x0
5026 # Reserved. Returns zeroes on reads.
5027 # PSU_DDR_PHY_VTCR1_RESERVED_27 0x0
5029 # Maximum VREF limit value used during DRAM VREF training.
5030 # PSU_DDR_PHY_VTCR1_HVMAX 0x7f
5032 # Reserved. Returns zeroes on reads.
5033 # PSU_DDR_PHY_VTCR1_RESERVED_19 0x0
5035 # Minimum VREF limit value used during DRAM VREF training.
5036 # PSU_DDR_PHY_VTCR1_HVMIN 0x0
5038 # Reserved. Returns zeroes on reads.
5039 # PSU_DDR_PHY_VTCR1_RESERVED_11 0x0
5041 # Static Host Vref Rank Value
5042 # PSU_DDR_PHY_VTCR1_SHRNK 0x0
5044 # Static Host Vref Rank Enable
5045 # PSU_DDR_PHY_VTCR1_SHREN 0x1
5047 # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
5048 # PSU_DDR_PHY_VTCR1_TVREFIO 0x4
5050 # Eye LCDL Offset value for VREF training
5051 # PSU_DDR_PHY_VTCR1_EOFF 0x1
5053 # Number of LCDL Eye points for which VREF training is repeated
5054 # PSU_DDR_PHY_VTCR1_ENUM 0x1
5056 # HOST (IO) internal VREF training Enable
5057 # PSU_DDR_PHY_VTCR1_HVEN 0x1
5059 # Host IO Type Control
5060 # PSU_DDR_PHY_VTCR1_HVIO 0x1
5062 # VREF Training Control Register 1
5063 #(OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU) */
5064 mask_write 0XFD08052C 0xFFFFFFFF 0x07F0018F
5065 # Register : ACBDLR6 @ 0XFD080558</p>
5067 # Reserved. Return zeroes on reads.
5068 # PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
5070 # Delay select for the BDL on Address A[3].
5071 # PSU_DDR_PHY_ACBDLR6_A03BD 0x0
5073 # Reserved. Return zeroes on reads.
5074 # PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
5076 # Delay select for the BDL on Address A[2].
5077 # PSU_DDR_PHY_ACBDLR6_A02BD 0x0
5079 # Reserved. Return zeroes on reads.
5080 # PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
5082 # Delay select for the BDL on Address A[1].
5083 # PSU_DDR_PHY_ACBDLR6_A01BD 0x0
5085 # Reserved. Return zeroes on reads.
5086 # PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
5088 # Delay select for the BDL on Address A[0].
5089 # PSU_DDR_PHY_ACBDLR6_A00BD 0x0
5091 # AC Bit Delay Line Register 6
5092 #(OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) */
5093 mask_write 0XFD080558 0xFFFFFFFF 0x00000000
5094 # Register : ACBDLR7 @ 0XFD08055C</p>
5096 # Reserved. Return zeroes on reads.
5097 # PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
5099 # Delay select for the BDL on Address A[7].
5100 # PSU_DDR_PHY_ACBDLR7_A07BD 0x0
5102 # Reserved. Return zeroes on reads.
5103 # PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
5105 # Delay select for the BDL on Address A[6].
5106 # PSU_DDR_PHY_ACBDLR7_A06BD 0x0
5108 # Reserved. Return zeroes on reads.
5109 # PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0
5111 # Delay select for the BDL on Address A[5].
5112 # PSU_DDR_PHY_ACBDLR7_A05BD 0x0
5114 # Reserved. Return zeroes on reads.
5115 # PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0
5117 # Delay select for the BDL on Address A[4].
5118 # PSU_DDR_PHY_ACBDLR7_A04BD 0x0
5120 # AC Bit Delay Line Register 7
5121 #(OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) */
5122 mask_write 0XFD08055C 0xFFFFFFFF 0x00000000
5123 # Register : ACBDLR8 @ 0XFD080560</p>
5125 # Reserved. Return zeroes on reads.
5126 # PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0
5128 # Delay select for the BDL on Address A[11].
5129 # PSU_DDR_PHY_ACBDLR8_A11BD 0x0
5131 # Reserved. Return zeroes on reads.
5132 # PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0
5134 # Delay select for the BDL on Address A[10].
5135 # PSU_DDR_PHY_ACBDLR8_A10BD 0x0
5137 # Reserved. Return zeroes on reads.
5138 # PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0
5140 # Delay select for the BDL on Address A[9].
5141 # PSU_DDR_PHY_ACBDLR8_A09BD 0x0
5143 # Reserved. Return zeroes on reads.
5144 # PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0
5146 # Delay select for the BDL on Address A[8].
5147 # PSU_DDR_PHY_ACBDLR8_A08BD 0x0
5149 # AC Bit Delay Line Register 8
5150 #(OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) */
5151 mask_write 0XFD080560 0xFFFFFFFF 0x00000000
5152 # Register : ZQCR @ 0XFD080680</p>
5154 # Reserved. Return zeroes on reads.
5155 # PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
5158 # PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0
5160 # Programmable Wait for Frequency B
5161 # PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11
5163 # Programmable Wait for Frequency A
5164 # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11
5166 # ZQ VREF Pad Enable
5167 # PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0
5169 # ZQ Internal VREF Enable
5170 # PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1
5172 # Choice of termination mode
5173 # PSU_DDR_PHY_ZQCR_ODT_MODE 0x1
5175 # Force ZCAL VT update
5176 # PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0
5179 # PSU_DDR_PHY_ZQCR_IODLMT 0x2
5181 # Averaging algorithm enable, if set, enables averaging algorithm
5182 # PSU_DDR_PHY_ZQCR_AVGEN 0x1
5184 # Maximum number of averaging rounds to be used by averaging algorithm
5185 # PSU_DDR_PHY_ZQCR_AVGMAX 0x2
5187 # ZQ Calibration Type
5188 # PSU_DDR_PHY_ZQCR_ZCALT 0x0
5191 # PSU_DDR_PHY_ZQCR_ZQPD 0x0
5193 # ZQ Impedance Control Register
5194 #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) */
5195 mask_write 0XFD080680 0xFFFFFFFF 0x008A2A58
5196 # Register : ZQ0PR0 @ 0XFD080684</p>
5198 # Pull-down drive strength ZCTRL over-ride enable
5199 # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0
5201 # Pull-up drive strength ZCTRL over-ride enable
5202 # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0
5204 # Pull-down termination ZCTRL over-ride enable
5205 # PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0
5207 # Pull-up termination ZCTRL over-ride enable
5208 # PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0
5210 # Calibration segment bypass
5211 # PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0
5213 # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
5214 # PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0
5216 # Termination adjustment
5217 # PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0
5219 # Pulldown drive strength adjustment
5220 # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0
5222 # Pullup drive strength adjustment
5223 # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0
5225 # DRAM Impedance Divide Ratio
5226 # PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7
5228 # HOST Impedance Divide Ratio
5229 # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7
5231 # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
5232 # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd
5234 # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
5235 # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd
5237 # ZQ n Impedance Control Program Register 0
5238 #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) */
5239 mask_write 0XFD080684 0xFFFFFFFF 0x000077DD
5240 # Register : ZQ0OR0 @ 0XFD080694</p>
5242 # Reserved. Return zeros on reads.
5243 # PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0
5245 # Override value for the pull-up output impedance
5246 # PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1
5248 # Reserved. Return zeros on reads.
5249 # PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0
5251 # Override value for the pull-down output impedance
5252 # PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210
5254 # ZQ n Impedance Control Override Data Register 0
5255 #(OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) */
5256 mask_write 0XFD080694 0xFFFFFFFF 0x01E10210
5257 # Register : ZQ0OR1 @ 0XFD080698</p>
5259 # Reserved. Return zeros on reads.
5260 # PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0
5262 # Override value for the pull-up termination
5263 # PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1
5265 # Reserved. Return zeros on reads.
5266 # PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0
5268 # Override value for the pull-down termination
5269 # PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0
5271 # ZQ n Impedance Control Override Data Register 1
5272 #(OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) */
5273 mask_write 0XFD080698 0xFFFFFFFF 0x01E10000
5274 # Register : ZQ1PR0 @ 0XFD0806A4</p>
5276 # Pull-down drive strength ZCTRL over-ride enable
5277 # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0
5279 # Pull-up drive strength ZCTRL over-ride enable
5280 # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0
5282 # Pull-down termination ZCTRL over-ride enable
5283 # PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0
5285 # Pull-up termination ZCTRL over-ride enable
5286 # PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0
5288 # Calibration segment bypass
5289 # PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0
5291 # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
5292 # PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0
5294 # Termination adjustment
5295 # PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0
5297 # Pulldown drive strength adjustment
5298 # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1
5300 # Pullup drive strength adjustment
5301 # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0
5303 # DRAM Impedance Divide Ratio
5304 # PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7
5306 # HOST Impedance Divide Ratio
5307 # PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb
5309 # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
5310 # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd
5312 # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
5313 # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb
5315 # ZQ n Impedance Control Program Register 0
5316 #(OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) */
5317 mask_write 0XFD0806A4 0xFFFFFFFF 0x00087BDB
5318 # Register : DX0GCR0 @ 0XFD080700</p>
5320 # Calibration Bypass
5321 # PSU_DDR_PHY_DX0GCR0_CALBYP 0x0
5323 # Master Delay Line Enable
5324 # PSU_DDR_PHY_DX0GCR0_MDLEN 0x1
5326 # Configurable ODT(TE) Phase Shift
5327 # PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0
5329 # DQS Duty Cycle Correction
5330 # PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0
5332 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
5333 # PSU_DDR_PHY_DX0GCR0_RDDLY 0x8
5335 # Reserved. Return zeroes on reads.
5336 # PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0
5338 # DQSNSE Power Down Receiver
5339 # PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0
5341 # DQSSE Power Down Receiver
5342 # PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0
5344 # RTT On Additive Latency
5345 # PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0
5348 # PSU_DDR_PHY_DX0GCR0_RTTOH 0x3
5350 # Configurable PDR Phase Shift
5351 # PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0
5354 # PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0
5356 # DQSG Power Down Receiver
5357 # PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0
5359 # Reserved. Return zeroes on reads.
5360 # PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0
5362 # DQSG On-Die Termination
5363 # PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0
5365 # DQSG Output Enable
5366 # PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1
5368 # Reserved. Return zeroes on reads.
5369 # PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0
5371 # DATX8 n General Configuration Register 0
5372 #(OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) */
5373 mask_write 0XFD080700 0xFFFFFFFF 0x40800604
5374 # Register : DX0GCR4 @ 0XFD080710</p>
5376 # Byte lane VREF IOM (Used only by D4MU IOs)
5377 # PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0
5379 # Byte Lane VREF Pad Enable
5380 # PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0
5382 # Byte Lane Internal VREF Enable
5383 # PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3
5385 # Byte Lane Single-End VREF Enable
5386 # PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1
5388 # Reserved. Returns zeros on reads.
5389 # PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0
5391 # External VREF generator REFSEL range select
5392 # PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0
5394 # Byte Lane External VREF Select
5395 # PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0
5397 # Single ended VREF generator REFSEL range select
5398 # PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1
5400 # Byte Lane Single-End VREF Select
5401 # PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30
5403 # Reserved. Returns zeros on reads.
5404 # PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0
5406 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
5407 # PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf
5409 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
5410 # PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0
5412 # DATX8 n General Configuration Register 4
5413 #(OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) */
5414 mask_write 0XFD080710 0xFFFFFFFF 0x0E00B03C
5415 # Register : DX0GCR5 @ 0XFD080714</p>
5417 # Reserved. Returns zeros on reads.
5418 # PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0
5420 # Byte Lane internal VREF Select for Rank 3
5421 # PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9
5423 # Reserved. Returns zeros on reads.
5424 # PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0
5426 # Byte Lane internal VREF Select for Rank 2
5427 # PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9
5429 # Reserved. Returns zeros on reads.
5430 # PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
5432 # Byte Lane internal VREF Select for Rank 1
5433 # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
5435 # Reserved. Returns zeros on reads.
5436 # PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
5438 # Byte Lane internal VREF Select for Rank 0
5439 # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
5441 # DATX8 n General Configuration Register 5
5442 #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */
5443 mask_write 0XFD080714 0xFFFFFFFF 0x09095555
5444 # Register : DX0GCR6 @ 0XFD080718</p>
5446 # Reserved. Returns zeros on reads.
5447 # PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0
5449 # DRAM DQ VREF Select for Rank3
5450 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9
5452 # Reserved. Returns zeros on reads.
5453 # PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0
5455 # DRAM DQ VREF Select for Rank2
5456 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9
5458 # Reserved. Returns zeros on reads.
5459 # PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0
5461 # DRAM DQ VREF Select for Rank1
5462 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b
5464 # Reserved. Returns zeros on reads.
5465 # PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0
5467 # DRAM DQ VREF Select for Rank0
5468 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b
5470 # DATX8 n General Configuration Register 6
5471 #(OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) */
5472 mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B
5473 # Register : DX0LCDLR2 @ 0XFD080788</p>
5475 # Reserved. Return zeroes on reads.
5476 # PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0
5478 # Reserved. Caution, do not write to this register field.
5479 # PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0
5481 # Reserved. Return zeroes on reads.
5482 # PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0
5484 # Read DQS Gating Delay
5485 # PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0
5487 # DATX8 n Local Calibrated Delay Line Register 2
5488 #(OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) */
5489 mask_write 0XFD080788 0xFFFFFFFF 0x00000000
5490 # Register : DX0GTR0 @ 0XFD0807C0</p>
5492 # Reserved. Return zeroes on reads.
5493 # PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0
5495 # DQ Write Path Latency Pipeline
5496 # PSU_DDR_PHY_DX0GTR0_WDQSL 0x0
5498 # Reserved. Caution, do not write to this register field.
5499 # PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0
5501 # Write Leveling System Latency
5502 # PSU_DDR_PHY_DX0GTR0_WLSL 0x2
5504 # Reserved. Return zeroes on reads.
5505 # PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0
5507 # Reserved. Caution, do not write to this register field.
5508 # PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0
5510 # Reserved. Return zeroes on reads.
5511 # PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0
5513 # DQS Gating System Latency
5514 # PSU_DDR_PHY_DX0GTR0_DGSL 0x0
5516 # DATX8 n General Timing Register 0
5517 #(OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) */
5518 mask_write 0XFD0807C0 0xFFFFFFFF 0x00020000
5519 # Register : DX1GCR0 @ 0XFD080800</p>
5521 # Calibration Bypass
5522 # PSU_DDR_PHY_DX1GCR0_CALBYP 0x0
5524 # Master Delay Line Enable
5525 # PSU_DDR_PHY_DX1GCR0_MDLEN 0x1
5527 # Configurable ODT(TE) Phase Shift
5528 # PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0
5530 # DQS Duty Cycle Correction
5531 # PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0
5533 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
5534 # PSU_DDR_PHY_DX1GCR0_RDDLY 0x8
5536 # Reserved. Return zeroes on reads.
5537 # PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0
5539 # DQSNSE Power Down Receiver
5540 # PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0
5542 # DQSSE Power Down Receiver
5543 # PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0
5545 # RTT On Additive Latency
5546 # PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0
5549 # PSU_DDR_PHY_DX1GCR0_RTTOH 0x3
5551 # Configurable PDR Phase Shift
5552 # PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0
5555 # PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0
5557 # DQSG Power Down Receiver
5558 # PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0
5560 # Reserved. Return zeroes on reads.
5561 # PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0
5563 # DQSG On-Die Termination
5564 # PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0
5566 # DQSG Output Enable
5567 # PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1
5569 # Reserved. Return zeroes on reads.
5570 # PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0
5572 # DATX8 n General Configuration Register 0
5573 #(OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) */
5574 mask_write 0XFD080800 0xFFFFFFFF 0x40800604
5575 # Register : DX1GCR4 @ 0XFD080810</p>
5577 # Byte lane VREF IOM (Used only by D4MU IOs)
5578 # PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0
5580 # Byte Lane VREF Pad Enable
5581 # PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0
5583 # Byte Lane Internal VREF Enable
5584 # PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3
5586 # Byte Lane Single-End VREF Enable
5587 # PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1
5589 # Reserved. Returns zeros on reads.
5590 # PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0
5592 # External VREF generator REFSEL range select
5593 # PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0
5595 # Byte Lane External VREF Select
5596 # PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0
5598 # Single ended VREF generator REFSEL range select
5599 # PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1
5601 # Byte Lane Single-End VREF Select
5602 # PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30
5604 # Reserved. Returns zeros on reads.
5605 # PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0
5607 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
5608 # PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf
5610 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
5611 # PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0
5613 # DATX8 n General Configuration Register 4
5614 #(OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) */
5615 mask_write 0XFD080810 0xFFFFFFFF 0x0E00B03C
5616 # Register : DX1GCR5 @ 0XFD080814</p>
5618 # Reserved. Returns zeros on reads.
5619 # PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0
5621 # Byte Lane internal VREF Select for Rank 3
5622 # PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9
5624 # Reserved. Returns zeros on reads.
5625 # PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0
5627 # Byte Lane internal VREF Select for Rank 2
5628 # PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9
5630 # Reserved. Returns zeros on reads.
5631 # PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
5633 # Byte Lane internal VREF Select for Rank 1
5634 # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
5636 # Reserved. Returns zeros on reads.
5637 # PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
5639 # Byte Lane internal VREF Select for Rank 0
5640 # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
5642 # DATX8 n General Configuration Register 5
5643 #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */
5644 mask_write 0XFD080814 0xFFFFFFFF 0x09095555
5645 # Register : DX1GCR6 @ 0XFD080818</p>
5647 # Reserved. Returns zeros on reads.
5648 # PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0
5650 # DRAM DQ VREF Select for Rank3
5651 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9
5653 # Reserved. Returns zeros on reads.
5654 # PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0
5656 # DRAM DQ VREF Select for Rank2
5657 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9
5659 # Reserved. Returns zeros on reads.
5660 # PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0
5662 # DRAM DQ VREF Select for Rank1
5663 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b
5665 # Reserved. Returns zeros on reads.
5666 # PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0
5668 # DRAM DQ VREF Select for Rank0
5669 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b
5671 # DATX8 n General Configuration Register 6
5672 #(OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) */
5673 mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B
5674 # Register : DX1LCDLR2 @ 0XFD080888</p>
5676 # Reserved. Return zeroes on reads.
5677 # PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0
5679 # Reserved. Caution, do not write to this register field.
5680 # PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0
5682 # Reserved. Return zeroes on reads.
5683 # PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0
5685 # Read DQS Gating Delay
5686 # PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0
5688 # DATX8 n Local Calibrated Delay Line Register 2
5689 #(OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) */
5690 mask_write 0XFD080888 0xFFFFFFFF 0x00000000
5691 # Register : DX1GTR0 @ 0XFD0808C0</p>
5693 # Reserved. Return zeroes on reads.
5694 # PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0
5696 # DQ Write Path Latency Pipeline
5697 # PSU_DDR_PHY_DX1GTR0_WDQSL 0x0
5699 # Reserved. Caution, do not write to this register field.
5700 # PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0
5702 # Write Leveling System Latency
5703 # PSU_DDR_PHY_DX1GTR0_WLSL 0x2
5705 # Reserved. Return zeroes on reads.
5706 # PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0
5708 # Reserved. Caution, do not write to this register field.
5709 # PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0
5711 # Reserved. Return zeroes on reads.
5712 # PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0
5714 # DQS Gating System Latency
5715 # PSU_DDR_PHY_DX1GTR0_DGSL 0x0
5717 # DATX8 n General Timing Register 0
5718 #(OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) */
5719 mask_write 0XFD0808C0 0xFFFFFFFF 0x00020000
5720 # Register : DX2GCR0 @ 0XFD080900</p>
5722 # Calibration Bypass
5723 # PSU_DDR_PHY_DX2GCR0_CALBYP 0x0
5725 # Master Delay Line Enable
5726 # PSU_DDR_PHY_DX2GCR0_MDLEN 0x1
5728 # Configurable ODT(TE) Phase Shift
5729 # PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0
5731 # DQS Duty Cycle Correction
5732 # PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0
5734 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
5735 # PSU_DDR_PHY_DX2GCR0_RDDLY 0x8
5737 # Reserved. Return zeroes on reads.
5738 # PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0
5740 # DQSNSE Power Down Receiver
5741 # PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0
5743 # DQSSE Power Down Receiver
5744 # PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0
5746 # RTT On Additive Latency
5747 # PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0
5750 # PSU_DDR_PHY_DX2GCR0_RTTOH 0x3
5752 # Configurable PDR Phase Shift
5753 # PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0
5756 # PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0
5758 # DQSG Power Down Receiver
5759 # PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0
5761 # Reserved. Return zeroes on reads.
5762 # PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0
5764 # DQSG On-Die Termination
5765 # PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0
5767 # DQSG Output Enable
5768 # PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1
5770 # Reserved. Return zeroes on reads.
5771 # PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0
5773 # DATX8 n General Configuration Register 0
5774 #(OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) */
5775 mask_write 0XFD080900 0xFFFFFFFF 0x40800604
5776 # Register : DX2GCR1 @ 0XFD080904</p>
5778 # Enables the PDR mode for DQ[7:0]
5779 # PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0
5781 # Reserved. Returns zeroes on reads.
5782 # PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0
5784 # Select the delayed or non-delayed read data strobe #
5785 # PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1
5787 # Select the delayed or non-delayed read data strobe
5788 # PSU_DDR_PHY_DX2GCR1_QSSEL 0x1
5790 # Enables Read Data Strobe in a byte lane
5791 # PSU_DDR_PHY_DX2GCR1_OEEN 0x1
5793 # Enables PDR in a byte lane
5794 # PSU_DDR_PHY_DX2GCR1_PDREN 0x1
5796 # Enables ODT/TE in a byte lane
5797 # PSU_DDR_PHY_DX2GCR1_TEEN 0x1
5799 # Enables Write Data strobe in a byte lane
5800 # PSU_DDR_PHY_DX2GCR1_DSEN 0x1
5802 # Enables DM pin in a byte lane
5803 # PSU_DDR_PHY_DX2GCR1_DMEN 0x1
5805 # Enables DQ corresponding to each bit in a byte
5806 # PSU_DDR_PHY_DX2GCR1_DQEN 0xff
5808 # DATX8 n General Configuration Register 1
5809 #(OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) */
5810 mask_write 0XFD080904 0xFFFFFFFF 0x00007FFF
5811 # Register : DX2GCR4 @ 0XFD080910</p>
5813 # Byte lane VREF IOM (Used only by D4MU IOs)
5814 # PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0
5816 # Byte Lane VREF Pad Enable
5817 # PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0
5819 # Byte Lane Internal VREF Enable
5820 # PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3
5822 # Byte Lane Single-End VREF Enable
5823 # PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1
5825 # Reserved. Returns zeros on reads.
5826 # PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0
5828 # External VREF generator REFSEL range select
5829 # PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0
5831 # Byte Lane External VREF Select
5832 # PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0
5834 # Single ended VREF generator REFSEL range select
5835 # PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1
5837 # Byte Lane Single-End VREF Select
5838 # PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30
5840 # Reserved. Returns zeros on reads.
5841 # PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0
5843 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
5844 # PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf
5846 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
5847 # PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0
5849 # DATX8 n General Configuration Register 4
5850 #(OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) */
5851 mask_write 0XFD080910 0xFFFFFFFF 0x0E00B03C
5852 # Register : DX2GCR5 @ 0XFD080914</p>
5854 # Reserved. Returns zeros on reads.
5855 # PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0
5857 # Byte Lane internal VREF Select for Rank 3
5858 # PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9
5860 # Reserved. Returns zeros on reads.
5861 # PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0
5863 # Byte Lane internal VREF Select for Rank 2
5864 # PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9
5866 # Reserved. Returns zeros on reads.
5867 # PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
5869 # Byte Lane internal VREF Select for Rank 1
5870 # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
5872 # Reserved. Returns zeros on reads.
5873 # PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
5875 # Byte Lane internal VREF Select for Rank 0
5876 # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
5878 # DATX8 n General Configuration Register 5
5879 #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */
5880 mask_write 0XFD080914 0xFFFFFFFF 0x09095555
5881 # Register : DX2GCR6 @ 0XFD080918</p>
5883 # Reserved. Returns zeros on reads.
5884 # PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0
5886 # DRAM DQ VREF Select for Rank3
5887 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9
5889 # Reserved. Returns zeros on reads.
5890 # PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0
5892 # DRAM DQ VREF Select for Rank2
5893 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9
5895 # Reserved. Returns zeros on reads.
5896 # PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0
5898 # DRAM DQ VREF Select for Rank1
5899 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b
5901 # Reserved. Returns zeros on reads.
5902 # PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0
5904 # DRAM DQ VREF Select for Rank0
5905 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b
5907 # DATX8 n General Configuration Register 6
5908 #(OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) */
5909 mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B
5910 # Register : DX2LCDLR2 @ 0XFD080988</p>
5912 # Reserved. Return zeroes on reads.
5913 # PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0
5915 # Reserved. Caution, do not write to this register field.
5916 # PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0
5918 # Reserved. Return zeroes on reads.
5919 # PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0
5921 # Read DQS Gating Delay
5922 # PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0
5924 # DATX8 n Local Calibrated Delay Line Register 2
5925 #(OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) */
5926 mask_write 0XFD080988 0xFFFFFFFF 0x00000000
5927 # Register : DX2GTR0 @ 0XFD0809C0</p>
5929 # Reserved. Return zeroes on reads.
5930 # PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0
5932 # DQ Write Path Latency Pipeline
5933 # PSU_DDR_PHY_DX2GTR0_WDQSL 0x0
5935 # Reserved. Caution, do not write to this register field.
5936 # PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0
5938 # Write Leveling System Latency
5939 # PSU_DDR_PHY_DX2GTR0_WLSL 0x2
5941 # Reserved. Return zeroes on reads.
5942 # PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0
5944 # Reserved. Caution, do not write to this register field.
5945 # PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0
5947 # Reserved. Return zeroes on reads.
5948 # PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0
5950 # DQS Gating System Latency
5951 # PSU_DDR_PHY_DX2GTR0_DGSL 0x0
5953 # DATX8 n General Timing Register 0
5954 #(OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) */
5955 mask_write 0XFD0809C0 0xFFFFFFFF 0x00020000
5956 # Register : DX3GCR0 @ 0XFD080A00</p>
5958 # Calibration Bypass
5959 # PSU_DDR_PHY_DX3GCR0_CALBYP 0x0
5961 # Master Delay Line Enable
5962 # PSU_DDR_PHY_DX3GCR0_MDLEN 0x1
5964 # Configurable ODT(TE) Phase Shift
5965 # PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0
5967 # DQS Duty Cycle Correction
5968 # PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0
5970 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
5971 # PSU_DDR_PHY_DX3GCR0_RDDLY 0x8
5973 # Reserved. Return zeroes on reads.
5974 # PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0
5976 # DQSNSE Power Down Receiver
5977 # PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0
5979 # DQSSE Power Down Receiver
5980 # PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0
5982 # RTT On Additive Latency
5983 # PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0
5986 # PSU_DDR_PHY_DX3GCR0_RTTOH 0x3
5988 # Configurable PDR Phase Shift
5989 # PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0
5992 # PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0
5994 # DQSG Power Down Receiver
5995 # PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0
5997 # Reserved. Return zeroes on reads.
5998 # PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0
6000 # DQSG On-Die Termination
6001 # PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0
6003 # DQSG Output Enable
6004 # PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1
6006 # Reserved. Return zeroes on reads.
6007 # PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0
6009 # DATX8 n General Configuration Register 0
6010 #(OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) */
6011 mask_write 0XFD080A00 0xFFFFFFFF 0x40800604
6012 # Register : DX3GCR1 @ 0XFD080A04</p>
6014 # Enables the PDR mode for DQ[7:0]
6015 # PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0
6017 # Reserved. Returns zeroes on reads.
6018 # PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0
6020 # Select the delayed or non-delayed read data strobe #
6021 # PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1
6023 # Select the delayed or non-delayed read data strobe
6024 # PSU_DDR_PHY_DX3GCR1_QSSEL 0x1
6026 # Enables Read Data Strobe in a byte lane
6027 # PSU_DDR_PHY_DX3GCR1_OEEN 0x1
6029 # Enables PDR in a byte lane
6030 # PSU_DDR_PHY_DX3GCR1_PDREN 0x1
6032 # Enables ODT/TE in a byte lane
6033 # PSU_DDR_PHY_DX3GCR1_TEEN 0x1
6035 # Enables Write Data strobe in a byte lane
6036 # PSU_DDR_PHY_DX3GCR1_DSEN 0x1
6038 # Enables DM pin in a byte lane
6039 # PSU_DDR_PHY_DX3GCR1_DMEN 0x1
6041 # Enables DQ corresponding to each bit in a byte
6042 # PSU_DDR_PHY_DX3GCR1_DQEN 0xff
6044 # DATX8 n General Configuration Register 1
6045 #(OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) */
6046 mask_write 0XFD080A04 0xFFFFFFFF 0x00007FFF
6047 # Register : DX3GCR4 @ 0XFD080A10</p>
6049 # Byte lane VREF IOM (Used only by D4MU IOs)
6050 # PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0
6052 # Byte Lane VREF Pad Enable
6053 # PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0
6055 # Byte Lane Internal VREF Enable
6056 # PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3
6058 # Byte Lane Single-End VREF Enable
6059 # PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1
6061 # Reserved. Returns zeros on reads.
6062 # PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0
6064 # External VREF generator REFSEL range select
6065 # PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0
6067 # Byte Lane External VREF Select
6068 # PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0
6070 # Single ended VREF generator REFSEL range select
6071 # PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1
6073 # Byte Lane Single-End VREF Select
6074 # PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30
6076 # Reserved. Returns zeros on reads.
6077 # PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0
6079 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6080 # PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf
6082 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6083 # PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0
6085 # DATX8 n General Configuration Register 4
6086 #(OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) */
6087 mask_write 0XFD080A10 0xFFFFFFFF 0x0E00B03C
6088 # Register : DX3GCR5 @ 0XFD080A14</p>
6090 # Reserved. Returns zeros on reads.
6091 # PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0
6093 # Byte Lane internal VREF Select for Rank 3
6094 # PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9
6096 # Reserved. Returns zeros on reads.
6097 # PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0
6099 # Byte Lane internal VREF Select for Rank 2
6100 # PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9
6102 # Reserved. Returns zeros on reads.
6103 # PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
6105 # Byte Lane internal VREF Select for Rank 1
6106 # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
6108 # Reserved. Returns zeros on reads.
6109 # PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
6111 # Byte Lane internal VREF Select for Rank 0
6112 # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
6114 # DATX8 n General Configuration Register 5
6115 #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */
6116 mask_write 0XFD080A14 0xFFFFFFFF 0x09095555
6117 # Register : DX3GCR6 @ 0XFD080A18</p>
6119 # Reserved. Returns zeros on reads.
6120 # PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0
6122 # DRAM DQ VREF Select for Rank3
6123 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9
6125 # Reserved. Returns zeros on reads.
6126 # PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0
6128 # DRAM DQ VREF Select for Rank2
6129 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9
6131 # Reserved. Returns zeros on reads.
6132 # PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0
6134 # DRAM DQ VREF Select for Rank1
6135 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b
6137 # Reserved. Returns zeros on reads.
6138 # PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0
6140 # DRAM DQ VREF Select for Rank0
6141 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b
6143 # DATX8 n General Configuration Register 6
6144 #(OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) */
6145 mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B
6146 # Register : DX3LCDLR2 @ 0XFD080A88</p>
6148 # Reserved. Return zeroes on reads.
6149 # PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0
6151 # Reserved. Caution, do not write to this register field.
6152 # PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0
6154 # Reserved. Return zeroes on reads.
6155 # PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0
6157 # Read DQS Gating Delay
6158 # PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0
6160 # DATX8 n Local Calibrated Delay Line Register 2
6161 #(OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) */
6162 mask_write 0XFD080A88 0xFFFFFFFF 0x00000000
6163 # Register : DX3GTR0 @ 0XFD080AC0</p>
6165 # Reserved. Return zeroes on reads.
6166 # PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0
6168 # DQ Write Path Latency Pipeline
6169 # PSU_DDR_PHY_DX3GTR0_WDQSL 0x0
6171 # Reserved. Caution, do not write to this register field.
6172 # PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0
6174 # Write Leveling System Latency
6175 # PSU_DDR_PHY_DX3GTR0_WLSL 0x2
6177 # Reserved. Return zeroes on reads.
6178 # PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0
6180 # Reserved. Caution, do not write to this register field.
6181 # PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0
6183 # Reserved. Return zeroes on reads.
6184 # PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0
6186 # DQS Gating System Latency
6187 # PSU_DDR_PHY_DX3GTR0_DGSL 0x0
6189 # DATX8 n General Timing Register 0
6190 #(OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) */
6191 mask_write 0XFD080AC0 0xFFFFFFFF 0x00020000
6192 # Register : DX4GCR0 @ 0XFD080B00</p>
6194 # Calibration Bypass
6195 # PSU_DDR_PHY_DX4GCR0_CALBYP 0x0
6197 # Master Delay Line Enable
6198 # PSU_DDR_PHY_DX4GCR0_MDLEN 0x1
6200 # Configurable ODT(TE) Phase Shift
6201 # PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0
6203 # DQS Duty Cycle Correction
6204 # PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0
6206 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
6207 # PSU_DDR_PHY_DX4GCR0_RDDLY 0x8
6209 # Reserved. Return zeroes on reads.
6210 # PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0
6212 # DQSNSE Power Down Receiver
6213 # PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0
6215 # DQSSE Power Down Receiver
6216 # PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0
6218 # RTT On Additive Latency
6219 # PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0
6222 # PSU_DDR_PHY_DX4GCR0_RTTOH 0x3
6224 # Configurable PDR Phase Shift
6225 # PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0
6228 # PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0
6230 # DQSG Power Down Receiver
6231 # PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0
6233 # Reserved. Return zeroes on reads.
6234 # PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0
6236 # DQSG On-Die Termination
6237 # PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0
6239 # DQSG Output Enable
6240 # PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1
6242 # Reserved. Return zeroes on reads.
6243 # PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0
6245 # DATX8 n General Configuration Register 0
6246 #(OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) */
6247 mask_write 0XFD080B00 0xFFFFFFFF 0x40800604
6248 # Register : DX4GCR1 @ 0XFD080B04</p>
6250 # Enables the PDR mode for DQ[7:0]
6251 # PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0
6253 # Reserved. Returns zeroes on reads.
6254 # PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0
6256 # Select the delayed or non-delayed read data strobe #
6257 # PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1
6259 # Select the delayed or non-delayed read data strobe
6260 # PSU_DDR_PHY_DX4GCR1_QSSEL 0x1
6262 # Enables Read Data Strobe in a byte lane
6263 # PSU_DDR_PHY_DX4GCR1_OEEN 0x1
6265 # Enables PDR in a byte lane
6266 # PSU_DDR_PHY_DX4GCR1_PDREN 0x1
6268 # Enables ODT/TE in a byte lane
6269 # PSU_DDR_PHY_DX4GCR1_TEEN 0x1
6271 # Enables Write Data strobe in a byte lane
6272 # PSU_DDR_PHY_DX4GCR1_DSEN 0x1
6274 # Enables DM pin in a byte lane
6275 # PSU_DDR_PHY_DX4GCR1_DMEN 0x1
6277 # Enables DQ corresponding to each bit in a byte
6278 # PSU_DDR_PHY_DX4GCR1_DQEN 0xff
6280 # DATX8 n General Configuration Register 1
6281 #(OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) */
6282 mask_write 0XFD080B04 0xFFFFFFFF 0x00007FFF
6283 # Register : DX4GCR4 @ 0XFD080B10</p>
6285 # Byte lane VREF IOM (Used only by D4MU IOs)
6286 # PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0
6288 # Byte Lane VREF Pad Enable
6289 # PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0
6291 # Byte Lane Internal VREF Enable
6292 # PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3
6294 # Byte Lane Single-End VREF Enable
6295 # PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1
6297 # Reserved. Returns zeros on reads.
6298 # PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0
6300 # External VREF generator REFSEL range select
6301 # PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0
6303 # Byte Lane External VREF Select
6304 # PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0
6306 # Single ended VREF generator REFSEL range select
6307 # PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1
6309 # Byte Lane Single-End VREF Select
6310 # PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30
6312 # Reserved. Returns zeros on reads.
6313 # PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0
6315 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6316 # PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf
6318 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6319 # PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0
6321 # DATX8 n General Configuration Register 4
6322 #(OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) */
6323 mask_write 0XFD080B10 0xFFFFFFFF 0x0E00B03C
6324 # Register : DX4GCR5 @ 0XFD080B14</p>
6326 # Reserved. Returns zeros on reads.
6327 # PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0
6329 # Byte Lane internal VREF Select for Rank 3
6330 # PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9
6332 # Reserved. Returns zeros on reads.
6333 # PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0
6335 # Byte Lane internal VREF Select for Rank 2
6336 # PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9
6338 # Reserved. Returns zeros on reads.
6339 # PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
6341 # Byte Lane internal VREF Select for Rank 1
6342 # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
6344 # Reserved. Returns zeros on reads.
6345 # PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
6347 # Byte Lane internal VREF Select for Rank 0
6348 # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
6350 # DATX8 n General Configuration Register 5
6351 #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */
6352 mask_write 0XFD080B14 0xFFFFFFFF 0x09095555
6353 # Register : DX4GCR6 @ 0XFD080B18</p>
6355 # Reserved. Returns zeros on reads.
6356 # PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0
6358 # DRAM DQ VREF Select for Rank3
6359 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9
6361 # Reserved. Returns zeros on reads.
6362 # PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0
6364 # DRAM DQ VREF Select for Rank2
6365 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9
6367 # Reserved. Returns zeros on reads.
6368 # PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0
6370 # DRAM DQ VREF Select for Rank1
6371 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b
6373 # Reserved. Returns zeros on reads.
6374 # PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0
6376 # DRAM DQ VREF Select for Rank0
6377 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b
6379 # DATX8 n General Configuration Register 6
6380 #(OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) */
6381 mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B
6382 # Register : DX4LCDLR2 @ 0XFD080B88</p>
6384 # Reserved. Return zeroes on reads.
6385 # PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0
6387 # Reserved. Caution, do not write to this register field.
6388 # PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0
6390 # Reserved. Return zeroes on reads.
6391 # PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0
6393 # Read DQS Gating Delay
6394 # PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0
6396 # DATX8 n Local Calibrated Delay Line Register 2
6397 #(OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) */
6398 mask_write 0XFD080B88 0xFFFFFFFF 0x00000000
6399 # Register : DX4GTR0 @ 0XFD080BC0</p>
6401 # Reserved. Return zeroes on reads.
6402 # PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0
6404 # DQ Write Path Latency Pipeline
6405 # PSU_DDR_PHY_DX4GTR0_WDQSL 0x0
6407 # Reserved. Caution, do not write to this register field.
6408 # PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0
6410 # Write Leveling System Latency
6411 # PSU_DDR_PHY_DX4GTR0_WLSL 0x2
6413 # Reserved. Return zeroes on reads.
6414 # PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0
6416 # Reserved. Caution, do not write to this register field.
6417 # PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0
6419 # Reserved. Return zeroes on reads.
6420 # PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0
6422 # DQS Gating System Latency
6423 # PSU_DDR_PHY_DX4GTR0_DGSL 0x0
6425 # DATX8 n General Timing Register 0
6426 #(OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) */
6427 mask_write 0XFD080BC0 0xFFFFFFFF 0x00020000
6428 # Register : DX5GCR0 @ 0XFD080C00</p>
6430 # Calibration Bypass
6431 # PSU_DDR_PHY_DX5GCR0_CALBYP 0x0
6433 # Master Delay Line Enable
6434 # PSU_DDR_PHY_DX5GCR0_MDLEN 0x1
6436 # Configurable ODT(TE) Phase Shift
6437 # PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0
6439 # DQS Duty Cycle Correction
6440 # PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0
6442 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
6443 # PSU_DDR_PHY_DX5GCR0_RDDLY 0x8
6445 # Reserved. Return zeroes on reads.
6446 # PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0
6448 # DQSNSE Power Down Receiver
6449 # PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0
6451 # DQSSE Power Down Receiver
6452 # PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0
6454 # RTT On Additive Latency
6455 # PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0
6458 # PSU_DDR_PHY_DX5GCR0_RTTOH 0x3
6460 # Configurable PDR Phase Shift
6461 # PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0
6464 # PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0
6466 # DQSG Power Down Receiver
6467 # PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0
6469 # Reserved. Return zeroes on reads.
6470 # PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0
6472 # DQSG On-Die Termination
6473 # PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0
6475 # DQSG Output Enable
6476 # PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1
6478 # Reserved. Return zeroes on reads.
6479 # PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0
6481 # DATX8 n General Configuration Register 0
6482 #(OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) */
6483 mask_write 0XFD080C00 0xFFFFFFFF 0x40800604
6484 # Register : DX5GCR1 @ 0XFD080C04</p>
6486 # Enables the PDR mode for DQ[7:0]
6487 # PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0
6489 # Reserved. Returns zeroes on reads.
6490 # PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0
6492 # Select the delayed or non-delayed read data strobe #
6493 # PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1
6495 # Select the delayed or non-delayed read data strobe
6496 # PSU_DDR_PHY_DX5GCR1_QSSEL 0x1
6498 # Enables Read Data Strobe in a byte lane
6499 # PSU_DDR_PHY_DX5GCR1_OEEN 0x1
6501 # Enables PDR in a byte lane
6502 # PSU_DDR_PHY_DX5GCR1_PDREN 0x1
6504 # Enables ODT/TE in a byte lane
6505 # PSU_DDR_PHY_DX5GCR1_TEEN 0x1
6507 # Enables Write Data strobe in a byte lane
6508 # PSU_DDR_PHY_DX5GCR1_DSEN 0x1
6510 # Enables DM pin in a byte lane
6511 # PSU_DDR_PHY_DX5GCR1_DMEN 0x1
6513 # Enables DQ corresponding to each bit in a byte
6514 # PSU_DDR_PHY_DX5GCR1_DQEN 0xff
6516 # DATX8 n General Configuration Register 1
6517 #(OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) */
6518 mask_write 0XFD080C04 0xFFFFFFFF 0x00007FFF
6519 # Register : DX5GCR4 @ 0XFD080C10</p>
6521 # Byte lane VREF IOM (Used only by D4MU IOs)
6522 # PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0
6524 # Byte Lane VREF Pad Enable
6525 # PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0
6527 # Byte Lane Internal VREF Enable
6528 # PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3
6530 # Byte Lane Single-End VREF Enable
6531 # PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1
6533 # Reserved. Returns zeros on reads.
6534 # PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0
6536 # External VREF generator REFSEL range select
6537 # PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0
6539 # Byte Lane External VREF Select
6540 # PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0
6542 # Single ended VREF generator REFSEL range select
6543 # PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1
6545 # Byte Lane Single-End VREF Select
6546 # PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30
6548 # Reserved. Returns zeros on reads.
6549 # PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0
6551 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6552 # PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf
6554 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6555 # PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0
6557 # DATX8 n General Configuration Register 4
6558 #(OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) */
6559 mask_write 0XFD080C10 0xFFFFFFFF 0x0E00B03C
6560 # Register : DX5GCR5 @ 0XFD080C14</p>
6562 # Reserved. Returns zeros on reads.
6563 # PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0
6565 # Byte Lane internal VREF Select for Rank 3
6566 # PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9
6568 # Reserved. Returns zeros on reads.
6569 # PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0
6571 # Byte Lane internal VREF Select for Rank 2
6572 # PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9
6574 # Reserved. Returns zeros on reads.
6575 # PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
6577 # Byte Lane internal VREF Select for Rank 1
6578 # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
6580 # Reserved. Returns zeros on reads.
6581 # PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
6583 # Byte Lane internal VREF Select for Rank 0
6584 # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
6586 # DATX8 n General Configuration Register 5
6587 #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */
6588 mask_write 0XFD080C14 0xFFFFFFFF 0x09095555
6589 # Register : DX5GCR6 @ 0XFD080C18</p>
6591 # Reserved. Returns zeros on reads.
6592 # PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0
6594 # DRAM DQ VREF Select for Rank3
6595 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9
6597 # Reserved. Returns zeros on reads.
6598 # PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0
6600 # DRAM DQ VREF Select for Rank2
6601 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9
6603 # Reserved. Returns zeros on reads.
6604 # PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0
6606 # DRAM DQ VREF Select for Rank1
6607 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b
6609 # Reserved. Returns zeros on reads.
6610 # PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0
6612 # DRAM DQ VREF Select for Rank0
6613 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b
6615 # DATX8 n General Configuration Register 6
6616 #(OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) */
6617 mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B
6618 # Register : DX5LCDLR2 @ 0XFD080C88</p>
6620 # Reserved. Return zeroes on reads.
6621 # PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0
6623 # Reserved. Caution, do not write to this register field.
6624 # PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0
6626 # Reserved. Return zeroes on reads.
6627 # PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0
6629 # Read DQS Gating Delay
6630 # PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0
6632 # DATX8 n Local Calibrated Delay Line Register 2
6633 #(OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) */
6634 mask_write 0XFD080C88 0xFFFFFFFF 0x00000000
6635 # Register : DX5GTR0 @ 0XFD080CC0</p>
6637 # Reserved. Return zeroes on reads.
6638 # PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0
6640 # DQ Write Path Latency Pipeline
6641 # PSU_DDR_PHY_DX5GTR0_WDQSL 0x0
6643 # Reserved. Caution, do not write to this register field.
6644 # PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0
6646 # Write Leveling System Latency
6647 # PSU_DDR_PHY_DX5GTR0_WLSL 0x2
6649 # Reserved. Return zeroes on reads.
6650 # PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0
6652 # Reserved. Caution, do not write to this register field.
6653 # PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0
6655 # Reserved. Return zeroes on reads.
6656 # PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0
6658 # DQS Gating System Latency
6659 # PSU_DDR_PHY_DX5GTR0_DGSL 0x0
6661 # DATX8 n General Timing Register 0
6662 #(OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) */
6663 mask_write 0XFD080CC0 0xFFFFFFFF 0x00020000
6664 # Register : DX6GCR0 @ 0XFD080D00</p>
6666 # Calibration Bypass
6667 # PSU_DDR_PHY_DX6GCR0_CALBYP 0x0
6669 # Master Delay Line Enable
6670 # PSU_DDR_PHY_DX6GCR0_MDLEN 0x1
6672 # Configurable ODT(TE) Phase Shift
6673 # PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0
6675 # DQS Duty Cycle Correction
6676 # PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0
6678 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
6679 # PSU_DDR_PHY_DX6GCR0_RDDLY 0x8
6681 # Reserved. Return zeroes on reads.
6682 # PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0
6684 # DQSNSE Power Down Receiver
6685 # PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0
6687 # DQSSE Power Down Receiver
6688 # PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0
6690 # RTT On Additive Latency
6691 # PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0
6694 # PSU_DDR_PHY_DX6GCR0_RTTOH 0x3
6696 # Configurable PDR Phase Shift
6697 # PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0
6700 # PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0
6702 # DQSG Power Down Receiver
6703 # PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0
6705 # Reserved. Return zeroes on reads.
6706 # PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0
6708 # DQSG On-Die Termination
6709 # PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0
6711 # DQSG Output Enable
6712 # PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1
6714 # Reserved. Return zeroes on reads.
6715 # PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0
6717 # DATX8 n General Configuration Register 0
6718 #(OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) */
6719 mask_write 0XFD080D00 0xFFFFFFFF 0x40800604
6720 # Register : DX6GCR1 @ 0XFD080D04</p>
6722 # Enables the PDR mode for DQ[7:0]
6723 # PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0
6725 # Reserved. Returns zeroes on reads.
6726 # PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0
6728 # Select the delayed or non-delayed read data strobe #
6729 # PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1
6731 # Select the delayed or non-delayed read data strobe
6732 # PSU_DDR_PHY_DX6GCR1_QSSEL 0x1
6734 # Enables Read Data Strobe in a byte lane
6735 # PSU_DDR_PHY_DX6GCR1_OEEN 0x1
6737 # Enables PDR in a byte lane
6738 # PSU_DDR_PHY_DX6GCR1_PDREN 0x1
6740 # Enables ODT/TE in a byte lane
6741 # PSU_DDR_PHY_DX6GCR1_TEEN 0x1
6743 # Enables Write Data strobe in a byte lane
6744 # PSU_DDR_PHY_DX6GCR1_DSEN 0x1
6746 # Enables DM pin in a byte lane
6747 # PSU_DDR_PHY_DX6GCR1_DMEN 0x1
6749 # Enables DQ corresponding to each bit in a byte
6750 # PSU_DDR_PHY_DX6GCR1_DQEN 0xff
6752 # DATX8 n General Configuration Register 1
6753 #(OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) */
6754 mask_write 0XFD080D04 0xFFFFFFFF 0x00007FFF
6755 # Register : DX6GCR4 @ 0XFD080D10</p>
6757 # Byte lane VREF IOM (Used only by D4MU IOs)
6758 # PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0
6760 # Byte Lane VREF Pad Enable
6761 # PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0
6763 # Byte Lane Internal VREF Enable
6764 # PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3
6766 # Byte Lane Single-End VREF Enable
6767 # PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1
6769 # Reserved. Returns zeros on reads.
6770 # PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0
6772 # External VREF generator REFSEL range select
6773 # PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0
6775 # Byte Lane External VREF Select
6776 # PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0
6778 # Single ended VREF generator REFSEL range select
6779 # PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1
6781 # Byte Lane Single-End VREF Select
6782 # PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30
6784 # Reserved. Returns zeros on reads.
6785 # PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0
6787 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6788 # PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf
6790 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6791 # PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0
6793 # DATX8 n General Configuration Register 4
6794 #(OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) */
6795 mask_write 0XFD080D10 0xFFFFFFFF 0x0E00B03C
6796 # Register : DX6GCR5 @ 0XFD080D14</p>
6798 # Reserved. Returns zeros on reads.
6799 # PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0
6801 # Byte Lane internal VREF Select for Rank 3
6802 # PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9
6804 # Reserved. Returns zeros on reads.
6805 # PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0
6807 # Byte Lane internal VREF Select for Rank 2
6808 # PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9
6810 # Reserved. Returns zeros on reads.
6811 # PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
6813 # Byte Lane internal VREF Select for Rank 1
6814 # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
6816 # Reserved. Returns zeros on reads.
6817 # PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
6819 # Byte Lane internal VREF Select for Rank 0
6820 # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
6822 # DATX8 n General Configuration Register 5
6823 #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */
6824 mask_write 0XFD080D14 0xFFFFFFFF 0x09095555
6825 # Register : DX6GCR6 @ 0XFD080D18</p>
6827 # Reserved. Returns zeros on reads.
6828 # PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0
6830 # DRAM DQ VREF Select for Rank3
6831 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9
6833 # Reserved. Returns zeros on reads.
6834 # PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0
6836 # DRAM DQ VREF Select for Rank2
6837 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9
6839 # Reserved. Returns zeros on reads.
6840 # PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0
6842 # DRAM DQ VREF Select for Rank1
6843 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b
6845 # Reserved. Returns zeros on reads.
6846 # PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0
6848 # DRAM DQ VREF Select for Rank0
6849 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b
6851 # DATX8 n General Configuration Register 6
6852 #(OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) */
6853 mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B
6854 # Register : DX6LCDLR2 @ 0XFD080D88</p>
6856 # Reserved. Return zeroes on reads.
6857 # PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0
6859 # Reserved. Caution, do not write to this register field.
6860 # PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0
6862 # Reserved. Return zeroes on reads.
6863 # PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0
6865 # Read DQS Gating Delay
6866 # PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0
6868 # DATX8 n Local Calibrated Delay Line Register 2
6869 #(OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) */
6870 mask_write 0XFD080D88 0xFFFFFFFF 0x00000000
6871 # Register : DX6GTR0 @ 0XFD080DC0</p>
6873 # Reserved. Return zeroes on reads.
6874 # PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0
6876 # DQ Write Path Latency Pipeline
6877 # PSU_DDR_PHY_DX6GTR0_WDQSL 0x0
6879 # Reserved. Caution, do not write to this register field.
6880 # PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0
6882 # Write Leveling System Latency
6883 # PSU_DDR_PHY_DX6GTR0_WLSL 0x2
6885 # Reserved. Return zeroes on reads.
6886 # PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0
6888 # Reserved. Caution, do not write to this register field.
6889 # PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0
6891 # Reserved. Return zeroes on reads.
6892 # PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0
6894 # DQS Gating System Latency
6895 # PSU_DDR_PHY_DX6GTR0_DGSL 0x0
6897 # DATX8 n General Timing Register 0
6898 #(OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) */
6899 mask_write 0XFD080DC0 0xFFFFFFFF 0x00020000
6900 # Register : DX7GCR0 @ 0XFD080E00</p>
6902 # Calibration Bypass
6903 # PSU_DDR_PHY_DX7GCR0_CALBYP 0x0
6905 # Master Delay Line Enable
6906 # PSU_DDR_PHY_DX7GCR0_MDLEN 0x1
6908 # Configurable ODT(TE) Phase Shift
6909 # PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0
6911 # DQS Duty Cycle Correction
6912 # PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0
6914 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
6915 # PSU_DDR_PHY_DX7GCR0_RDDLY 0x8
6917 # Reserved. Return zeroes on reads.
6918 # PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0
6920 # DQSNSE Power Down Receiver
6921 # PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0
6923 # DQSSE Power Down Receiver
6924 # PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0
6926 # RTT On Additive Latency
6927 # PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0
6930 # PSU_DDR_PHY_DX7GCR0_RTTOH 0x3
6932 # Configurable PDR Phase Shift
6933 # PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0
6936 # PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0
6938 # DQSG Power Down Receiver
6939 # PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0
6941 # Reserved. Return zeroes on reads.
6942 # PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0
6944 # DQSG On-Die Termination
6945 # PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0
6947 # DQSG Output Enable
6948 # PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1
6950 # Reserved. Return zeroes on reads.
6951 # PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0
6953 # DATX8 n General Configuration Register 0
6954 #(OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) */
6955 mask_write 0XFD080E00 0xFFFFFFFF 0x40800604
6956 # Register : DX7GCR1 @ 0XFD080E04</p>
6958 # Enables the PDR mode for DQ[7:0]
6959 # PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0
6961 # Reserved. Returns zeroes on reads.
6962 # PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0
6964 # Select the delayed or non-delayed read data strobe #
6965 # PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1
6967 # Select the delayed or non-delayed read data strobe
6968 # PSU_DDR_PHY_DX7GCR1_QSSEL 0x1
6970 # Enables Read Data Strobe in a byte lane
6971 # PSU_DDR_PHY_DX7GCR1_OEEN 0x1
6973 # Enables PDR in a byte lane
6974 # PSU_DDR_PHY_DX7GCR1_PDREN 0x1
6976 # Enables ODT/TE in a byte lane
6977 # PSU_DDR_PHY_DX7GCR1_TEEN 0x1
6979 # Enables Write Data strobe in a byte lane
6980 # PSU_DDR_PHY_DX7GCR1_DSEN 0x1
6982 # Enables DM pin in a byte lane
6983 # PSU_DDR_PHY_DX7GCR1_DMEN 0x1
6985 # Enables DQ corresponding to each bit in a byte
6986 # PSU_DDR_PHY_DX7GCR1_DQEN 0xff
6988 # DATX8 n General Configuration Register 1
6989 #(OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) */
6990 mask_write 0XFD080E04 0xFFFFFFFF 0x00007FFF
6991 # Register : DX7GCR4 @ 0XFD080E10</p>
6993 # Byte lane VREF IOM (Used only by D4MU IOs)
6994 # PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0
6996 # Byte Lane VREF Pad Enable
6997 # PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0
6999 # Byte Lane Internal VREF Enable
7000 # PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3
7002 # Byte Lane Single-End VREF Enable
7003 # PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1
7005 # Reserved. Returns zeros on reads.
7006 # PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0
7008 # External VREF generator REFSEL range select
7009 # PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0
7011 # Byte Lane External VREF Select
7012 # PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0
7014 # Single ended VREF generator REFSEL range select
7015 # PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1
7017 # Byte Lane Single-End VREF Select
7018 # PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30
7020 # Reserved. Returns zeros on reads.
7021 # PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0
7023 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7024 # PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf
7026 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7027 # PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0
7029 # DATX8 n General Configuration Register 4
7030 #(OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) */
7031 mask_write 0XFD080E10 0xFFFFFFFF 0x0E00B03C
7032 # Register : DX7GCR5 @ 0XFD080E14</p>
7034 # Reserved. Returns zeros on reads.
7035 # PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0
7037 # Byte Lane internal VREF Select for Rank 3
7038 # PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9
7040 # Reserved. Returns zeros on reads.
7041 # PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0
7043 # Byte Lane internal VREF Select for Rank 2
7044 # PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9
7046 # Reserved. Returns zeros on reads.
7047 # PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
7049 # Byte Lane internal VREF Select for Rank 1
7050 # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
7052 # Reserved. Returns zeros on reads.
7053 # PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
7055 # Byte Lane internal VREF Select for Rank 0
7056 # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
7058 # DATX8 n General Configuration Register 5
7059 #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */
7060 mask_write 0XFD080E14 0xFFFFFFFF 0x09095555
7061 # Register : DX7GCR6 @ 0XFD080E18</p>
7063 # Reserved. Returns zeros on reads.
7064 # PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0
7066 # DRAM DQ VREF Select for Rank3
7067 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9
7069 # Reserved. Returns zeros on reads.
7070 # PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0
7072 # DRAM DQ VREF Select for Rank2
7073 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9
7075 # Reserved. Returns zeros on reads.
7076 # PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0
7078 # DRAM DQ VREF Select for Rank1
7079 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b
7081 # Reserved. Returns zeros on reads.
7082 # PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0
7084 # DRAM DQ VREF Select for Rank0
7085 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b
7087 # DATX8 n General Configuration Register 6
7088 #(OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) */
7089 mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B
7090 # Register : DX7LCDLR2 @ 0XFD080E88</p>
7092 # Reserved. Return zeroes on reads.
7093 # PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0
7095 # Reserved. Caution, do not write to this register field.
7096 # PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0
7098 # Reserved. Return zeroes on reads.
7099 # PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0
7101 # Read DQS Gating Delay
7102 # PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa
7104 # DATX8 n Local Calibrated Delay Line Register 2
7105 #(OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) */
7106 mask_write 0XFD080E88 0xFFFFFFFF 0x0000000A
7107 # Register : DX7GTR0 @ 0XFD080EC0</p>
7109 # Reserved. Return zeroes on reads.
7110 # PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0
7112 # DQ Write Path Latency Pipeline
7113 # PSU_DDR_PHY_DX7GTR0_WDQSL 0x0
7115 # Reserved. Caution, do not write to this register field.
7116 # PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0
7118 # Write Leveling System Latency
7119 # PSU_DDR_PHY_DX7GTR0_WLSL 0x2
7121 # Reserved. Return zeroes on reads.
7122 # PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0
7124 # Reserved. Caution, do not write to this register field.
7125 # PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0
7127 # Reserved. Return zeroes on reads.
7128 # PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0
7130 # DQS Gating System Latency
7131 # PSU_DDR_PHY_DX7GTR0_DGSL 0x0
7133 # DATX8 n General Timing Register 0
7134 #(OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) */
7135 mask_write 0XFD080EC0 0xFFFFFFFF 0x00020000
7136 # Register : DX8GCR0 @ 0XFD080F00</p>
7138 # Calibration Bypass
7139 # PSU_DDR_PHY_DX8GCR0_CALBYP 0x0
7141 # Master Delay Line Enable
7142 # PSU_DDR_PHY_DX8GCR0_MDLEN 0x1
7144 # Configurable ODT(TE) Phase Shift
7145 # PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0
7147 # DQS Duty Cycle Correction
7148 # PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0
7150 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7151 # PSU_DDR_PHY_DX8GCR0_RDDLY 0x8
7153 # Reserved. Return zeroes on reads.
7154 # PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0
7156 # DQSNSE Power Down Receiver
7157 # PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0
7159 # DQSSE Power Down Receiver
7160 # PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0
7162 # RTT On Additive Latency
7163 # PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0
7166 # PSU_DDR_PHY_DX8GCR0_RTTOH 0x3
7168 # Configurable PDR Phase Shift
7169 # PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0
7172 # PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0
7174 # DQSG Power Down Receiver
7175 # PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1
7177 # Reserved. Return zeroes on reads.
7178 # PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0
7180 # DQSG On-Die Termination
7181 # PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0
7183 # DQSG Output Enable
7184 # PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1
7186 # Reserved. Return zeroes on reads.
7187 # PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0
7189 # DATX8 n General Configuration Register 0
7190 #(OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) */
7191 mask_write 0XFD080F00 0xFFFFFFFF 0x40800624
7192 # Register : DX8GCR1 @ 0XFD080F04</p>
7194 # Enables the PDR mode for DQ[7:0]
7195 # PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0
7197 # Reserved. Returns zeroes on reads.
7198 # PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0
7200 # Select the delayed or non-delayed read data strobe #
7201 # PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1
7203 # Select the delayed or non-delayed read data strobe
7204 # PSU_DDR_PHY_DX8GCR1_QSSEL 0x1
7206 # Enables Read Data Strobe in a byte lane
7207 # PSU_DDR_PHY_DX8GCR1_OEEN 0x1
7209 # Enables PDR in a byte lane
7210 # PSU_DDR_PHY_DX8GCR1_PDREN 0x1
7212 # Enables ODT/TE in a byte lane
7213 # PSU_DDR_PHY_DX8GCR1_TEEN 0x1
7215 # Enables Write Data strobe in a byte lane
7216 # PSU_DDR_PHY_DX8GCR1_DSEN 0x1
7218 # Enables DM pin in a byte lane
7219 # PSU_DDR_PHY_DX8GCR1_DMEN 0x1
7221 # Enables DQ corresponding to each bit in a byte
7222 # PSU_DDR_PHY_DX8GCR1_DQEN 0x0
7224 # DATX8 n General Configuration Register 1
7225 #(OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) */
7226 mask_write 0XFD080F04 0xFFFFFFFF 0x00007F00
7227 # Register : DX8GCR4 @ 0XFD080F10</p>
7229 # Byte lane VREF IOM (Used only by D4MU IOs)
7230 # PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0
7232 # Byte Lane VREF Pad Enable
7233 # PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0
7235 # Byte Lane Internal VREF Enable
7236 # PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3
7238 # Byte Lane Single-End VREF Enable
7239 # PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1
7241 # Reserved. Returns zeros on reads.
7242 # PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0
7244 # External VREF generator REFSEL range select
7245 # PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0
7247 # Byte Lane External VREF Select
7248 # PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0
7250 # Single ended VREF generator REFSEL range select
7251 # PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1
7253 # Byte Lane Single-End VREF Select
7254 # PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30
7256 # Reserved. Returns zeros on reads.
7257 # PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0
7259 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7260 # PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf
7262 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7263 # PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0
7265 # DATX8 n General Configuration Register 4
7266 #(OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) */
7267 mask_write 0XFD080F10 0xFFFFFFFF 0x0E00B03C
7268 # Register : DX8GCR5 @ 0XFD080F14</p>
7270 # Reserved. Returns zeros on reads.
7271 # PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0
7273 # Byte Lane internal VREF Select for Rank 3
7274 # PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9
7276 # Reserved. Returns zeros on reads.
7277 # PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0
7279 # Byte Lane internal VREF Select for Rank 2
7280 # PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9
7282 # Reserved. Returns zeros on reads.
7283 # PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
7285 # Byte Lane internal VREF Select for Rank 1
7286 # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
7288 # Reserved. Returns zeros on reads.
7289 # PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
7291 # Byte Lane internal VREF Select for Rank 0
7292 # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
7294 # DATX8 n General Configuration Register 5
7295 #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */
7296 mask_write 0XFD080F14 0xFFFFFFFF 0x09095555
7297 # Register : DX8GCR6 @ 0XFD080F18</p>
7299 # Reserved. Returns zeros on reads.
7300 # PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0
7302 # DRAM DQ VREF Select for Rank3
7303 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9
7305 # Reserved. Returns zeros on reads.
7306 # PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0
7308 # DRAM DQ VREF Select for Rank2
7309 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9
7311 # Reserved. Returns zeros on reads.
7312 # PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0
7314 # DRAM DQ VREF Select for Rank1
7315 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b
7317 # Reserved. Returns zeros on reads.
7318 # PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0
7320 # DRAM DQ VREF Select for Rank0
7321 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b
7323 # DATX8 n General Configuration Register 6
7324 #(OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) */
7325 mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B
7326 # Register : DX8LCDLR2 @ 0XFD080F88</p>
7328 # Reserved. Return zeroes on reads.
7329 # PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0
7331 # Reserved. Caution, do not write to this register field.
7332 # PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0
7334 # Reserved. Return zeroes on reads.
7335 # PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0
7337 # Read DQS Gating Delay
7338 # PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0
7340 # DATX8 n Local Calibrated Delay Line Register 2
7341 #(OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) */
7342 mask_write 0XFD080F88 0xFFFFFFFF 0x00000000
7343 # Register : DX8GTR0 @ 0XFD080FC0</p>
7345 # Reserved. Return zeroes on reads.
7346 # PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0
7348 # DQ Write Path Latency Pipeline
7349 # PSU_DDR_PHY_DX8GTR0_WDQSL 0x0
7351 # Reserved. Caution, do not write to this register field.
7352 # PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0
7354 # Write Leveling System Latency
7355 # PSU_DDR_PHY_DX8GTR0_WLSL 0x2
7357 # Reserved. Return zeroes on reads.
7358 # PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0
7360 # Reserved. Caution, do not write to this register field.
7361 # PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0
7363 # Reserved. Return zeroes on reads.
7364 # PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0
7366 # DQS Gating System Latency
7367 # PSU_DDR_PHY_DX8GTR0_DGSL 0x0
7369 # DATX8 n General Timing Register 0
7370 #(OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) */
7371 mask_write 0XFD080FC0 0xFFFFFFFF 0x00020000
7372 # Register : DX8SL0DQSCTL @ 0XFD08141C</p>
7374 # Reserved. Return zeroes on reads.
7375 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0
7377 # Read Path Rise-to-Rise Mode
7378 # PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1
7380 # Reserved. Return zeroes on reads.
7381 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0
7383 # Write Path Rise-to-Rise Mode
7384 # PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1
7386 # DQS Gate Extension
7387 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0
7389 # Low Power PLL Power Down
7390 # PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1
7392 # Low Power I/O Power Down
7393 # PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1
7395 # Reserved. Return zeroes on reads.
7396 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0
7399 # PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1
7401 # Unused DQ I/O Mode
7402 # PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0
7404 # Reserved. Return zeroes on reads.
7405 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0
7408 # PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
7411 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0xc
7414 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x4
7416 # DATX8 0-1 DQS Control Register
7417 #(OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U) */
7418 mask_write 0XFD08141C 0xFFFFFFFF 0x012643C4
7419 # Register : DX8SL0DXCTL2 @ 0XFD08142C</p>
7421 # Reserved. Return zeroes on reads.
7422 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0
7424 # Configurable Read Data Enable
7425 # PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0
7427 # OX Extension during Post-amble
7428 # PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
7430 # OE Extension during Pre-amble
7431 # PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x0
7433 # Reserved. Return zeroes on reads.
7434 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
7436 # I/O Assisted Gate Select
7437 # PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0
7439 # I/O Loopback Select
7440 # PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0
7442 # Reserved. Return zeroes on reads.
7443 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0
7445 # Low Power Wakeup Threshold
7446 # PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc
7448 # Read Data Bus Inversion Enable
7449 # PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0
7451 # Write Data Bus Inversion Enable
7452 # PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0
7454 # PUB Read FIFO Bypass
7455 # PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0
7457 # DATX8 Receive FIFO Read Mode
7458 # PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0
7460 # Disables the Read FIFO Reset
7461 # PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0
7463 # Read DQS Gate I/O Loopback
7464 # PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0
7466 # Reserved. Return zeroes on reads.
7467 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
7469 # DATX8 0-1 DX Control Register 2
7470 #(OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00001800U) */
7471 mask_write 0XFD08142C 0xFFFFFFFF 0x00001800
7472 # Register : DX8SL0IOCR @ 0XFD081430</p>
7474 # Reserved. Return zeroes on reads.
7475 # PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0
7477 # PVREF_DAC REFSEL range select
7478 # PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7
7480 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
7481 # PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0
7484 # PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2
7486 # DX IO Transmitter Mode
7487 # PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0
7489 # DX IO Receiver Mode
7490 # PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0
7492 # DATX8 0-1 I/O Configuration Register
7493 #(OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) */
7494 mask_write 0XFD081430 0xFFFFFFFF 0x70800000
7495 # Register : DX8SL1DQSCTL @ 0XFD08145C</p>
7497 # Reserved. Return zeroes on reads.
7498 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0
7500 # Read Path Rise-to-Rise Mode
7501 # PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1
7503 # Reserved. Return zeroes on reads.
7504 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0
7506 # Write Path Rise-to-Rise Mode
7507 # PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1
7509 # DQS Gate Extension
7510 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0
7512 # Low Power PLL Power Down
7513 # PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1
7515 # Low Power I/O Power Down
7516 # PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1
7518 # Reserved. Return zeroes on reads.
7519 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0
7522 # PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1
7524 # Unused DQ I/O Mode
7525 # PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0
7527 # Reserved. Return zeroes on reads.
7528 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0
7531 # PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
7534 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0xc
7537 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x4
7539 # DATX8 0-1 DQS Control Register
7540 #(OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U) */
7541 mask_write 0XFD08145C 0xFFFFFFFF 0x012643C4
7542 # Register : DX8SL1DXCTL2 @ 0XFD08146C</p>
7544 # Reserved. Return zeroes on reads.
7545 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0
7547 # Configurable Read Data Enable
7548 # PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0
7550 # OX Extension during Post-amble
7551 # PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
7553 # OE Extension during Pre-amble
7554 # PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x0
7556 # Reserved. Return zeroes on reads.
7557 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
7559 # I/O Assisted Gate Select
7560 # PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0
7562 # I/O Loopback Select
7563 # PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0
7565 # Reserved. Return zeroes on reads.
7566 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0
7568 # Low Power Wakeup Threshold
7569 # PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc
7571 # Read Data Bus Inversion Enable
7572 # PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0
7574 # Write Data Bus Inversion Enable
7575 # PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0
7577 # PUB Read FIFO Bypass
7578 # PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0
7580 # DATX8 Receive FIFO Read Mode
7581 # PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0
7583 # Disables the Read FIFO Reset
7584 # PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0
7586 # Read DQS Gate I/O Loopback
7587 # PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0
7589 # Reserved. Return zeroes on reads.
7590 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
7592 # DATX8 0-1 DX Control Register 2
7593 #(OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00001800U) */
7594 mask_write 0XFD08146C 0xFFFFFFFF 0x00001800
7595 # Register : DX8SL1IOCR @ 0XFD081470</p>
7597 # Reserved. Return zeroes on reads.
7598 # PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0
7600 # PVREF_DAC REFSEL range select
7601 # PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7
7603 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
7604 # PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0
7607 # PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2
7609 # DX IO Transmitter Mode
7610 # PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0
7612 # DX IO Receiver Mode
7613 # PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0
7615 # DATX8 0-1 I/O Configuration Register
7616 #(OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) */
7617 mask_write 0XFD081470 0xFFFFFFFF 0x70800000
7618 # Register : DX8SL2DQSCTL @ 0XFD08149C</p>
7620 # Reserved. Return zeroes on reads.
7621 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
7623 # Read Path Rise-to-Rise Mode
7624 # PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
7626 # Reserved. Return zeroes on reads.
7627 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
7629 # Write Path Rise-to-Rise Mode
7630 # PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1
7632 # DQS Gate Extension
7633 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0
7635 # Low Power PLL Power Down
7636 # PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1
7638 # Low Power I/O Power Down
7639 # PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1
7641 # Reserved. Return zeroes on reads.
7642 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0
7645 # PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1
7647 # Unused DQ I/O Mode
7648 # PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0
7650 # Reserved. Return zeroes on reads.
7651 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0
7654 # PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
7657 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0xc
7660 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x4
7662 # DATX8 0-1 DQS Control Register
7663 #(OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U) */
7664 mask_write 0XFD08149C 0xFFFFFFFF 0x012643C4
7665 # Register : DX8SL2DXCTL2 @ 0XFD0814AC</p>
7667 # Reserved. Return zeroes on reads.
7668 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0
7670 # Configurable Read Data Enable
7671 # PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0
7673 # OX Extension during Post-amble
7674 # PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
7676 # OE Extension during Pre-amble
7677 # PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x0
7679 # Reserved. Return zeroes on reads.
7680 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
7682 # I/O Assisted Gate Select
7683 # PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0
7685 # I/O Loopback Select
7686 # PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0
7688 # Reserved. Return zeroes on reads.
7689 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0
7691 # Low Power Wakeup Threshold
7692 # PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc
7694 # Read Data Bus Inversion Enable
7695 # PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0
7697 # Write Data Bus Inversion Enable
7698 # PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0
7700 # PUB Read FIFO Bypass
7701 # PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0
7703 # DATX8 Receive FIFO Read Mode
7704 # PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0
7706 # Disables the Read FIFO Reset
7707 # PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0
7709 # Read DQS Gate I/O Loopback
7710 # PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0
7712 # Reserved. Return zeroes on reads.
7713 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
7715 # DATX8 0-1 DX Control Register 2
7716 #(OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U) */
7717 mask_write 0XFD0814AC 0xFFFFFFFF 0x00001800
7718 # Register : DX8SL2IOCR @ 0XFD0814B0</p>
7720 # Reserved. Return zeroes on reads.
7721 # PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0
7723 # PVREF_DAC REFSEL range select
7724 # PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7
7726 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
7727 # PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0
7730 # PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2
7732 # DX IO Transmitter Mode
7733 # PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0
7735 # DX IO Receiver Mode
7736 # PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0
7738 # DATX8 0-1 I/O Configuration Register
7739 #(OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) */
7740 mask_write 0XFD0814B0 0xFFFFFFFF 0x70800000
7741 # Register : DX8SL3DQSCTL @ 0XFD0814DC</p>
7743 # Reserved. Return zeroes on reads.
7744 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0
7746 # Read Path Rise-to-Rise Mode
7747 # PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1
7749 # Reserved. Return zeroes on reads.
7750 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0
7752 # Write Path Rise-to-Rise Mode
7753 # PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1
7755 # DQS Gate Extension
7756 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0
7758 # Low Power PLL Power Down
7759 # PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1
7761 # Low Power I/O Power Down
7762 # PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1
7764 # Reserved. Return zeroes on reads.
7765 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0
7768 # PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1
7770 # Unused DQ I/O Mode
7771 # PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0
7773 # Reserved. Return zeroes on reads.
7774 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0
7777 # PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
7780 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0xc
7783 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x4
7785 # DATX8 0-1 DQS Control Register
7786 #(OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U) */
7787 mask_write 0XFD0814DC 0xFFFFFFFF 0x012643C4
7788 # Register : DX8SL3DXCTL2 @ 0XFD0814EC</p>
7790 # Reserved. Return zeroes on reads.
7791 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0
7793 # Configurable Read Data Enable
7794 # PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0
7796 # OX Extension during Post-amble
7797 # PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
7799 # OE Extension during Pre-amble
7800 # PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x0
7802 # Reserved. Return zeroes on reads.
7803 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
7805 # I/O Assisted Gate Select
7806 # PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0
7808 # I/O Loopback Select
7809 # PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0
7811 # Reserved. Return zeroes on reads.
7812 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0
7814 # Low Power Wakeup Threshold
7815 # PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc
7817 # Read Data Bus Inversion Enable
7818 # PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0
7820 # Write Data Bus Inversion Enable
7821 # PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0
7823 # PUB Read FIFO Bypass
7824 # PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0
7826 # DATX8 Receive FIFO Read Mode
7827 # PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0
7829 # Disables the Read FIFO Reset
7830 # PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0
7832 # Read DQS Gate I/O Loopback
7833 # PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0
7835 # Reserved. Return zeroes on reads.
7836 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
7838 # DATX8 0-1 DX Control Register 2
7839 #(OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U) */
7840 mask_write 0XFD0814EC 0xFFFFFFFF 0x00001800
7841 # Register : DX8SL3IOCR @ 0XFD0814F0</p>
7843 # Reserved. Return zeroes on reads.
7844 # PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0
7846 # PVREF_DAC REFSEL range select
7847 # PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7
7849 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
7850 # PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0
7853 # PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2
7855 # DX IO Transmitter Mode
7856 # PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0
7858 # DX IO Receiver Mode
7859 # PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0
7861 # DATX8 0-1 I/O Configuration Register
7862 #(OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) */
7863 mask_write 0XFD0814F0 0xFFFFFFFF 0x70800000
7864 # Register : DX8SL4DQSCTL @ 0XFD08151C</p>
7866 # Reserved. Return zeroes on reads.
7867 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0
7869 # Read Path Rise-to-Rise Mode
7870 # PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1
7872 # Reserved. Return zeroes on reads.
7873 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0
7875 # Write Path Rise-to-Rise Mode
7876 # PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1
7878 # DQS Gate Extension
7879 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0
7881 # Low Power PLL Power Down
7882 # PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1
7884 # Low Power I/O Power Down
7885 # PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1
7887 # Reserved. Return zeroes on reads.
7888 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0
7891 # PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1
7893 # Unused DQ I/O Mode
7894 # PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0
7896 # Reserved. Return zeroes on reads.
7897 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0
7900 # PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
7903 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0xc
7906 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x4
7908 # DATX8 0-1 DQS Control Register
7909 #(OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U) */
7910 mask_write 0XFD08151C 0xFFFFFFFF 0x012643C4
7911 # Register : DX8SL4DXCTL2 @ 0XFD08152C</p>
7913 # Reserved. Return zeroes on reads.
7914 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0
7916 # Configurable Read Data Enable
7917 # PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0
7919 # OX Extension during Post-amble
7920 # PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
7922 # OE Extension during Pre-amble
7923 # PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x0
7925 # Reserved. Return zeroes on reads.
7926 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
7928 # I/O Assisted Gate Select
7929 # PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0
7931 # I/O Loopback Select
7932 # PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0
7934 # Reserved. Return zeroes on reads.
7935 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0
7937 # Low Power Wakeup Threshold
7938 # PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc
7940 # Read Data Bus Inversion Enable
7941 # PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0
7943 # Write Data Bus Inversion Enable
7944 # PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0
7946 # PUB Read FIFO Bypass
7947 # PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0
7949 # DATX8 Receive FIFO Read Mode
7950 # PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0
7952 # Disables the Read FIFO Reset
7953 # PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0
7955 # Read DQS Gate I/O Loopback
7956 # PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0
7958 # Reserved. Return zeroes on reads.
7959 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
7961 # DATX8 0-1 DX Control Register 2
7962 #(OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00001800U) */
7963 mask_write 0XFD08152C 0xFFFFFFFF 0x00001800
7964 # Register : DX8SL4IOCR @ 0XFD081530</p>
7966 # Reserved. Return zeroes on reads.
7967 # PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0
7969 # PVREF_DAC REFSEL range select
7970 # PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7
7972 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
7973 # PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0
7976 # PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2
7978 # DX IO Transmitter Mode
7979 # PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0
7981 # DX IO Receiver Mode
7982 # PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0
7984 # DATX8 0-1 I/O Configuration Register
7985 #(OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) */
7986 mask_write 0XFD081530 0xFFFFFFFF 0x70800000
7987 # Register : DX8SLbDQSCTL @ 0XFD0817DC</p>
7989 # Reserved. Return zeroes on reads.
7990 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0
7992 # Read Path Rise-to-Rise Mode
7993 # PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1
7995 # Reserved. Return zeroes on reads.
7996 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0
7998 # Write Path Rise-to-Rise Mode
7999 # PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1
8001 # DQS Gate Extension
8002 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0
8004 # Low Power PLL Power Down
8005 # PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1
8007 # Low Power I/O Power Down
8008 # PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1
8010 # Reserved. Return zeroes on reads.
8011 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0
8014 # PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1
8016 # Unused DQ I/O Mode
8017 # PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0
8019 # Reserved. Return zeroes on reads.
8020 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0
8023 # PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3
8026 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc
8029 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4
8031 # DATX8 0-8 DQS Control Register
8032 #(OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) */
8033 mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4
8034 # Register : PIR @ 0XFD080004</p>
8036 # Reserved. Return zeroes on reads.
8037 # PSU_DDR_PHY_PIR_RESERVED_31 0x0
8039 # Impedance Calibration Bypass
8040 # PSU_DDR_PHY_PIR_ZCALBYP 0x0
8042 # Digital Delay Line (DDL) Calibration Pause
8043 # PSU_DDR_PHY_PIR_DCALPSE 0x0
8045 # Reserved. Return zeroes on reads.
8046 # PSU_DDR_PHY_PIR_RESERVED_28_21 0x0
8048 # Write DQS2DQ Training
8049 # PSU_DDR_PHY_PIR_DQS2DQ 0x0
8051 # RDIMM Initialization
8052 # PSU_DDR_PHY_PIR_RDIMMINIT 0x0
8054 # Controller DRAM Initialization
8055 # PSU_DDR_PHY_PIR_CTLDINIT 0x1
8058 # PSU_DDR_PHY_PIR_VREF 0x0
8060 # Static Read Training
8061 # PSU_DDR_PHY_PIR_SRD 0x0
8063 # Write Data Eye Training
8064 # PSU_DDR_PHY_PIR_WREYE 0x0
8066 # Read Data Eye Training
8067 # PSU_DDR_PHY_PIR_RDEYE 0x0
8069 # Write Data Bit Deskew
8070 # PSU_DDR_PHY_PIR_WRDSKW 0x0
8072 # Read Data Bit Deskew
8073 # PSU_DDR_PHY_PIR_RDDSKW 0x0
8075 # Write Leveling Adjust
8076 # PSU_DDR_PHY_PIR_WLADJ 0x0
8078 # Read DQS Gate Training
8079 # PSU_DDR_PHY_PIR_QSGATE 0x0
8082 # PSU_DDR_PHY_PIR_WL 0x0
8084 # DRAM Initialization
8085 # PSU_DDR_PHY_PIR_DRAMINIT 0x0
8087 # DRAM Reset (DDR3/DDR4/LPDDR4 Only)
8088 # PSU_DDR_PHY_PIR_DRAMRST 0x0
8091 # PSU_DDR_PHY_PIR_PHYRST 0x1
8093 # Digital Delay Line (DDL) Calibration
8094 # PSU_DDR_PHY_PIR_DCAL 0x1
8096 # PLL Initialiazation
8097 # PSU_DDR_PHY_PIR_PLLINIT 0x1
8099 # Reserved. Return zeroes on reads.
8100 # PSU_DDR_PHY_PIR_RESERVED_3 0x0
8103 # PSU_DDR_PHY_PIR_CA 0x0
8105 # Impedance Calibration
8106 # PSU_DDR_PHY_PIR_ZCAL 0x1
8108 # Initialization Trigger
8109 # PSU_DDR_PHY_PIR_INIT 0x1
8111 # PHY Initialization Register
8112 #(OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) */
8113 mask_write 0XFD080004 0xFFFFFFFF 0x00040073
8116 set psu_mio_init_data {
8118 # Register : MIO_PIN_0 @ 0XFF180000</p>
8120 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
8121 # PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1
8123 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8124 # PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0
8126 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
8127 # t, test_scan_out[0]- (Test Scan Port) 3= Not Used
8128 # PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0
8130 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
8131 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
8132 # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
8133 # ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
8134 # lk- (Trace Port Clock)
8135 # PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0
8137 # Configures MIO Pin 0 peripheral interface mapping. S
8138 #(OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) */
8139 mask_write 0XFF180000 0x000000FE 0x00000002
8140 # Register : MIO_PIN_1 @ 0XFF180004</p>
8142 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
8144 # PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1
8146 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8147 # PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0
8149 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
8150 # t, test_scan_out[1]- (Test Scan Port) 3= Not Used
8151 # PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0
8153 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
8154 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
8155 # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
8156 # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
8158 # PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0
8160 # Configures MIO Pin 1 peripheral interface mapping
8161 #(OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) */
8162 mask_write 0XFF180004 0x000000FE 0x00000002
8163 # Register : MIO_PIN_2 @ 0XFF180008</p>
8165 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
8166 # PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1
8168 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8169 # PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0
8171 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
8172 # t, test_scan_out[2]- (Test Scan Port) 3= Not Used
8173 # PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0
8175 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
8176 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
8177 # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
8178 # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
8179 # PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0
8181 # Configures MIO Pin 2 peripheral interface mapping
8182 #(OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) */
8183 mask_write 0XFF180008 0x000000FE 0x00000002
8184 # Register : MIO_PIN_3 @ 0XFF18000C</p>
8186 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
8187 # PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1
8189 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8190 # PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0
8192 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
8193 # t, test_scan_out[3]- (Test Scan Port) 3= Not Used
8194 # PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0
8196 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
8197 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
8198 # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
8199 # - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
8200 # output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
8201 # PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0
8203 # Configures MIO Pin 3 peripheral interface mapping
8204 #(OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) */
8205 mask_write 0XFF18000C 0x000000FE 0x00000002
8206 # Register : MIO_PIN_4 @ 0XFF180010</p>
8208 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
8210 # PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1
8212 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8213 # PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0
8215 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
8216 # t, test_scan_out[4]- (Test Scan Port) 3= Not Used
8217 # PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0
8219 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
8220 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
8221 # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
8222 # - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
8223 # utput, tracedq[2]- (Trace Port Databus)
8224 # PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0
8226 # Configures MIO Pin 4 peripheral interface mapping
8227 #(OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) */
8228 mask_write 0XFF180010 0x000000FE 0x00000002
8229 # Register : MIO_PIN_5 @ 0XFF180014</p>
8231 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
8232 # PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1
8234 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8235 # PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0
8237 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
8238 # t, test_scan_out[5]- (Test Scan Port) 3= Not Used
8239 # PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0
8241 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
8242 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
8243 # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
8244 # si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
8245 # trace, Output, tracedq[3]- (Trace Port Databus)
8246 # PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0
8248 # Configures MIO Pin 5 peripheral interface mapping
8249 #(OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) */
8250 mask_write 0XFF180014 0x000000FE 0x00000002
8251 # Register : MIO_PIN_6 @ 0XFF180018</p>
8253 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
8254 # PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1
8256 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8257 # PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0
8259 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
8260 # t, test_scan_out[6]- (Test Scan Port) 3= Not Used
8261 # PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0
8263 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
8264 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
8265 # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
8266 # sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
8267 # Output, tracedq[4]- (Trace Port Databus)
8268 # PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0
8270 # Configures MIO Pin 6 peripheral interface mapping
8271 #(OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) */
8272 mask_write 0XFF180018 0x000000FE 0x00000002
8273 # Register : MIO_PIN_7 @ 0XFF18001C</p>
8275 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
8276 # PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1
8278 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8279 # PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0
8281 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
8282 # t, test_scan_out[7]- (Test Scan Port) 3= Not Used
8283 # PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0
8285 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
8286 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
8287 # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
8288 # tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
8289 # racedq[5]- (Trace Port Databus)
8290 # PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0
8292 # Configures MIO Pin 7 peripheral interface mapping
8293 #(OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) */
8294 mask_write 0XFF18001C 0x000000FE 0x00000002
8295 # Register : MIO_PIN_8 @ 0XFF180020</p>
8297 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
8298 # [0]- (QSPI Upper Databus)
8299 # PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1
8301 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8302 # PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0
8304 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
8305 # t, test_scan_out[8]- (Test Scan Port) 3= Not Used
8306 # PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0
8308 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
8309 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
8310 # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
8311 # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
8313 # PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0
8315 # Configures MIO Pin 8 peripheral interface mapping
8316 #(OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) */
8317 mask_write 0XFF180020 0x000000FE 0x00000002
8318 # Register : MIO_PIN_9 @ 0XFF180024</p>
8320 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
8321 # [1]- (QSPI Upper Databus)
8322 # PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1
8324 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
8325 # PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0
8327 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
8328 # t, test_scan_out[9]- (Test Scan Port) 3= Not Used
8329 # PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0
8331 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
8332 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
8333 # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
8334 # utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
8335 # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
8336 # PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0
8338 # Configures MIO Pin 9 peripheral interface mapping
8339 #(OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) */
8340 mask_write 0XFF180024 0x000000FE 0x00000002
8341 # Register : MIO_PIN_10 @ 0XFF180028</p>
8343 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
8344 # [2]- (QSPI Upper Databus)
8345 # PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1
8347 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
8348 # PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0
8350 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
8351 # ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
8352 # PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0
8354 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
8355 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
8356 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
8357 # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
8358 # t, tracedq[8]- (Trace Port Databus)
8359 # PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0
8361 # Configures MIO Pin 10 peripheral interface mapping
8362 #(OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) */
8363 mask_write 0XFF180028 0x000000FE 0x00000002
8364 # Register : MIO_PIN_11 @ 0XFF18002C</p>
8366 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
8367 # [3]- (QSPI Upper Databus)
8368 # PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1
8370 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
8371 # PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0
8373 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
8374 # ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
8375 # PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0
8377 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
8378 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
8379 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
8380 # i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
8381 # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
8382 # PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0
8384 # Configures MIO Pin 11 peripheral interface mapping
8385 #(OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) */
8386 mask_write 0XFF18002C 0x000000FE 0x00000002
8387 # Register : MIO_PIN_12 @ 0XFF180030</p>
8389 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
8390 # PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1
8392 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
8394 # PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0
8396 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
8397 # ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
8398 # PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0
8400 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
8401 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
8402 # al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
8403 # ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
8404 # dq[10]- (Trace Port Databus)
8405 # PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0
8407 # Configures MIO Pin 12 peripheral interface mapping
8408 #(OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) */
8409 mask_write 0XFF180030 0x000000FE 0x00000002
8410 # Register : MIO_PIN_13 @ 0XFF180034</p>
8412 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8413 # PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0
8415 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
8416 # PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0
8418 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
8419 # bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
8421 # PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0
8423 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
8424 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
8425 # l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
8426 # out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
8428 # PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0
8430 # Configures MIO Pin 13 peripheral interface mapping
8431 #(OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) */
8432 mask_write 0XFF180034 0x000000FE 0x00000000
8433 # Register : MIO_PIN_14 @ 0XFF180038</p>
8435 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8436 # PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0
8438 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
8439 # PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0
8441 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
8442 # bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
8444 # PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0
8446 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
8447 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
8448 # l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
8449 # n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
8450 # PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2
8452 # Configures MIO Pin 14 peripheral interface mapping
8453 #(OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) */
8454 mask_write 0XFF180038 0x000000FE 0x00000040
8455 # Register : MIO_PIN_15 @ 0XFF18003C</p>
8457 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8458 # PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0
8460 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
8461 # PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0
8463 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
8464 # bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
8466 # PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0
8468 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
8469 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
8470 # al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
8471 # 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
8472 # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
8473 # PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2
8475 # Configures MIO Pin 15 peripheral interface mapping
8476 #(OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) */
8477 mask_write 0XFF18003C 0x000000FE 0x00000040
8478 # Register : MIO_PIN_16 @ 0XFF180040</p>
8480 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8481 # PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0
8483 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
8485 # PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0
8487 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
8488 # bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
8490 # PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0
8492 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
8493 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
8494 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
8495 # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
8496 # Output, tracedq[14]- (Trace Port Databus)
8497 # PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2
8499 # Configures MIO Pin 16 peripheral interface mapping
8500 #(OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) */
8501 mask_write 0XFF180040 0x000000FE 0x00000040
8502 # Register : MIO_PIN_17 @ 0XFF180044</p>
8504 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8505 # PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0
8507 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
8509 # PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0
8511 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
8512 # bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
8514 # PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0
8516 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
8517 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
8518 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
8519 # 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
8520 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
8521 # PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2
8523 # Configures MIO Pin 17 peripheral interface mapping
8524 #(OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) */
8525 mask_write 0XFF180044 0x000000FE 0x00000040
8526 # Register : MIO_PIN_18 @ 0XFF180048</p>
8528 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8529 # PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0
8531 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
8533 # PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0
8535 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
8536 # bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
8537 # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8538 # PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0
8540 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
8541 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
8542 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
8543 # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
8544 # PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6
8546 # Configures MIO Pin 18 peripheral interface mapping
8547 #(OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) */
8548 mask_write 0XFF180048 0x000000FE 0x000000C0
8549 # Register : MIO_PIN_19 @ 0XFF18004C</p>
8551 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8552 # PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0
8554 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
8556 # PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0
8558 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
8559 # bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
8560 # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8561 # PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0
8563 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
8564 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
8565 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
8566 # ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
8567 # PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6
8569 # Configures MIO Pin 19 peripheral interface mapping
8570 #(OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) */
8571 mask_write 0XFF18004C 0x000000FE 0x000000C0
8572 # Register : MIO_PIN_20 @ 0XFF180050</p>
8574 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8575 # PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0
8577 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
8579 # PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0
8581 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
8582 # bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
8583 # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8584 # PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0
8586 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
8587 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
8588 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
8589 # c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
8590 # PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6
8592 # Configures MIO Pin 20 peripheral interface mapping
8593 #(OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) */
8594 mask_write 0XFF180050 0x000000FE 0x000000C0
8595 # Register : MIO_PIN_21 @ 0XFF180054</p>
8597 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8598 # PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0
8600 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
8602 # PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0
8604 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
8605 # Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
8606 # = csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8607 # PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0
8609 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
8610 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
8611 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
8612 # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
8613 # UART receiver serial input) 7= Not Used
8614 # PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6
8616 # Configures MIO Pin 21 peripheral interface mapping
8617 #(OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) */
8618 mask_write 0XFF180054 0x000000FE 0x000000C0
8619 # Register : MIO_PIN_22 @ 0XFF180058</p>
8621 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8622 # PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0
8624 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
8625 # PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0
8627 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
8628 # (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8629 # PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0
8631 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
8632 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
8633 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
8634 # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
8636 # PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0
8638 # Configures MIO Pin 22 peripheral interface mapping
8639 #(OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) */
8640 mask_write 0XFF180058 0x000000FE 0x00000000
8641 # Register : MIO_PIN_23 @ 0XFF18005C</p>
8643 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8644 # PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0
8646 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
8648 # PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0
8650 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
8651 # 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
8653 # PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0
8655 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
8656 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
8657 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
8658 # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
8660 # PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0
8662 # Configures MIO Pin 23 peripheral interface mapping
8663 #(OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) */
8664 mask_write 0XFF18005C 0x000000FE 0x00000000
8665 # Register : MIO_PIN_24 @ 0XFF180060</p>
8667 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8668 # PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0
8670 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
8672 # PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0
8674 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
8675 # scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
8677 # PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0
8679 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
8680 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
8681 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
8682 # Output, ua1_txd- (UART transmitter serial output) 7= Not Used
8683 # PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1
8685 # Configures MIO Pin 24 peripheral interface mapping
8686 #(OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) */
8687 mask_write 0XFF180060 0x000000FE 0x00000020
8688 # Register : MIO_PIN_25 @ 0XFF180064</p>
8690 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
8691 # PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0
8693 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
8694 # PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0
8696 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
8697 # test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
8699 # PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0
8701 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
8702 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
8703 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
8704 # lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
8705 # PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1
8707 # Configures MIO Pin 25 peripheral interface mapping
8708 #(OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) */
8709 mask_write 0XFF180064 0x000000FE 0x00000020
8710 # Register : MIO_PIN_26 @ 0XFF180068</p>
8712 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
8713 # PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0
8715 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
8716 # PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0
8718 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
8719 # n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8720 # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 1
8722 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
8723 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
8724 # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
8725 # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
8726 # Trace Port Databus)
8727 # PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
8729 # Configures MIO Pin 26 peripheral interface mapping
8730 #(OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000008U) */
8731 mask_write 0XFF180068 0x000000FE 0x00000008
8732 # Register : MIO_PIN_27 @ 0XFF18006C</p>
8734 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
8735 # PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0
8737 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
8738 # PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0
8740 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
8741 # n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
8742 # t, dp_aux_data_out- (Dp Aux Data)
8743 # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 0
8745 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
8746 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
8747 # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
8748 # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
8750 # PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
8752 # Configures MIO Pin 27 peripheral interface mapping
8753 #(OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000000U) */
8754 mask_write 0XFF18006C 0x000000FE 0x00000000
8755 # Register : MIO_PIN_28 @ 0XFF180070</p>
8757 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
8758 # PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0
8760 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
8761 # PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0
8763 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
8764 # n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
8765 # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 0
8767 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
8768 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
8769 # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
8770 # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
8771 # PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
8773 # Configures MIO Pin 28 peripheral interface mapping
8774 #(OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000000U) */
8775 mask_write 0XFF180070 0x000000FE 0x00000000
8776 # Register : MIO_PIN_29 @ 0XFF180074</p>
8778 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
8779 # PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0
8781 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8782 # PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0
8784 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
8785 # n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
8786 # t, dp_aux_data_out- (Dp Aux Data)
8787 # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 0
8789 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
8790 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
8791 # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
8792 # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
8793 # ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
8794 # PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
8796 # Configures MIO Pin 29 peripheral interface mapping
8797 #(OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000000U) */
8798 mask_write 0XFF180074 0x000000FE 0x00000000
8799 # Register : MIO_PIN_30 @ 0XFF180078</p>
8801 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
8802 # PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0
8804 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8805 # PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0
8807 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
8808 # n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
8809 # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 0
8811 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
8812 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
8813 # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
8814 # (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
8815 # tracedq[8]- (Trace Port Databus)
8816 # PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
8818 # Configures MIO Pin 30 peripheral interface mapping
8819 #(OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000000U) */
8820 mask_write 0XFF180078 0x000000FE 0x00000000
8821 # Register : MIO_PIN_31 @ 0XFF18007C</p>
8823 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
8824 # PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0
8826 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8827 # PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0
8829 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
8830 # n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8831 # PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0
8833 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
8834 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
8835 # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
8836 # _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
8837 # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
8838 # PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0
8840 # Configures MIO Pin 31 peripheral interface mapping
8841 #(OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) */
8842 mask_write 0XFF18007C 0x000000FE 0x00000000
8843 # Register : MIO_PIN_32 @ 0XFF180080</p>
8845 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
8846 # PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0
8848 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
8850 # PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0
8852 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
8853 # an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8854 # PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1
8856 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
8857 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
8858 # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
8859 # _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
8860 # race, Output, tracedq[10]- (Trace Port Databus)
8861 # PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0
8863 # Configures MIO Pin 32 peripheral interface mapping
8864 #(OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) */
8865 mask_write 0XFF180080 0x000000FE 0x00000008
8866 # Register : MIO_PIN_33 @ 0XFF180084</p>
8868 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
8869 # PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0
8871 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8872 # PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0
8874 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
8875 # an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
8876 # PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1
8878 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
8879 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
8880 # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
8881 # c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
8882 # [11]- (Trace Port Databus)
8883 # PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0
8885 # Configures MIO Pin 33 peripheral interface mapping
8886 #(OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) */
8887 mask_write 0XFF180084 0x000000FE 0x00000008
8888 # Register : MIO_PIN_34 @ 0XFF180088</p>
8890 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
8891 # PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0
8893 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8894 # PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0
8896 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
8897 # an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
8898 # ut, dp_aux_data_out- (Dp Aux Data)
8899 # PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1
8901 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
8902 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
8903 # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
8904 # Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
8906 # PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0
8908 # Configures MIO Pin 34 peripheral interface mapping
8909 #(OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) */
8910 mask_write 0XFF180088 0x000000FE 0x00000008
8911 # Register : MIO_PIN_35 @ 0XFF18008C</p>
8913 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
8914 # PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0
8916 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8917 # PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0
8919 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
8920 # an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
8921 # PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1
8923 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
8924 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
8925 # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
8926 # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
8927 # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
8928 # PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0
8930 # Configures MIO Pin 35 peripheral interface mapping
8931 #(OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) */
8932 mask_write 0XFF18008C 0x000000FE 0x00000008
8933 # Register : MIO_PIN_36 @ 0XFF180090</p>
8935 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
8936 # PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0
8938 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8939 # PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0
8941 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
8942 # an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
8943 # ut, dp_aux_data_out- (Dp Aux Data)
8944 # PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1
8946 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
8947 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
8948 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
8949 # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
8950 # Output, tracedq[14]- (Trace Port Databus)
8951 # PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0
8953 # Configures MIO Pin 36 peripheral interface mapping
8954 #(OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) */
8955 mask_write 0XFF180090 0x000000FE 0x00000008
8956 # Register : MIO_PIN_37 @ 0XFF180094</p>
8958 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
8959 # PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0
8961 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
8962 # PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0
8964 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
8965 # an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
8966 # PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1
8968 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
8969 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
8970 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
8971 # 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
8972 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
8973 # PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0
8975 # Configures MIO Pin 37 peripheral interface mapping
8976 #(OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) */
8977 mask_write 0XFF180094 0x000000FE 0x00000008
8978 # Register : MIO_PIN_38 @ 0XFF180098</p>
8980 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
8981 # PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0
8983 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
8984 # PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0
8986 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
8987 # PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0
8989 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
8990 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
8991 # l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
8992 # k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
8993 # (Trace Port Clock)
8994 # PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0
8996 # Configures MIO Pin 38 peripheral interface mapping
8997 #(OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) */
8998 mask_write 0XFF180098 0x000000FE 0x00000000
8999 # Register : MIO_PIN_39 @ 0XFF18009C</p>
9001 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
9002 # PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0
9004 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9005 # PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0
9007 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
9008 # [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
9009 # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0
9011 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
9012 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9013 # al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
9014 # _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
9016 # PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0
9018 # Configures MIO Pin 39 peripheral interface mapping
9019 #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) */
9020 mask_write 0XFF18009C 0x000000FE 0x00000000
9021 # Register : MIO_PIN_40 @ 0XFF1800A0</p>
9023 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
9024 # PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0
9026 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9027 # PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0
9029 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
9030 # Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
9031 # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0
9033 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
9034 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9035 # al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
9036 # in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
9037 # PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0
9039 # Configures MIO Pin 40 peripheral interface mapping
9040 #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) */
9041 mask_write 0XFF1800A0 0x000000FE 0x00000000
9042 # Register : MIO_PIN_41 @ 0XFF1800A4</p>
9044 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
9045 # PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0
9047 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9048 # PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0
9050 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
9051 # bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
9052 # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0
9054 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
9055 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9056 # l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
9057 # ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
9058 # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
9059 # PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0
9061 # Configures MIO Pin 41 peripheral interface mapping
9062 #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) */
9063 mask_write 0XFF1800A4 0x000000FE 0x00000000
9064 # Register : MIO_PIN_42 @ 0XFF1800A8</p>
9066 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
9067 # PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0
9069 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9070 # PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0
9072 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
9073 # bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
9074 # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0
9076 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
9077 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9078 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
9079 # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
9080 # t, tracedq[2]- (Trace Port Databus)
9081 # PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0
9083 # Configures MIO Pin 42 peripheral interface mapping
9084 #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) */
9085 mask_write 0XFF1800A8 0x000000FE 0x00000000
9086 # Register : MIO_PIN_43 @ 0XFF1800AC</p>
9088 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
9089 # PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0
9091 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9092 # PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0
9094 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
9095 # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
9096 # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2
9098 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
9099 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9100 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
9101 # i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
9102 # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
9103 # PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0
9105 # Configures MIO Pin 43 peripheral interface mapping
9106 #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) */
9107 mask_write 0XFF1800AC 0x000000FE 0x00000010
9108 # Register : MIO_PIN_44 @ 0XFF1800B0</p>
9110 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
9111 # PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0
9113 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9114 # PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0
9116 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
9117 # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
9118 # PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2
9120 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
9121 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9122 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
9123 # i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
9125 # PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0
9127 # Configures MIO Pin 44 peripheral interface mapping
9128 #(OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) */
9129 mask_write 0XFF1800B0 0x000000FE 0x00000010
9130 # Register : MIO_PIN_45 @ 0XFF1800B4</p>
9132 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
9133 # PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0
9135 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9136 # PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0
9138 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
9139 # bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
9140 # PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2
9142 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
9143 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9144 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
9145 # ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
9146 # PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0
9148 # Configures MIO Pin 45 peripheral interface mapping
9149 #(OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) */
9150 mask_write 0XFF1800B4 0x000000FE 0x00000010
9151 # Register : MIO_PIN_46 @ 0XFF1800B8</p>
9153 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
9154 # PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0
9156 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9157 # PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0
9159 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
9160 # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
9161 # PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2
9163 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
9164 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9165 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
9166 # 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
9167 # PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0
9169 # Configures MIO Pin 46 peripheral interface mapping
9170 #(OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) */
9171 mask_write 0XFF1800B8 0x000000FE 0x00000010
9172 # Register : MIO_PIN_47 @ 0XFF1800BC</p>
9174 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
9175 # PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0
9177 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9178 # PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0
9180 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
9181 # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
9182 # PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2
9184 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
9185 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9186 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
9187 # , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
9188 # (UART transmitter serial output) 7= Not Used
9189 # PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0
9191 # Configures MIO Pin 47 peripheral interface mapping
9192 #(OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) */
9193 mask_write 0XFF1800BC 0x000000FE 0x00000010
9194 # Register : MIO_PIN_48 @ 0XFF1800C0</p>
9196 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
9197 # PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0
9199 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9200 # PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0
9202 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
9203 # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
9204 # PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2
9206 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
9207 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9208 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
9209 # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
9211 # PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0
9213 # Configures MIO Pin 48 peripheral interface mapping
9214 #(OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) */
9215 mask_write 0XFF1800C0 0x000000FE 0x00000010
9216 # Register : MIO_PIN_49 @ 0XFF1800C4</p>
9218 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
9219 # PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0
9221 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9222 # PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0
9224 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
9225 # bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
9226 # PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2
9228 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
9229 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9230 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
9231 # 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
9233 # PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0
9235 # Configures MIO Pin 49 peripheral interface mapping
9236 #(OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) */
9237 mask_write 0XFF1800C4 0x000000FE 0x00000010
9238 # Register : MIO_PIN_50 @ 0XFF1800C8</p>
9240 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
9241 # PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0
9243 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9244 # PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0
9246 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
9247 # d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
9248 # PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2
9250 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
9251 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9252 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
9253 # clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
9254 # PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0
9256 # Configures MIO Pin 50 peripheral interface mapping
9257 #(OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) */
9258 mask_write 0XFF1800C8 0x000000FE 0x00000010
9259 # Register : MIO_PIN_51 @ 0XFF1800CC</p>
9261 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
9262 # PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0
9264 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9265 # PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0
9267 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
9268 # PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2
9270 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
9271 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9272 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
9273 # t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
9274 # serial output) 7= Not Used
9275 # PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0
9277 # Configures MIO Pin 51 peripheral interface mapping
9278 #(OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) */
9279 mask_write 0XFF1800CC 0x000000FE 0x00000010
9280 # Register : MIO_PIN_52 @ 0XFF1800D0</p>
9282 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
9283 # PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0
9285 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
9286 # PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1
9288 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9289 # PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0
9291 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
9292 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
9293 # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
9294 # ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
9295 # lk- (Trace Port Clock)
9296 # PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0
9298 # Configures MIO Pin 52 peripheral interface mapping
9299 #(OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) */
9300 mask_write 0XFF1800D0 0x000000FE 0x00000004
9301 # Register : MIO_PIN_53 @ 0XFF1800D4</p>
9303 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
9304 # PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0
9306 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
9307 # PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1
9309 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9310 # PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0
9312 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
9313 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
9314 # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
9315 # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
9317 # PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0
9319 # Configures MIO Pin 53 peripheral interface mapping
9320 #(OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) */
9321 mask_write 0XFF1800D4 0x000000FE 0x00000004
9322 # Register : MIO_PIN_54 @ 0XFF1800D8</p>
9324 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
9325 # PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0
9327 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9328 # ata[2]- (ULPI data bus)
9329 # PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1
9331 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9332 # PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0
9334 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
9335 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
9336 # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
9337 # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
9338 # PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0
9340 # Configures MIO Pin 54 peripheral interface mapping
9341 #(OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) */
9342 mask_write 0XFF1800D8 0x000000FE 0x00000004
9343 # Register : MIO_PIN_55 @ 0XFF1800DC</p>
9345 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
9346 # PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0
9348 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
9349 # PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1
9351 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9352 # PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0
9354 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
9355 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
9356 # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
9357 # - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
9358 # output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
9359 # PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0
9361 # Configures MIO Pin 55 peripheral interface mapping
9362 #(OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) */
9363 mask_write 0XFF1800DC 0x000000FE 0x00000004
9364 # Register : MIO_PIN_56 @ 0XFF1800E0</p>
9366 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
9367 # PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0
9369 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9370 # ata[0]- (ULPI data bus)
9371 # PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1
9373 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9374 # PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0
9376 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
9377 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
9378 # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
9379 # - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
9380 # utput, tracedq[2]- (Trace Port Databus)
9381 # PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0
9383 # Configures MIO Pin 56 peripheral interface mapping
9384 #(OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) */
9385 mask_write 0XFF1800E0 0x000000FE 0x00000004
9386 # Register : MIO_PIN_57 @ 0XFF1800E4</p>
9388 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
9389 # PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0
9391 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9392 # ata[1]- (ULPI data bus)
9393 # PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1
9395 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9396 # PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0
9398 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
9399 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
9400 # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
9401 # si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
9402 # trace, Output, tracedq[3]- (Trace Port Databus)
9403 # PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0
9405 # Configures MIO Pin 57 peripheral interface mapping
9406 #(OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) */
9407 mask_write 0XFF1800E4 0x000000FE 0x00000004
9408 # Register : MIO_PIN_58 @ 0XFF1800E8</p>
9410 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
9411 # PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0
9413 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
9414 # PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1
9416 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9417 # PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0
9419 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
9420 # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
9421 # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
9422 # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
9423 # Trace Port Databus)
9424 # PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0
9426 # Configures MIO Pin 58 peripheral interface mapping
9427 #(OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) */
9428 mask_write 0XFF1800E8 0x000000FE 0x00000004
9429 # Register : MIO_PIN_59 @ 0XFF1800EC</p>
9431 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
9432 # PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0
9434 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9435 # ata[3]- (ULPI data bus)
9436 # PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1
9438 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9439 # PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0
9441 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
9442 # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
9443 # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
9444 # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
9446 # PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0
9448 # Configures MIO Pin 59 peripheral interface mapping
9449 #(OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) */
9450 mask_write 0XFF1800EC 0x000000FE 0x00000004
9451 # Register : MIO_PIN_60 @ 0XFF1800F0</p>
9453 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
9454 # PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0
9456 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9457 # ata[4]- (ULPI data bus)
9458 # PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1
9460 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9461 # PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0
9463 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
9464 # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
9465 # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
9466 # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
9467 # PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0
9469 # Configures MIO Pin 60 peripheral interface mapping
9470 #(OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) */
9471 mask_write 0XFF1800F0 0x000000FE 0x00000004
9472 # Register : MIO_PIN_61 @ 0XFF1800F4</p>
9474 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
9475 # PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0
9477 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9478 # ata[5]- (ULPI data bus)
9479 # PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1
9481 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9482 # PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0
9484 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
9485 # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
9486 # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
9487 # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
9488 # ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
9489 # PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0
9491 # Configures MIO Pin 61 peripheral interface mapping
9492 #(OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) */
9493 mask_write 0XFF1800F4 0x000000FE 0x00000004
9494 # Register : MIO_PIN_62 @ 0XFF1800F8</p>
9496 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
9497 # PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0
9499 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9500 # ata[6]- (ULPI data bus)
9501 # PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1
9503 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9504 # PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0
9506 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
9507 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9508 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
9509 # o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
9510 # t, tracedq[8]- (Trace Port Databus)
9511 # PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0
9513 # Configures MIO Pin 62 peripheral interface mapping
9514 #(OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) */
9515 mask_write 0XFF1800F8 0x000000FE 0x00000004
9516 # Register : MIO_PIN_63 @ 0XFF1800FC</p>
9518 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
9519 # PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0
9521 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
9522 # ata[7]- (ULPI data bus)
9523 # PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1
9525 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
9526 # PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0
9528 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
9529 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9530 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
9531 # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
9532 # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
9533 # PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0
9535 # Configures MIO Pin 63 peripheral interface mapping
9536 #(OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) */
9537 mask_write 0XFF1800FC 0x000000FE 0x00000004
9538 # Register : MIO_PIN_64 @ 0XFF180100</p>
9540 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
9541 # PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1
9543 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
9544 # PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0
9546 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
9547 # PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0
9549 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
9550 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9551 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
9552 # i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
9553 # trace, Output, tracedq[10]- (Trace Port Databus)
9554 # PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0
9556 # Configures MIO Pin 64 peripheral interface mapping
9557 #(OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) */
9558 mask_write 0XFF180100 0x000000FE 0x00000002
9559 # Register : MIO_PIN_65 @ 0XFF180104</p>
9561 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
9562 # PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1
9564 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
9565 # PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0
9567 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
9568 # PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0
9570 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
9571 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9572 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
9573 # ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
9574 # dq[11]- (Trace Port Databus)
9575 # PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0
9577 # Configures MIO Pin 65 peripheral interface mapping
9578 #(OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) */
9579 mask_write 0XFF180104 0x000000FE 0x00000002
9580 # Register : MIO_PIN_66 @ 0XFF180108</p>
9582 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
9583 # PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1
9585 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9586 # ata[2]- (ULPI data bus)
9587 # PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0
9589 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
9590 # Indicator) 2= Not Used 3= Not Used
9591 # PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0
9593 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
9594 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9595 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
9596 # 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
9598 # PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0
9600 # Configures MIO Pin 66 peripheral interface mapping
9601 #(OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) */
9602 mask_write 0XFF180108 0x000000FE 0x00000002
9603 # Register : MIO_PIN_67 @ 0XFF18010C</p>
9605 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
9606 # PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1
9608 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
9609 # PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0
9611 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
9612 # bit Data bus) 2= Not Used 3= Not Used
9613 # PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0
9615 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
9616 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9617 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
9618 # , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
9619 # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
9620 # PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0
9622 # Configures MIO Pin 67 peripheral interface mapping
9623 #(OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) */
9624 mask_write 0XFF18010C 0x000000FE 0x00000002
9625 # Register : MIO_PIN_68 @ 0XFF180110</p>
9627 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
9628 # PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1
9630 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9631 # ata[0]- (ULPI data bus)
9632 # PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0
9634 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
9635 # bit Data bus) 2= Not Used 3= Not Used
9636 # PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0
9638 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
9639 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9640 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
9641 # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
9642 # Output, tracedq[14]- (Trace Port Databus)
9643 # PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0
9645 # Configures MIO Pin 68 peripheral interface mapping
9646 #(OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) */
9647 mask_write 0XFF180110 0x000000FE 0x00000002
9648 # Register : MIO_PIN_69 @ 0XFF180114</p>
9650 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
9651 # PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1
9653 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9654 # ata[1]- (ULPI data bus)
9655 # PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0
9657 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
9658 # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
9659 # PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0
9661 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
9662 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9663 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
9664 # 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
9665 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
9666 # PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0
9668 # Configures MIO Pin 69 peripheral interface mapping
9669 #(OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) */
9670 mask_write 0XFF180114 0x000000FE 0x00000002
9671 # Register : MIO_PIN_70 @ 0XFF180118</p>
9673 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
9674 # PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1
9676 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
9677 # PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0
9679 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
9680 # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
9681 # PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0
9683 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
9684 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9685 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
9686 # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
9688 # PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0
9690 # Configures MIO Pin 70 peripheral interface mapping
9691 #(OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) */
9692 mask_write 0XFF180118 0x000000FE 0x00000002
9693 # Register : MIO_PIN_71 @ 0XFF18011C</p>
9695 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
9696 # PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1
9698 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9699 # ata[3]- (ULPI data bus)
9700 # PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0
9702 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
9703 # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
9704 # PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0
9706 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
9707 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9708 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
9709 # ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
9710 # PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0
9712 # Configures MIO Pin 71 peripheral interface mapping
9713 #(OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) */
9714 mask_write 0XFF18011C 0x000000FE 0x00000002
9715 # Register : MIO_PIN_72 @ 0XFF180120</p>
9717 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
9718 # PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1
9720 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9721 # ata[4]- (ULPI data bus)
9722 # PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0
9724 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
9725 # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
9726 # PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0
9728 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
9729 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9730 # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
9731 # t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
9732 # PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0
9734 # Configures MIO Pin 72 peripheral interface mapping
9735 #(OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) */
9736 mask_write 0XFF180120 0x000000FE 0x00000002
9737 # Register : MIO_PIN_73 @ 0XFF180124</p>
9739 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
9740 # PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1
9742 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9743 # ata[5]- (ULPI data bus)
9744 # PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0
9746 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
9747 # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
9748 # PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0
9750 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
9751 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9752 # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
9753 # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
9754 # PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0
9756 # Configures MIO Pin 73 peripheral interface mapping
9757 #(OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) */
9758 mask_write 0XFF180124 0x000000FE 0x00000002
9759 # Register : MIO_PIN_74 @ 0XFF180128</p>
9761 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
9762 # PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1
9764 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9765 # ata[6]- (ULPI data bus)
9766 # PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0
9768 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
9769 # bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
9770 # PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0
9772 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
9773 # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
9774 # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
9775 # o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
9776 # PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0
9778 # Configures MIO Pin 74 peripheral interface mapping
9779 #(OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) */
9780 mask_write 0XFF180128 0x000000FE 0x00000002
9781 # Register : MIO_PIN_75 @ 0XFF18012C</p>
9783 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
9784 # PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1
9786 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
9787 # ata[7]- (ULPI data bus)
9788 # PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0
9790 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
9791 # d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
9792 # PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0
9794 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
9795 # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
9796 # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
9797 # i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
9798 # PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0
9800 # Configures MIO Pin 75 peripheral interface mapping
9801 #(OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) */
9802 mask_write 0XFF18012C 0x000000FE 0x00000002
9803 # Register : MIO_PIN_76 @ 0XFF180130</p>
9805 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9806 # PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0
9808 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9809 # PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0
9811 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
9812 # _clk_out- (SDSDIO clock) 3= Not Used
9813 # PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0
9815 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
9816 # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
9817 # al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
9818 # 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
9819 # PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6
9821 # Configures MIO Pin 76 peripheral interface mapping
9822 #(OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) */
9823 mask_write 0XFF180130 0x000000FE 0x000000C0
9824 # Register : MIO_PIN_77 @ 0XFF180134</p>
9826 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9827 # PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0
9829 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9830 # PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0
9832 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
9833 # PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0
9835 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
9836 # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
9837 # l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
9838 # O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
9839 # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
9840 # PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6
9842 # Configures MIO Pin 77 peripheral interface mapping
9843 #(OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) */
9844 mask_write 0XFF180134 0x000000FE 0x000000C0
9845 # Register : MIO_MST_TRI0 @ 0XFF180204</p>
9847 # Master Tri-state Enable for pin 0, active high
9848 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0
9850 # Master Tri-state Enable for pin 1, active high
9851 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0
9853 # Master Tri-state Enable for pin 2, active high
9854 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0
9856 # Master Tri-state Enable for pin 3, active high
9857 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0
9859 # Master Tri-state Enable for pin 4, active high
9860 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0
9862 # Master Tri-state Enable for pin 5, active high
9863 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0
9865 # Master Tri-state Enable for pin 6, active high
9866 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0
9868 # Master Tri-state Enable for pin 7, active high
9869 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0
9871 # Master Tri-state Enable for pin 8, active high
9872 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0
9874 # Master Tri-state Enable for pin 9, active high
9875 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0
9877 # Master Tri-state Enable for pin 10, active high
9878 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0
9880 # Master Tri-state Enable for pin 11, active high
9881 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0
9883 # Master Tri-state Enable for pin 12, active high
9884 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0
9886 # Master Tri-state Enable for pin 13, active high
9887 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0
9889 # Master Tri-state Enable for pin 14, active high
9890 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0
9892 # Master Tri-state Enable for pin 15, active high
9893 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0
9895 # Master Tri-state Enable for pin 16, active high
9896 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0
9898 # Master Tri-state Enable for pin 17, active high
9899 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0
9901 # Master Tri-state Enable for pin 18, active high
9902 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1
9904 # Master Tri-state Enable for pin 19, active high
9905 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0
9907 # Master Tri-state Enable for pin 20, active high
9908 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0
9910 # Master Tri-state Enable for pin 21, active high
9911 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1
9913 # Master Tri-state Enable for pin 22, active high
9914 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0
9916 # Master Tri-state Enable for pin 23, active high
9917 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0
9919 # Master Tri-state Enable for pin 24, active high
9920 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0
9922 # Master Tri-state Enable for pin 25, active high
9923 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
9925 # Master Tri-state Enable for pin 26, active high
9926 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 1
9928 # Master Tri-state Enable for pin 27, active high
9929 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
9931 # Master Tri-state Enable for pin 28, active high
9932 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 0
9934 # Master Tri-state Enable for pin 29, active high
9935 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
9937 # Master Tri-state Enable for pin 30, active high
9938 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 0
9940 # Master Tri-state Enable for pin 31, active high
9941 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
9943 # MIO pin Tri-state Enables, 31:0
9944 #(OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x06240000U) */
9945 mask_write 0XFF180204 0xFFFFFFFF 0x06240000
9946 # Register : MIO_MST_TRI1 @ 0XFF180208</p>
9948 # Master Tri-state Enable for pin 32, active high
9949 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0
9951 # Master Tri-state Enable for pin 33, active high
9952 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0
9954 # Master Tri-state Enable for pin 34, active high
9955 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0
9957 # Master Tri-state Enable for pin 35, active high
9958 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0
9960 # Master Tri-state Enable for pin 36, active high
9961 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0
9963 # Master Tri-state Enable for pin 37, active high
9964 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0
9966 # Master Tri-state Enable for pin 38, active high
9967 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0
9969 # Master Tri-state Enable for pin 39, active high
9970 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0
9972 # Master Tri-state Enable for pin 40, active high
9973 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0
9975 # Master Tri-state Enable for pin 41, active high
9976 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0
9978 # Master Tri-state Enable for pin 42, active high
9979 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0
9981 # Master Tri-state Enable for pin 43, active high
9982 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0
9984 # Master Tri-state Enable for pin 44, active high
9985 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1
9987 # Master Tri-state Enable for pin 45, active high
9988 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1
9990 # Master Tri-state Enable for pin 46, active high
9991 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0
9993 # Master Tri-state Enable for pin 47, active high
9994 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0
9996 # Master Tri-state Enable for pin 48, active high
9997 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0
9999 # Master Tri-state Enable for pin 49, active high
10000 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0
10002 # Master Tri-state Enable for pin 50, active high
10003 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0
10005 # Master Tri-state Enable for pin 51, active high
10006 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0
10008 # Master Tri-state Enable for pin 52, active high
10009 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1
10011 # Master Tri-state Enable for pin 53, active high
10012 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1
10014 # Master Tri-state Enable for pin 54, active high
10015 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0
10017 # Master Tri-state Enable for pin 55, active high
10018 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1
10020 # Master Tri-state Enable for pin 56, active high
10021 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0
10023 # Master Tri-state Enable for pin 57, active high
10024 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
10026 # Master Tri-state Enable for pin 58, active high
10027 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0
10029 # Master Tri-state Enable for pin 59, active high
10030 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0
10032 # Master Tri-state Enable for pin 60, active high
10033 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0
10035 # Master Tri-state Enable for pin 61, active high
10036 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0
10038 # Master Tri-state Enable for pin 62, active high
10039 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0
10041 # Master Tri-state Enable for pin 63, active high
10042 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0
10044 # MIO pin Tri-state Enables, 63:32
10045 #(OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) */
10046 mask_write 0XFF180208 0xFFFFFFFF 0x00B03000
10047 # Register : MIO_MST_TRI2 @ 0XFF18020C</p>
10049 # Master Tri-state Enable for pin 64, active high
10050 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0
10052 # Master Tri-state Enable for pin 65, active high
10053 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0
10055 # Master Tri-state Enable for pin 66, active high
10056 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0
10058 # Master Tri-state Enable for pin 67, active high
10059 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0
10061 # Master Tri-state Enable for pin 68, active high
10062 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0
10064 # Master Tri-state Enable for pin 69, active high
10065 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0
10067 # Master Tri-state Enable for pin 70, active high
10068 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1
10070 # Master Tri-state Enable for pin 71, active high
10071 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1
10073 # Master Tri-state Enable for pin 72, active high
10074 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1
10076 # Master Tri-state Enable for pin 73, active high
10077 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1
10079 # Master Tri-state Enable for pin 74, active high
10080 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1
10082 # Master Tri-state Enable for pin 75, active high
10083 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1
10085 # Master Tri-state Enable for pin 76, active high
10086 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0
10088 # Master Tri-state Enable for pin 77, active high
10089 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0
10091 # MIO pin Tri-state Enables, 77:64
10092 #(OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) */
10093 mask_write 0XFF18020C 0x00003FFF 0x00000FC0
10094 # Register : bank0_ctrl0 @ 0XFF180138</p>
10096 # Each bit applies to a single IO. Bit 0 for MIO[0].
10097 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1
10099 # Each bit applies to a single IO. Bit 0 for MIO[0].
10100 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1
10102 # Each bit applies to a single IO. Bit 0 for MIO[0].
10103 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1
10105 # Each bit applies to a single IO. Bit 0 for MIO[0].
10106 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1
10108 # Each bit applies to a single IO. Bit 0 for MIO[0].
10109 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1
10111 # Each bit applies to a single IO. Bit 0 for MIO[0].
10112 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1
10114 # Each bit applies to a single IO. Bit 0 for MIO[0].
10115 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1
10117 # Each bit applies to a single IO. Bit 0 for MIO[0].
10118 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1
10120 # Each bit applies to a single IO. Bit 0 for MIO[0].
10121 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1
10123 # Each bit applies to a single IO. Bit 0 for MIO[0].
10124 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1
10126 # Each bit applies to a single IO. Bit 0 for MIO[0].
10127 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1
10129 # Each bit applies to a single IO. Bit 0 for MIO[0].
10130 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1
10132 # Each bit applies to a single IO. Bit 0 for MIO[0].
10133 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1
10135 # Each bit applies to a single IO. Bit 0 for MIO[0].
10136 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1
10138 # Each bit applies to a single IO. Bit 0 for MIO[0].
10139 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1
10141 # Each bit applies to a single IO. Bit 0 for MIO[0].
10142 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1
10144 # Each bit applies to a single IO. Bit 0 for MIO[0].
10145 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1
10147 # Each bit applies to a single IO. Bit 0 for MIO[0].
10148 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1
10150 # Each bit applies to a single IO. Bit 0 for MIO[0].
10151 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1
10153 # Each bit applies to a single IO. Bit 0 for MIO[0].
10154 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1
10156 # Each bit applies to a single IO. Bit 0 for MIO[0].
10157 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1
10159 # Each bit applies to a single IO. Bit 0 for MIO[0].
10160 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1
10162 # Each bit applies to a single IO. Bit 0 for MIO[0].
10163 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1
10165 # Each bit applies to a single IO. Bit 0 for MIO[0].
10166 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1
10168 # Each bit applies to a single IO. Bit 0 for MIO[0].
10169 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1
10171 # Each bit applies to a single IO. Bit 0 for MIO[0].
10172 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1
10174 # Drive0 control to MIO Bank 0 - control MIO[25:0]
10175 #(OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) */
10176 mask_write 0XFF180138 0x03FFFFFF 0x03FFFFFF
10177 # Register : bank0_ctrl1 @ 0XFF18013C</p>
10179 # Each bit applies to a single IO. Bit 0 for MIO[0].
10180 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1
10182 # Each bit applies to a single IO. Bit 0 for MIO[0].
10183 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1
10185 # Each bit applies to a single IO. Bit 0 for MIO[0].
10186 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1
10188 # Each bit applies to a single IO. Bit 0 for MIO[0].
10189 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1
10191 # Each bit applies to a single IO. Bit 0 for MIO[0].
10192 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1
10194 # Each bit applies to a single IO. Bit 0 for MIO[0].
10195 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1
10197 # Each bit applies to a single IO. Bit 0 for MIO[0].
10198 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1
10200 # Each bit applies to a single IO. Bit 0 for MIO[0].
10201 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1
10203 # Each bit applies to a single IO. Bit 0 for MIO[0].
10204 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1
10206 # Each bit applies to a single IO. Bit 0 for MIO[0].
10207 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1
10209 # Each bit applies to a single IO. Bit 0 for MIO[0].
10210 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1
10212 # Each bit applies to a single IO. Bit 0 for MIO[0].
10213 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1
10215 # Each bit applies to a single IO. Bit 0 for MIO[0].
10216 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1
10218 # Each bit applies to a single IO. Bit 0 for MIO[0].
10219 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1
10221 # Each bit applies to a single IO. Bit 0 for MIO[0].
10222 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1
10224 # Each bit applies to a single IO. Bit 0 for MIO[0].
10225 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1
10227 # Each bit applies to a single IO. Bit 0 for MIO[0].
10228 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1
10230 # Each bit applies to a single IO. Bit 0 for MIO[0].
10231 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1
10233 # Each bit applies to a single IO. Bit 0 for MIO[0].
10234 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1
10236 # Each bit applies to a single IO. Bit 0 for MIO[0].
10237 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1
10239 # Each bit applies to a single IO. Bit 0 for MIO[0].
10240 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1
10242 # Each bit applies to a single IO. Bit 0 for MIO[0].
10243 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1
10245 # Each bit applies to a single IO. Bit 0 for MIO[0].
10246 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1
10248 # Each bit applies to a single IO. Bit 0 for MIO[0].
10249 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1
10251 # Each bit applies to a single IO. Bit 0 for MIO[0].
10252 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1
10254 # Each bit applies to a single IO. Bit 0 for MIO[0].
10255 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1
10257 # Drive1 control to MIO Bank 0 - control MIO[25:0]
10258 #(OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) */
10259 mask_write 0XFF18013C 0x03FFFFFF 0x03FFFFFF
10260 # Register : bank0_ctrl3 @ 0XFF180140</p>
10262 # Each bit applies to a single IO. Bit 0 for MIO[0].
10263 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0
10265 # Each bit applies to a single IO. Bit 0 for MIO[0].
10266 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0
10268 # Each bit applies to a single IO. Bit 0 for MIO[0].
10269 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0
10271 # Each bit applies to a single IO. Bit 0 for MIO[0].
10272 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0
10274 # Each bit applies to a single IO. Bit 0 for MIO[0].
10275 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0
10277 # Each bit applies to a single IO. Bit 0 for MIO[0].
10278 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0
10280 # Each bit applies to a single IO. Bit 0 for MIO[0].
10281 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0
10283 # Each bit applies to a single IO. Bit 0 for MIO[0].
10284 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0
10286 # Each bit applies to a single IO. Bit 0 for MIO[0].
10287 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0
10289 # Each bit applies to a single IO. Bit 0 for MIO[0].
10290 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0
10292 # Each bit applies to a single IO. Bit 0 for MIO[0].
10293 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0
10295 # Each bit applies to a single IO. Bit 0 for MIO[0].
10296 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0
10298 # Each bit applies to a single IO. Bit 0 for MIO[0].
10299 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0
10301 # Each bit applies to a single IO. Bit 0 for MIO[0].
10302 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0
10304 # Each bit applies to a single IO. Bit 0 for MIO[0].
10305 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0
10307 # Each bit applies to a single IO. Bit 0 for MIO[0].
10308 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0
10310 # Each bit applies to a single IO. Bit 0 for MIO[0].
10311 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0
10313 # Each bit applies to a single IO. Bit 0 for MIO[0].
10314 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0
10316 # Each bit applies to a single IO. Bit 0 for MIO[0].
10317 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0
10319 # Each bit applies to a single IO. Bit 0 for MIO[0].
10320 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0
10322 # Each bit applies to a single IO. Bit 0 for MIO[0].
10323 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0
10325 # Each bit applies to a single IO. Bit 0 for MIO[0].
10326 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0
10328 # Each bit applies to a single IO. Bit 0 for MIO[0].
10329 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0
10331 # Each bit applies to a single IO. Bit 0 for MIO[0].
10332 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0
10334 # Each bit applies to a single IO. Bit 0 for MIO[0].
10335 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0
10337 # Each bit applies to a single IO. Bit 0 for MIO[0].
10338 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0
10340 # Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
10341 #(OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) */
10342 mask_write 0XFF180140 0x03FFFFFF 0x00000000
10343 # Register : bank0_ctrl4 @ 0XFF180144</p>
10345 # Each bit applies to a single IO. Bit 0 for MIO[0].
10346 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
10348 # Each bit applies to a single IO. Bit 0 for MIO[0].
10349 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
10351 # Each bit applies to a single IO. Bit 0 for MIO[0].
10352 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
10354 # Each bit applies to a single IO. Bit 0 for MIO[0].
10355 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
10357 # Each bit applies to a single IO. Bit 0 for MIO[0].
10358 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
10360 # Each bit applies to a single IO. Bit 0 for MIO[0].
10361 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
10363 # Each bit applies to a single IO. Bit 0 for MIO[0].
10364 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
10366 # Each bit applies to a single IO. Bit 0 for MIO[0].
10367 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
10369 # Each bit applies to a single IO. Bit 0 for MIO[0].
10370 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
10372 # Each bit applies to a single IO. Bit 0 for MIO[0].
10373 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
10375 # Each bit applies to a single IO. Bit 0 for MIO[0].
10376 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
10378 # Each bit applies to a single IO. Bit 0 for MIO[0].
10379 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
10381 # Each bit applies to a single IO. Bit 0 for MIO[0].
10382 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
10384 # Each bit applies to a single IO. Bit 0 for MIO[0].
10385 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
10387 # Each bit applies to a single IO. Bit 0 for MIO[0].
10388 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
10390 # Each bit applies to a single IO. Bit 0 for MIO[0].
10391 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
10393 # Each bit applies to a single IO. Bit 0 for MIO[0].
10394 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
10396 # Each bit applies to a single IO. Bit 0 for MIO[0].
10397 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
10399 # Each bit applies to a single IO. Bit 0 for MIO[0].
10400 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
10402 # Each bit applies to a single IO. Bit 0 for MIO[0].
10403 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
10405 # Each bit applies to a single IO. Bit 0 for MIO[0].
10406 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
10408 # Each bit applies to a single IO. Bit 0 for MIO[0].
10409 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
10411 # Each bit applies to a single IO. Bit 0 for MIO[0].
10412 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
10414 # Each bit applies to a single IO. Bit 0 for MIO[0].
10415 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
10417 # Each bit applies to a single IO. Bit 0 for MIO[0].
10418 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
10420 # Each bit applies to a single IO. Bit 0 for MIO[0].
10421 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
10423 # When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
10424 #(OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) */
10425 mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF
10426 # Register : bank0_ctrl5 @ 0XFF180148</p>
10428 # Each bit applies to a single IO. Bit 0 for MIO[0].
10429 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1
10431 # Each bit applies to a single IO. Bit 0 for MIO[0].
10432 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1
10434 # Each bit applies to a single IO. Bit 0 for MIO[0].
10435 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1
10437 # Each bit applies to a single IO. Bit 0 for MIO[0].
10438 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1
10440 # Each bit applies to a single IO. Bit 0 for MIO[0].
10441 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1
10443 # Each bit applies to a single IO. Bit 0 for MIO[0].
10444 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1
10446 # Each bit applies to a single IO. Bit 0 for MIO[0].
10447 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1
10449 # Each bit applies to a single IO. Bit 0 for MIO[0].
10450 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1
10452 # Each bit applies to a single IO. Bit 0 for MIO[0].
10453 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1
10455 # Each bit applies to a single IO. Bit 0 for MIO[0].
10456 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1
10458 # Each bit applies to a single IO. Bit 0 for MIO[0].
10459 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1
10461 # Each bit applies to a single IO. Bit 0 for MIO[0].
10462 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1
10464 # Each bit applies to a single IO. Bit 0 for MIO[0].
10465 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1
10467 # Each bit applies to a single IO. Bit 0 for MIO[0].
10468 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1
10470 # Each bit applies to a single IO. Bit 0 for MIO[0].
10471 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1
10473 # Each bit applies to a single IO. Bit 0 for MIO[0].
10474 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1
10476 # Each bit applies to a single IO. Bit 0 for MIO[0].
10477 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1
10479 # Each bit applies to a single IO. Bit 0 for MIO[0].
10480 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1
10482 # Each bit applies to a single IO. Bit 0 for MIO[0].
10483 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1
10485 # Each bit applies to a single IO. Bit 0 for MIO[0].
10486 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1
10488 # Each bit applies to a single IO. Bit 0 for MIO[0].
10489 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1
10491 # Each bit applies to a single IO. Bit 0 for MIO[0].
10492 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1
10494 # Each bit applies to a single IO. Bit 0 for MIO[0].
10495 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1
10497 # Each bit applies to a single IO. Bit 0 for MIO[0].
10498 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1
10500 # Each bit applies to a single IO. Bit 0 for MIO[0].
10501 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1
10503 # Each bit applies to a single IO. Bit 0 for MIO[0].
10504 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1
10506 # When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
10507 #(OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) */
10508 mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF
10509 # Register : bank0_ctrl6 @ 0XFF18014C</p>
10511 # Each bit applies to a single IO. Bit 0 for MIO[0].
10512 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
10514 # Each bit applies to a single IO. Bit 0 for MIO[0].
10515 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
10517 # Each bit applies to a single IO. Bit 0 for MIO[0].
10518 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
10520 # Each bit applies to a single IO. Bit 0 for MIO[0].
10521 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
10523 # Each bit applies to a single IO. Bit 0 for MIO[0].
10524 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
10526 # Each bit applies to a single IO. Bit 0 for MIO[0].
10527 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
10529 # Each bit applies to a single IO. Bit 0 for MIO[0].
10530 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
10532 # Each bit applies to a single IO. Bit 0 for MIO[0].
10533 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
10535 # Each bit applies to a single IO. Bit 0 for MIO[0].
10536 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
10538 # Each bit applies to a single IO. Bit 0 for MIO[0].
10539 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
10541 # Each bit applies to a single IO. Bit 0 for MIO[0].
10542 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
10544 # Each bit applies to a single IO. Bit 0 for MIO[0].
10545 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
10547 # Each bit applies to a single IO. Bit 0 for MIO[0].
10548 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
10550 # Each bit applies to a single IO. Bit 0 for MIO[0].
10551 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
10553 # Each bit applies to a single IO. Bit 0 for MIO[0].
10554 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
10556 # Each bit applies to a single IO. Bit 0 for MIO[0].
10557 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
10559 # Each bit applies to a single IO. Bit 0 for MIO[0].
10560 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
10562 # Each bit applies to a single IO. Bit 0 for MIO[0].
10563 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
10565 # Each bit applies to a single IO. Bit 0 for MIO[0].
10566 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
10568 # Each bit applies to a single IO. Bit 0 for MIO[0].
10569 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
10571 # Each bit applies to a single IO. Bit 0 for MIO[0].
10572 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
10574 # Each bit applies to a single IO. Bit 0 for MIO[0].
10575 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
10577 # Each bit applies to a single IO. Bit 0 for MIO[0].
10578 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
10580 # Each bit applies to a single IO. Bit 0 for MIO[0].
10581 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
10583 # Each bit applies to a single IO. Bit 0 for MIO[0].
10584 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
10586 # Each bit applies to a single IO. Bit 0 for MIO[0].
10587 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
10589 # Slew rate control to MIO Bank 0 - control MIO[25:0]
10590 #(OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) */
10591 mask_write 0XFF18014C 0x03FFFFFF 0x00000000
10592 # Register : bank1_ctrl0 @ 0XFF180154</p>
10594 # Each bit applies to a single IO. Bit 0 for MIO[26].
10595 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1
10597 # Each bit applies to a single IO. Bit 0 for MIO[26].
10598 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1
10600 # Each bit applies to a single IO. Bit 0 for MIO[26].
10601 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1
10603 # Each bit applies to a single IO. Bit 0 for MIO[26].
10604 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1
10606 # Each bit applies to a single IO. Bit 0 for MIO[26].
10607 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1
10609 # Each bit applies to a single IO. Bit 0 for MIO[26].
10610 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1
10612 # Each bit applies to a single IO. Bit 0 for MIO[26].
10613 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1
10615 # Each bit applies to a single IO. Bit 0 for MIO[26].
10616 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1
10618 # Each bit applies to a single IO. Bit 0 for MIO[26].
10619 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1
10621 # Each bit applies to a single IO. Bit 0 for MIO[26].
10622 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1
10624 # Each bit applies to a single IO. Bit 0 for MIO[26].
10625 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1
10627 # Each bit applies to a single IO. Bit 0 for MIO[26].
10628 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1
10630 # Each bit applies to a single IO. Bit 0 for MIO[26].
10631 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1
10633 # Each bit applies to a single IO. Bit 0 for MIO[26].
10634 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1
10636 # Each bit applies to a single IO. Bit 0 for MIO[26].
10637 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1
10639 # Each bit applies to a single IO. Bit 0 for MIO[26].
10640 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1
10642 # Each bit applies to a single IO. Bit 0 for MIO[26].
10643 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1
10645 # Each bit applies to a single IO. Bit 0 for MIO[26].
10646 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1
10648 # Each bit applies to a single IO. Bit 0 for MIO[26].
10649 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1
10651 # Each bit applies to a single IO. Bit 0 for MIO[26].
10652 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1
10654 # Each bit applies to a single IO. Bit 0 for MIO[26].
10655 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1
10657 # Each bit applies to a single IO. Bit 0 for MIO[26].
10658 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1
10660 # Each bit applies to a single IO. Bit 0 for MIO[26].
10661 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1
10663 # Each bit applies to a single IO. Bit 0 for MIO[26].
10664 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1
10666 # Each bit applies to a single IO. Bit 0 for MIO[26].
10667 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1
10669 # Each bit applies to a single IO. Bit 0 for MIO[26].
10670 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1
10672 # Drive0 control to MIO Bank 1 - control MIO[51:26]
10673 #(OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) */
10674 mask_write 0XFF180154 0x03FFFFFF 0x03FFFFFF
10675 # Register : bank1_ctrl1 @ 0XFF180158</p>
10677 # Each bit applies to a single IO. Bit 0 for MIO[26].
10678 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1
10680 # Each bit applies to a single IO. Bit 0 for MIO[26].
10681 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1
10683 # Each bit applies to a single IO. Bit 0 for MIO[26].
10684 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1
10686 # Each bit applies to a single IO. Bit 0 for MIO[26].
10687 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1
10689 # Each bit applies to a single IO. Bit 0 for MIO[26].
10690 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1
10692 # Each bit applies to a single IO. Bit 0 for MIO[26].
10693 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1
10695 # Each bit applies to a single IO. Bit 0 for MIO[26].
10696 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1
10698 # Each bit applies to a single IO. Bit 0 for MIO[26].
10699 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1
10701 # Each bit applies to a single IO. Bit 0 for MIO[26].
10702 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1
10704 # Each bit applies to a single IO. Bit 0 for MIO[26].
10705 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1
10707 # Each bit applies to a single IO. Bit 0 for MIO[26].
10708 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1
10710 # Each bit applies to a single IO. Bit 0 for MIO[26].
10711 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1
10713 # Each bit applies to a single IO. Bit 0 for MIO[26].
10714 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1
10716 # Each bit applies to a single IO. Bit 0 for MIO[26].
10717 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1
10719 # Each bit applies to a single IO. Bit 0 for MIO[26].
10720 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1
10722 # Each bit applies to a single IO. Bit 0 for MIO[26].
10723 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1
10725 # Each bit applies to a single IO. Bit 0 for MIO[26].
10726 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1
10728 # Each bit applies to a single IO. Bit 0 for MIO[26].
10729 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1
10731 # Each bit applies to a single IO. Bit 0 for MIO[26].
10732 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1
10734 # Each bit applies to a single IO. Bit 0 for MIO[26].
10735 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1
10737 # Each bit applies to a single IO. Bit 0 for MIO[26].
10738 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1
10740 # Each bit applies to a single IO. Bit 0 for MIO[26].
10741 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1
10743 # Each bit applies to a single IO. Bit 0 for MIO[26].
10744 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1
10746 # Each bit applies to a single IO. Bit 0 for MIO[26].
10747 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1
10749 # Each bit applies to a single IO. Bit 0 for MIO[26].
10750 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1
10752 # Each bit applies to a single IO. Bit 0 for MIO[26].
10753 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1
10755 # Drive1 control to MIO Bank 1 - control MIO[51:26]
10756 #(OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) */
10757 mask_write 0XFF180158 0x03FFFFFF 0x03FFFFFF
10758 # Register : bank1_ctrl3 @ 0XFF18015C</p>
10760 # Each bit applies to a single IO. Bit 0 for MIO[26].
10761 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0
10763 # Each bit applies to a single IO. Bit 0 for MIO[26].
10764 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0
10766 # Each bit applies to a single IO. Bit 0 for MIO[26].
10767 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0
10769 # Each bit applies to a single IO. Bit 0 for MIO[26].
10770 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0
10772 # Each bit applies to a single IO. Bit 0 for MIO[26].
10773 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0
10775 # Each bit applies to a single IO. Bit 0 for MIO[26].
10776 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0
10778 # Each bit applies to a single IO. Bit 0 for MIO[26].
10779 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0
10781 # Each bit applies to a single IO. Bit 0 for MIO[26].
10782 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0
10784 # Each bit applies to a single IO. Bit 0 for MIO[26].
10785 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0
10787 # Each bit applies to a single IO. Bit 0 for MIO[26].
10788 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0
10790 # Each bit applies to a single IO. Bit 0 for MIO[26].
10791 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0
10793 # Each bit applies to a single IO. Bit 0 for MIO[26].
10794 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0
10796 # Each bit applies to a single IO. Bit 0 for MIO[26].
10797 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0
10799 # Each bit applies to a single IO. Bit 0 for MIO[26].
10800 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0
10802 # Each bit applies to a single IO. Bit 0 for MIO[26].
10803 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0
10805 # Each bit applies to a single IO. Bit 0 for MIO[26].
10806 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0
10808 # Each bit applies to a single IO. Bit 0 for MIO[26].
10809 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0
10811 # Each bit applies to a single IO. Bit 0 for MIO[26].
10812 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0
10814 # Each bit applies to a single IO. Bit 0 for MIO[26].
10815 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0
10817 # Each bit applies to a single IO. Bit 0 for MIO[26].
10818 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0
10820 # Each bit applies to a single IO. Bit 0 for MIO[26].
10821 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0
10823 # Each bit applies to a single IO. Bit 0 for MIO[26].
10824 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0
10826 # Each bit applies to a single IO. Bit 0 for MIO[26].
10827 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0
10829 # Each bit applies to a single IO. Bit 0 for MIO[26].
10830 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0
10832 # Each bit applies to a single IO. Bit 0 for MIO[26].
10833 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0
10835 # Each bit applies to a single IO. Bit 0 for MIO[26].
10836 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0
10838 # Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
10839 #(OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) */
10840 mask_write 0XFF18015C 0x03FFFFFF 0x00000000
10841 # Register : bank1_ctrl4 @ 0XFF180160</p>
10843 # Each bit applies to a single IO. Bit 0 for MIO[26].
10844 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
10846 # Each bit applies to a single IO. Bit 0 for MIO[26].
10847 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
10849 # Each bit applies to a single IO. Bit 0 for MIO[26].
10850 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
10852 # Each bit applies to a single IO. Bit 0 for MIO[26].
10853 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
10855 # Each bit applies to a single IO. Bit 0 for MIO[26].
10856 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
10858 # Each bit applies to a single IO. Bit 0 for MIO[26].
10859 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
10861 # Each bit applies to a single IO. Bit 0 for MIO[26].
10862 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
10864 # Each bit applies to a single IO. Bit 0 for MIO[26].
10865 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
10867 # Each bit applies to a single IO. Bit 0 for MIO[26].
10868 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
10870 # Each bit applies to a single IO. Bit 0 for MIO[26].
10871 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
10873 # Each bit applies to a single IO. Bit 0 for MIO[26].
10874 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
10876 # Each bit applies to a single IO. Bit 0 for MIO[26].
10877 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
10879 # Each bit applies to a single IO. Bit 0 for MIO[26].
10880 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
10882 # Each bit applies to a single IO. Bit 0 for MIO[26].
10883 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
10885 # Each bit applies to a single IO. Bit 0 for MIO[26].
10886 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
10888 # Each bit applies to a single IO. Bit 0 for MIO[26].
10889 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
10891 # Each bit applies to a single IO. Bit 0 for MIO[26].
10892 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
10894 # Each bit applies to a single IO. Bit 0 for MIO[26].
10895 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
10897 # Each bit applies to a single IO. Bit 0 for MIO[26].
10898 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
10900 # Each bit applies to a single IO. Bit 0 for MIO[26].
10901 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
10903 # Each bit applies to a single IO. Bit 0 for MIO[26].
10904 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
10906 # Each bit applies to a single IO. Bit 0 for MIO[26].
10907 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
10909 # Each bit applies to a single IO. Bit 0 for MIO[26].
10910 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
10912 # Each bit applies to a single IO. Bit 0 for MIO[26].
10913 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
10915 # Each bit applies to a single IO. Bit 0 for MIO[26].
10916 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
10918 # Each bit applies to a single IO. Bit 0 for MIO[26].
10919 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
10921 # When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
10922 #(OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) */
10923 mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF
10924 # Register : bank1_ctrl5 @ 0XFF180164</p>
10926 # Each bit applies to a single IO. Bit 0 for MIO[26].
10927 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1
10929 # Each bit applies to a single IO. Bit 0 for MIO[26].
10930 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1
10932 # Each bit applies to a single IO. Bit 0 for MIO[26].
10933 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1
10935 # Each bit applies to a single IO. Bit 0 for MIO[26].
10936 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1
10938 # Each bit applies to a single IO. Bit 0 for MIO[26].
10939 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1
10941 # Each bit applies to a single IO. Bit 0 for MIO[26].
10942 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1
10944 # Each bit applies to a single IO. Bit 0 for MIO[26].
10945 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1
10947 # Each bit applies to a single IO. Bit 0 for MIO[26].
10948 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1
10950 # Each bit applies to a single IO. Bit 0 for MIO[26].
10951 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1
10953 # Each bit applies to a single IO. Bit 0 for MIO[26].
10954 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1
10956 # Each bit applies to a single IO. Bit 0 for MIO[26].
10957 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1
10959 # Each bit applies to a single IO. Bit 0 for MIO[26].
10960 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1
10962 # Each bit applies to a single IO. Bit 0 for MIO[26].
10963 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1
10965 # Each bit applies to a single IO. Bit 0 for MIO[26].
10966 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1
10968 # Each bit applies to a single IO. Bit 0 for MIO[26].
10969 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1
10971 # Each bit applies to a single IO. Bit 0 for MIO[26].
10972 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1
10974 # Each bit applies to a single IO. Bit 0 for MIO[26].
10975 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1
10977 # Each bit applies to a single IO. Bit 0 for MIO[26].
10978 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1
10980 # Each bit applies to a single IO. Bit 0 for MIO[26].
10981 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1
10983 # Each bit applies to a single IO. Bit 0 for MIO[26].
10984 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1
10986 # Each bit applies to a single IO. Bit 0 for MIO[26].
10987 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1
10989 # Each bit applies to a single IO. Bit 0 for MIO[26].
10990 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1
10992 # Each bit applies to a single IO. Bit 0 for MIO[26].
10993 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1
10995 # Each bit applies to a single IO. Bit 0 for MIO[26].
10996 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1
10998 # Each bit applies to a single IO. Bit 0 for MIO[26].
10999 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1
11001 # Each bit applies to a single IO. Bit 0 for MIO[26].
11002 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1
11004 # When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
11005 #(OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) */
11006 mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF
11007 # Register : bank1_ctrl6 @ 0XFF180168</p>
11009 # Each bit applies to a single IO. Bit 0 for MIO[26].
11010 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
11012 # Each bit applies to a single IO. Bit 0 for MIO[26].
11013 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
11015 # Each bit applies to a single IO. Bit 0 for MIO[26].
11016 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
11018 # Each bit applies to a single IO. Bit 0 for MIO[26].
11019 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
11021 # Each bit applies to a single IO. Bit 0 for MIO[26].
11022 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
11024 # Each bit applies to a single IO. Bit 0 for MIO[26].
11025 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
11027 # Each bit applies to a single IO. Bit 0 for MIO[26].
11028 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
11030 # Each bit applies to a single IO. Bit 0 for MIO[26].
11031 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
11033 # Each bit applies to a single IO. Bit 0 for MIO[26].
11034 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
11036 # Each bit applies to a single IO. Bit 0 for MIO[26].
11037 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
11039 # Each bit applies to a single IO. Bit 0 for MIO[26].
11040 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
11042 # Each bit applies to a single IO. Bit 0 for MIO[26].
11043 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
11045 # Each bit applies to a single IO. Bit 0 for MIO[26].
11046 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
11048 # Each bit applies to a single IO. Bit 0 for MIO[26].
11049 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
11051 # Each bit applies to a single IO. Bit 0 for MIO[26].
11052 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
11054 # Each bit applies to a single IO. Bit 0 for MIO[26].
11055 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
11057 # Each bit applies to a single IO. Bit 0 for MIO[26].
11058 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
11060 # Each bit applies to a single IO. Bit 0 for MIO[26].
11061 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
11063 # Each bit applies to a single IO. Bit 0 for MIO[26].
11064 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
11066 # Each bit applies to a single IO. Bit 0 for MIO[26].
11067 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
11069 # Each bit applies to a single IO. Bit 0 for MIO[26].
11070 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
11072 # Each bit applies to a single IO. Bit 0 for MIO[26].
11073 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
11075 # Each bit applies to a single IO. Bit 0 for MIO[26].
11076 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
11078 # Each bit applies to a single IO. Bit 0 for MIO[26].
11079 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
11081 # Each bit applies to a single IO. Bit 0 for MIO[26].
11082 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
11084 # Each bit applies to a single IO. Bit 0 for MIO[26].
11085 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
11087 # Slew rate control to MIO Bank 1 - control MIO[51:26]
11088 #(OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) */
11089 mask_write 0XFF180168 0x03FFFFFF 0x00000000
11090 # Register : bank2_ctrl0 @ 0XFF180170</p>
11092 # Each bit applies to a single IO. Bit 0 for MIO[52].
11093 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1
11095 # Each bit applies to a single IO. Bit 0 for MIO[52].
11096 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1
11098 # Each bit applies to a single IO. Bit 0 for MIO[52].
11099 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1
11101 # Each bit applies to a single IO. Bit 0 for MIO[52].
11102 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1
11104 # Each bit applies to a single IO. Bit 0 for MIO[52].
11105 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1
11107 # Each bit applies to a single IO. Bit 0 for MIO[52].
11108 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1
11110 # Each bit applies to a single IO. Bit 0 for MIO[52].
11111 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1
11113 # Each bit applies to a single IO. Bit 0 for MIO[52].
11114 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1
11116 # Each bit applies to a single IO. Bit 0 for MIO[52].
11117 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1
11119 # Each bit applies to a single IO. Bit 0 for MIO[52].
11120 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1
11122 # Each bit applies to a single IO. Bit 0 for MIO[52].
11123 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1
11125 # Each bit applies to a single IO. Bit 0 for MIO[52].
11126 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1
11128 # Each bit applies to a single IO. Bit 0 for MIO[52].
11129 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1
11131 # Each bit applies to a single IO. Bit 0 for MIO[52].
11132 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1
11134 # Each bit applies to a single IO. Bit 0 for MIO[52].
11135 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1
11137 # Each bit applies to a single IO. Bit 0 for MIO[52].
11138 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1
11140 # Each bit applies to a single IO. Bit 0 for MIO[52].
11141 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1
11143 # Each bit applies to a single IO. Bit 0 for MIO[52].
11144 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1
11146 # Each bit applies to a single IO. Bit 0 for MIO[52].
11147 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1
11149 # Each bit applies to a single IO. Bit 0 for MIO[52].
11150 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1
11152 # Each bit applies to a single IO. Bit 0 for MIO[52].
11153 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1
11155 # Each bit applies to a single IO. Bit 0 for MIO[52].
11156 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1
11158 # Each bit applies to a single IO. Bit 0 for MIO[52].
11159 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1
11161 # Each bit applies to a single IO. Bit 0 for MIO[52].
11162 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1
11164 # Each bit applies to a single IO. Bit 0 for MIO[52].
11165 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1
11167 # Each bit applies to a single IO. Bit 0 for MIO[52].
11168 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1
11170 # Drive0 control to MIO Bank 2 - control MIO[77:52]
11171 #(OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) */
11172 mask_write 0XFF180170 0x03FFFFFF 0x03FFFFFF
11173 # Register : bank2_ctrl1 @ 0XFF180174</p>
11175 # Each bit applies to a single IO. Bit 0 for MIO[52].
11176 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1
11178 # Each bit applies to a single IO. Bit 0 for MIO[52].
11179 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1
11181 # Each bit applies to a single IO. Bit 0 for MIO[52].
11182 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1
11184 # Each bit applies to a single IO. Bit 0 for MIO[52].
11185 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1
11187 # Each bit applies to a single IO. Bit 0 for MIO[52].
11188 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1
11190 # Each bit applies to a single IO. Bit 0 for MIO[52].
11191 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1
11193 # Each bit applies to a single IO. Bit 0 for MIO[52].
11194 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1
11196 # Each bit applies to a single IO. Bit 0 for MIO[52].
11197 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1
11199 # Each bit applies to a single IO. Bit 0 for MIO[52].
11200 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1
11202 # Each bit applies to a single IO. Bit 0 for MIO[52].
11203 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1
11205 # Each bit applies to a single IO. Bit 0 for MIO[52].
11206 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1
11208 # Each bit applies to a single IO. Bit 0 for MIO[52].
11209 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1
11211 # Each bit applies to a single IO. Bit 0 for MIO[52].
11212 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1
11214 # Each bit applies to a single IO. Bit 0 for MIO[52].
11215 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1
11217 # Each bit applies to a single IO. Bit 0 for MIO[52].
11218 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1
11220 # Each bit applies to a single IO. Bit 0 for MIO[52].
11221 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1
11223 # Each bit applies to a single IO. Bit 0 for MIO[52].
11224 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1
11226 # Each bit applies to a single IO. Bit 0 for MIO[52].
11227 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1
11229 # Each bit applies to a single IO. Bit 0 for MIO[52].
11230 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1
11232 # Each bit applies to a single IO. Bit 0 for MIO[52].
11233 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1
11235 # Each bit applies to a single IO. Bit 0 for MIO[52].
11236 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1
11238 # Each bit applies to a single IO. Bit 0 for MIO[52].
11239 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1
11241 # Each bit applies to a single IO. Bit 0 for MIO[52].
11242 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1
11244 # Each bit applies to a single IO. Bit 0 for MIO[52].
11245 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1
11247 # Each bit applies to a single IO. Bit 0 for MIO[52].
11248 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1
11250 # Each bit applies to a single IO. Bit 0 for MIO[52].
11251 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1
11253 # Drive1 control to MIO Bank 2 - control MIO[77:52]
11254 #(OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) */
11255 mask_write 0XFF180174 0x03FFFFFF 0x03FFFFFF
11256 # Register : bank2_ctrl3 @ 0XFF180178</p>
11258 # Each bit applies to a single IO. Bit 0 for MIO[52].
11259 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0
11261 # Each bit applies to a single IO. Bit 0 for MIO[52].
11262 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0
11264 # Each bit applies to a single IO. Bit 0 for MIO[52].
11265 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0
11267 # Each bit applies to a single IO. Bit 0 for MIO[52].
11268 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0
11270 # Each bit applies to a single IO. Bit 0 for MIO[52].
11271 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0
11273 # Each bit applies to a single IO. Bit 0 for MIO[52].
11274 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0
11276 # Each bit applies to a single IO. Bit 0 for MIO[52].
11277 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0
11279 # Each bit applies to a single IO. Bit 0 for MIO[52].
11280 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0
11282 # Each bit applies to a single IO. Bit 0 for MIO[52].
11283 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0
11285 # Each bit applies to a single IO. Bit 0 for MIO[52].
11286 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0
11288 # Each bit applies to a single IO. Bit 0 for MIO[52].
11289 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0
11291 # Each bit applies to a single IO. Bit 0 for MIO[52].
11292 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0
11294 # Each bit applies to a single IO. Bit 0 for MIO[52].
11295 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0
11297 # Each bit applies to a single IO. Bit 0 for MIO[52].
11298 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0
11300 # Each bit applies to a single IO. Bit 0 for MIO[52].
11301 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0
11303 # Each bit applies to a single IO. Bit 0 for MIO[52].
11304 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0
11306 # Each bit applies to a single IO. Bit 0 for MIO[52].
11307 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0
11309 # Each bit applies to a single IO. Bit 0 for MIO[52].
11310 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0
11312 # Each bit applies to a single IO. Bit 0 for MIO[52].
11313 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0
11315 # Each bit applies to a single IO. Bit 0 for MIO[52].
11316 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0
11318 # Each bit applies to a single IO. Bit 0 for MIO[52].
11319 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0
11321 # Each bit applies to a single IO. Bit 0 for MIO[52].
11322 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0
11324 # Each bit applies to a single IO. Bit 0 for MIO[52].
11325 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0
11327 # Each bit applies to a single IO. Bit 0 for MIO[52].
11328 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0
11330 # Each bit applies to a single IO. Bit 0 for MIO[52].
11331 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0
11333 # Each bit applies to a single IO. Bit 0 for MIO[52].
11334 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0
11336 # Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
11337 #(OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) */
11338 mask_write 0XFF180178 0x03FFFFFF 0x00000000
11339 # Register : bank2_ctrl4 @ 0XFF18017C</p>
11341 # Each bit applies to a single IO. Bit 0 for MIO[52].
11342 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
11344 # Each bit applies to a single IO. Bit 0 for MIO[52].
11345 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
11347 # Each bit applies to a single IO. Bit 0 for MIO[52].
11348 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
11350 # Each bit applies to a single IO. Bit 0 for MIO[52].
11351 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
11353 # Each bit applies to a single IO. Bit 0 for MIO[52].
11354 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
11356 # Each bit applies to a single IO. Bit 0 for MIO[52].
11357 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
11359 # Each bit applies to a single IO. Bit 0 for MIO[52].
11360 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
11362 # Each bit applies to a single IO. Bit 0 for MIO[52].
11363 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
11365 # Each bit applies to a single IO. Bit 0 for MIO[52].
11366 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
11368 # Each bit applies to a single IO. Bit 0 for MIO[52].
11369 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
11371 # Each bit applies to a single IO. Bit 0 for MIO[52].
11372 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
11374 # Each bit applies to a single IO. Bit 0 for MIO[52].
11375 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
11377 # Each bit applies to a single IO. Bit 0 for MIO[52].
11378 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
11380 # Each bit applies to a single IO. Bit 0 for MIO[52].
11381 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
11383 # Each bit applies to a single IO. Bit 0 for MIO[52].
11384 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
11386 # Each bit applies to a single IO. Bit 0 for MIO[52].
11387 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
11389 # Each bit applies to a single IO. Bit 0 for MIO[52].
11390 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
11392 # Each bit applies to a single IO. Bit 0 for MIO[52].
11393 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
11395 # Each bit applies to a single IO. Bit 0 for MIO[52].
11396 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
11398 # Each bit applies to a single IO. Bit 0 for MIO[52].
11399 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
11401 # Each bit applies to a single IO. Bit 0 for MIO[52].
11402 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
11404 # Each bit applies to a single IO. Bit 0 for MIO[52].
11405 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
11407 # Each bit applies to a single IO. Bit 0 for MIO[52].
11408 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
11410 # Each bit applies to a single IO. Bit 0 for MIO[52].
11411 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
11413 # Each bit applies to a single IO. Bit 0 for MIO[52].
11414 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
11416 # Each bit applies to a single IO. Bit 0 for MIO[52].
11417 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
11419 # When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
11420 #(OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) */
11421 mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF
11422 # Register : bank2_ctrl5 @ 0XFF180180</p>
11424 # Each bit applies to a single IO. Bit 0 for MIO[52].
11425 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1
11427 # Each bit applies to a single IO. Bit 0 for MIO[52].
11428 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1
11430 # Each bit applies to a single IO. Bit 0 for MIO[52].
11431 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1
11433 # Each bit applies to a single IO. Bit 0 for MIO[52].
11434 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1
11436 # Each bit applies to a single IO. Bit 0 for MIO[52].
11437 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1
11439 # Each bit applies to a single IO. Bit 0 for MIO[52].
11440 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1
11442 # Each bit applies to a single IO. Bit 0 for MIO[52].
11443 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1
11445 # Each bit applies to a single IO. Bit 0 for MIO[52].
11446 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1
11448 # Each bit applies to a single IO. Bit 0 for MIO[52].
11449 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1
11451 # Each bit applies to a single IO. Bit 0 for MIO[52].
11452 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1
11454 # Each bit applies to a single IO. Bit 0 for MIO[52].
11455 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1
11457 # Each bit applies to a single IO. Bit 0 for MIO[52].
11458 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1
11460 # Each bit applies to a single IO. Bit 0 for MIO[52].
11461 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1
11463 # Each bit applies to a single IO. Bit 0 for MIO[52].
11464 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1
11466 # Each bit applies to a single IO. Bit 0 for MIO[52].
11467 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1
11469 # Each bit applies to a single IO. Bit 0 for MIO[52].
11470 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1
11472 # Each bit applies to a single IO. Bit 0 for MIO[52].
11473 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1
11475 # Each bit applies to a single IO. Bit 0 for MIO[52].
11476 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1
11478 # Each bit applies to a single IO. Bit 0 for MIO[52].
11479 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1
11481 # Each bit applies to a single IO. Bit 0 for MIO[52].
11482 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1
11484 # Each bit applies to a single IO. Bit 0 for MIO[52].
11485 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1
11487 # Each bit applies to a single IO. Bit 0 for MIO[52].
11488 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1
11490 # Each bit applies to a single IO. Bit 0 for MIO[52].
11491 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1
11493 # Each bit applies to a single IO. Bit 0 for MIO[52].
11494 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1
11496 # Each bit applies to a single IO. Bit 0 for MIO[52].
11497 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1
11499 # Each bit applies to a single IO. Bit 0 for MIO[52].
11500 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1
11502 # When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
11503 #(OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) */
11504 mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF
11505 # Register : bank2_ctrl6 @ 0XFF180184</p>
11507 # Each bit applies to a single IO. Bit 0 for MIO[52].
11508 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
11510 # Each bit applies to a single IO. Bit 0 for MIO[52].
11511 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
11513 # Each bit applies to a single IO. Bit 0 for MIO[52].
11514 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
11516 # Each bit applies to a single IO. Bit 0 for MIO[52].
11517 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
11519 # Each bit applies to a single IO. Bit 0 for MIO[52].
11520 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
11522 # Each bit applies to a single IO. Bit 0 for MIO[52].
11523 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
11525 # Each bit applies to a single IO. Bit 0 for MIO[52].
11526 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
11528 # Each bit applies to a single IO. Bit 0 for MIO[52].
11529 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
11531 # Each bit applies to a single IO. Bit 0 for MIO[52].
11532 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
11534 # Each bit applies to a single IO. Bit 0 for MIO[52].
11535 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
11537 # Each bit applies to a single IO. Bit 0 for MIO[52].
11538 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
11540 # Each bit applies to a single IO. Bit 0 for MIO[52].
11541 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
11543 # Each bit applies to a single IO. Bit 0 for MIO[52].
11544 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
11546 # Each bit applies to a single IO. Bit 0 for MIO[52].
11547 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
11549 # Each bit applies to a single IO. Bit 0 for MIO[52].
11550 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
11552 # Each bit applies to a single IO. Bit 0 for MIO[52].
11553 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
11555 # Each bit applies to a single IO. Bit 0 for MIO[52].
11556 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
11558 # Each bit applies to a single IO. Bit 0 for MIO[52].
11559 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
11561 # Each bit applies to a single IO. Bit 0 for MIO[52].
11562 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
11564 # Each bit applies to a single IO. Bit 0 for MIO[52].
11565 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
11567 # Each bit applies to a single IO. Bit 0 for MIO[52].
11568 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
11570 # Each bit applies to a single IO. Bit 0 for MIO[52].
11571 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
11573 # Each bit applies to a single IO. Bit 0 for MIO[52].
11574 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
11576 # Each bit applies to a single IO. Bit 0 for MIO[52].
11577 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
11579 # Each bit applies to a single IO. Bit 0 for MIO[52].
11580 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
11582 # Each bit applies to a single IO. Bit 0 for MIO[52].
11583 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
11585 # Slew rate control to MIO Bank 2 - control MIO[77:52]
11586 #(OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) */
11587 mask_write 0XFF180184 0x03FFFFFF 0x00000000
11589 # Register : MIO_LOOPBACK @ 0XFF180200</p>
11591 # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
11592 # ts to I2C 0 inputs.
11593 # PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0
11595 # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
11597 # PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0
11599 # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
11600 # outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
11601 # PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0
11603 # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
11604 # ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
11605 # PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0
11607 # Loopback function within MIO
11608 #(OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) */
11609 mask_write 0XFF180200 0x0000000F 0x00000000
11612 set psu_peripherals_init_data {
11615 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
11618 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0
11620 # Software controlled reset for the GEMs
11621 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */
11622 mask_write 0XFF5E0230 0x00000008 0x00000000
11624 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11626 # Block level reset
11627 # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0
11629 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11630 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */
11631 mask_write 0XFF5E0238 0x00000001 0x00000000
11634 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
11636 # USB 0 reset for control registers
11637 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0
11639 # USB 0 sleep circuit reset
11640 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0
11643 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0
11645 # Software control register for the LPD block.
11646 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */
11647 mask_write 0XFF5E023C 0x00000540 0x00000000
11649 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
11651 # PCIE config reset
11652 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0
11654 # PCIE control block level reset
11655 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0
11657 # PCIE bridge block level reset (AXI interface)
11658 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0
11660 # Display Port block level reset (includes DPDMA)
11661 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0
11664 # PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0
11666 # GDMA block level reset
11667 # PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0
11669 # Pixel Processor (submodule of GPU) block level reset
11670 # PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0
11672 # Pixel Processor (submodule of GPU) block level reset
11673 # PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0
11675 # GPU block level reset
11676 # PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0
11678 # GT block level reset
11679 # PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0
11681 # Sata block level reset
11682 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0
11684 # FPD Block level software controlled reset
11685 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) */
11686 mask_write 0XFD1A0100 0x000F807E 0x00000000
11688 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11690 # Block level reset
11691 # PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0
11693 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11694 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) */
11695 mask_write 0XFF5E0238 0x00000040 0x00000000
11696 # Register : CTRL_REG_SD @ 0XFF180310</p>
11698 # SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
11699 # PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0
11701 # SD eMMC selection
11702 #(OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) */
11703 mask_write 0XFF180310 0x00008000 0x00000000
11704 # Register : SD_CONFIG_REG2 @ 0XFF180320</p>
11706 # Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
11708 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0
11710 # 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
11711 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0
11713 # 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
11714 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0
11716 # 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
11717 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1
11719 # SD Config Register 2
11720 #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) */
11721 mask_write 0XFF180320 0x33800000 0x00800000
11723 # Register : SD_CONFIG_REG1 @ 0XFF18031C</p>
11725 # Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
11726 # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7
11728 # SD Config Register 1
11729 #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) */
11730 mask_write 0XFF18031C 0x7F800000 0x63800000
11732 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11734 # Block level reset
11735 # PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0
11737 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11738 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) */
11739 mask_write 0XFF5E0238 0x00000100 0x00000000
11741 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11743 # Block level reset
11744 # PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0
11746 # Block level reset
11747 # PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0
11749 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11750 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) */
11751 mask_write 0XFF5E0238 0x00000600 0x00000000
11753 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11755 # Block level reset
11756 # PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0
11758 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11759 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) */
11760 mask_write 0XFF5E0238 0x00008000 0x00000000
11763 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11765 # Block level reset
11766 # PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0
11768 # Block level reset
11769 # PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0
11771 # Block level reset
11772 # PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0
11774 # Block level reset
11775 # PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0
11777 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11778 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) */
11779 mask_write 0XFF5E0238 0x00007800 0x00000000
11781 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
11783 # Block level reset
11784 # PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0
11786 # Block level reset
11787 # PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0
11789 # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
11790 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) */
11791 mask_write 0XFF5E0238 0x00000006 0x00000000
11793 # Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
11795 # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
11796 # PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
11798 # Baud Rate Divider Register
11799 #(OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) */
11800 mask_write 0XFF000034 0x000000FF 0x00000005
11801 # Register : Baud_rate_gen_reg0 @ 0XFF000018</p>
11803 # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
11804 # PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f
11806 # Baud Rate Generator Register.
11807 #(OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) */
11808 mask_write 0XFF000018 0x0000FFFF 0x0000008F
11809 # Register : Control_reg0 @ 0XFF000000</p>
11811 # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
11812 # high level during 12 bit periods. It can be set regardless of the value of STTBRK.
11813 # PSU_UART0_CONTROL_REG0_STPBRK 0x0
11815 # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
11816 # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
11817 # PSU_UART0_CONTROL_REG0_STTBRK 0x0
11819 # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
11821 # PSU_UART0_CONTROL_REG0_RSTTO 0x0
11823 # Transmit disable: 0: enable transmitter 1: disable transmitter
11824 # PSU_UART0_CONTROL_REG0_TXDIS 0x0
11826 # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
11827 # PSU_UART0_CONTROL_REG0_TXEN 0x1
11829 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN
11830 # PSU_UART0_CONTROL_REG0_RXDIS 0x0
11832 # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
11833 # PSU_UART0_CONTROL_REG0_RXEN 0x1
11835 # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
11836 # bit is self clearing once the reset has completed.
11837 # PSU_UART0_CONTROL_REG0_TXRES 0x1
11839 # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
11840 # is self clearing once the reset has completed.
11841 # PSU_UART0_CONTROL_REG0_RXRES 0x1
11843 # UART Control Register
11844 #(OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) */
11845 mask_write 0XFF000000 0x000001FF 0x00000017
11846 # Register : mode_reg0 @ 0XFF000004</p>
11848 # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
11849 # PSU_UART0_MODE_REG0_CHMODE 0x0
11851 # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
11852 # stop bits 10: 2 stop bits 11: reserved
11853 # PSU_UART0_MODE_REG0_NBSTOP 0x0
11855 # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
11856 # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
11857 # PSU_UART0_MODE_REG0_PAR 0x4
11859 # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
11860 # PSU_UART0_MODE_REG0_CHRL 0x0
11862 # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
11863 # source is uart_ref_clk 1: clock source is uart_ref_clk/8
11864 # PSU_UART0_MODE_REG0_CLKS 0x0
11866 # UART Mode Register
11867 #(OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) */
11868 mask_write 0XFF000004 0x000003FF 0x00000020
11869 # Register : Baud_rate_divider_reg0 @ 0XFF010034</p>
11871 # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
11872 # PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
11874 # Baud Rate Divider Register
11875 #(OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) */
11876 mask_write 0XFF010034 0x000000FF 0x00000005
11877 # Register : Baud_rate_gen_reg0 @ 0XFF010018</p>
11879 # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
11880 # PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f
11882 # Baud Rate Generator Register.
11883 #(OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) */
11884 mask_write 0XFF010018 0x0000FFFF 0x0000008F
11885 # Register : Control_reg0 @ 0XFF010000</p>
11887 # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
11888 # high level during 12 bit periods. It can be set regardless of the value of STTBRK.
11889 # PSU_UART1_CONTROL_REG0_STPBRK 0x0
11891 # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
11892 # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
11893 # PSU_UART1_CONTROL_REG0_STTBRK 0x0
11895 # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
11897 # PSU_UART1_CONTROL_REG0_RSTTO 0x0
11899 # Transmit disable: 0: enable transmitter 1: disable transmitter
11900 # PSU_UART1_CONTROL_REG0_TXDIS 0x0
11902 # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
11903 # PSU_UART1_CONTROL_REG0_TXEN 0x1
11905 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN
11906 # PSU_UART1_CONTROL_REG0_RXDIS 0x0
11908 # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
11909 # PSU_UART1_CONTROL_REG0_RXEN 0x1
11911 # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
11912 # bit is self clearing once the reset has completed.
11913 # PSU_UART1_CONTROL_REG0_TXRES 0x1
11915 # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
11916 # is self clearing once the reset has completed.
11917 # PSU_UART1_CONTROL_REG0_RXRES 0x1
11919 # UART Control Register
11920 #(OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) */
11921 mask_write 0XFF010000 0x000001FF 0x00000017
11922 # Register : mode_reg0 @ 0XFF010004</p>
11924 # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
11925 # PSU_UART1_MODE_REG0_CHMODE 0x0
11927 # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
11928 # stop bits 10: 2 stop bits 11: reserved
11929 # PSU_UART1_MODE_REG0_NBSTOP 0x0
11931 # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
11932 # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
11933 # PSU_UART1_MODE_REG0_PAR 0x4
11935 # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
11936 # PSU_UART1_MODE_REG0_CHRL 0x0
11938 # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
11939 # source is uart_ref_clk 1: clock source is uart_ref_clk/8
11940 # PSU_UART1_MODE_REG0_CLKS 0x0
11942 # UART Mode Register
11943 #(OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) */
11944 mask_write 0XFF010004 0x000003FF 0x00000020
11947 # Register : slcr_adma @ 0XFF4B0024</p>
11949 # TrustZone Classification for ADMA
11950 # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF
11952 # RPU TrustZone settings
11953 #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */
11954 mask_write 0XFF4B0024 0x000000FF 0x000000FF
11956 # : CSU TAMPER STATUS
11957 # Register : tamper_status @ 0XFFCA5000</p>
11960 # PSU_CSU_TAMPER_STATUS_TAMPER_0 0
11963 # PSU_CSU_TAMPER_STATUS_TAMPER_1 0
11965 # JTAG toggle detect
11966 # PSU_CSU_TAMPER_STATUS_TAMPER_2 0
11969 # PSU_CSU_TAMPER_STATUS_TAMPER_3 0
11971 # AMS over temperature alarm for LPD
11972 # PSU_CSU_TAMPER_STATUS_TAMPER_4 0
11974 # AMS over temperature alarm for APU
11975 # PSU_CSU_TAMPER_STATUS_TAMPER_5 0
11977 # AMS voltage alarm for VCCPINT_FPD
11978 # PSU_CSU_TAMPER_STATUS_TAMPER_6 0
11980 # AMS voltage alarm for VCCPINT_LPD
11981 # PSU_CSU_TAMPER_STATUS_TAMPER_7 0
11983 # AMS voltage alarm for VCCPAUX
11984 # PSU_CSU_TAMPER_STATUS_TAMPER_8 0
11986 # AMS voltage alarm for DDRPHY
11987 # PSU_CSU_TAMPER_STATUS_TAMPER_9 0
11989 # AMS voltage alarm for PSIO bank 0/1/2
11990 # PSU_CSU_TAMPER_STATUS_TAMPER_10 0
11992 # AMS voltage alarm for PSIO bank 3 (dedicated pins)
11993 # PSU_CSU_TAMPER_STATUS_TAMPER_11 0
11995 # AMS voltaage alarm for GT
11996 # PSU_CSU_TAMPER_STATUS_TAMPER_12 0
11998 # Tamper Response Status
11999 #(OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) */
12000 mask_write 0XFFCA5000 0x00001FFF 0x00000000
12001 # : CSU TAMPER RESPONSE
12002 # : AFIFM INTERFACE WIDTH
12003 # : CPU QOS DEFAULT
12004 # Register : ACE_CTRL @ 0XFD5C0060</p>
12006 # Set ACE outgoing AWQOS value
12007 # PSU_APU_ACE_CTRL_AWQOS 0X0
12009 # Set ACE outgoing ARQOS value
12010 # PSU_APU_ACE_CTRL_ARQOS 0X0
12012 # ACE Control Register
12013 #(OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) */
12014 mask_write 0XFD5C0060 0x000F000F 0x00000000
12015 # : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
12016 # Register : CONTROL @ 0XFFA60040</p>
12018 # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
12019 # he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
12020 # pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
12021 # g a 0 to this bit.
12022 # PSU_RTC_CONTROL_BATTERY_DISABLE 0X1
12024 # This register controls various functionalities within the RTC
12025 #(OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) */
12026 mask_write 0XFFA60040 0x80000000 0x80000000
12029 set psu_post_config_data {
12033 set psu_peripherals_powerdwn_data {
12034 # : POWER DOWN REQUEST INTERRUPT ENABLE
12035 # : POWER DOWN TRIGGER
12038 set psu_serdes_init_data {
12039 # : SERDES INITIALIZATION
12040 # : GT REFERENCE CLOCK SOURCE SELECTION
12041 # Register : PLL_REF_SEL0 @ 0XFD410000</p>
12043 # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
12044 # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
12045 # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
12046 # PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
12048 # PLL0 Reference Selection Register
12049 #(OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) */
12050 mask_write 0XFD410000 0x0000001F 0x0000000D
12051 # Register : PLL_REF_SEL1 @ 0XFD410004</p>
12053 # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
12054 # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
12055 # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
12056 # PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9
12058 # PLL1 Reference Selection Register
12059 #(OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) */
12060 mask_write 0XFD410004 0x0000001F 0x00000009
12061 # Register : PLL_REF_SEL2 @ 0XFD410008</p>
12063 # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
12064 # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
12065 # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
12066 # PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
12068 # PLL2 Reference Selection Register
12069 #(OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) */
12070 mask_write 0XFD410008 0x0000001F 0x00000008
12071 # Register : PLL_REF_SEL3 @ 0XFD41000C</p>
12073 # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
12074 # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
12075 # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
12076 # PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF
12078 # PLL3 Reference Selection Register
12079 #(OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) */
12080 mask_write 0XFD41000C 0x0000001F 0x0000000F
12081 # : GT REFERENCE CLOCK FREQUENCY SELECTION
12082 # Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
12084 # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
12085 # PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1
12087 # Lane0 Ref Clock Selection Register
12088 #(OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) */
12089 mask_write 0XFD402860 0x00000080 0x00000080
12090 # Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
12092 # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
12093 # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
12095 # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
12096 # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
12098 # Lane1 Ref Clock Selection Register
12099 #(OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) */
12100 mask_write 0XFD402864 0x00000088 0x00000008
12101 # Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
12103 # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
12104 # PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
12106 # Lane2 Ref Clock Selection Register
12107 #(OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) */
12108 mask_write 0XFD402868 0x00000080 0x00000080
12109 # Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
12111 # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
12112 # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
12114 # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
12115 # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
12117 # Lane3 Ref Clock Selection Register
12118 #(OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) */
12119 mask_write 0XFD40286C 0x00000082 0x00000002
12120 # : ENABLE SPREAD SPECTRUM
12121 # Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
12123 # Enable/Disable coarse code satureation limiting logic
12124 # PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
12126 # Test mode register 37
12127 #(OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) */
12128 mask_write 0XFD40A094 0x00000010 0x00000010
12129 # Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
12131 # Spread Spectrum No of Steps [7:0]
12132 # PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
12134 # Spread Spectrum No of Steps bits 7:0
12135 #(OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) */
12136 mask_write 0XFD40A368 0x000000FF 0x00000038
12137 # Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
12139 # Spread Spectrum No of Steps [10:8]
12140 # PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
12142 # Spread Spectrum No of Steps bits 10:8
12143 #(OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) */
12144 mask_write 0XFD40A36C 0x00000007 0x00000003
12145 # Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
12147 # Spread Spectrum No of Steps [7:0]
12148 # PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
12150 # Spread Spectrum No of Steps bits 7:0
12151 #(OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x00000000U) */
12152 mask_write 0XFD40E368 0x000000FF 0x00000000
12153 # Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
12155 # Spread Spectrum No of Steps [10:8]
12156 # PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
12158 # Spread Spectrum No of Steps bits 10:8
12159 #(OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000000U) */
12160 mask_write 0XFD40E36C 0x00000007 0x00000000
12161 # Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
12163 # Spread Spectrum No of Steps [7:0]
12164 # PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x0
12166 # Spread Spectrum No of Steps bits 7:0
12167 #(OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000000U) */
12168 mask_write 0XFD406368 0x000000FF 0x00000000
12169 # Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
12171 # Spread Spectrum No of Steps [10:8]
12172 # PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x0
12174 # Spread Spectrum No of Steps bits 10:8
12175 #(OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000000U) */
12176 mask_write 0XFD40636C 0x00000007 0x00000000
12177 # Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
12179 # Step Size for Spread Spectrum [7:0]
12180 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
12182 # Step Size for Spread Spectrum LSB
12183 #(OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x00000000U) */
12184 mask_write 0XFD406370 0x000000FF 0x00000000
12185 # Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
12187 # Step Size for Spread Spectrum [15:8]
12188 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
12190 # Step Size for Spread Spectrum 1
12191 #(OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000000U) */
12192 mask_write 0XFD406374 0x000000FF 0x00000000
12193 # Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
12195 # Step Size for Spread Spectrum [23:16]
12196 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
12198 # Step Size for Spread Spectrum 2
12199 #(OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000000U) */
12200 mask_write 0XFD406378 0x000000FF 0x00000000
12201 # Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
12203 # Step Size for Spread Spectrum [25:24]
12204 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
12206 # Enable/Disable test mode force on SS step size
12207 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
12209 # Enable/Disable test mode force on SS no of steps
12210 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
12212 # Enable force on enable Spread Spectrum
12213 #(OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) */
12214 mask_write 0XFD40637C 0x00000033 0x00000030
12215 # Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
12217 # Step Size for Spread Spectrum [7:0]
12218 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
12220 # Step Size for Spread Spectrum LSB
12221 #(OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) */
12222 mask_write 0XFD40A370 0x000000FF 0x000000F4
12223 # Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
12225 # Step Size for Spread Spectrum [15:8]
12226 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
12228 # Step Size for Spread Spectrum 1
12229 #(OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) */
12230 mask_write 0XFD40A374 0x000000FF 0x00000031
12231 # Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
12233 # Step Size for Spread Spectrum [23:16]
12234 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
12236 # Step Size for Spread Spectrum 2
12237 #(OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) */
12238 mask_write 0XFD40A378 0x000000FF 0x00000002
12239 # Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
12241 # Step Size for Spread Spectrum [25:24]
12242 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
12244 # Enable/Disable test mode force on SS step size
12245 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
12247 # Enable/Disable test mode force on SS no of steps
12248 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
12250 # Enable force on enable Spread Spectrum
12251 #(OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) */
12252 mask_write 0XFD40A37C 0x00000033 0x00000030
12253 # Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
12255 # Step Size for Spread Spectrum [7:0]
12256 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x0
12258 # Step Size for Spread Spectrum LSB
12259 #(OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x00000000U) */
12260 mask_write 0XFD40E370 0x000000FF 0x00000000
12261 # Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
12263 # Step Size for Spread Spectrum [15:8]
12264 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x0
12266 # Step Size for Spread Spectrum 1
12267 #(OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x00000000U) */
12268 mask_write 0XFD40E374 0x000000FF 0x00000000
12269 # Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
12271 # Step Size for Spread Spectrum [23:16]
12272 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x0
12274 # Step Size for Spread Spectrum 2
12275 #(OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000000U) */
12276 mask_write 0XFD40E378 0x000000FF 0x00000000
12277 # Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
12279 # Step Size for Spread Spectrum [25:24]
12280 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
12282 # Enable/Disable test mode force on SS step size
12283 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
12285 # Enable/Disable test mode force on SS no of steps
12286 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
12288 # Enable test mode forcing on enable Spread Spectrum
12289 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
12291 # Enable force on enable Spread Spectrum
12292 #(OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) */
12293 mask_write 0XFD40E37C 0x000000B3 0x000000B0
12294 # Register : L2_TM_DIG_6 @ 0XFD40906C</p>
12296 # Bypass Descrambler
12297 # PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
12299 # Enable Bypass for <1> TM_DIG_CTRL_6
12300 # PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
12302 # Data path test modes in decoder and descram
12303 #(OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) */
12304 mask_write 0XFD40906C 0x00000003 0x00000003
12305 # Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
12307 # Bypass scrambler signal
12308 # PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
12310 # Enable/disable scrambler bypass signal
12311 # PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
12313 # MPHY PLL Gear and bypass scrambler
12314 #(OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) */
12315 mask_write 0XFD4080F4 0x00000003 0x00000003
12316 # Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
12318 # Enable test mode force on fractional mode enable
12319 # PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
12321 # Fractional feedback division control and fractional value for feedback division bits 26:24
12322 #(OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) */
12323 mask_write 0XFD40E360 0x00000040 0x00000040
12324 # Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
12326 # Bypass 8b10b decoder
12327 # PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
12329 # Enable Bypass for <3> TM_DIG_CTRL_6
12330 # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
12332 # Bypass Descrambler
12333 # PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
12335 # Enable Bypass for <1> TM_DIG_CTRL_6
12336 # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
12338 # Data path test modes in decoder and descram
12339 #(OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) */
12340 mask_write 0XFD40D06C 0x0000000F 0x0000000F
12341 # Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
12343 # Enable/disable encoder bypass signal
12344 # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
12346 # Bypass scrambler signal
12347 # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
12349 # Enable/disable scrambler bypass signal
12350 # PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
12352 # MPHY PLL Gear and bypass scrambler
12353 #(OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) */
12354 mask_write 0XFD40C0F4 0x0000000B 0x0000000B
12355 # Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
12357 # PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
12358 # PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21
12361 #(OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) */
12362 mask_write 0XFD40CB00 0x000000F0 0x000000F0
12363 # : GT LANE SETTINGS
12364 # Register : ICM_CFG0 @ 0XFD410010</p>
12366 # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
12368 # PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
12370 # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
12372 # PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
12374 # ICM Configuration Register 0
12375 #(OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) */
12376 mask_write 0XFD410010 0x00000077 0x00000041
12377 # Register : ICM_CFG1 @ 0XFD410014</p>
12379 # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
12381 # PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
12383 # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
12385 # PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
12387 # ICM Configuration Register 1
12388 #(OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) */
12389 mask_write 0XFD410014 0x00000077 0x00000023
12390 # : CHECKING PLL LOCK
12391 # : ENABLE SERIAL DATA MUX DEEMPH
12392 # Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
12394 # Enable/disable DP post2 path
12395 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
12397 # Override enable/disable of DP post2 path
12398 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
12400 # Override enable/disable of DP post1 path
12401 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
12403 # Enable/disable DP main path
12404 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
12406 # Override enable/disable of DP main path
12407 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
12409 # Post or pre or main DP path selection
12410 #(OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) */
12411 mask_write 0XFD404CB4 0x00000037 0x00000037
12412 # Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
12414 # Test register force for enabling/disablign TX deemphasis bits <17:0>
12415 # PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
12417 # Enable Override of TX deemphasis
12418 #(OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) */
12419 mask_write 0XFD4041D8 0x00000001 0x00000001
12420 # : ENABLE PRE EMPHAIS AND VOLTAGE SWING
12421 # Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
12423 # Margining factor value
12424 # PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
12427 #(OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) */
12428 mask_write 0XFD404CC0 0x0000001F 0x00000000
12429 # Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
12431 # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
12432 # PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
12434 # Override for PIPE TX de-emphasis
12435 #(OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) */
12436 mask_write 0XFD404048 0x000000FF 0x00000000
12439 set psu_resetout_init_data {
12440 # : TAKING SERDES PERIPHERAL OUT OF RESET RESET
12441 # : PUTTING USB0 IN RESET
12442 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
12444 # USB 0 reset for control registers
12445 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
12447 # Software control register for the LPD block.
12448 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */
12449 mask_write 0XFF5E023C 0x00000400 0x00000000
12450 # : USB0 PIPE POWER PRESENT
12451 # Register : fpd_power_prsnt @ 0XFF9D0080</p>
12453 # This bit is used to choose between PIPE power present and 1'b1
12454 # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
12457 #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */
12458 mask_write 0XFF9D0080 0x00000001 0x00000001
12460 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
12462 # USB 0 sleep circuit reset
12463 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
12466 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
12468 # Software control register for the LPD block.
12469 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) */
12470 mask_write 0XFF5E023C 0x00000140 0x00000000
12471 # : PUTTING GEM0 IN RESET
12472 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
12475 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
12477 # Software controlled reset for the GEMs
12478 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */
12479 mask_write 0XFF5E0230 0x00000008 0x00000000
12480 # : PUTTING SATA IN RESET
12481 # Register : sata_misc_ctrl @ 0XFD3D0100</p>
12483 # Sata PM clock control select
12484 # PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
12486 # Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
12487 #(OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) */
12488 mask_write 0XFD3D0100 0x00000003 0x00000003
12489 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
12491 # Sata block level reset
12492 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
12494 # FPD Block level software controlled reset
12495 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) */
12496 mask_write 0XFD1A0100 0x00000002 0x00000000
12497 # : PUTTING PCIE IN RESET
12498 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
12500 # PCIE config reset
12501 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
12503 # PCIE control block level reset
12504 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
12506 # PCIE bridge block level reset (AXI interface)
12507 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
12509 # FPD Block level software controlled reset
12510 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x00000000U) */
12511 mask_write 0XFD1A0100 0x000E0000 0x00000000
12512 # : PUTTING DP IN RESET
12513 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
12515 # Display Port block level reset (includes DPDMA)
12516 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
12518 # FPD Block level software controlled reset
12519 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) */
12520 mask_write 0XFD1A0100 0x00010000 0x00000000
12521 # Register : DP_PHY_RESET @ 0XFD4A0200</p>
12523 # Set to '1' to hold the GT in reset. Clear to release.
12524 # PSU_DP_DP_PHY_RESET_GT_RESET 0X0
12526 # Reset the transmitter PHY.
12527 #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) */
12528 mask_write 0XFD4A0200 0x00000002 0x00000000
12529 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
12531 # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
12532 # ane0 Bits [3:2] - lane 1
12533 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
12535 # Control PHY Power down
12536 #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) */
12537 mask_write 0XFD4A0238 0x0000000F 0x00000000
12539 # Register : GUSB2PHYCFG @ 0XFE20C200</p>
12541 # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
12542 # he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
12543 # C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
12544 # . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
12545 # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
12546 # alue. Note: This field is valid only in device mode.
12547 # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
12549 # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
12550 # of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
12551 # time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
12552 # ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
12553 # off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
12554 # ng hibernation. - This bit is valid only in device mode.
12555 # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
12557 # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
12558 # _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
12559 # to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
12560 # ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
12561 # n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
12562 # d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
12564 # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
12566 # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
12567 # Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
12568 # 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
12569 # in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
12570 # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
12571 # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0X0
12573 # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
12574 # figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
12575 # ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
12576 # r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
12577 # t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
12578 # g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
12579 # when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
12580 # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
12582 # Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
12583 # full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
12584 # ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
12585 # B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
12586 # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0X0
12588 # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
12589 # e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
12590 # ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
12591 # lected through DWC_USB3_HSPHY_INTERFACE.
12592 # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
12594 # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
12595 # 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
12596 # lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
12597 # ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
12598 # any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
12599 # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0X0
12601 # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
12602 # a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
12603 # dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
12604 # e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
12605 # The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
12606 # ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
12607 # clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
12608 # 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
12609 # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
12611 # Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
12612 # he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
12614 #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FFFU ,0x00002457U) */
12615 mask_write 0XFE20C200 0x00003FFF 0x00002457
12616 # Register : GFLADJ @ 0XFE20C630</p>
12618 # This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
12619 # alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
12620 # _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
12621 # TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
12622 # riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
12623 # cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
12624 # uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
12625 # ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
12626 # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
12627 # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
12629 # Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
12630 # ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
12631 # to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
12632 # rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
12633 #(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */
12634 mask_write 0XFE20C630 0x003FFF00 0x00000000
12635 # : CHECK PLL LOCK FOR LANE0
12636 # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4</p>
12638 # Status Read value of PLL Lock
12639 # PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
12640 mask_poll 0XFD4023E4 0x00000010
12641 # : CHECK PLL LOCK FOR LANE1
12642 # Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
12644 # Status Read value of PLL Lock
12645 # PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
12646 mask_poll 0XFD4063E4 0x00000010
12647 # : CHECK PLL LOCK FOR LANE2
12648 # Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
12650 # Status Read value of PLL Lock
12651 # PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
12652 mask_poll 0XFD40A3E4 0x00000010
12653 # : CHECK PLL LOCK FOR LANE3
12654 # Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
12656 # Status Read value of PLL Lock
12657 # PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
12658 mask_poll 0XFD40E3E4 0x00000010
12659 # : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
12660 # Register : ATTR_37 @ 0XFD480094</p>
12662 # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
12663 # gister.; EP=0x0001; RP=0x0001
12664 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0X1
12667 #(OFFSET, MASK, VALUE) (0XFD480094, 0x00004000U ,0x00004000U) */
12668 mask_write 0XFD480094 0x00004000 0x00004000
12669 # Register : ATTR_25 @ 0XFD480064</p>
12671 # If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
12672 # ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
12673 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
12676 #(OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) */
12677 mask_write 0XFD480064 0x00000200 0x00000200
12679 # Register : ATTR_7 @ 0XFD48001C</p>
12681 # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
12682 # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
12683 # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
12684 # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
12685 # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
12686 # re size in bytes.; EP=0x0004; RP=0x0000
12687 # PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0
12690 #(OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) */
12691 mask_write 0XFD48001C 0x0000FFFF 0x00000000
12692 # Register : ATTR_8 @ 0XFD480020</p>
12694 # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
12695 # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
12696 # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
12697 # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
12698 # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
12699 # re size in bytes.; EP=0xFFF0; RP=0x0000
12700 # PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0
12703 #(OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) */
12704 mask_write 0XFD480020 0x0000FFFF 0x00000000
12705 # Register : ATTR_9 @ 0XFD480024</p>
12707 # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
12708 # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
12709 # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
12710 # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
12711 # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
12712 # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
12713 # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
12714 # PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0
12717 #(OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) */
12718 mask_write 0XFD480024 0x0000FFFF 0x00000000
12719 # Register : ATTR_10 @ 0XFD480028</p>
12721 # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
12722 # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
12723 # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
12724 # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
12725 # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
12726 # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
12727 # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
12728 # PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0
12731 #(OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) */
12732 mask_write 0XFD480028 0x0000FFFF 0x00000000
12733 # Register : ATTR_11 @ 0XFD48002C</p>
12735 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
12736 # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
12737 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
12738 # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
12739 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
12740 # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
12741 # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
12742 # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
12743 # PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF
12746 #(OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) */
12747 mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF
12748 # Register : ATTR_12 @ 0XFD480030</p>
12750 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
12751 # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
12752 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
12753 # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
12754 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
12755 # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
12756 # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
12757 # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
12758 # PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF
12761 #(OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) */
12762 mask_write 0XFD480030 0x0000FFFF 0x000000FF
12763 # Register : ATTR_13 @ 0XFD480034</p>
12765 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
12766 # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
12767 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
12768 # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
12769 # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
12770 # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
12771 # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
12772 # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
12773 # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
12774 # PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0
12777 #(OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) */
12778 mask_write 0XFD480034 0x0000FFFF 0x00000000
12779 # Register : ATTR_14 @ 0XFD480038</p>
12781 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
12782 # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
12783 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
12784 # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
12785 # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
12786 # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
12787 # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
12788 # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
12789 # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
12790 # PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF
12793 #(OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) */
12794 mask_write 0XFD480038 0x0000FFFF 0x0000FFFF
12795 # Register : ATTR_15 @ 0XFD48003C</p>
12797 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
12798 # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
12799 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
12800 # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
12801 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
12802 # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
12803 # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
12804 # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
12805 # PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0
12808 #(OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) */
12809 mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0
12810 # Register : ATTR_16 @ 0XFD480040</p>
12812 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
12813 # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
12814 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
12815 # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
12816 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
12817 # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
12818 # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
12819 # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
12820 # PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0
12823 #(OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) */
12824 mask_write 0XFD480040 0x0000FFFF 0x0000FFF0
12825 # Register : ATTR_17 @ 0XFD480044</p>
12827 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
12828 # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
12829 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
12830 # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
12831 # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
12832 # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
12833 # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
12834 # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
12835 # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
12836 # PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1
12839 #(OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) */
12840 mask_write 0XFD480044 0x0000FFFF 0x0000FFF1
12841 # Register : ATTR_18 @ 0XFD480048</p>
12843 # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
12844 # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
12845 # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
12846 # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
12847 # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
12848 # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
12849 # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
12850 # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
12851 # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
12852 # PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1
12855 #(OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) */
12856 mask_write 0XFD480048 0x0000FFFF 0x0000FFF1
12857 # Register : ATTR_27 @ 0XFD48006C</p>
12859 # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
12860 # to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
12861 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1
12863 # Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
12864 # state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
12865 # 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
12866 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0
12869 #(OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) */
12870 mask_write 0XFD48006C 0x00000738 0x00000100
12871 # Register : ATTR_50 @ 0XFD4800C8</p>
12873 # Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
12874 # 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
12875 # tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
12876 # gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
12877 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4
12879 # PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
12880 # lity.; EP=0x009C; RP=0x0000
12881 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0
12884 #(OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) */
12885 mask_write 0XFD4800C8 0x0000FFF0 0x00000040
12886 # Register : ATTR_105 @ 0XFD4801A4</p>
12888 # Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
12889 # ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
12890 # PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD
12893 #(OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) */
12894 mask_write 0XFD4801A4 0x000007FF 0x000000CD
12895 # Register : ATTR_106 @ 0XFD4801A8</p>
12897 # Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
12898 # osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
12899 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24
12901 # Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
12902 # a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
12903 # completion header credits must be <= 80; EP=0x0004; RP=0x000C
12904 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC
12907 #(OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) */
12908 mask_write 0XFD4801A8 0x00003FFF 0x00000624
12909 # Register : ATTR_107 @ 0XFD4801AC</p>
12911 # Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
12912 # redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
12913 # d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
12914 # less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
12915 # PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18
12918 #(OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) */
12919 mask_write 0XFD4801AC 0x000007FF 0x00000018
12920 # Register : ATTR_108 @ 0XFD4801B0</p>
12922 # Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
12923 # han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
12924 # PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5
12927 #(OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) */
12928 mask_write 0XFD4801B0 0x000007FF 0x000000B5
12929 # Register : ATTR_109 @ 0XFD4801B4</p>
12931 # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
12933 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0
12935 # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
12936 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1
12938 # Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
12939 # cap structure; EP=0x0003; RP=0x0003
12940 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3
12942 # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
12943 # mber of brams configured for transmit; EP=0x001C; RP=0x001C
12944 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c
12946 # Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
12947 # d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
12948 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20
12951 #(OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) */
12952 mask_write 0XFD4801B4 0x0000FFFF 0x00007E20
12953 # Register : ATTR_34 @ 0XFD480088</p>
12955 # Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
12956 # 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
12957 # PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1
12960 #(OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) */
12961 mask_write 0XFD480088 0x000000FF 0x00000001
12962 # Register : ATTR_53 @ 0XFD4800D4</p>
12964 # PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
12965 # ty.; EP=0x0048; RP=0x0060
12966 # PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60
12969 #(OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) */
12970 mask_write 0XFD4800D4 0x000000FF 0x00000060
12971 # Register : ATTR_41 @ 0XFD4800A4</p>
12973 # MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
12974 # to Cap structure; EP=0x0000; RP=0x0000
12975 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0
12977 # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
12978 # he management port.; EP=0x0001; RP=0x0000
12979 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
12981 # MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
12982 # ity.; EP=0x0060; RP=0x0000
12983 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0
12985 # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
12986 # he management port.; EP=0x0001; RP=0x0000
12987 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
12990 #(OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) */
12991 mask_write 0XFD4800A4 0x000003FF 0x00000000
12992 # Register : ATTR_97 @ 0XFD480184</p>
12994 # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
12995 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1
12997 # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
12999 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1
13002 #(OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) */
13003 mask_write 0XFD480184 0x00000FFF 0x00000041
13004 # Register : ATTR_100 @ 0XFD480190</p>
13006 # TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
13007 # PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0
13010 #(OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) */
13011 mask_write 0XFD480190 0x00000040 0x00000000
13012 # Register : ATTR_101 @ 0XFD480194</p>
13014 # Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
13015 # LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
13016 # Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
13017 # EP=0x0000; RP=0x07FF
13018 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF
13020 # Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
13021 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1
13024 #(OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) */
13025 mask_write 0XFD480194 0x0000FFE2 0x0000FFE2
13026 # Register : ATTR_37 @ 0XFD480094</p>
13028 # Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
13029 # Required for Root.; EP=0x0000; RP=0x0001
13030 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
13033 #(OFFSET, MASK, VALUE) (0XFD480094, 0x00000200U ,0x00000200U) */
13034 mask_write 0XFD480094 0x00000200 0x00000200
13035 # Register : ATTR_93 @ 0XFD480174</p>
13037 # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
13038 # _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
13039 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1
13041 # Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
13042 # TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
13043 # 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
13044 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000
13047 #(OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) */
13048 mask_write 0XFD480174 0x0000FFFF 0x00009000
13049 # Register : ID @ 0XFD480200</p>
13051 # Device ID for the the PCIe Cap Structure Device ID field
13052 # PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021
13054 # Vendor ID for the PCIe Cap Structure Vendor ID field
13055 # PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee
13058 #(OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) */
13059 mask_write 0XFD480200 0xFFFFFFFF 0x10EED021
13060 # Register : SUBSYS_ID @ 0XFD480204</p>
13062 # Subsystem ID for the the PCIe Cap Structure Subsystem ID field
13063 # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7
13065 # Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
13066 # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee
13069 #(OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) */
13070 mask_write 0XFD480204 0xFFFFFFFF 0x10EE0007
13071 # Register : REV_ID @ 0XFD480208</p>
13073 # Revision ID for the the PCIe Cap Structure
13074 # PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0
13077 #(OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) */
13078 mask_write 0XFD480208 0x000000FF 0x00000000
13079 # Register : ATTR_24 @ 0XFD480060</p>
13081 # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
13083 # PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400
13086 #(OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) */
13087 mask_write 0XFD480060 0x0000FFFF 0x00000400
13088 # Register : ATTR_25 @ 0XFD480064</p>
13090 # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
13092 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6
13094 # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
13095 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0
13098 #(OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) */
13099 mask_write 0XFD480064 0x000001FF 0x00000006
13100 # Register : ATTR_4 @ 0XFD480010</p>
13102 # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
13103 # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
13104 # ges are sent if an error is detected).; EP=0x0001; RP=0x0001
13105 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
13107 # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
13108 # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
13109 # ges are sent if an error is detected).; EP=0x0001; RP=0x0001
13110 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
13113 #(OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) */
13114 mask_write 0XFD480010 0x00001000 0x00000000
13115 # Register : ATTR_89 @ 0XFD480164</p>
13117 # VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
13118 # 0x0140; RP=0x0140
13119 # PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0
13122 #(OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) */
13123 mask_write 0XFD480164 0x00001FFE 0x00000000
13124 # Register : ATTR_79 @ 0XFD48013C</p>
13126 # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
13127 # PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1
13130 #(OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) */
13131 mask_write 0XFD48013C 0x00000020 0x00000020
13132 # Register : ATTR_43 @ 0XFD4800AC</p>
13134 # Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
13135 # the management port.; EP=0x0001; RP=0x0000
13136 # PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0
13139 #(OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) */
13140 mask_write 0XFD4800AC 0x00000100 0x00000000
13143 set psu_resetin_init_data {
13144 # : PUTTING SERDES PERIPHERAL IN RESET
13145 # : PUTTING USB0 IN RESET
13146 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
13148 # USB 0 reset for control registers
13149 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1
13151 # USB 0 sleep circuit reset
13152 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1
13155 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1
13157 # Software control register for the LPD block.
13158 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) */
13159 mask_write 0XFF5E023C 0x00000540 0x00000540
13160 # : PUTTING GEM0 IN RESET
13161 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
13164 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1
13166 # Software controlled reset for the GEMs
13167 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) */
13168 mask_write 0XFF5E0230 0x00000008 0x00000008
13169 # : PUTTING SATA IN RESET
13170 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
13172 # Sata block level reset
13173 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1
13175 # FPD Block level software controlled reset
13176 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) */
13177 mask_write 0XFD1A0100 0x00000002 0x00000002
13178 # : PUTTING PCIE IN RESET
13179 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
13181 # PCIE config reset
13182 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1
13184 # PCIE control block level reset
13185 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1
13187 # PCIE bridge block level reset (AXI interface)
13188 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1
13190 # FPD Block level software controlled reset
13191 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) */
13192 mask_write 0XFD1A0100 0x000E0000 0x000E0000
13193 # : PUTTING DP IN RESET
13194 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
13196 # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
13197 # ane0 Bits [3:2] - lane 1
13198 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA
13200 # Control PHY Power down
13201 #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) */
13202 mask_write 0XFD4A0238 0x0000000F 0x0000000A
13203 # Register : DP_PHY_RESET @ 0XFD4A0200</p>
13205 # Set to '1' to hold the GT in reset. Clear to release.
13206 # PSU_DP_DP_PHY_RESET_GT_RESET 0X1
13208 # Reset the transmitter PHY.
13209 #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) */
13210 mask_write 0XFD4A0200 0x00000002 0x00000002
13211 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
13213 # Display Port block level reset (includes DPDMA)
13214 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1
13216 # FPD Block level software controlled reset
13217 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) */
13218 mask_write 0XFD1A0100 0x00010000 0x00010000
13221 set psu_ps_pl_isolation_removal_data {
13222 # : PS-PL POWER UP REQUEST
13223 # Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
13225 # Power-up Request Interrupt Enable for PL
13226 # PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1
13228 # Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
13229 #(OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) */
13230 mask_write 0XFFD80118 0x00800000 0x00800000
13231 # Register : REQ_PWRUP_TRIG @ 0XFFD80120</p>
13233 # Power-up Request Trigger for PL
13234 # PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1
13236 # Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
13237 #(OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) */
13238 mask_write 0XFFD80120 0x00800000 0x00800000
13239 # : POLL ON PL POWER STATUS
13240 # Register : REQ_PWRUP_STATUS @ 0XFFD80110</p>
13242 # Power-up Request Status for PL
13243 # PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1
13244 mask_poll 0XFFD80110 0x00800000 0x00000000
13247 set psu_ps_pl_reset_config_data {
13248 # : PS PL RESET SEQUENCE
13249 # : FABRIC RESET USING EMIO
13250 # Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>
13252 # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
13253 # PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000
13255 # Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
13256 #(OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) */
13257 mask_write 0XFF0A002C 0xFFFF0000 0x80000000
13258 # Register : DIRM_5 @ 0XFF0A0344</p>
13260 # Operation is the same as DIRM_0[DIRECTION_0]
13261 # PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000
13263 # Direction mode (GPIO Bank5, EMIO)
13264 #(OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) */
13265 mask_write 0XFF0A0344 0xFFFFFFFF 0x80000000
13266 # Register : OEN_5 @ 0XFF0A0348</p>
13268 # Operation is the same as OEN_0[OP_ENABLE_0]
13269 # PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000
13271 # Output enable (GPIO Bank5, EMIO)
13272 #(OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) */
13273 mask_write 0XFF0A0348 0xFFFFFFFF 0x80000000
13274 # Register : DATA_5 @ 0XFF0A0054</p>
13277 # PSU_GPIO_DATA_5_DATA_5 0x80000000
13279 # Output Data (GPIO Bank5, EMIO)
13280 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */
13281 mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
13282 mask_delay 0x00000000 1
13283 # : FABRIC RESET USING DATA_5 TOGGLE
13284 # Register : DATA_5 @ 0XFF0A0054</p>
13287 # PSU_GPIO_DATA_5_DATA_5 0X00000000
13289 # Output Data (GPIO Bank5, EMIO)
13290 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) */
13291 mask_write 0XFF0A0054 0xFFFFFFFF 0x00000000
13292 mask_delay 0x00000000 1
13293 # : FABRIC RESET USING DATA_5 TOGGLE
13294 # Register : DATA_5 @ 0XFF0A0054</p>
13297 # PSU_GPIO_DATA_5_DATA_5 0x80000000
13299 # Output Data (GPIO Bank5, EMIO)
13300 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */
13301 mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
13305 # save current mode
13306 set saved_mode [configparams force-mem-accesses]
13308 configparams force-mem-accesses 1
13309 variable psu_mio_init_data
13310 variable psu_pll_init_data
13311 variable psu_clock_init_data
13312 variable psu_ddr_init_data
13313 variable psu_peripherals_init_data
13314 variable psu_resetin_init_data
13315 variable psu_resetout_init_data
13316 variable psu_serdes_init_data
13317 variable psu_resetin_init_data
13318 variable psu_peripherals_powerdwn_data
13320 init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }]
13321 psu_ddr_phybringup_data
13322 init_ps [subst {$psu_peripherals_init_data $psu_resetin_init_data }]
13324 init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }]
13326 init_ps [subst {$psu_peripherals_powerdwn_data }]
13327 # restore original mode
13328 configparams force-mem-accesses $saved_mode
13331 proc psu_post_config {} {
13332 variable psu_post_config_data
13333 init_ps [subst {$psu_post_config_data}]
13336 proc psu_ps_pl_reset_config {} {
13337 variable psu_ps_pl_reset_config_data
13338 init_ps [subst {$psu_ps_pl_reset_config_data}]
13341 proc psu_ps_pl_isolation_removal {} {
13342 variable psu_ps_pl_isolation_removal_data
13343 init_ps [subst {$psu_ps_pl_isolation_removal_data}]
13347 proc mask_read { addr mask } {
13348 set curval "0x[string range [mrd -force $addr] end-8 end]"
13349 set maskedval [expr {$curval & $mask}]
13354 proc mask_poll { addr mask } {
13356 set curval "0x[string range [mrd -force $addr] end-8 end]"
13357 set maskedval [expr {$curval & $mask}]
13358 while { $maskedval == 0 } {
13359 set curval "0x[string range [mrd -force $addr] end-8 end]"
13360 set maskedval [expr {$curval & $mask}]
13361 set count [ expr { $count + 1 } ]
13362 if { $count == 100000000 } {
13363 puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
13369 proc psu_mask_write { addr mask value } {
13370 set curval "0x[string range [mrd -force $addr] end-8 end]"
13371 set curval [expr {$curval & ~($mask)}]
13372 set maskedval [expr {$value & $mask}]
13373 set maskedval [expr {$curval | $maskedval}]
13374 mwr -force $addr $maskedval
13378 proc serdes_fixcal_code {} {
13380 # * L3_TM_CALIB_DIG19
13382 mask_write 0xFD40EC4C 0xFFFFFFFF 0x00000020
13388 mask_write 0xFD410010 0xFFFFFFFF 0x00000001
13392 # * is calibration done, polling on L3_CALIB_DONE_STATUS
13394 mask_poll 0xFD40EF14 0x2
13396 #unsigned int tmp_0_1;
13397 set tmp_0_1 [mrd -force -value 0xFD400B0C]
13398 set tmp_0_1 [expr {$tmp_0_1 & 0x3F}]
13400 set tmp_0_2 [expr {$tmp_0_1 & 0x7}]
13401 set tmp_0_3 [expr {$tmp_0_1 & 0x38}]
13403 #Configure ICM for de-asserting CMN_Resetn
13404 mask_write 0xFD410010 0xFFFFFFFF 0x00000000
13405 mask_write 0xFD410014 0xFFFFFFFF 0x00000000
13407 set tmp_0_2_mod [expr {($tmp_0_2 << 1) | (0x1)}]
13408 set tmp_0_2_mod [expr {$tmp_0_2_mod << 4}]
13410 set tmp_0_3 [expr {$tmp_0_3 >> 3}]
13411 mask_write 0xFD40EC4C 0xFFFFFFFF $tmp_0_3
13414 mask_write 0xFD40EC48 0xFFFFFFFF $tmp_0_2_mod
13419 proc serdes_enb_coarse_saturation {} {
13421 # * Enable PLL Coarse Code saturation Logic
13423 mask_write 0xFD402094 0xFFFFFFFF 0x00000010
13424 mask_write 0xFD406094 0xFFFFFFFF 0x00000010
13425 mask_write 0xFD40A094 0xFFFFFFFF 0x00000010
13426 mask_write 0xFD40E094 0xFFFFFFFF 0x00000010
13431 proc init_serdes {} {
13434 serdes_enb_coarse_saturation
13438 proc poll { addr mask data} {
13439 set curval "0x[string range [mrd -force $addr] end-8 end]"
13440 set maskedval [expr {$curval & $mask}]
13441 while { $maskedval != $data } {
13442 set curval "0x[string range [mrd -force $addr] end-8 end]"
13443 set maskedval [expr {$curval & $mask}]
13447 proc init_peripheral {} {
13449 # Release all resets in the IOU */
13450 mask_write 0xFF5E0230 0xFFFFFFFF 0x00000000
13451 mask_write 0xFF5E0234 0xFFFFFFFF 0x00000000
13452 mask_write 0xFF5E0238 0xFFFFFFFF 0x00000000
13454 # Take LPD out of reset except R5 */
13455 set tmp_0_1 [mrd -force -value 0xFF5E023C]
13456 set tmp_0_1 [expr {$tmp_0_1 & 0x7}]
13457 mask_write 0xFF5E023C 0xFFFFFFFF $tmp_0_1
13459 # Take most of FPD out of reset */
13460 mask_write 0XFD1A0100 0xFFFFFFFF 0x00000000
13462 # Making DPDMA as secure
13463 mask_write 0xFD690040 0x00000001 0x00000000
13464 # Making PCIe as secure
13465 mask_write 0xFD690030 0x00000001 0x00000000
13470 proc psu_ddr_phybringup_data {} {
13471 mwr -force 0xFD090000 0x0000A845
13472 mwr -force 0xFD090004 0x003FFFFF
13473 mwr -force 0xFD09000C 0x00000010
13474 mwr -force 0xFD090010 0x00000010
13476 poll 0xFD080030 0x0000000F 0x0000000F
13477 psu_mask_write 0xFD080004 0x00000001 0x00000001
13478 #poll for PHY initialization to complete
13479 poll 0xFD080030 0x000000FF 0x0000001F
13481 mwr -force 0xFD0701B0 0x00000001
13482 mwr -force 0xFD070320 0x00000001
13483 #//poll for DDR initialization to complete
13484 poll 0xFD070004 0x0000000F 0x00000001
13486 psu_mask_write 0xFD080014 0x00000040 0x00000040
13487 #Dummy reads before PHY training starts
13488 mrd -force 0xFD070004
13490 mrd -force 0xFD070004
13492 mrd -force 0xFD070004
13494 mrd -force 0xFD070004
13496 mrd -force 0xFD070004
13498 mrd -force 0xFD070004
13500 psu_mask_write 0xFD080004 0xFFFFFFFF 0x0004FE01
13501 #trigger PHY training
13502 poll 0xFD080030 0x00000FFF 0x00000FFF
13504 #Poll PUB_PGSR0 for Trng complete
13507 # Run Vref training in static read mode
13508 mwr -force 0xFD080200 0x110011C7
13509 mwr -force 0xFD080018 0x00F01EF2
13510 mwr -force 0xFD08001C 0x55AA0098
13511 mwr -force 0xFD08142C 0x00001830
13512 mwr -force 0xFD08146C 0x00001830
13513 mwr -force 0xFD0814AC 0x00001830
13514 mwr -force 0xFD0814EC 0x00001830
13515 mwr -force 0xFD08152C 0x00001830
13516 psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001
13518 #trigger VreFPHY training
13519 poll 0xFD080030 0x00004001 0x00004001
13521 #//Poll PUB_PGSR0 for Trng complete
13522 # Vref training is complete, disabling static read mode
13523 mwr -force 0xFD080200 0x810011C7
13524 mwr -force 0xFD080018 0x00F12302
13525 mwr -force 0xFD08001C 0x55AA0080
13526 mwr -force 0xFD08142C 0x00001800
13527 mwr -force 0xFD08146C 0x00001800
13528 mwr -force 0xFD0814AC 0x00001800
13529 mwr -force 0xFD0814EC 0x00001800
13530 mwr -force 0xFD08152C 0x00001800
13531 mwr -force 0xFD070180 0x01000040
13532 mwr -force 0xFD070060 0x00000000
13533 psu_mask_write 0xFD080014 0x00000040 0x00000000