git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c

   1 /******************************************************************************\r
   2 /****************************************************************************** \r
   3 *\r
   4 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.\r
   5 * \r
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy \r
   7 * of this software and associated documentation files (the "Software"), to deal \r
   8 * in the Software without restriction, including without limitation the rights \r
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell \r
  10 * copies of the Software, and to permit persons to whom the Software is \r
  11 * furnished to do so, subject to the following conditions: \r
  12 * \r
  13 * The above copyright notice and this permission notice shall be included in \r
  14 * all copies or substantial portions of the Software. \r
  15 * \r
  16 * Use of the Software is limited solely to applications: \r
  17 * (a) running on a Xilinx device, or \r
  18 * (b) that interact with a Xilinx device through a bus or interconnect. \r
  19 * \r
  20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR \r
  21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \r
  22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r
  23 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, \r
  24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF \r
  25 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE \r
  26 * SOFTWARE.\r
  27 * \r
  28 * Except as contained in this notice, the name of the Xilinx shall not be used \r
  29 * in advertising or otherwise to promote the sale, use or other dealings in \r
  30 * this Software without prior written authorization from Xilinx. \r
  31 * \r
  32 ******************************************************************************/ \r
  33 \r
  34 #include "psu_init_gpl.h"\r
  35 \r
  36 static unsigned int RegMask = 0x0;\r
  37 \r
  38 static unsigned int RegVal = 0x0;\r
  39 \r
  40 unsigned long psu_pll_init_data() {\r
  41                 // : RPLL INIT\r
  42                 // : UPDATE FB_DIV\r
  43                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>\r
  44 \r
  45                 The integer portion of the feedback divider to the PLL\r
  46                 PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x30\r
  47 \r
  48                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency\r
  49                 PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1\r
  50 \r
  51                 PLL Basic Control\r
  52                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00017F00U ,0x00013000U)  */\r
  53                 RegMask = (CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );\r
  54 \r
  55                 RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);\r
  56                 RegVal &= ~(RegMask);\r
  57                 RegVal |= ((0x00000030U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT\r
  58                         | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT\r
  59                         |  0 ) & RegMask);\r
  60                 Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);\r
  61 \r
  62         /*############################################################################################################################ */\r
  63 \r
  64                 // : BY PASS PLL\r
  65                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>\r
  66 \r
  67                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
  68                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
  69                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1\r
  70 \r
  71                 PLL Basic Control\r
  72                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  */\r
  73                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );\r
  74 \r
  75                 RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);\r
  76                 RegVal &= ~(RegMask);\r
  77                 RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT\r
  78                         |  0 ) & RegMask);\r
  79                 Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);\r
  80 \r
  81         /*############################################################################################################################ */\r
  82 \r
  83                 // : ASSERT RESET\r
  84                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>\r
  85 \r
  86                 Asserts Reset to the PLL\r
  87                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     1\r
  88 \r
  89                 PLL Basic Control\r
  90                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  */\r
  91                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );\r
  92 \r
  93                 RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);\r
  94                 RegVal &= ~(RegMask);\r
  95                 RegVal |= ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT\r
  96                         |  0 ) & RegMask);\r
  97                 Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);\r
  98 \r
  99         /*############################################################################################################################ */\r
 100 \r
 101                 // : DEASSERT RESET\r
 102                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>\r
 103 \r
 104                 Asserts Reset to the PLL\r
 105                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     0\r
 106 \r
 107                 PLL Basic Control\r
 108                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  */\r
 109                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );\r
 110 \r
 111                 RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);\r
 112                 RegVal &= ~(RegMask);\r
 113                 RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT\r
 114                         |  0 ) & RegMask);\r
 115                 Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);\r
 116 \r
 117         /*############################################################################################################################ */\r
 118 \r
 119                 // : CHECK PLL STATUS\r
 120                 /*Register : PLL_STATUS @ 0XFF5E0040</p>\r
 121 \r
 122                 RPLL is locked\r
 123                 PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1\r
 124                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */\r
 125                 while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000002U));\r
 126 \r
 127         /*############################################################################################################################ */\r
 128 \r
 129                 // : REMOVE PLL BY PASS\r
 130                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>\r
 131 \r
 132                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 133                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 134                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0\r
 135 \r
 136                 PLL Basic Control\r
 137                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  */\r
 138                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );\r
 139 \r
 140                 RegVal = Xil_In32 (CRL_APB_RPLL_CTRL_OFFSET);\r
 141                 RegVal &= ~(RegMask);\r
 142                 RegVal |= ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT\r
 143                         |  0 ) & RegMask);\r
 144                 Xil_Out32 ( CRL_APB_RPLL_CTRL_OFFSET , RegVal);\r
 145 \r
 146         /*############################################################################################################################ */\r
 147 \r
 148                 /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>\r
 149 \r
 150                 Divisor value for this clock.\r
 151                 PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3\r
 152 \r
 153                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.\r
 154                 (OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  */\r
 155                 RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );\r
 156 \r
 157                 RegVal = Xil_In32 (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET);\r
 158                 RegVal &= ~(RegMask);\r
 159                 RegVal |= ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT\r
 160                         |  0 ) & RegMask);\r
 161                 Xil_Out32 ( CRL_APB_RPLL_TO_FPD_CTRL_OFFSET , RegVal);\r
 162 \r
 163         /*############################################################################################################################ */\r
 164 \r
 165                 // : RPLL FRAC CFG\r
 166                 // : IOPLL INIT\r
 167                 // : UPDATE FB_DIV\r
 168                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>\r
 169 \r
 170                 The integer portion of the feedback divider to the PLL\r
 171                 PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x3c\r
 172 \r
 173                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency\r
 174                 PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x1\r
 175 \r
 176                 PLL Basic Control\r
 177                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00017F00U ,0x00013C00U)  */\r
 178                 RegMask = (CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );\r
 179 \r
 180                 RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);\r
 181                 RegVal &= ~(RegMask);\r
 182                 RegVal |= ((0x0000003CU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT\r
 183                         | 0x00000001U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT\r
 184                         |  0 ) & RegMask);\r
 185                 Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);\r
 186 \r
 187         /*############################################################################################################################ */\r
 188 \r
 189                 // : BY PASS PLL\r
 190                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>\r
 191 \r
 192                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 193                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 194                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1\r
 195 \r
 196                 PLL Basic Control\r
 197                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  */\r
 198                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );\r
 199 \r
 200                 RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);\r
 201                 RegVal &= ~(RegMask);\r
 202                 RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT\r
 203                         |  0 ) & RegMask);\r
 204                 Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);\r
 205 \r
 206         /*############################################################################################################################ */\r
 207 \r
 208                 // : ASSERT RESET\r
 209                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>\r
 210 \r
 211                 Asserts Reset to the PLL\r
 212                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1\r
 213 \r
 214                 PLL Basic Control\r
 215                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  */\r
 216                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );\r
 217 \r
 218                 RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);\r
 219                 RegVal &= ~(RegMask);\r
 220                 RegVal |= ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT\r
 221                         |  0 ) & RegMask);\r
 222                 Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);\r
 223 \r
 224         /*############################################################################################################################ */\r
 225 \r
 226                 // : DEASSERT RESET\r
 227                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>\r
 228 \r
 229                 Asserts Reset to the PLL\r
 230                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0\r
 231 \r
 232                 PLL Basic Control\r
 233                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  */\r
 234                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );\r
 235 \r
 236                 RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);\r
 237                 RegVal &= ~(RegMask);\r
 238                 RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT\r
 239                         |  0 ) & RegMask);\r
 240                 Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);\r
 241 \r
 242         /*############################################################################################################################ */\r
 243 \r
 244                 // : CHECK PLL STATUS\r
 245                 /*Register : PLL_STATUS @ 0XFF5E0040</p>\r
 246 \r
 247                 IOPLL is locked\r
 248                 PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1\r
 249                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */\r
 250                 while(!(Xil_In32 ( CRL_APB_PLL_STATUS_OFFSET) & 0x00000001U));\r
 251 \r
 252         /*############################################################################################################################ */\r
 253 \r
 254                 // : REMOVE PLL BY PASS\r
 255                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>\r
 256 \r
 257                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 258                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 259                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0\r
 260 \r
 261                 PLL Basic Control\r
 262                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  */\r
 263                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );\r
 264 \r
 265                 RegVal = Xil_In32 (CRL_APB_IOPLL_CTRL_OFFSET);\r
 266                 RegVal &= ~(RegMask);\r
 267                 RegVal |= ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT\r
 268                         |  0 ) & RegMask);\r
 269                 Xil_Out32 ( CRL_APB_IOPLL_CTRL_OFFSET , RegVal);\r
 270 \r
 271         /*############################################################################################################################ */\r
 272 \r
 273                 /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>\r
 274 \r
 275                 Divisor value for this clock.\r
 276                 PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x4\r
 277 \r
 278                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.\r
 279                 (OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000400U)  */\r
 280                 RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );\r
 281 \r
 282                 RegVal = Xil_In32 (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET);\r
 283                 RegVal &= ~(RegMask);\r
 284                 RegVal |= ((0x00000004U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT\r
 285                         |  0 ) & RegMask);\r
 286                 Xil_Out32 ( CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET , RegVal);\r
 287 \r
 288         /*############################################################################################################################ */\r
 289 \r
 290                 // : IOPLL FRAC CFG\r
 291                 // : APU_PLL INIT\r
 292                 // : UPDATE FB_DIV\r
 293                 /*Register : APLL_CTRL @ 0XFD1A0020</p>\r
 294 \r
 295                 The integer portion of the feedback divider to the PLL\r
 296                 PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x3c\r
 297 \r
 298                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency\r
 299                 PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1\r
 300 \r
 301                 PLL Basic Control\r
 302                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00017F00U ,0x00013C00U)  */\r
 303                 RegMask = (CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );\r
 304 \r
 305                 RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);\r
 306                 RegVal &= ~(RegMask);\r
 307                 RegVal |= ((0x0000003CU << CRF_APB_APLL_CTRL_FBDIV_SHIFT\r
 308                         | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT\r
 309                         |  0 ) & RegMask);\r
 310                 Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);\r
 311 \r
 312         /*############################################################################################################################ */\r
 313 \r
 314                 // : BY PASS PLL\r
 315                 /*Register : APLL_CTRL @ 0XFD1A0020</p>\r
 316 \r
 317                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 318                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 319                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1\r
 320 \r
 321                 PLL Basic Control\r
 322                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  */\r
 323                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );\r
 324 \r
 325                 RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);\r
 326                 RegVal &= ~(RegMask);\r
 327                 RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT\r
 328                         |  0 ) & RegMask);\r
 329                 Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);\r
 330 \r
 331         /*############################################################################################################################ */\r
 332 \r
 333                 // : ASSERT RESET\r
 334                 /*Register : APLL_CTRL @ 0XFD1A0020</p>\r
 335 \r
 336                 Asserts Reset to the PLL\r
 337                 PSU_CRF_APB_APLL_CTRL_RESET                                                     1\r
 338 \r
 339                 PLL Basic Control\r
 340                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  */\r
 341                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );\r
 342 \r
 343                 RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);\r
 344                 RegVal &= ~(RegMask);\r
 345                 RegVal |= ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT\r
 346                         |  0 ) & RegMask);\r
 347                 Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);\r
 348 \r
 349         /*############################################################################################################################ */\r
 350 \r
 351                 // : DEASSERT RESET\r
 352                 /*Register : APLL_CTRL @ 0XFD1A0020</p>\r
 353 \r
 354                 Asserts Reset to the PLL\r
 355                 PSU_CRF_APB_APLL_CTRL_RESET                                                     0\r
 356 \r
 357                 PLL Basic Control\r
 358                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  */\r
 359                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );\r
 360 \r
 361                 RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);\r
 362                 RegVal &= ~(RegMask);\r
 363                 RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT\r
 364                         |  0 ) & RegMask);\r
 365                 Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);\r
 366 \r
 367         /*############################################################################################################################ */\r
 368 \r
 369                 // : CHECK PLL STATUS\r
 370                 /*Register : PLL_STATUS @ 0XFD1A0044</p>\r
 371 \r
 372                 APLL is locked\r
 373                 PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1\r
 374                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */\r
 375                 while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000001U));\r
 376 \r
 377         /*############################################################################################################################ */\r
 378 \r
 379                 // : REMOVE PLL BY PASS\r
 380                 /*Register : APLL_CTRL @ 0XFD1A0020</p>\r
 381 \r
 382                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 383                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 384                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0\r
 385 \r
 386                 PLL Basic Control\r
 387                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  */\r
 388                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );\r
 389 \r
 390                 RegVal = Xil_In32 (CRF_APB_APLL_CTRL_OFFSET);\r
 391                 RegVal &= ~(RegMask);\r
 392                 RegVal |= ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT\r
 393                         |  0 ) & RegMask);\r
 394                 Xil_Out32 ( CRF_APB_APLL_CTRL_OFFSET , RegVal);\r
 395 \r
 396         /*############################################################################################################################ */\r
 397 \r
 398                 /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>\r
 399 \r
 400                 Divisor value for this clock.\r
 401                 PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x4\r
 402 \r
 403                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.\r
 404                 (OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000400U)  */\r
 405                 RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );\r
 406 \r
 407                 RegVal = Xil_In32 (CRF_APB_APLL_TO_LPD_CTRL_OFFSET);\r
 408                 RegVal &= ~(RegMask);\r
 409                 RegVal |= ((0x00000004U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT\r
 410                         |  0 ) & RegMask);\r
 411                 Xil_Out32 ( CRF_APB_APLL_TO_LPD_CTRL_OFFSET , RegVal);\r
 412 \r
 413         /*############################################################################################################################ */\r
 414 \r
 415                 // : APLL FRAC CFG\r
 416                 // : DDR_PLL INIT\r
 417                 // : UPDATE FB_DIV\r
 418                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>\r
 419 \r
 420                 The integer portion of the feedback divider to the PLL\r
 421                 PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x3c\r
 422 \r
 423                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency\r
 424                 PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1\r
 425 \r
 426                 PLL Basic Control\r
 427                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00017F00U ,0x00013C00U)  */\r
 428                 RegMask = (CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );\r
 429 \r
 430                 RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);\r
 431                 RegVal &= ~(RegMask);\r
 432                 RegVal |= ((0x0000003CU << CRF_APB_DPLL_CTRL_FBDIV_SHIFT\r
 433                         | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT\r
 434                         |  0 ) & RegMask);\r
 435                 Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);\r
 436 \r
 437         /*############################################################################################################################ */\r
 438 \r
 439                 // : BY PASS PLL\r
 440                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>\r
 441 \r
 442                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 443                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 444                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1\r
 445 \r
 446                 PLL Basic Control\r
 447                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  */\r
 448                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );\r
 449 \r
 450                 RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);\r
 451                 RegVal &= ~(RegMask);\r
 452                 RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT\r
 453                         |  0 ) & RegMask);\r
 454                 Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);\r
 455 \r
 456         /*############################################################################################################################ */\r
 457 \r
 458                 // : ASSERT RESET\r
 459                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>\r
 460 \r
 461                 Asserts Reset to the PLL\r
 462                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     1\r
 463 \r
 464                 PLL Basic Control\r
 465                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  */\r
 466                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );\r
 467 \r
 468                 RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);\r
 469                 RegVal &= ~(RegMask);\r
 470                 RegVal |= ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT\r
 471                         |  0 ) & RegMask);\r
 472                 Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);\r
 473 \r
 474         /*############################################################################################################################ */\r
 475 \r
 476                 // : DEASSERT RESET\r
 477                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>\r
 478 \r
 479                 Asserts Reset to the PLL\r
 480                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     0\r
 481 \r
 482                 PLL Basic Control\r
 483                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  */\r
 484                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );\r
 485 \r
 486                 RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);\r
 487                 RegVal &= ~(RegMask);\r
 488                 RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT\r
 489                         |  0 ) & RegMask);\r
 490                 Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);\r
 491 \r
 492         /*############################################################################################################################ */\r
 493 \r
 494                 // : CHECK PLL STATUS\r
 495                 /*Register : PLL_STATUS @ 0XFD1A0044</p>\r
 496 \r
 497                 DPLL is locked\r
 498                 PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1\r
 499                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */\r
 500                 while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000002U));\r
 501 \r
 502         /*############################################################################################################################ */\r
 503 \r
 504                 // : REMOVE PLL BY PASS\r
 505                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>\r
 506 \r
 507                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 508                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 509                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0\r
 510 \r
 511                 PLL Basic Control\r
 512                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  */\r
 513                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );\r
 514 \r
 515                 RegVal = Xil_In32 (CRF_APB_DPLL_CTRL_OFFSET);\r
 516                 RegVal &= ~(RegMask);\r
 517                 RegVal |= ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT\r
 518                         |  0 ) & RegMask);\r
 519                 Xil_Out32 ( CRF_APB_DPLL_CTRL_OFFSET , RegVal);\r
 520 \r
 521         /*############################################################################################################################ */\r
 522 \r
 523                 /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>\r
 524 \r
 525                 Divisor value for this clock.\r
 526                 PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x4\r
 527 \r
 528                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.\r
 529                 (OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000400U)  */\r
 530                 RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );\r
 531 \r
 532                 RegVal = Xil_In32 (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET);\r
 533                 RegVal &= ~(RegMask);\r
 534                 RegVal |= ((0x00000004U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT\r
 535                         |  0 ) & RegMask);\r
 536                 Xil_Out32 ( CRF_APB_DPLL_TO_LPD_CTRL_OFFSET , RegVal);\r
 537 \r
 538         /*############################################################################################################################ */\r
 539 \r
 540                 // : DPLL FRAC CFG\r
 541                 // : VIDEO_PLL INIT\r
 542                 // : UPDATE FB_DIV\r
 543                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>\r
 544 \r
 545                 The integer portion of the feedback divider to the PLL\r
 546                 PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x3f\r
 547 \r
 548                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency\r
 549                 PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1\r
 550 \r
 551                 PLL Basic Control\r
 552                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00017F00U ,0x00013F00U)  */\r
 553                 RegMask = (CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );\r
 554 \r
 555                 RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);\r
 556                 RegVal &= ~(RegMask);\r
 557                 RegVal |= ((0x0000003FU << CRF_APB_VPLL_CTRL_FBDIV_SHIFT\r
 558                         | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT\r
 559                         |  0 ) & RegMask);\r
 560                 Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);\r
 561 \r
 562         /*############################################################################################################################ */\r
 563 \r
 564                 // : BY PASS PLL\r
 565                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>\r
 566 \r
 567                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 568                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 569                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1\r
 570 \r
 571                 PLL Basic Control\r
 572                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  */\r
 573                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );\r
 574 \r
 575                 RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);\r
 576                 RegVal &= ~(RegMask);\r
 577                 RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT\r
 578                         |  0 ) & RegMask);\r
 579                 Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);\r
 580 \r
 581         /*############################################################################################################################ */\r
 582 \r
 583                 // : ASSERT RESET\r
 584                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>\r
 585 \r
 586                 Asserts Reset to the PLL\r
 587                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     1\r
 588 \r
 589                 PLL Basic Control\r
 590                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  */\r
 591                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );\r
 592 \r
 593                 RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);\r
 594                 RegVal &= ~(RegMask);\r
 595                 RegVal |= ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT\r
 596                         |  0 ) & RegMask);\r
 597                 Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);\r
 598 \r
 599         /*############################################################################################################################ */\r
 600 \r
 601                 // : DEASSERT RESET\r
 602                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>\r
 603 \r
 604                 Asserts Reset to the PLL\r
 605                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     0\r
 606 \r
 607                 PLL Basic Control\r
 608                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  */\r
 609                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );\r
 610 \r
 611                 RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);\r
 612                 RegVal &= ~(RegMask);\r
 613                 RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT\r
 614                         |  0 ) & RegMask);\r
 615                 Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);\r
 616 \r
 617         /*############################################################################################################################ */\r
 618 \r
 619                 // : CHECK PLL STATUS\r
 620                 /*Register : PLL_STATUS @ 0XFD1A0044</p>\r
 621 \r
 622                 VPLL is locked\r
 623                 PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1\r
 624                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */\r
 625                 while(!(Xil_In32 ( CRF_APB_PLL_STATUS_OFFSET) & 0x00000004U));\r
 626 \r
 627         /*############################################################################################################################ */\r
 628 \r
 629                 // : REMOVE PLL BY PASS\r
 630                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>\r
 631 \r
 632                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4\r
 633                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
 634                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0\r
 635 \r
 636                 PLL Basic Control\r
 637                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  */\r
 638                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );\r
 639 \r
 640                 RegVal = Xil_In32 (CRF_APB_VPLL_CTRL_OFFSET);\r
 641                 RegVal &= ~(RegMask);\r
 642                 RegVal |= ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT\r
 643                         |  0 ) & RegMask);\r
 644                 Xil_Out32 ( CRF_APB_VPLL_CTRL_OFFSET , RegVal);\r
 645 \r
 646         /*############################################################################################################################ */\r
 647 \r
 648                 /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>\r
 649 \r
 650                 Divisor value for this clock.\r
 651                 PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x4\r
 652 \r
 653                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.\r
 654                 (OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000400U)  */\r
 655                 RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );\r
 656 \r
 657                 RegVal = Xil_In32 (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET);\r
 658                 RegVal &= ~(RegMask);\r
 659                 RegVal |= ((0x00000004U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT\r
 660                         |  0 ) & RegMask);\r
 661                 Xil_Out32 ( CRF_APB_VPLL_TO_LPD_CTRL_OFFSET , RegVal);\r
 662 \r
 663         /*############################################################################################################################ */\r
 664 \r
 665                 // : VIDEO FRAC CFG\r
 666 \r
 667 }\r
 668 unsigned long psu_clock_init_data() {\r
 669                 // : CLOCK CONTROL SLCR REGISTER\r
 670                 /*Register : GEM0_REF_CTRL @ 0XFF5E0050</p>\r
 671 \r
 672                 Clock active for the RX channel\r
 673                 PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1\r
 674 \r
 675                 Clock active signal. Switch to 0 to disable the clock\r
 676                 PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1\r
 677 \r
 678                 6 bit divider\r
 679                 PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x2\r
 680 \r
 681                 6 bit divider\r
 682                 PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x28\r
 683 \r
 684                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 685                 clock. This is not usually an issue, but designers must be aware.)\r
 686                 PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0\r
 687 \r
 688                 This register controls this reference clock\r
 689                 (OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06022800U)  */\r
 690                 RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );\r
 691 \r
 692                 RegVal = Xil_In32 (CRL_APB_GEM0_REF_CTRL_OFFSET);\r
 693                 RegVal &= ~(RegMask);\r
 694                 RegVal |= ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT\r
 695                         | 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT\r
 696                         | 0x00000002U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT\r
 697                         | 0x00000028U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT\r
 698                         | 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT\r
 699                         |  0 ) & RegMask);\r
 700                 Xil_Out32 ( CRL_APB_GEM0_REF_CTRL_OFFSET , RegVal);\r
 701 \r
 702         /*############################################################################################################################ */\r
 703 \r
 704                 /*Register : GEM1_REF_CTRL @ 0XFF5E0054</p>\r
 705 \r
 706                 Clock active for the RX channel\r
 707                 PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1\r
 708 \r
 709                 Clock active signal. Switch to 0 to disable the clock\r
 710                 PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1\r
 711 \r
 712                 6 bit divider\r
 713                 PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x2\r
 714 \r
 715                 6 bit divider\r
 716                 PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x28\r
 717 \r
 718                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 719                 clock. This is not usually an issue, but designers must be aware.)\r
 720                 PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0\r
 721 \r
 722                 This register controls this reference clock\r
 723                 (OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06022800U)  */\r
 724                 RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );\r
 725 \r
 726                 RegVal = Xil_In32 (CRL_APB_GEM1_REF_CTRL_OFFSET);\r
 727                 RegVal &= ~(RegMask);\r
 728                 RegVal |= ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT\r
 729                         | 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT\r
 730                         | 0x00000002U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT\r
 731                         | 0x00000028U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT\r
 732                         | 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT\r
 733                         |  0 ) & RegMask);\r
 734                 Xil_Out32 ( CRL_APB_GEM1_REF_CTRL_OFFSET , RegVal);\r
 735 \r
 736         /*############################################################################################################################ */\r
 737 \r
 738                 /*Register : GEM2_REF_CTRL @ 0XFF5E0058</p>\r
 739 \r
 740                 Clock active for the RX channel\r
 741                 PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1\r
 742 \r
 743                 Clock active signal. Switch to 0 to disable the clock\r
 744                 PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1\r
 745 \r
 746                 6 bit divider\r
 747                 PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x2\r
 748 \r
 749                 6 bit divider\r
 750                 PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x28\r
 751 \r
 752                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 753                 clock. This is not usually an issue, but designers must be aware.)\r
 754                 PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0\r
 755 \r
 756                 This register controls this reference clock\r
 757                 (OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06022800U)  */\r
 758                 RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );\r
 759 \r
 760                 RegVal = Xil_In32 (CRL_APB_GEM2_REF_CTRL_OFFSET);\r
 761                 RegVal &= ~(RegMask);\r
 762                 RegVal |= ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT\r
 763                         | 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT\r
 764                         | 0x00000002U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT\r
 765                         | 0x00000028U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT\r
 766                         | 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT\r
 767                         |  0 ) & RegMask);\r
 768                 Xil_Out32 ( CRL_APB_GEM2_REF_CTRL_OFFSET , RegVal);\r
 769 \r
 770         /*############################################################################################################################ */\r
 771 \r
 772                 /*Register : GEM3_REF_CTRL @ 0XFF5E005C</p>\r
 773 \r
 774                 Clock active for the RX channel\r
 775                 PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1\r
 776 \r
 777                 Clock active signal. Switch to 0 to disable the clock\r
 778                 PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1\r
 779 \r
 780                 6 bit divider\r
 781                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x2\r
 782 \r
 783                 6 bit divider\r
 784                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0x28\r
 785 \r
 786                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 787                 clock. This is not usually an issue, but designers must be aware.)\r
 788                 PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0\r
 789 \r
 790                 This register controls this reference clock\r
 791                 (OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06022800U)  */\r
 792                 RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );\r
 793 \r
 794                 RegVal = Xil_In32 (CRL_APB_GEM3_REF_CTRL_OFFSET);\r
 795                 RegVal &= ~(RegMask);\r
 796                 RegVal |= ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT\r
 797                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT\r
 798                         | 0x00000002U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT\r
 799                         | 0x00000028U << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT\r
 800                         | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT\r
 801                         |  0 ) & RegMask);\r
 802                 Xil_Out32 ( CRL_APB_GEM3_REF_CTRL_OFFSET , RegVal);\r
 803 \r
 804         /*############################################################################################################################ */\r
 805 \r
 806                 /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>\r
 807 \r
 808                 Clock active signal. Switch to 0 to disable the clock\r
 809                 PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1\r
 810 \r
 811                 6 bit divider\r
 812                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1\r
 813 \r
 814                 6 bit divider\r
 815                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x32\r
 816 \r
 817                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 818                 clock. This is not usually an issue, but designers must be aware.)\r
 819                 PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0\r
 820 \r
 821                 This register controls this reference clock\r
 822                 (OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02013200U)  */\r
 823                 RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );\r
 824 \r
 825                 RegVal = Xil_In32 (CRL_APB_USB0_BUS_REF_CTRL_OFFSET);\r
 826                 RegVal &= ~(RegMask);\r
 827                 RegVal |= ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT\r
 828                         | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT\r
 829                         | 0x00000032U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT\r
 830                         | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT\r
 831                         |  0 ) & RegMask);\r
 832                 Xil_Out32 ( CRL_APB_USB0_BUS_REF_CTRL_OFFSET , RegVal);\r
 833 \r
 834         /*############################################################################################################################ */\r
 835 \r
 836                 /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>\r
 837 \r
 838                 Clock active signal. Switch to 0 to disable the clock\r
 839                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1\r
 840 \r
 841                 6 bit divider\r
 842                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0x1\r
 843 \r
 844                 6 bit divider\r
 845                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x8\r
 846 \r
 847                 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 848                 clock. This is not usually an issue, but designers must be aware.)\r
 849                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0\r
 850 \r
 851                 This register controls this reference clock\r
 852                 (OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x02010800U)  */\r
 853                 RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );\r
 854 \r
 855                 RegVal = Xil_In32 (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET);\r
 856                 RegVal &= ~(RegMask);\r
 857                 RegVal |= ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT\r
 858                         | 0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT\r
 859                         | 0x00000008U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT\r
 860                         | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT\r
 861                         |  0 ) & RegMask);\r
 862                 Xil_Out32 ( CRL_APB_USB3_DUAL_REF_CTRL_OFFSET , RegVal);\r
 863 \r
 864         /*############################################################################################################################ */\r
 865 \r
 866                 /*Register : QSPI_REF_CTRL @ 0XFF5E0068</p>\r
 867 \r
 868                 Clock active signal. Switch to 0 to disable the clock\r
 869                 PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1\r
 870 \r
 871                 6 bit divider\r
 872                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x2\r
 873 \r
 874                 6 bit divider\r
 875                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0x32\r
 876 \r
 877                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 878                 clock. This is not usually an issue, but designers must be aware.)\r
 879                 PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0\r
 880 \r
 881                 This register controls this reference clock\r
 882                 (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01023200U)  */\r
 883                 RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );\r
 884 \r
 885                 RegVal = Xil_In32 (CRL_APB_QSPI_REF_CTRL_OFFSET);\r
 886                 RegVal &= ~(RegMask);\r
 887                 RegVal |= ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT\r
 888                         | 0x00000002U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT\r
 889                         | 0x00000032U << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT\r
 890                         | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT\r
 891                         |  0 ) & RegMask);\r
 892                 Xil_Out32 ( CRL_APB_QSPI_REF_CTRL_OFFSET , RegVal);\r
 893 \r
 894         /*############################################################################################################################ */\r
 895 \r
 896                 /*Register : SDIO0_REF_CTRL @ 0XFF5E006C</p>\r
 897 \r
 898                 Clock active signal. Switch to 0 to disable the clock\r
 899                 PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1\r
 900 \r
 901                 6 bit divider\r
 902                 PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x2\r
 903 \r
 904                 6 bit divider\r
 905                 PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x32\r
 906 \r
 907                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 908                 clock. This is not usually an issue, but designers must be aware.)\r
 909                 PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x0\r
 910 \r
 911                 This register controls this reference clock\r
 912                 (OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01023200U)  */\r
 913                 RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );\r
 914 \r
 915                 RegVal = Xil_In32 (CRL_APB_SDIO0_REF_CTRL_OFFSET);\r
 916                 RegVal &= ~(RegMask);\r
 917                 RegVal |= ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT\r
 918                         | 0x00000002U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT\r
 919                         | 0x00000032U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT\r
 920                         | 0x00000000U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT\r
 921                         |  0 ) & RegMask);\r
 922                 Xil_Out32 ( CRL_APB_SDIO0_REF_CTRL_OFFSET , RegVal);\r
 923 \r
 924         /*############################################################################################################################ */\r
 925 \r
 926                 /*Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>\r
 927 \r
 928                 Clock active signal. Switch to 0 to disable the clock\r
 929                 PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1\r
 930 \r
 931                 6 bit divider\r
 932                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x2\r
 933 \r
 934                 6 bit divider\r
 935                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x32\r
 936 \r
 937                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 938                 clock. This is not usually an issue, but designers must be aware.)\r
 939                 PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x0\r
 940 \r
 941                 This register controls this reference clock\r
 942                 (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01023200U)  */\r
 943                 RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );\r
 944 \r
 945                 RegVal = Xil_In32 (CRL_APB_SDIO1_REF_CTRL_OFFSET);\r
 946                 RegVal &= ~(RegMask);\r
 947                 RegVal |= ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT\r
 948                         | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT\r
 949                         | 0x00000032U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT\r
 950                         | 0x00000000U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT\r
 951                         |  0 ) & RegMask);\r
 952                 Xil_Out32 ( CRL_APB_SDIO1_REF_CTRL_OFFSET , RegVal);\r
 953 \r
 954         /*############################################################################################################################ */\r
 955 \r
 956                 /*Register : UART0_REF_CTRL @ 0XFF5E0074</p>\r
 957 \r
 958                 Clock active signal. Switch to 0 to disable the clock\r
 959                 PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1\r
 960 \r
 961                 6 bit divider\r
 962                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x2\r
 963 \r
 964                 6 bit divider\r
 965                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0x28\r
 966 \r
 967                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 968                 clock. This is not usually an issue, but designers must be aware.)\r
 969                 PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0\r
 970 \r
 971                 This register controls this reference clock\r
 972                 (OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01022800U)  */\r
 973                 RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );\r
 974 \r
 975                 RegVal = Xil_In32 (CRL_APB_UART0_REF_CTRL_OFFSET);\r
 976                 RegVal &= ~(RegMask);\r
 977                 RegVal |= ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT\r
 978                         | 0x00000002U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT\r
 979                         | 0x00000028U << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT\r
 980                         | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT\r
 981                         |  0 ) & RegMask);\r
 982                 Xil_Out32 ( CRL_APB_UART0_REF_CTRL_OFFSET , RegVal);\r
 983 \r
 984         /*############################################################################################################################ */\r
 985 \r
 986                 /*Register : UART1_REF_CTRL @ 0XFF5E0078</p>\r
 987 \r
 988                 Clock active signal. Switch to 0 to disable the clock\r
 989                 PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1\r
 990 \r
 991                 6 bit divider\r
 992                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x2\r
 993 \r
 994                 6 bit divider\r
 995                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0x28\r
 996 \r
 997                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
 998                 clock. This is not usually an issue, but designers must be aware.)\r
 999                 PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0\r
1000 \r
1001                 This register controls this reference clock\r
1002                 (OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01022800U)  */\r
1003                 RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );\r
1004 \r
1005                 RegVal = Xil_In32 (CRL_APB_UART1_REF_CTRL_OFFSET);\r
1006                 RegVal &= ~(RegMask);\r
1007                 RegVal |= ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT\r
1008                         | 0x00000002U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT\r
1009                         | 0x00000028U << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT\r
1010                         | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT\r
1011                         |  0 ) & RegMask);\r
1012                 Xil_Out32 ( CRL_APB_UART1_REF_CTRL_OFFSET , RegVal);\r
1013 \r
1014         /*############################################################################################################################ */\r
1015 \r
1016                 /*Register : I2C0_REF_CTRL @ 0XFF5E0120</p>\r
1017 \r
1018                 Clock active signal. Switch to 0 to disable the clock\r
1019                 PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1\r
1020 \r
1021                 6 bit divider\r
1022                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x2\r
1023 \r
1024                 6 bit divider\r
1025                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0x28\r
1026 \r
1027                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1028                 clock. This is not usually an issue, but designers must be aware.)\r
1029                 PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0\r
1030 \r
1031                 This register controls this reference clock\r
1032                 (OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01022800U)  */\r
1033                 RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );\r
1034 \r
1035                 RegVal = Xil_In32 (CRL_APB_I2C0_REF_CTRL_OFFSET);\r
1036                 RegVal &= ~(RegMask);\r
1037                 RegVal |= ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT\r
1038                         | 0x00000002U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT\r
1039                         | 0x00000028U << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT\r
1040                         | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT\r
1041                         |  0 ) & RegMask);\r
1042                 Xil_Out32 ( CRL_APB_I2C0_REF_CTRL_OFFSET , RegVal);\r
1043 \r
1044         /*############################################################################################################################ */\r
1045 \r
1046                 /*Register : I2C1_REF_CTRL @ 0XFF5E0124</p>\r
1047 \r
1048                 Clock active signal. Switch to 0 to disable the clock\r
1049                 PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1\r
1050 \r
1051                 6 bit divider\r
1052                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0xa\r
1053 \r
1054                 6 bit divider\r
1055                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0x32\r
1056 \r
1057                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1058                 clock. This is not usually an issue, but designers must be aware.)\r
1059                 PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0\r
1060 \r
1061                 This register controls this reference clock\r
1062                 (OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x010A3200U)  */\r
1063                 RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );\r
1064 \r
1065                 RegVal = Xil_In32 (CRL_APB_I2C1_REF_CTRL_OFFSET);\r
1066                 RegVal &= ~(RegMask);\r
1067                 RegVal |= ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT\r
1068                         | 0x0000000AU << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT\r
1069                         | 0x00000032U << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT\r
1070                         | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT\r
1071                         |  0 ) & RegMask);\r
1072                 Xil_Out32 ( CRL_APB_I2C1_REF_CTRL_OFFSET , RegVal);\r
1073 \r
1074         /*############################################################################################################################ */\r
1075 \r
1076                 /*Register : SPI0_REF_CTRL @ 0XFF5E007C</p>\r
1077 \r
1078                 Clock active signal. Switch to 0 to disable the clock\r
1079                 PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1\r
1080 \r
1081                 6 bit divider\r
1082                 PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x2\r
1083 \r
1084                 6 bit divider\r
1085                 PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x28\r
1086 \r
1087                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1088                 clock. This is not usually an issue, but designers must be aware.)\r
1089                 PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x0\r
1090 \r
1091                 This register controls this reference clock\r
1092                 (OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01022800U)  */\r
1093                 RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );\r
1094 \r
1095                 RegVal = Xil_In32 (CRL_APB_SPI0_REF_CTRL_OFFSET);\r
1096                 RegVal &= ~(RegMask);\r
1097                 RegVal |= ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT\r
1098                         | 0x00000002U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT\r
1099                         | 0x00000028U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT\r
1100                         | 0x00000000U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT\r
1101                         |  0 ) & RegMask);\r
1102                 Xil_Out32 ( CRL_APB_SPI0_REF_CTRL_OFFSET , RegVal);\r
1103 \r
1104         /*############################################################################################################################ */\r
1105 \r
1106                 /*Register : SPI1_REF_CTRL @ 0XFF5E0080</p>\r
1107 \r
1108                 Clock active signal. Switch to 0 to disable the clock\r
1109                 PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1\r
1110 \r
1111                 6 bit divider\r
1112                 PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0xa\r
1113 \r
1114                 6 bit divider\r
1115                 PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x32\r
1116 \r
1117                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1118                 clock. This is not usually an issue, but designers must be aware.)\r
1119                 PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x0\r
1120 \r
1121                 This register controls this reference clock\r
1122                 (OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x010A3200U)  */\r
1123                 RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );\r
1124 \r
1125                 RegVal = Xil_In32 (CRL_APB_SPI1_REF_CTRL_OFFSET);\r
1126                 RegVal &= ~(RegMask);\r
1127                 RegVal |= ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT\r
1128                         | 0x0000000AU << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT\r
1129                         | 0x00000032U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT\r
1130                         | 0x00000000U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT\r
1131                         |  0 ) & RegMask);\r
1132                 Xil_Out32 ( CRL_APB_SPI1_REF_CTRL_OFFSET , RegVal);\r
1133 \r
1134         /*############################################################################################################################ */\r
1135 \r
1136                 /*Register : CAN0_REF_CTRL @ 0XFF5E0084</p>\r
1137 \r
1138                 Clock active signal. Switch to 0 to disable the clock\r
1139                 PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1\r
1140 \r
1141                 6 bit divider\r
1142                 PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x2\r
1143 \r
1144                 6 bit divider\r
1145                 PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0x28\r
1146 \r
1147                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1148                 clock. This is not usually an issue, but designers must be aware.)\r
1149                 PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0\r
1150 \r
1151                 This register controls this reference clock\r
1152                 (OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01022800U)  */\r
1153                 RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );\r
1154 \r
1155                 RegVal = Xil_In32 (CRL_APB_CAN0_REF_CTRL_OFFSET);\r
1156                 RegVal &= ~(RegMask);\r
1157                 RegVal |= ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT\r
1158                         | 0x00000002U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT\r
1159                         | 0x00000028U << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT\r
1160                         | 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT\r
1161                         |  0 ) & RegMask);\r
1162                 Xil_Out32 ( CRL_APB_CAN0_REF_CTRL_OFFSET , RegVal);\r
1163 \r
1164         /*############################################################################################################################ */\r
1165 \r
1166                 /*Register : CAN1_REF_CTRL @ 0XFF5E0088</p>\r
1167 \r
1168                 Clock active signal. Switch to 0 to disable the clock\r
1169                 PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1\r
1170 \r
1171                 6 bit divider\r
1172                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x2\r
1173 \r
1174                 6 bit divider\r
1175                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0x28\r
1176 \r
1177                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1178                 clock. This is not usually an issue, but designers must be aware.)\r
1179                 PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0\r
1180 \r
1181                 This register controls this reference clock\r
1182                 (OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01022800U)  */\r
1183                 RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );\r
1184 \r
1185                 RegVal = Xil_In32 (CRL_APB_CAN1_REF_CTRL_OFFSET);\r
1186                 RegVal &= ~(RegMask);\r
1187                 RegVal |= ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT\r
1188                         | 0x00000002U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT\r
1189                         | 0x00000028U << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT\r
1190                         | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT\r
1191                         |  0 ) & RegMask);\r
1192                 Xil_Out32 ( CRL_APB_CAN1_REF_CTRL_OFFSET , RegVal);\r
1193 \r
1194         /*############################################################################################################################ */\r
1195 \r
1196                 /*Register : CPU_R5_CTRL @ 0XFF5E0090</p>\r
1197 \r
1198                 Clock active signal. Switch to 0 to disable the clock\r
1199                 PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1\r
1200 \r
1201                 6 bit divider\r
1202                 PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x1f4\r
1203 \r
1204                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1205                 clock. This is not usually an issue, but designers must be aware.)\r
1206                 PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2\r
1207 \r
1208                 This register controls this reference clock\r
1209                 (OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01003F02U)  */\r
1210                 RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );\r
1211 \r
1212                 RegVal = Xil_In32 (CRL_APB_CPU_R5_CTRL_OFFSET);\r
1213                 RegVal &= ~(RegMask);\r
1214                 RegVal |= ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT\r
1215                         | 0x000001F4U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT\r
1216                         | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT\r
1217                         |  0 ) & RegMask);\r
1218                 Xil_Out32 ( CRL_APB_CPU_R5_CTRL_OFFSET , RegVal);\r
1219 \r
1220         /*############################################################################################################################ */\r
1221 \r
1222                 /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>\r
1223 \r
1224                 Clock active signal. Switch to 0 to disable the clock\r
1225                 PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1\r
1226 \r
1227                 6 bit divider\r
1228                 PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6\r
1229 \r
1230                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1231                 clock. This is not usually an issue, but designers must be aware.)\r
1232                 PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x0\r
1233 \r
1234                 This register controls this reference clock\r
1235                 (OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000600U)  */\r
1236                 RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );\r
1237 \r
1238                 RegVal = Xil_In32 (CRL_APB_IOU_SWITCH_CTRL_OFFSET);\r
1239                 RegVal &= ~(RegMask);\r
1240                 RegVal |= ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT\r
1241                         | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT\r
1242                         | 0x00000000U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT\r
1243                         |  0 ) & RegMask);\r
1244                 Xil_Out32 ( CRL_APB_IOU_SWITCH_CTRL_OFFSET , RegVal);\r
1245 \r
1246         /*############################################################################################################################ */\r
1247 \r
1248                 /*Register : PCAP_CTRL @ 0XFF5E00A4</p>\r
1249 \r
1250                 Clock active signal. Switch to 0 to disable the clock\r
1251                 PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1\r
1252 \r
1253                 6 bit divider\r
1254                 PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x8\r
1255 \r
1256                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1257                 clock. This is not usually an issue, but designers must be aware.)\r
1258                 PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x0\r
1259 \r
1260                 This register controls this reference clock\r
1261                 (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000800U)  */\r
1262                 RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );\r
1263 \r
1264                 RegVal = Xil_In32 (CRL_APB_PCAP_CTRL_OFFSET);\r
1265                 RegVal &= ~(RegMask);\r
1266                 RegVal |= ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT\r
1267                         | 0x00000008U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT\r
1268                         | 0x00000000U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT\r
1269                         |  0 ) & RegMask);\r
1270                 Xil_Out32 ( CRL_APB_PCAP_CTRL_OFFSET , RegVal);\r
1271 \r
1272         /*############################################################################################################################ */\r
1273 \r
1274                 /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>\r
1275 \r
1276                 Clock active signal. Switch to 0 to disable the clock\r
1277                 PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1\r
1278 \r
1279                 6 bit divider\r
1280                 PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x4\r
1281 \r
1282                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1283                 clock. This is not usually an issue, but designers must be aware.)\r
1284                 PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2\r
1285 \r
1286                 This register controls this reference clock\r
1287                 (OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000402U)  */\r
1288                 RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );\r
1289 \r
1290                 RegVal = Xil_In32 (CRL_APB_LPD_SWITCH_CTRL_OFFSET);\r
1291                 RegVal &= ~(RegMask);\r
1292                 RegVal |= ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT\r
1293                         | 0x00000004U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT\r
1294                         | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT\r
1295                         |  0 ) & RegMask);\r
1296                 Xil_Out32 ( CRL_APB_LPD_SWITCH_CTRL_OFFSET , RegVal);\r
1297 \r
1298         /*############################################################################################################################ */\r
1299 \r
1300                 /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>\r
1301 \r
1302                 Clock active signal. Switch to 0 to disable the clock\r
1303                 PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1\r
1304 \r
1305                 6 bit divider\r
1306                 PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0x14\r
1307 \r
1308                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1309                 clock. This is not usually an issue, but designers must be aware.)\r
1310                 PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2\r
1311 \r
1312                 This register controls this reference clock\r
1313                 (OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01001402U)  */\r
1314                 RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );\r
1315 \r
1316                 RegVal = Xil_In32 (CRL_APB_LPD_LSBUS_CTRL_OFFSET);\r
1317                 RegVal &= ~(RegMask);\r
1318                 RegVal |= ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT\r
1319                         | 0x00000014U << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT\r
1320                         | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT\r
1321                         |  0 ) & RegMask);\r
1322                 Xil_Out32 ( CRL_APB_LPD_LSBUS_CTRL_OFFSET , RegVal);\r
1323 \r
1324         /*############################################################################################################################ */\r
1325 \r
1326                 /*Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>\r
1327 \r
1328                 Clock active signal. Switch to 0 to disable the clock\r
1329                 PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1\r
1330 \r
1331                 6 bit divider\r
1332                 PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x190\r
1333 \r
1334                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1335                 clock. This is not usually an issue, but designers must be aware.)\r
1336                 PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x0\r
1337 \r
1338                 This register controls this reference clock\r
1339                 (OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01003F00U)  */\r
1340                 RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );\r
1341 \r
1342                 RegVal = Xil_In32 (CRL_APB_DBG_LPD_CTRL_OFFSET);\r
1343                 RegVal &= ~(RegMask);\r
1344                 RegVal |= ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT\r
1345                         | 0x00000190U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT\r
1346                         | 0x00000000U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT\r
1347                         |  0 ) & RegMask);\r
1348                 Xil_Out32 ( CRL_APB_DBG_LPD_CTRL_OFFSET , RegVal);\r
1349 \r
1350         /*############################################################################################################################ */\r
1351 \r
1352                 /*Register : NAND_REF_CTRL @ 0XFF5E00B4</p>\r
1353 \r
1354                 Clock active signal. Switch to 0 to disable the clock\r
1355                 PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1\r
1356 \r
1357                 6 bit divider\r
1358                 PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x2\r
1359 \r
1360                 6 bit divider\r
1361                 PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0x32\r
1362 \r
1363                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1364                 clock. This is not usually an issue, but designers must be aware.)\r
1365                 PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0\r
1366 \r
1367                 This register controls this reference clock\r
1368                 (OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01023200U)  */\r
1369                 RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );\r
1370 \r
1371                 RegVal = Xil_In32 (CRL_APB_NAND_REF_CTRL_OFFSET);\r
1372                 RegVal &= ~(RegMask);\r
1373                 RegVal |= ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT\r
1374                         | 0x00000002U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT\r
1375                         | 0x00000032U << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT\r
1376                         | 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT\r
1377                         |  0 ) & RegMask);\r
1378                 Xil_Out32 ( CRL_APB_NAND_REF_CTRL_OFFSET , RegVal);\r
1379 \r
1380         /*############################################################################################################################ */\r
1381 \r
1382                 /*Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>\r
1383 \r
1384                 Clock active signal. Switch to 0 to disable the clock\r
1385                 PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1\r
1386 \r
1387                 6 bit divider\r
1388                 PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x4\r
1389 \r
1390                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1391                 clock. This is not usually an issue, but designers must be aware.)\r
1392                 PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2\r
1393 \r
1394                 This register controls this reference clock\r
1395                 (OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000402U)  */\r
1396                 RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );\r
1397 \r
1398                 RegVal = Xil_In32 (CRL_APB_ADMA_REF_CTRL_OFFSET);\r
1399                 RegVal &= ~(RegMask);\r
1400                 RegVal |= ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT\r
1401                         | 0x00000004U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT\r
1402                         | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT\r
1403                         |  0 ) & RegMask);\r
1404                 Xil_Out32 ( CRL_APB_ADMA_REF_CTRL_OFFSET , RegVal);\r
1405 \r
1406         /*############################################################################################################################ */\r
1407 \r
1408                 /*Register : AMS_REF_CTRL @ 0XFF5E0108</p>\r
1409 \r
1410                 6 bit divider\r
1411                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1\r
1412 \r
1413                 6 bit divider\r
1414                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x28\r
1415 \r
1416                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1417                 clock. This is not usually an issue, but designers must be aware.)\r
1418                 PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x0\r
1419 \r
1420                 Clock active signal. Switch to 0 to disable the clock\r
1421                 PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1\r
1422 \r
1423                 This register controls this reference clock\r
1424                 (OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01012800U)  */\r
1425                 RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );\r
1426 \r
1427                 RegVal = Xil_In32 (CRL_APB_AMS_REF_CTRL_OFFSET);\r
1428                 RegVal &= ~(RegMask);\r
1429                 RegVal |= ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT\r
1430                         | 0x00000028U << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT\r
1431                         | 0x00000000U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT\r
1432                         | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT\r
1433                         |  0 ) & RegMask);\r
1434                 Xil_Out32 ( CRL_APB_AMS_REF_CTRL_OFFSET , RegVal);\r
1435 \r
1436         /*############################################################################################################################ */\r
1437 \r
1438                 /*Register : DLL_REF_CTRL @ 0XFF5E0104</p>\r
1439 \r
1440                 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This\r
1441                 is not usually an issue, but designers must be aware.)\r
1442                 PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0\r
1443 \r
1444                 This register controls this reference clock\r
1445                 (OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  */\r
1446                 RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );\r
1447 \r
1448                 RegVal = Xil_In32 (CRL_APB_DLL_REF_CTRL_OFFSET);\r
1449                 RegVal &= ~(RegMask);\r
1450                 RegVal |= ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT\r
1451                         |  0 ) & RegMask);\r
1452                 Xil_Out32 ( CRL_APB_DLL_REF_CTRL_OFFSET , RegVal);\r
1453 \r
1454         /*############################################################################################################################ */\r
1455 \r
1456                 /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>\r
1457 \r
1458                 6 bit divider\r
1459                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0x14\r
1460 \r
1461                 1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and \r
1462                  cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
1463                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x2\r
1464 \r
1465                 Clock active signal. Switch to 0 to disable the clock\r
1466                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1\r
1467 \r
1468                 This register controls this reference clock\r
1469                 (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01001402U)  */\r
1470                 RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );\r
1471 \r
1472                 RegVal = Xil_In32 (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET);\r
1473                 RegVal &= ~(RegMask);\r
1474                 RegVal |= ((0x00000014U << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT\r
1475                         | 0x00000002U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT\r
1476                         | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT\r
1477                         |  0 ) & RegMask);\r
1478                 Xil_Out32 ( CRL_APB_TIMESTAMP_REF_CTRL_OFFSET , RegVal);\r
1479 \r
1480         /*############################################################################################################################ */\r
1481 \r
1482                 /*Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>\r
1483 \r
1484                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1485                 clock. This is not usually an issue, but designers must be aware.)\r
1486                 PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0\r
1487 \r
1488                 Clock active signal. Switch to 0 to disable the clock\r
1489                 PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1\r
1490 \r
1491                 6 bit divider\r
1492                 PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x7d\r
1493 \r
1494                 This register controls this reference clock\r
1495                 (OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01003F00U)  */\r
1496                 RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );\r
1497 \r
1498                 RegVal = Xil_In32 (CRF_APB_PCIE_REF_CTRL_OFFSET);\r
1499                 RegVal &= ~(RegMask);\r
1500                 RegVal |= ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT\r
1501                         | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT\r
1502                         | 0x0000007DU << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT\r
1503                         |  0 ) & RegMask);\r
1504                 Xil_Out32 ( CRF_APB_PCIE_REF_CTRL_OFFSET , RegVal);\r
1505 \r
1506         /*############################################################################################################################ */\r
1507 \r
1508                 /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>\r
1509 \r
1510                 6 bit divider\r
1511                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x15\r
1512 \r
1513                 6 bit divider\r
1514                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x32\r
1515 \r
1516                 000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo\r
1517                 k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
1518                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x0\r
1519 \r
1520                 Clock active signal. Switch to 0 to disable the clock\r
1521                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1\r
1522 \r
1523                 This register controls this reference clock\r
1524                 (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01153200U)  */\r
1525                 RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );\r
1526 \r
1527                 RegVal = Xil_In32 (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET);\r
1528                 RegVal &= ~(RegMask);\r
1529                 RegVal |= ((0x00000015U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT\r
1530                         | 0x00000032U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT\r
1531                         | 0x00000000U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT\r
1532                         | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT\r
1533                         |  0 ) & RegMask);\r
1534                 Xil_Out32 ( CRF_APB_DP_VIDEO_REF_CTRL_OFFSET , RegVal);\r
1535 \r
1536         /*############################################################################################################################ */\r
1537 \r
1538                 /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>\r
1539 \r
1540                 6 bit divider\r
1541                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x2\r
1542 \r
1543                 6 bit divider\r
1544                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x2a\r
1545 \r
1546                 000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clo\r
1547                 k and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)\r
1548                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0\r
1549 \r
1550                 Clock active signal. Switch to 0 to disable the clock\r
1551                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1\r
1552 \r
1553                 This register controls this reference clock\r
1554                 (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01022A00U)  */\r
1555                 RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );\r
1556 \r
1557                 RegVal = Xil_In32 (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET);\r
1558                 RegVal &= ~(RegMask);\r
1559                 RegVal |= ((0x00000002U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT\r
1560                         | 0x0000002AU << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT\r
1561                         | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT\r
1562                         | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT\r
1563                         |  0 ) & RegMask);\r
1564                 Xil_Out32 ( CRF_APB_DP_AUDIO_REF_CTRL_OFFSET , RegVal);\r
1565 \r
1566         /*############################################################################################################################ */\r
1567 \r
1568                 /*Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>\r
1569 \r
1570                 6 bit divider\r
1571                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x2\r
1572 \r
1573                 6 bit divider\r
1574                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x2a\r
1575 \r
1576                 000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1577                 lock. This is not usually an issue, but designers must be aware.)\r
1578                 PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x0\r
1579 \r
1580                 Clock active signal. Switch to 0 to disable the clock\r
1581                 PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1\r
1582 \r
1583                 This register controls this reference clock\r
1584                 (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01022A00U)  */\r
1585                 RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );\r
1586 \r
1587                 RegVal = Xil_In32 (CRF_APB_DP_STC_REF_CTRL_OFFSET);\r
1588                 RegVal &= ~(RegMask);\r
1589                 RegVal |= ((0x00000002U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT\r
1590                         | 0x0000002AU << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT\r
1591                         | 0x00000000U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT\r
1592                         | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT\r
1593                         |  0 ) & RegMask);\r
1594                 Xil_Out32 ( CRF_APB_DP_STC_REF_CTRL_OFFSET , RegVal);\r
1595 \r
1596         /*############################################################################################################################ */\r
1597 \r
1598                 /*Register : ACPU_CTRL @ 0XFD1A0060</p>\r
1599 \r
1600                 6 bit divider\r
1601                 PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0xfa\r
1602 \r
1603                 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1604                 lock. This is not usually an issue, but designers must be aware.)\r
1605                 PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0\r
1606 \r
1607                 Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock\r
1608                 PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1\r
1609 \r
1610                 Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc\r
1611                  to the entire APU\r
1612                 PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1\r
1613 \r
1614                 This register controls this reference clock\r
1615                 (OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03003F00U)  */\r
1616                 RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );\r
1617 \r
1618                 RegVal = Xil_In32 (CRF_APB_ACPU_CTRL_OFFSET);\r
1619                 RegVal &= ~(RegMask);\r
1620                 RegVal |= ((0x000000FAU << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT\r
1621                         | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT\r
1622                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT\r
1623                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT\r
1624                         |  0 ) & RegMask);\r
1625                 Xil_Out32 ( CRF_APB_ACPU_CTRL_OFFSET , RegVal);\r
1626 \r
1627         /*############################################################################################################################ */\r
1628 \r
1629                 /*Register : DBG_TRACE_CTRL @ 0XFD1A0064</p>\r
1630 \r
1631                 6 bit divider\r
1632                 PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x1f4\r
1633 \r
1634                 000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1635                 clock. This is not usually an issue, but designers must be aware.)\r
1636                 PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x2\r
1637 \r
1638                 Clock active signal. Switch to 0 to disable the clock\r
1639                 PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1\r
1640 \r
1641                 This register controls this reference clock\r
1642                 (OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01003F02U)  */\r
1643                 RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );\r
1644 \r
1645                 RegVal = Xil_In32 (CRF_APB_DBG_TRACE_CTRL_OFFSET);\r
1646                 RegVal &= ~(RegMask);\r
1647                 RegVal |= ((0x000001F4U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT\r
1648                         | 0x00000002U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT\r
1649                         | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT\r
1650                         |  0 ) & RegMask);\r
1651                 Xil_Out32 ( CRF_APB_DBG_TRACE_CTRL_OFFSET , RegVal);\r
1652 \r
1653         /*############################################################################################################################ */\r
1654 \r
1655                 /*Register : DBG_FPD_CTRL @ 0XFD1A0068</p>\r
1656 \r
1657                 6 bit divider\r
1658                 PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x1f4\r
1659 \r
1660                 000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1661                 clock. This is not usually an issue, but designers must be aware.)\r
1662                 PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x2\r
1663 \r
1664                 Clock active signal. Switch to 0 to disable the clock\r
1665                 PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1\r
1666 \r
1667                 This register controls this reference clock\r
1668                 (OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01003F02U)  */\r
1669                 RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );\r
1670 \r
1671                 RegVal = Xil_In32 (CRF_APB_DBG_FPD_CTRL_OFFSET);\r
1672                 RegVal &= ~(RegMask);\r
1673                 RegVal |= ((0x000001F4U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT\r
1674                         | 0x00000002U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT\r
1675                         | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT\r
1676                         |  0 ) & RegMask);\r
1677                 Xil_Out32 ( CRF_APB_DBG_FPD_CTRL_OFFSET , RegVal);\r
1678 \r
1679         /*############################################################################################################################ */\r
1680 \r
1681                 /*Register : DDR_CTRL @ 0XFD1A0080</p>\r
1682 \r
1683                 6 bit divider\r
1684                 PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0xa\r
1685 \r
1686                 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This \r
1687                 s not usually an issue, but designers must be aware.)\r
1688                 PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0\r
1689 \r
1690                 This register controls this reference clock\r
1691                 (OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000A00U)  */\r
1692                 RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );\r
1693 \r
1694                 RegVal = Xil_In32 (CRF_APB_DDR_CTRL_OFFSET);\r
1695                 RegVal &= ~(RegMask);\r
1696                 RegVal |= ((0x0000000AU << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT\r
1697                         | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT\r
1698                         |  0 ) & RegMask);\r
1699                 Xil_Out32 ( CRF_APB_DDR_CTRL_OFFSET , RegVal);\r
1700 \r
1701         /*############################################################################################################################ */\r
1702 \r
1703                 /*Register : GPU_REF_CTRL @ 0XFD1A0084</p>\r
1704 \r
1705                 6 bit divider\r
1706                 PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x20d\r
1707 \r
1708                 000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1709                 clock. This is not usually an issue, but designers must be aware.)\r
1710                 PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x2\r
1711 \r
1712                 Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below\r
1713                 PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1\r
1714 \r
1715                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock\r
1716                 PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1\r
1717 \r
1718                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock\r
1719                 PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1\r
1720 \r
1721                 This register controls this reference clock\r
1722                 (OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07003F02U)  */\r
1723                 RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );\r
1724 \r
1725                 RegVal = Xil_In32 (CRF_APB_GPU_REF_CTRL_OFFSET);\r
1726                 RegVal &= ~(RegMask);\r
1727                 RegVal |= ((0x0000020DU << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT\r
1728                         | 0x00000002U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT\r
1729                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT\r
1730                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT\r
1731                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT\r
1732                         |  0 ) & RegMask);\r
1733                 Xil_Out32 ( CRF_APB_GPU_REF_CTRL_OFFSET , RegVal);\r
1734 \r
1735         /*############################################################################################################################ */\r
1736 \r
1737                 /*Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>\r
1738 \r
1739                 6 bit divider\r
1740                 PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x3\r
1741 \r
1742                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1743                 lock. This is not usually an issue, but designers must be aware.)\r
1744                 PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x3\r
1745 \r
1746                 Clock active signal. Switch to 0 to disable the clock\r
1747                 PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1\r
1748 \r
1749                 This register controls this reference clock\r
1750                 (OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000303U)  */\r
1751                 RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );\r
1752 \r
1753                 RegVal = Xil_In32 (CRF_APB_GDMA_REF_CTRL_OFFSET);\r
1754                 RegVal &= ~(RegMask);\r
1755                 RegVal |= ((0x00000003U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT\r
1756                         | 0x00000003U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT\r
1757                         | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT\r
1758                         |  0 ) & RegMask);\r
1759                 Xil_Out32 ( CRF_APB_GDMA_REF_CTRL_OFFSET , RegVal);\r
1760 \r
1761         /*############################################################################################################################ */\r
1762 \r
1763                 /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>\r
1764 \r
1765                 6 bit divider\r
1766                 PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x3\r
1767 \r
1768                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1769                 lock. This is not usually an issue, but designers must be aware.)\r
1770                 PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x3\r
1771 \r
1772                 Clock active signal. Switch to 0 to disable the clock\r
1773                 PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1\r
1774 \r
1775                 This register controls this reference clock\r
1776                 (OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000303U)  */\r
1777                 RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );\r
1778 \r
1779                 RegVal = Xil_In32 (CRF_APB_DPDMA_REF_CTRL_OFFSET);\r
1780                 RegVal &= ~(RegMask);\r
1781                 RegVal |= ((0x00000003U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT\r
1782                         | 0x00000003U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT\r
1783                         | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT\r
1784                         |  0 ) & RegMask);\r
1785                 Xil_Out32 ( CRF_APB_DPDMA_REF_CTRL_OFFSET , RegVal);\r
1786 \r
1787         /*############################################################################################################################ */\r
1788 \r
1789                 /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>\r
1790 \r
1791                 6 bit divider\r
1792                 PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x3\r
1793 \r
1794                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1795                 lock. This is not usually an issue, but designers must be aware.)\r
1796                 PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x3\r
1797 \r
1798                 Clock active signal. Switch to 0 to disable the clock\r
1799                 PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1\r
1800 \r
1801                 This register controls this reference clock\r
1802                 (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000303U)  */\r
1803                 RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );\r
1804 \r
1805                 RegVal = Xil_In32 (CRF_APB_TOPSW_MAIN_CTRL_OFFSET);\r
1806                 RegVal &= ~(RegMask);\r
1807                 RegVal |= ((0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT\r
1808                         | 0x00000003U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT\r
1809                         | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT\r
1810                         |  0 ) & RegMask);\r
1811                 Xil_Out32 ( CRF_APB_TOPSW_MAIN_CTRL_OFFSET , RegVal);\r
1812 \r
1813         /*############################################################################################################################ */\r
1814 \r
1815                 /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>\r
1816 \r
1817                 6 bit divider\r
1818                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x14\r
1819 \r
1820                 000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1821                 clock. This is not usually an issue, but designers must be aware.)\r
1822                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x0\r
1823 \r
1824                 Clock active signal. Switch to 0 to disable the clock\r
1825                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1\r
1826 \r
1827                 This register controls this reference clock\r
1828                 (OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01001400U)  */\r
1829                 RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );\r
1830 \r
1831                 RegVal = Xil_In32 (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET);\r
1832                 RegVal &= ~(RegMask);\r
1833                 RegVal |= ((0x00000014U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT\r
1834                         | 0x00000000U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT\r
1835                         | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT\r
1836                         |  0 ) & RegMask);\r
1837                 Xil_Out32 ( CRF_APB_TOPSW_LSBUS_CTRL_OFFSET , RegVal);\r
1838 \r
1839         /*############################################################################################################################ */\r
1840 \r
1841                 /*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8</p>\r
1842 \r
1843                 6 bit divider\r
1844                 PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x11\r
1845 \r
1846                 000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new\r
1847                 clock. This is not usually an issue, but designers must be aware.)\r
1848                 PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x2\r
1849 \r
1850                 Clock active signal. Switch to 0 to disable the clock\r
1851                 PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1\r
1852 \r
1853                 This register controls this reference clock\r
1854                 (OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01001102U)  */\r
1855                 RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );\r
1856 \r
1857                 RegVal = Xil_In32 (CRF_APB_GTGREF0_REF_CTRL_OFFSET);\r
1858                 RegVal &= ~(RegMask);\r
1859                 RegVal |= ((0x00000011U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT\r
1860                         | 0x00000002U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT\r
1861                         | 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT\r
1862                         |  0 ) & RegMask);\r
1863                 Xil_Out32 ( CRF_APB_GTGREF0_REF_CTRL_OFFSET , RegVal);\r
1864 \r
1865         /*############################################################################################################################ */\r
1866 \r
1867                 /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>\r
1868 \r
1869                 6 bit divider\r
1870                 PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x8\r
1871 \r
1872                 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new \r
1873                 lock. This is not usually an issue, but designers must be aware.)\r
1874                 PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x2\r
1875 \r
1876                 This register controls this reference clock\r
1877                 (OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000802U)  */\r
1878                 RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );\r
1879 \r
1880                 RegVal = Xil_In32 (CRF_APB_DBG_TSTMP_CTRL_OFFSET);\r
1881                 RegVal &= ~(RegMask);\r
1882                 RegVal |= ((0x00000008U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT\r
1883                         | 0x00000002U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT\r
1884                         |  0 ) & RegMask);\r
1885                 Xil_Out32 ( CRF_APB_DBG_TSTMP_CTRL_OFFSET , RegVal);\r
1886 \r
1887         /*############################################################################################################################ */\r
1888 \r
1889 \r
1890 }\r
1891 unsigned long psu_ddr_init_data_3_0() {\r
1892 \r
1893 }\r
1894 unsigned long psu_mio_init_data() {\r
1895                 // : MIO PROGRAMMING\r
1896                 /*Register : MIO_PIN_0 @ 0XFF180000</p>\r
1897 \r
1898                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)\r
1899                 PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1\r
1900 \r
1901                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
1902                 PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0\r
1903 \r
1904                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp\r
1905                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used\r
1906                 PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0\r
1907 \r
1908                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can\r
1909                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
1910                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc\r
1911                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_\r
1912                 lk- (Trace Port Clock)\r
1913                 PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0\r
1914 \r
1915                 Configures MIO Pin 0 peripheral interface mapping. S\r
1916                 (OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  */\r
1917                 RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );\r
1918 \r
1919                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_0_OFFSET);\r
1920                 RegVal &= ~(RegMask);\r
1921                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT\r
1922                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT\r
1923                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT\r
1924                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT\r
1925                         |  0 ) & RegMask);\r
1926                 Xil_Out32 ( IOU_SLCR_MIO_PIN_0_OFFSET , RegVal);\r
1927 \r
1928         /*############################################################################################################################ */\r
1929 \r
1930                 /*Register : MIO_PIN_1 @ 0XFF180004</p>\r
1931 \r
1932                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data\r
1933                 us)\r
1934                 PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1\r
1935 \r
1936                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
1937                 PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0\r
1938 \r
1939                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp\r
1940                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used\r
1941                 PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0\r
1942 \r
1943                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can\r
1944                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
1945                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o\r
1946                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control\r
1947                 Signal)\r
1948                 PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0\r
1949 \r
1950                 Configures MIO Pin 1 peripheral interface mapping\r
1951                 (OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  */\r
1952                 RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );\r
1953 \r
1954                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_1_OFFSET);\r
1955                 RegVal &= ~(RegMask);\r
1956                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT\r
1957                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT\r
1958                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT\r
1959                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT\r
1960                         |  0 ) & RegMask);\r
1961                 Xil_Out32 ( IOU_SLCR_MIO_PIN_1_OFFSET , RegVal);\r
1962 \r
1963         /*############################################################################################################################ */\r
1964 \r
1965                 /*Register : MIO_PIN_2 @ 0XFF180008</p>\r
1966 \r
1967                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)\r
1968                 PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1\r
1969 \r
1970                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
1971                 PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0\r
1972 \r
1973                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp\r
1974                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used\r
1975                 PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0\r
1976 \r
1977                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can\r
1978                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
1979                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in\r
1980                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)\r
1981                 PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0\r
1982 \r
1983                 Configures MIO Pin 2 peripheral interface mapping\r
1984                 (OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  */\r
1985                 RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );\r
1986 \r
1987                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_2_OFFSET);\r
1988                 RegVal &= ~(RegMask);\r
1989                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT\r
1990                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT\r
1991                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT\r
1992                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT\r
1993                         |  0 ) & RegMask);\r
1994                 Xil_Out32 ( IOU_SLCR_MIO_PIN_2_OFFSET , RegVal);\r
1995 \r
1996         /*############################################################################################################################ */\r
1997 \r
1998                 /*Register : MIO_PIN_3 @ 0XFF18000C</p>\r
1999 \r
2000                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)\r
2001                 PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1\r
2002 \r
2003                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2004                 PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0\r
2005 \r
2006                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp\r
2007                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used\r
2008                 PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0\r
2009 \r
2010                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can\r
2011                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
2012                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0\r
2013                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial\r
2014                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)\r
2015                 PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0\r
2016 \r
2017                 Configures MIO Pin 3 peripheral interface mapping\r
2018                 (OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  */\r
2019                 RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );\r
2020 \r
2021                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_3_OFFSET);\r
2022                 RegVal &= ~(RegMask);\r
2023                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT\r
2024                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT\r
2025                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT\r
2026                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT\r
2027                         |  0 ) & RegMask);\r
2028                 Xil_Out32 ( IOU_SLCR_MIO_PIN_3_OFFSET , RegVal);\r
2029 \r
2030         /*############################################################################################################################ */\r
2031 \r
2032                 /*Register : MIO_PIN_4 @ 0XFF180010</p>\r
2033 \r
2034                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data\r
2035                 us)\r
2036                 PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1\r
2037 \r
2038                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2039                 PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0\r
2040 \r
2041                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp\r
2042                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used\r
2043                 PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0\r
2044 \r
2045                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can\r
2046                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
2047                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s\r
2048                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, \r
2049                 utput, tracedq[2]- (Trace Port Databus)\r
2050                 PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0\r
2051 \r
2052                 Configures MIO Pin 4 peripheral interface mapping\r
2053                 (OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  */\r
2054                 RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );\r
2055 \r
2056                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_4_OFFSET);\r
2057                 RegVal &= ~(RegMask);\r
2058                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT\r
2059                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT\r
2060                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT\r
2061                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT\r
2062                         |  0 ) & RegMask);\r
2063                 Xil_Out32 ( IOU_SLCR_MIO_PIN_4_OFFSET , RegVal);\r
2064 \r
2065         /*############################################################################################################################ */\r
2066 \r
2067                 /*Register : MIO_PIN_5 @ 0XFF180014</p>\r
2068 \r
2069                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)\r
2070                 PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1\r
2071 \r
2072                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2073                 PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0\r
2074 \r
2075                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp\r
2076                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used\r
2077                 PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0\r
2078 \r
2079                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can\r
2080                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
2081                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0\r
2082                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7\r
2083                  trace, Output, tracedq[3]- (Trace Port Databus)\r
2084                 PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0\r
2085 \r
2086                 Configures MIO Pin 5 peripheral interface mapping\r
2087                 (OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  */\r
2088                 RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );\r
2089 \r
2090                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_5_OFFSET);\r
2091                 RegVal &= ~(RegMask);\r
2092                 RegVal |= ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT\r
2093                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT\r
2094                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT\r
2095                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT\r
2096                         |  0 ) & RegMask);\r
2097                 Xil_Out32 ( IOU_SLCR_MIO_PIN_5_OFFSET , RegVal);\r
2098 \r
2099         /*############################################################################################################################ */\r
2100 \r
2101                 /*Register : MIO_PIN_6 @ 0XFF180018</p>\r
2102 \r
2103                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)\r
2104                 PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   0\r
2105 \r
2106                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2107                 PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0\r
2108 \r
2109                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp\r
2110                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used\r
2111                 PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0\r
2112 \r
2113                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can\r
2114                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
2115                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1\r
2116                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,\r
2117                 Output, tracedq[4]- (Trace Port Databus)\r
2118                 PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0\r
2119 \r
2120                 Configures MIO Pin 6 peripheral interface mapping\r
2121                 (OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000000U)  */\r
2122                 RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );\r
2123 \r
2124                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_6_OFFSET);\r
2125                 RegVal &= ~(RegMask);\r
2126                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT\r
2127                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT\r
2128                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT\r
2129                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT\r
2130                         |  0 ) & RegMask);\r
2131                 Xil_Out32 ( IOU_SLCR_MIO_PIN_6_OFFSET , RegVal);\r
2132 \r
2133         /*############################################################################################################################ */\r
2134 \r
2135                 /*Register : MIO_PIN_7 @ 0XFF18001C</p>\r
2136 \r
2137                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)\r
2138                 PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   0\r
2139 \r
2140                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2141                 PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0\r
2142 \r
2143                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp\r
2144                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used\r
2145                 PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0\r
2146 \r
2147                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can\r
2148                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
2149                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= \r
2150                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, \r
2151                 racedq[5]- (Trace Port Databus)\r
2152                 PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0\r
2153 \r
2154                 Configures MIO Pin 7 peripheral interface mapping\r
2155                 (OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000000U)  */\r
2156                 RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );\r
2157 \r
2158                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_7_OFFSET);\r
2159                 RegVal &= ~(RegMask);\r
2160                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT\r
2161                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT\r
2162                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT\r
2163                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT\r
2164                         |  0 ) & RegMask);\r
2165                 Xil_Out32 ( IOU_SLCR_MIO_PIN_7_OFFSET , RegVal);\r
2166 \r
2167         /*############################################################################################################################ */\r
2168 \r
2169                 /*Register : MIO_PIN_8 @ 0XFF180020</p>\r
2170 \r
2171                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe\r
2172                 [0]- (QSPI Upper Databus)\r
2173                 PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   0\r
2174 \r
2175                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
2176                 PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0\r
2177 \r
2178                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp\r
2179                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used\r
2180                 PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0\r
2181 \r
2182                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can\r
2183                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
2184                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc\r
2185                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr\r
2186                 ce Port Databus)\r
2187                 PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0\r
2188 \r
2189                 Configures MIO Pin 8 peripheral interface mapping\r
2190                 (OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000000U)  */\r
2191                 RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );\r
2192 \r
2193                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_8_OFFSET);\r
2194                 RegVal &= ~(RegMask);\r
2195                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT\r
2196                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT\r
2197                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT\r
2198                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT\r
2199                         |  0 ) & RegMask);\r
2200                 Xil_Out32 ( IOU_SLCR_MIO_PIN_8_OFFSET , RegVal);\r
2201 \r
2202         /*############################################################################################################################ */\r
2203 \r
2204                 /*Register : MIO_PIN_9 @ 0XFF180024</p>\r
2205 \r
2206                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe\r
2207                 [1]- (QSPI Upper Databus)\r
2208                 PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   0\r
2209 \r
2210                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)\r
2211                 PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0\r
2212 \r
2213                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp\r
2214                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used\r
2215                 PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0\r
2216 \r
2217                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can\r
2218                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
2219                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, \r
2220                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U\r
2221                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)\r
2222                 PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0\r
2223 \r
2224                 Configures MIO Pin 9 peripheral interface mapping\r
2225                 (OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000000U)  */\r
2226                 RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );\r
2227 \r
2228                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_9_OFFSET);\r
2229                 RegVal &= ~(RegMask);\r
2230                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT\r
2231                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT\r
2232                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT\r
2233                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT\r
2234                         |  0 ) & RegMask);\r
2235                 Xil_Out32 ( IOU_SLCR_MIO_PIN_9_OFFSET , RegVal);\r
2236 \r
2237         /*############################################################################################################################ */\r
2238 \r
2239                 /*Register : MIO_PIN_10 @ 0XFF180028</p>\r
2240 \r
2241                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe\r
2242                 [2]- (QSPI Upper Databus)\r
2243                 PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  0\r
2244 \r
2245                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)\r
2246                 PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  1\r
2247 \r
2248                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out\r
2249                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used\r
2250                 PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0\r
2251 \r
2252                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c\r
2253                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
2254                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_\r
2255                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp\r
2256                 t, tracedq[8]- (Trace Port Databus)\r
2257                 PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0\r
2258 \r
2259                 Configures MIO Pin 10 peripheral interface mapping\r
2260                 (OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000004U)  */\r
2261                 RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );\r
2262 \r
2263                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_10_OFFSET);\r
2264                 RegVal &= ~(RegMask);\r
2265                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT\r
2266                         | 0x00000001U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT\r
2267                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT\r
2268                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT\r
2269                         |  0 ) & RegMask);\r
2270                 Xil_Out32 ( IOU_SLCR_MIO_PIN_10_OFFSET , RegVal);\r
2271 \r
2272         /*############################################################################################################################ */\r
2273 \r
2274                 /*Register : MIO_PIN_11 @ 0XFF18002C</p>\r
2275 \r
2276                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe\r
2277                 [3]- (QSPI Upper Databus)\r
2278                 PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  0\r
2279 \r
2280                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)\r
2281                 PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  1\r
2282 \r
2283                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out\r
2284                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used\r
2285                 PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0\r
2286 \r
2287                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c\r
2288                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
2289                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s\r
2290                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o\r
2291                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)\r
2292                 PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0\r
2293 \r
2294                 Configures MIO Pin 11 peripheral interface mapping\r
2295                 (OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000004U)  */\r
2296                 RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );\r
2297 \r
2298                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_11_OFFSET);\r
2299                 RegVal &= ~(RegMask);\r
2300                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT\r
2301                         | 0x00000001U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT\r
2302                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT\r
2303                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT\r
2304                         |  0 ) & RegMask);\r
2305                 Xil_Out32 ( IOU_SLCR_MIO_PIN_11_OFFSET , RegVal);\r
2306 \r
2307         /*############################################################################################################################ */\r
2308 \r
2309                 /*Register : MIO_PIN_12 @ 0XFF180030</p>\r
2310 \r
2311                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)\r
2312                 PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  0\r
2313 \r
2314                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe\r
2315                 \r
2316                 PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0\r
2317 \r
2318                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out\r
2319                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used\r
2320                 PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0\r
2321 \r
2322                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c\r
2323                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
2324                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl\r
2325                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac\r
2326                 dq[10]- (Trace Port Databus)\r
2327                 PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0\r
2328 \r
2329                 Configures MIO Pin 12 peripheral interface mapping\r
2330                 (OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000000U)  */\r
2331                 RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );\r
2332 \r
2333                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_12_OFFSET);\r
2334                 RegVal &= ~(RegMask);\r
2335                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT\r
2336                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT\r
2337                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT\r
2338                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT\r
2339                         |  0 ) & RegMask);\r
2340                 Xil_Out32 ( IOU_SLCR_MIO_PIN_12_OFFSET , RegVal);\r
2341 \r
2342         /*############################################################################################################################ */\r
2343 \r
2344                 /*Register : MIO_PIN_13 @ 0XFF180034</p>\r
2345 \r
2346                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2347                 PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0\r
2348 \r
2349                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)\r
2350                 PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  1\r
2351 \r
2352                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8\r
2353                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port\r
2354                  3= Not Used\r
2355                 PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0\r
2356 \r
2357                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c\r
2358                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
2359                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave\r
2360                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat\r
2361                 bus)\r
2362                 PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0\r
2363 \r
2364                 Configures MIO Pin 13 peripheral interface mapping\r
2365                 (OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000004U)  */\r
2366                 RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );\r
2367 \r
2368                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_13_OFFSET);\r
2369                 RegVal &= ~(RegMask);\r
2370                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT\r
2371                         | 0x00000001U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT\r
2372                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT\r
2373                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT\r
2374                         |  0 ) & RegMask);\r
2375                 Xil_Out32 ( IOU_SLCR_MIO_PIN_13_OFFSET , RegVal);\r
2376 \r
2377         /*############################################################################################################################ */\r
2378 \r
2379                 /*Register : MIO_PIN_14 @ 0XFF180038</p>\r
2380 \r
2381                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2382                 PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0\r
2383 \r
2384                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)\r
2385                 PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  1\r
2386 \r
2387                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8\r
2388                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port\r
2389                  3= Not Used\r
2390                 PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0\r
2391 \r
2392                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c\r
2393                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
2394                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_\r
2395                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)\r
2396                 PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  0\r
2397 \r
2398                 Configures MIO Pin 14 peripheral interface mapping\r
2399                 (OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000004U)  */\r
2400                 RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );\r
2401 \r
2402                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_14_OFFSET);\r
2403                 RegVal &= ~(RegMask);\r
2404                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT\r
2405                         | 0x00000001U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT\r
2406                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT\r
2407                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT\r
2408                         |  0 ) & RegMask);\r
2409                 Xil_Out32 ( IOU_SLCR_MIO_PIN_14_OFFSET , RegVal);\r
2410 \r
2411         /*############################################################################################################################ */\r
2412 \r
2413                 /*Register : MIO_PIN_15 @ 0XFF18003C</p>\r
2414 \r
2415                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2416                 PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0\r
2417 \r
2418                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)\r
2419                 PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  1\r
2420 \r
2421                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8\r
2422                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port\r
2423                  3= Not Used\r
2424                 PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0\r
2425 \r
2426                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c\r
2427                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
2428                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out\r
2429                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri\r
2430                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)\r
2431                 PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  0\r
2432 \r
2433                 Configures MIO Pin 15 peripheral interface mapping\r
2434                 (OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000004U)  */\r
2435                 RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );\r
2436 \r
2437                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_15_OFFSET);\r
2438                 RegVal &= ~(RegMask);\r
2439                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT\r
2440                         | 0x00000001U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT\r
2441                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT\r
2442                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT\r
2443                         |  0 ) & RegMask);\r
2444                 Xil_Out32 ( IOU_SLCR_MIO_PIN_15_OFFSET , RegVal);\r
2445 \r
2446         /*############################################################################################################################ */\r
2447 \r
2448                 /*Register : MIO_PIN_16 @ 0XFF180040</p>\r
2449 \r
2450                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2451                 PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0\r
2452 \r
2453                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND \r
2454                 ata Bus)\r
2455                 PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  1\r
2456 \r
2457                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8\r
2458                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port\r
2459                  3= Not Used\r
2460                 PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0\r
2461 \r
2462                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c\r
2463                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
2464                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0\r
2465                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace\r
2466                  Output, tracedq[14]- (Trace Port Databus)\r
2467                 PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  0\r
2468 \r
2469                 Configures MIO Pin 16 peripheral interface mapping\r
2470                 (OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000004U)  */\r
2471                 RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );\r
2472 \r
2473                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_16_OFFSET);\r
2474                 RegVal &= ~(RegMask);\r
2475                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT\r
2476                         | 0x00000001U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT\r
2477                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT\r
2478                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT\r
2479                         |  0 ) & RegMask);\r
2480                 Xil_Out32 ( IOU_SLCR_MIO_PIN_16_OFFSET , RegVal);\r
2481 \r
2482         /*############################################################################################################################ */\r
2483 \r
2484                 /*Register : MIO_PIN_17 @ 0XFF180044</p>\r
2485 \r
2486                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2487                 PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0\r
2488 \r
2489                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND \r
2490                 ata Bus)\r
2491                 PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  1\r
2492 \r
2493                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8\r
2494                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port\r
2495                  3= Not Used\r
2496                 PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0\r
2497 \r
2498                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c\r
2499                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
2500                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp\r
2501                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)\r
2502                 7= trace, Output, tracedq[15]- (Trace Port Databus)\r
2503                 PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  0\r
2504 \r
2505                 Configures MIO Pin 17 peripheral interface mapping\r
2506                 (OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000004U)  */\r
2507                 RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );\r
2508 \r
2509                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_17_OFFSET);\r
2510                 RegVal &= ~(RegMask);\r
2511                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT\r
2512                         | 0x00000001U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT\r
2513                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT\r
2514                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT\r
2515                         |  0 ) & RegMask);\r
2516                 Xil_Out32 ( IOU_SLCR_MIO_PIN_17_OFFSET , RegVal);\r
2517 \r
2518         /*############################################################################################################################ */\r
2519 \r
2520                 /*Register : MIO_PIN_18 @ 0XFF180048</p>\r
2521 \r
2522                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2523                 PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0\r
2524 \r
2525                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND \r
2526                 ata Bus)\r
2527                 PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  1\r
2528 \r
2529                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8\r
2530                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port\r
2531                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2532                 PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0\r
2533 \r
2534                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c\r
2535                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
2536                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_\r
2537                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used\r
2538                 PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  0\r
2539 \r
2540                 Configures MIO Pin 18 peripheral interface mapping\r
2541                 (OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x00000004U)  */\r
2542                 RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );\r
2543 \r
2544                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_18_OFFSET);\r
2545                 RegVal &= ~(RegMask);\r
2546                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT\r
2547                         | 0x00000001U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT\r
2548                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT\r
2549                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT\r
2550                         |  0 ) & RegMask);\r
2551                 Xil_Out32 ( IOU_SLCR_MIO_PIN_18_OFFSET , RegVal);\r
2552 \r
2553         /*############################################################################################################################ */\r
2554 \r
2555                 /*Register : MIO_PIN_19 @ 0XFF18004C</p>\r
2556 \r
2557                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2558                 PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0\r
2559 \r
2560                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND \r
2561                 ata Bus)\r
2562                 PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  1\r
2563 \r
2564                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8\r
2565                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port\r
2566                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2567                 PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0\r
2568 \r
2569                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c\r
2570                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
2571                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5\r
2572                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used\r
2573                 PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  0\r
2574 \r
2575                 Configures MIO Pin 19 peripheral interface mapping\r
2576                 (OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x00000004U)  */\r
2577                 RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );\r
2578 \r
2579                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_19_OFFSET);\r
2580                 RegVal &= ~(RegMask);\r
2581                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT\r
2582                         | 0x00000001U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT\r
2583                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT\r
2584                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT\r
2585                         |  0 ) & RegMask);\r
2586                 Xil_Out32 ( IOU_SLCR_MIO_PIN_19_OFFSET , RegVal);\r
2587 \r
2588         /*############################################################################################################################ */\r
2589 \r
2590                 /*Register : MIO_PIN_20 @ 0XFF180050</p>\r
2591 \r
2592                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2593                 PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0\r
2594 \r
2595                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND \r
2596                 ata Bus)\r
2597                 PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  1\r
2598 \r
2599                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8\r
2600                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port\r
2601                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2602                 PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0\r
2603 \r
2604                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c\r
2605                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
2606                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t\r
2607                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used\r
2608                 PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  0\r
2609 \r
2610                 Configures MIO Pin 20 peripheral interface mapping\r
2611                 (OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x00000004U)  */\r
2612                 RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );\r
2613 \r
2614                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_20_OFFSET);\r
2615                 RegVal &= ~(RegMask);\r
2616                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT\r
2617                         | 0x00000001U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT\r
2618                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT\r
2619                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT\r
2620                         |  0 ) & RegMask);\r
2621                 Xil_Out32 ( IOU_SLCR_MIO_PIN_20_OFFSET , RegVal);\r
2622 \r
2623         /*############################################################################################################################ */\r
2624 \r
2625                 /*Register : MIO_PIN_21 @ 0XFF180054</p>\r
2626 \r
2627                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2628                 PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0\r
2629 \r
2630                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND \r
2631                 ata Bus)\r
2632                 PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  1\r
2633 \r
2634                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman\r
2635                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) \r
2636                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2637                 PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0\r
2638 \r
2639                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c\r
2640                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
2641                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1\r
2642                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- \r
2643                 UART receiver serial input) 7= Not Used\r
2644                 PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  0\r
2645 \r
2646                 Configures MIO Pin 21 peripheral interface mapping\r
2647                 (OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x00000004U)  */\r
2648                 RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );\r
2649 \r
2650                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_21_OFFSET);\r
2651                 RegVal &= ~(RegMask);\r
2652                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT\r
2653                         | 0x00000001U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT\r
2654                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT\r
2655                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT\r
2656                         |  0 ) & RegMask);\r
2657                 Xil_Out32 ( IOU_SLCR_MIO_PIN_21_OFFSET , RegVal);\r
2658 \r
2659         /*############################################################################################################################ */\r
2660 \r
2661                 /*Register : MIO_PIN_22 @ 0XFF180058</p>\r
2662 \r
2663                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2664                 PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0\r
2665 \r
2666                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)\r
2667                 PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  1\r
2668 \r
2669                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-\r
2670                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2671                 PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0\r
2672 \r
2673                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c\r
2674                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
2675                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp\r
2676                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not \r
2677                 sed\r
2678                 PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0\r
2679 \r
2680                 Configures MIO Pin 22 peripheral interface mapping\r
2681                 (OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000004U)  */\r
2682                 RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );\r
2683 \r
2684                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_22_OFFSET);\r
2685                 RegVal &= ~(RegMask);\r
2686                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT\r
2687                         | 0x00000001U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT\r
2688                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT\r
2689                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT\r
2690                         |  0 ) & RegMask);\r
2691                 Xil_Out32 ( IOU_SLCR_MIO_PIN_22_OFFSET , RegVal);\r
2692 \r
2693         /*############################################################################################################################ */\r
2694 \r
2695                 /*Register : MIO_PIN_23 @ 0XFF18005C</p>\r
2696 \r
2697                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2698                 PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0\r
2699 \r
2700                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND \r
2701                 ata Bus)\r
2702                 PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  1\r
2703 \r
2704                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in\r
2705                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper\r
2706                 \r
2707                 PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0\r
2708 \r
2709                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c\r
2710                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
2711                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s\r
2712                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o\r
2713                 tput) 7= Not Used\r
2714                 PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0\r
2715 \r
2716                 Configures MIO Pin 23 peripheral interface mapping\r
2717                 (OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000004U)  */\r
2718                 RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );\r
2719 \r
2720                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_23_OFFSET);\r
2721                 RegVal &= ~(RegMask);\r
2722                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT\r
2723                         | 0x00000001U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT\r
2724                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT\r
2725                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT\r
2726                         |  0 ) & RegMask);\r
2727                 Xil_Out32 ( IOU_SLCR_MIO_PIN_23_OFFSET , RegVal);\r
2728 \r
2729         /*############################################################################################################################ */\r
2730 \r
2731                 /*Register : MIO_PIN_24 @ 0XFF180060</p>\r
2732 \r
2733                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2734                 PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0\r
2735 \r
2736                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND \r
2737                 ata Bus)\r
2738                 PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  1\r
2739 \r
2740                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test\r
2741                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex\r
2742                  Tamper)\r
2743                 PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0\r
2744 \r
2745                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c\r
2746                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
2747                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,\r
2748                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used\r
2749                 PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  0\r
2750 \r
2751                 Configures MIO Pin 24 peripheral interface mapping\r
2752                 (OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000004U)  */\r
2753                 RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );\r
2754 \r
2755                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_24_OFFSET);\r
2756                 RegVal &= ~(RegMask);\r
2757                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT\r
2758                         | 0x00000001U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT\r
2759                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT\r
2760                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT\r
2761                         |  0 ) & RegMask);\r
2762                 Xil_Out32 ( IOU_SLCR_MIO_PIN_24_OFFSET , RegVal);\r
2763 \r
2764         /*############################################################################################################################ */\r
2765 \r
2766                 /*Register : MIO_PIN_25 @ 0XFF180064</p>\r
2767 \r
2768                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
2769                 PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0\r
2770 \r
2771                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)\r
2772                 PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  1\r
2773 \r
2774                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,\r
2775                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C\r
2776                 U Ext Tamper)\r
2777                 PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0\r
2778 \r
2779                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c\r
2780                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
2781                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform \r
2782                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used\r
2783                 PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  0\r
2784 \r
2785                 Configures MIO Pin 25 peripheral interface mapping\r
2786                 (OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000004U)  */\r
2787                 RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );\r
2788 \r
2789                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_25_OFFSET);\r
2790                 RegVal &= ~(RegMask);\r
2791                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT\r
2792                         | 0x00000001U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT\r
2793                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT\r
2794                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT\r
2795                         |  0 ) & RegMask);\r
2796                 Xil_Out32 ( IOU_SLCR_MIO_PIN_25_OFFSET , RegVal);\r
2797 \r
2798         /*############################################################################################################################ */\r
2799 \r
2800                 /*Register : MIO_PIN_26 @ 0XFF180068</p>\r
2801 \r
2802                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)\r
2803                 PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0\r
2804 \r
2805                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)\r
2806                 PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  1\r
2807 \r
2808                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc\r
2809                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2810                 PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  0\r
2811 \r
2812                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can\r
2813                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
2814                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock\r
2815                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- \r
2816                 Trace Port Databus)\r
2817                 PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0\r
2818 \r
2819                 Configures MIO Pin 26 peripheral interface mapping\r
2820                 (OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000004U)  */\r
2821                 RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );\r
2822 \r
2823                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_26_OFFSET);\r
2824                 RegVal &= ~(RegMask);\r
2825                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT\r
2826                         | 0x00000001U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT\r
2827                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT\r
2828                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT\r
2829                         |  0 ) & RegMask);\r
2830                 Xil_Out32 ( IOU_SLCR_MIO_PIN_26_OFFSET , RegVal);\r
2831 \r
2832         /*############################################################################################################################ */\r
2833 \r
2834                 /*Register : MIO_PIN_27 @ 0XFF18006C</p>\r
2835 \r
2836                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)\r
2837                 PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0\r
2838 \r
2839                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)\r
2840                 PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0\r
2841 \r
2842                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc\r
2843                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp\r
2844                 t, dp_aux_data_out- (Dp Aux Data)\r
2845                 PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0\r
2846 \r
2847                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can\r
2848                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
2849                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_\r
2850                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port \r
2851                 atabus)\r
2852                 PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0\r
2853 \r
2854                 Configures MIO Pin 27 peripheral interface mapping\r
2855                 (OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  */\r
2856                 RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );\r
2857 \r
2858                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_27_OFFSET);\r
2859                 RegVal &= ~(RegMask);\r
2860                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT\r
2861                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT\r
2862                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT\r
2863                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT\r
2864                         |  0 ) & RegMask);\r
2865                 Xil_Out32 ( IOU_SLCR_MIO_PIN_27_OFFSET , RegVal);\r
2866 \r
2867         /*############################################################################################################################ */\r
2868 \r
2869                 /*Register : MIO_PIN_28 @ 0XFF180070</p>\r
2870 \r
2871                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)\r
2872                 PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0\r
2873 \r
2874                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)\r
2875                 PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0\r
2876 \r
2877                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc\r
2878                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)\r
2879                 PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0\r
2880 \r
2881                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can\r
2882                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
2883                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i\r
2884                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)\r
2885                 PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0\r
2886 \r
2887                 Configures MIO Pin 28 peripheral interface mapping\r
2888                 (OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  */\r
2889                 RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );\r
2890 \r
2891                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_28_OFFSET);\r
2892                 RegVal &= ~(RegMask);\r
2893                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT\r
2894                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT\r
2895                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT\r
2896                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT\r
2897                         |  0 ) & RegMask);\r
2898                 Xil_Out32 ( IOU_SLCR_MIO_PIN_28_OFFSET , RegVal);\r
2899 \r
2900         /*############################################################################################################################ */\r
2901 \r
2902                 /*Register : MIO_PIN_29 @ 0XFF180074</p>\r
2903 \r
2904                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)\r
2905                 PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0\r
2906 \r
2907                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
2908                 PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0\r
2909 \r
2910                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc\r
2911                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp\r
2912                 t, dp_aux_data_out- (Dp Aux Data)\r
2913                 PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0\r
2914 \r
2915                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can\r
2916                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
2917                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]\r
2918                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu\r
2919                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)\r
2920                 PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  4\r
2921 \r
2922                 Configures MIO Pin 29 peripheral interface mapping\r
2923                 (OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000080U)  */\r
2924                 RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );\r
2925 \r
2926                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_29_OFFSET);\r
2927                 RegVal &= ~(RegMask);\r
2928                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT\r
2929                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT\r
2930                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT\r
2931                         | 0x00000004U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT\r
2932                         |  0 ) & RegMask);\r
2933                 Xil_Out32 ( IOU_SLCR_MIO_PIN_29_OFFSET , RegVal);\r
2934 \r
2935         /*############################################################################################################################ */\r
2936 \r
2937                 /*Register : MIO_PIN_30 @ 0XFF180078</p>\r
2938 \r
2939                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)\r
2940                 PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0\r
2941 \r
2942                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
2943                 PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0\r
2944 \r
2945                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc\r
2946                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)\r
2947                 PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0\r
2948 \r
2949                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can\r
2950                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
2951                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so\r
2952                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output\r
2953                  tracedq[8]- (Trace Port Databus)\r
2954                 PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0\r
2955 \r
2956                 Configures MIO Pin 30 peripheral interface mapping\r
2957                 (OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  */\r
2958                 RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );\r
2959 \r
2960                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_30_OFFSET);\r
2961                 RegVal &= ~(RegMask);\r
2962                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT\r
2963                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT\r
2964                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT\r
2965                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT\r
2966                         |  0 ) & RegMask);\r
2967                 Xil_Out32 ( IOU_SLCR_MIO_PIN_30_OFFSET , RegVal);\r
2968 \r
2969         /*############################################################################################################################ */\r
2970 \r
2971                 /*Register : MIO_PIN_31 @ 0XFF18007C</p>\r
2972 \r
2973                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)\r
2974                 PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0\r
2975 \r
2976                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
2977                 PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0\r
2978 \r
2979                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc\r
2980                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
2981                 PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0\r
2982 \r
2983                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can\r
2984                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
2985                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi\r
2986                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out\r
2987                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)\r
2988                 PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0\r
2989 \r
2990                 Configures MIO Pin 31 peripheral interface mapping\r
2991                 (OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  */\r
2992                 RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );\r
2993 \r
2994                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_31_OFFSET);\r
2995                 RegVal &= ~(RegMask);\r
2996                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT\r
2997                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT\r
2998                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT\r
2999                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT\r
3000                         |  0 ) & RegMask);\r
3001                 Xil_Out32 ( IOU_SLCR_MIO_PIN_31_OFFSET , RegVal);\r
3002 \r
3003         /*############################################################################################################################ */\r
3004 \r
3005                 /*Register : MIO_PIN_32 @ 0XFF180080</p>\r
3006 \r
3007                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)\r
3008                 PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0\r
3009 \r
3010                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe\r
3011                 \r
3012                 PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  1\r
3013 \r
3014                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Sc\r
3015                 n Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
3016                 PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  0\r
3017 \r
3018                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can\r
3019                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
3020                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi\r
3021                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= \r
3022                 race, Output, tracedq[10]- (Trace Port Databus)\r
3023                 PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0\r
3024 \r
3025                 Configures MIO Pin 32 peripheral interface mapping\r
3026                 (OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000004U)  */\r
3027                 RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );\r
3028 \r
3029                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_32_OFFSET);\r
3030                 RegVal &= ~(RegMask);\r
3031                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT\r
3032                         | 0x00000001U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT\r
3033                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT\r
3034                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT\r
3035                         |  0 ) & RegMask);\r
3036                 Xil_Out32 ( IOU_SLCR_MIO_PIN_32_OFFSET , RegVal);\r
3037 \r
3038         /*############################################################################################################################ */\r
3039 \r
3040                 /*Register : MIO_PIN_33 @ 0XFF180084</p>\r
3041 \r
3042                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)\r
3043                 PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0\r
3044 \r
3045                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
3046                 PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0\r
3047 \r
3048                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Sc\r
3049                 n Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)\r
3050                 PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  0\r
3051 \r
3052                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can\r
3053                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
3054                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t\r
3055                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced\r
3056                 [11]- (Trace Port Databus)\r
3057                 PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0\r
3058 \r
3059                 Configures MIO Pin 33 peripheral interface mapping\r
3060                 (OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000000U)  */\r
3061                 RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );\r
3062 \r
3063                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_33_OFFSET);\r
3064                 RegVal &= ~(RegMask);\r
3065                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT\r
3066                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT\r
3067                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT\r
3068                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT\r
3069                         |  0 ) & RegMask);\r
3070                 Xil_Out32 ( IOU_SLCR_MIO_PIN_33_OFFSET , RegVal);\r
3071 \r
3072         /*############################################################################################################################ */\r
3073 \r
3074                 /*Register : MIO_PIN_34 @ 0XFF180088</p>\r
3075 \r
3076                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)\r
3077                 PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0\r
3078 \r
3079                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
3080                 PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0\r
3081 \r
3082                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Sc\r
3083                 n Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp\r
3084                 t, dp_aux_data_out- (Dp Aux Data)\r
3085                 PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  0\r
3086 \r
3087                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can\r
3088                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
3089                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2\r
3090                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P\r
3091                 rt Databus)\r
3092                 PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0\r
3093 \r
3094                 Configures MIO Pin 34 peripheral interface mapping\r
3095                 (OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000000U)  */\r
3096                 RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );\r
3097 \r
3098                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_34_OFFSET);\r
3099                 RegVal &= ~(RegMask);\r
3100                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT\r
3101                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT\r
3102                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT\r
3103                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT\r
3104                         |  0 ) & RegMask);\r
3105                 Xil_Out32 ( IOU_SLCR_MIO_PIN_34_OFFSET , RegVal);\r
3106 \r
3107         /*############################################################################################################################ */\r
3108 \r
3109                 /*Register : MIO_PIN_35 @ 0XFF18008C</p>\r
3110 \r
3111                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)\r
3112                 PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0\r
3113 \r
3114                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
3115                 PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0\r
3116 \r
3117                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Sc\r
3118                 n Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)\r
3119                 PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  0\r
3120 \r
3121                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can\r
3122                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
3123                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,\r
3124                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- \r
3125                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)\r
3126                 PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  4\r
3127 \r
3128                 Configures MIO Pin 35 peripheral interface mapping\r
3129                 (OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000080U)  */\r
3130                 RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );\r
3131 \r
3132                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_35_OFFSET);\r
3133                 RegVal &= ~(RegMask);\r
3134                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT\r
3135                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT\r
3136                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT\r
3137                         | 0x00000004U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT\r
3138                         |  0 ) & RegMask);\r
3139                 Xil_Out32 ( IOU_SLCR_MIO_PIN_35_OFFSET , RegVal);\r
3140 \r
3141         /*############################################################################################################################ */\r
3142 \r
3143                 /*Register : MIO_PIN_36 @ 0XFF180090</p>\r
3144 \r
3145                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)\r
3146                 PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0\r
3147 \r
3148                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
3149                 PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0\r
3150 \r
3151                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Sc\r
3152                 n Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp\r
3153                 t, dp_aux_data_out- (Dp Aux Data)\r
3154                 PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  0\r
3155 \r
3156                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c\r
3157                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
3158                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1\r
3159                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace\r
3160                  Output, tracedq[14]- (Trace Port Databus)\r
3161                 PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0\r
3162 \r
3163                 Configures MIO Pin 36 peripheral interface mapping\r
3164                 (OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000000U)  */\r
3165                 RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );\r
3166 \r
3167                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_36_OFFSET);\r
3168                 RegVal &= ~(RegMask);\r
3169                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT\r
3170                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT\r
3171                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT\r
3172                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT\r
3173                         |  0 ) & RegMask);\r
3174                 Xil_Out32 ( IOU_SLCR_MIO_PIN_36_OFFSET , RegVal);\r
3175 \r
3176         /*############################################################################################################################ */\r
3177 \r
3178                 /*Register : MIO_PIN_37 @ 0XFF180094</p>\r
3179 \r
3180                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )\r
3181                 PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0\r
3182 \r
3183                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)\r
3184                 PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0\r
3185 \r
3186                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Sc\r
3187                 n Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)\r
3188                 PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  0\r
3189 \r
3190                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c\r
3191                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
3192                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp\r
3193                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)\r
3194                 7= trace, Output, tracedq[15]- (Trace Port Databus)\r
3195                 PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0\r
3196 \r
3197                 Configures MIO Pin 37 peripheral interface mapping\r
3198                 (OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000000U)  */\r
3199                 RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );\r
3200 \r
3201                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_37_OFFSET);\r
3202                 RegVal &= ~(RegMask);\r
3203                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT\r
3204                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT\r
3205                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT\r
3206                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT\r
3207                         |  0 ) & RegMask);\r
3208                 Xil_Out32 ( IOU_SLCR_MIO_PIN_37_OFFSET , RegVal);\r
3209 \r
3210         /*############################################################################################################################ */\r
3211 \r
3212                 /*Register : MIO_PIN_38 @ 0XFF180098</p>\r
3213 \r
3214                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)\r
3215                 PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0\r
3216 \r
3217                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3218                 PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0\r
3219 \r
3220                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used\r
3221                 PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0\r
3222 \r
3223                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c\r
3224                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
3225                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo\r
3226                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-\r
3227                 (Trace Port Clock)\r
3228                 PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0\r
3229 \r
3230                 Configures MIO Pin 38 peripheral interface mapping\r
3231                 (OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  */\r
3232                 RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );\r
3233 \r
3234                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_38_OFFSET);\r
3235                 RegVal &= ~(RegMask);\r
3236                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT\r
3237                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT\r
3238                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT\r
3239                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT\r
3240                         |  0 ) & RegMask);\r
3241                 Xil_Out32 ( IOU_SLCR_MIO_PIN_38_OFFSET , RegVal);\r
3242 \r
3243         /*############################################################################################################################ */\r
3244 \r
3245                 /*Register : MIO_PIN_39 @ 0XFF18009C</p>\r
3246 \r
3247                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)\r
3248                 PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0\r
3249 \r
3250                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3251                 PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0\r
3252 \r
3253                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i\r
3254                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used\r
3255                 PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  2\r
3256 \r
3257                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c\r
3258                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
3259                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav\r
3260                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port\r
3261                 Control Signal)\r
3262                 PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0\r
3263 \r
3264                 Configures MIO Pin 39 peripheral interface mapping\r
3265                 (OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000010U)  */\r
3266                 RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );\r
3267 \r
3268                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_39_OFFSET);\r
3269                 RegVal &= ~(RegMask);\r
3270                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT\r
3271                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT\r
3272                         | 0x00000002U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT\r
3273                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT\r
3274                         |  0 ) & RegMask);\r
3275                 Xil_Out32 ( IOU_SLCR_MIO_PIN_39_OFFSET , RegVal);\r
3276 \r
3277         /*############################################################################################################################ */\r
3278 \r
3279                 /*Register : MIO_PIN_40 @ 0XFF1800A0</p>\r
3280 \r
3281                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)\r
3282                 PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0\r
3283 \r
3284                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3285                 PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0\r
3286 \r
3287                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman\r
3288                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used\r
3289                 PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  2\r
3290 \r
3291                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c\r
3292                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
3293                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk\r
3294                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)\r
3295                 PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0\r
3296 \r
3297                 Configures MIO Pin 40 peripheral interface mapping\r
3298                 (OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000010U)  */\r
3299                 RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );\r
3300 \r
3301                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_40_OFFSET);\r
3302                 RegVal &= ~(RegMask);\r
3303                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT\r
3304                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT\r
3305                         | 0x00000002U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT\r
3306                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT\r
3307                         |  0 ) & RegMask);\r
3308                 Xil_Out32 ( IOU_SLCR_MIO_PIN_40_OFFSET , RegVal);\r
3309 \r
3310         /*############################################################################################################################ */\r
3311 \r
3312                 /*Register : MIO_PIN_41 @ 0XFF1800A4</p>\r
3313 \r
3314                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)\r
3315                 PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0\r
3316 \r
3317                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3318                 PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0\r
3319 \r
3320                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8\r
3321                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used\r
3322                 PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  2\r
3323 \r
3324                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c\r
3325                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
3326                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[\r
3327                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in\r
3328                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)\r
3329                 PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0\r
3330 \r
3331                 Configures MIO Pin 41 peripheral interface mapping\r
3332                 (OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000010U)  */\r
3333                 RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );\r
3334 \r
3335                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_41_OFFSET);\r
3336                 RegVal &= ~(RegMask);\r
3337                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT\r
3338                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT\r
3339                         | 0x00000002U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT\r
3340                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT\r
3341                         |  0 ) & RegMask);\r
3342                 Xil_Out32 ( IOU_SLCR_MIO_PIN_41_OFFSET , RegVal);\r
3343 \r
3344         /*############################################################################################################################ */\r
3345 \r
3346                 /*Register : MIO_PIN_42 @ 0XFF1800A8</p>\r
3347 \r
3348                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)\r
3349                 PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0\r
3350 \r
3351                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3352                 PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0\r
3353 \r
3354                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8\r
3355                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used\r
3356                 PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  2\r
3357 \r
3358                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c\r
3359                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
3360                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_\r
3361                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp\r
3362                 t, tracedq[2]- (Trace Port Databus)\r
3363                 PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0\r
3364 \r
3365                 Configures MIO Pin 42 peripheral interface mapping\r
3366                 (OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000010U)  */\r
3367                 RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );\r
3368 \r
3369                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_42_OFFSET);\r
3370                 RegVal &= ~(RegMask);\r
3371                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT\r
3372                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT\r
3373                         | 0x00000002U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT\r
3374                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT\r
3375                         |  0 ) & RegMask);\r
3376                 Xil_Out32 ( IOU_SLCR_MIO_PIN_42_OFFSET , RegVal);\r
3377 \r
3378         /*############################################################################################################################ */\r
3379 \r
3380                 /*Register : MIO_PIN_43 @ 0XFF1800AC</p>\r
3381 \r
3382                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)\r
3383                 PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0\r
3384 \r
3385                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3386                 PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0\r
3387 \r
3388                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8\r
3389                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used\r
3390                 PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2\r
3391 \r
3392                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c\r
3393                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
3394                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s\r
3395                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o\r
3396                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)\r
3397                 PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0\r
3398 \r
3399                 Configures MIO Pin 43 peripheral interface mapping\r
3400                 (OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  */\r
3401                 RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );\r
3402 \r
3403                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_43_OFFSET);\r
3404                 RegVal &= ~(RegMask);\r
3405                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT\r
3406                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT\r
3407                         | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT\r
3408                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT\r
3409                         |  0 ) & RegMask);\r
3410                 Xil_Out32 ( IOU_SLCR_MIO_PIN_43_OFFSET , RegVal);\r
3411 \r
3412         /*############################################################################################################################ */\r
3413 \r
3414                 /*Register : MIO_PIN_44 @ 0XFF1800B0</p>\r
3415 \r
3416                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)\r
3417                 PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0\r
3418 \r
3419                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3420                 PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0\r
3421 \r
3422                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8\r
3423                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used\r
3424                 PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  0\r
3425 \r
3426                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c\r
3427                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
3428                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s\r
3429                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7\r
3430                  Not Used\r
3431                 PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0\r
3432 \r
3433                 Configures MIO Pin 44 peripheral interface mapping\r
3434                 (OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000000U)  */\r
3435                 RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );\r
3436 \r
3437                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_44_OFFSET);\r
3438                 RegVal &= ~(RegMask);\r
3439                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT\r
3440                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT\r
3441                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT\r
3442                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT\r
3443                         |  0 ) & RegMask);\r
3444                 Xil_Out32 ( IOU_SLCR_MIO_PIN_44_OFFSET , RegVal);\r
3445 \r
3446         /*############################################################################################################################ */\r
3447 \r
3448                 /*Register : MIO_PIN_45 @ 0XFF1800B4</p>\r
3449 \r
3450                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)\r
3451                 PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0\r
3452 \r
3453                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3454                 PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0\r
3455 \r
3456                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8\r
3457                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used\r
3458                 PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  0\r
3459 \r
3460                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c\r
3461                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
3462                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=\r
3463                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used\r
3464                 PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0\r
3465 \r
3466                 Configures MIO Pin 45 peripheral interface mapping\r
3467                 (OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000000U)  */\r
3468                 RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );\r
3469 \r
3470                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_45_OFFSET);\r
3471                 RegVal &= ~(RegMask);\r
3472                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT\r
3473                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT\r
3474                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT\r
3475                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT\r
3476                         |  0 ) & RegMask);\r
3477                 Xil_Out32 ( IOU_SLCR_MIO_PIN_45_OFFSET , RegVal);\r
3478 \r
3479         /*############################################################################################################################ */\r
3480 \r
3481                 /*Register : MIO_PIN_46 @ 0XFF1800B8</p>\r
3482 \r
3483                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)\r
3484                 PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0\r
3485 \r
3486                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3487                 PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0\r
3488 \r
3489                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8\r
3490                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used\r
3491                 PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2\r
3492 \r
3493                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c\r
3494                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
3495                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt\r
3496                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used\r
3497                 PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0\r
3498 \r
3499                 Configures MIO Pin 46 peripheral interface mapping\r
3500                 (OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  */\r
3501                 RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );\r
3502 \r
3503                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_46_OFFSET);\r
3504                 RegVal &= ~(RegMask);\r
3505                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT\r
3506                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT\r
3507                         | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT\r
3508                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT\r
3509                         |  0 ) & RegMask);\r
3510                 Xil_Out32 ( IOU_SLCR_MIO_PIN_46_OFFSET , RegVal);\r
3511 \r
3512         /*############################################################################################################################ */\r
3513 \r
3514                 /*Register : MIO_PIN_47 @ 0XFF1800BC</p>\r
3515 \r
3516                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)\r
3517                 PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0\r
3518 \r
3519                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3520                 PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0\r
3521 \r
3522                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8\r
3523                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used\r
3524                 PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2\r
3525 \r
3526                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c\r
3527                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
3528                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi\r
3529                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd\r
3530                  (UART transmitter serial output) 7= Not Used\r
3531                 PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0\r
3532 \r
3533                 Configures MIO Pin 47 peripheral interface mapping\r
3534                 (OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  */\r
3535                 RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );\r
3536 \r
3537                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_47_OFFSET);\r
3538                 RegVal &= ~(RegMask);\r
3539                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT\r
3540                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT\r
3541                         | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT\r
3542                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT\r
3543                         |  0 ) & RegMask);\r
3544                 Xil_Out32 ( IOU_SLCR_MIO_PIN_47_OFFSET , RegVal);\r
3545 \r
3546         /*############################################################################################################################ */\r
3547 \r
3548                 /*Register : MIO_PIN_48 @ 0XFF1800C0</p>\r
3549 \r
3550                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)\r
3551                 PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0\r
3552 \r
3553                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3554                 PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0\r
3555 \r
3556                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8\r
3557                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used\r
3558                 PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2\r
3559 \r
3560                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c\r
3561                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
3562                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1\r
3563                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U\r
3564                 ed\r
3565                 PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0\r
3566 \r
3567                 Configures MIO Pin 48 peripheral interface mapping\r
3568                 (OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  */\r
3569                 RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );\r
3570 \r
3571                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_48_OFFSET);\r
3572                 RegVal &= ~(RegMask);\r
3573                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT\r
3574                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT\r
3575                         | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT\r
3576                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT\r
3577                         |  0 ) & RegMask);\r
3578                 Xil_Out32 ( IOU_SLCR_MIO_PIN_48_OFFSET , RegVal);\r
3579 \r
3580         /*############################################################################################################################ */\r
3581 \r
3582                 /*Register : MIO_PIN_49 @ 0XFF1800C4</p>\r
3583 \r
3584                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )\r
3585                 PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0\r
3586 \r
3587                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3588                 PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0\r
3589 \r
3590                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8\r
3591                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used\r
3592                 PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2\r
3593 \r
3594                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c\r
3595                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
3596                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp\r
3597                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)\r
3598                 7= Not Used\r
3599                 PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0\r
3600 \r
3601                 Configures MIO Pin 49 peripheral interface mapping\r
3602                 (OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  */\r
3603                 RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );\r
3604 \r
3605                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_49_OFFSET);\r
3606                 RegVal &= ~(RegMask);\r
3607                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT\r
3608                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT\r
3609                         | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT\r
3610                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT\r
3611                         |  0 ) & RegMask);\r
3612                 Xil_Out32 ( IOU_SLCR_MIO_PIN_49_OFFSET , RegVal);\r
3613 \r
3614         /*############################################################################################################################ */\r
3615 \r
3616                 /*Register : MIO_PIN_50 @ 0XFF1800C8</p>\r
3617 \r
3618                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)\r
3619                 PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0\r
3620 \r
3621                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3622                 PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0\r
3623 \r
3624                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c\r
3625                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used\r
3626                 PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2\r
3627 \r
3628                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c\r
3629                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
3630                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2\r
3631                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used\r
3632                 PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0\r
3633 \r
3634                 Configures MIO Pin 50 peripheral interface mapping\r
3635                 (OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  */\r
3636                 RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );\r
3637 \r
3638                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_50_OFFSET);\r
3639                 RegVal &= ~(RegMask);\r
3640                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT\r
3641                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT\r
3642                         | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT\r
3643                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT\r
3644                         |  0 ) & RegMask);\r
3645                 Xil_Out32 ( IOU_SLCR_MIO_PIN_50_OFFSET , RegVal);\r
3646 \r
3647         /*############################################################################################################################ */\r
3648 \r
3649                 /*Register : MIO_PIN_51 @ 0XFF1800CC</p>\r
3650 \r
3651                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)\r
3652                 PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0\r
3653 \r
3654                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
3655                 PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0\r
3656 \r
3657                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used\r
3658                 PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2\r
3659 \r
3660                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c\r
3661                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
3662                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp\r
3663                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter\r
3664                 serial output) 7= Not Used\r
3665                 PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0\r
3666 \r
3667                 Configures MIO Pin 51 peripheral interface mapping\r
3668                 (OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  */\r
3669                 RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );\r
3670 \r
3671                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_51_OFFSET);\r
3672                 RegVal &= ~(RegMask);\r
3673                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT\r
3674                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT\r
3675                         | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT\r
3676                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT\r
3677                         |  0 ) & RegMask);\r
3678                 Xil_Out32 ( IOU_SLCR_MIO_PIN_51_OFFSET , RegVal);\r
3679 \r
3680         /*############################################################################################################################ */\r
3681 \r
3682                 /*Register : MIO_PIN_52 @ 0XFF1800D0</p>\r
3683 \r
3684                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)\r
3685                 PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0\r
3686 \r
3687                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)\r
3688                 PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1\r
3689 \r
3690                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3691                 PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0\r
3692 \r
3693                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can\r
3694                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
3695                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc\r
3696                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_\r
3697                 lk- (Trace Port Clock)\r
3698                 PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0\r
3699 \r
3700                 Configures MIO Pin 52 peripheral interface mapping\r
3701                 (OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  */\r
3702                 RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );\r
3703 \r
3704                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_52_OFFSET);\r
3705                 RegVal &= ~(RegMask);\r
3706                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT\r
3707                         | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT\r
3708                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT\r
3709                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT\r
3710                         |  0 ) & RegMask);\r
3711                 Xil_Out32 ( IOU_SLCR_MIO_PIN_52_OFFSET , RegVal);\r
3712 \r
3713         /*############################################################################################################################ */\r
3714 \r
3715                 /*Register : MIO_PIN_53 @ 0XFF1800D4</p>\r
3716 \r
3717                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)\r
3718                 PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0\r
3719 \r
3720                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)\r
3721                 PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1\r
3722 \r
3723                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3724                 PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0\r
3725 \r
3726                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can\r
3727                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
3728                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o\r
3729                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control\r
3730                 Signal)\r
3731                 PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0\r
3732 \r
3733                 Configures MIO Pin 53 peripheral interface mapping\r
3734                 (OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  */\r
3735                 RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );\r
3736 \r
3737                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_53_OFFSET);\r
3738                 RegVal &= ~(RegMask);\r
3739                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT\r
3740                         | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT\r
3741                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT\r
3742                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT\r
3743                         |  0 ) & RegMask);\r
3744                 Xil_Out32 ( IOU_SLCR_MIO_PIN_53_OFFSET , RegVal);\r
3745 \r
3746         /*############################################################################################################################ */\r
3747 \r
3748                 /*Register : MIO_PIN_54 @ 0XFF1800D8</p>\r
3749 \r
3750                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)\r
3751                 PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0\r
3752 \r
3753                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3754                 ata[2]- (ULPI data bus)\r
3755                 PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1\r
3756 \r
3757                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3758                 PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0\r
3759 \r
3760                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can\r
3761                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
3762                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in\r
3763                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)\r
3764                 PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0\r
3765 \r
3766                 Configures MIO Pin 54 peripheral interface mapping\r
3767                 (OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  */\r
3768                 RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );\r
3769 \r
3770                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_54_OFFSET);\r
3771                 RegVal &= ~(RegMask);\r
3772                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT\r
3773                         | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT\r
3774                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT\r
3775                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT\r
3776                         |  0 ) & RegMask);\r
3777                 Xil_Out32 ( IOU_SLCR_MIO_PIN_54_OFFSET , RegVal);\r
3778 \r
3779         /*############################################################################################################################ */\r
3780 \r
3781                 /*Register : MIO_PIN_55 @ 0XFF1800DC</p>\r
3782 \r
3783                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)\r
3784                 PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0\r
3785 \r
3786                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)\r
3787                 PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1\r
3788 \r
3789                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3790                 PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0\r
3791 \r
3792                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can\r
3793                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
3794                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0\r
3795                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial\r
3796                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)\r
3797                 PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0\r
3798 \r
3799                 Configures MIO Pin 55 peripheral interface mapping\r
3800                 (OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  */\r
3801                 RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );\r
3802 \r
3803                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_55_OFFSET);\r
3804                 RegVal &= ~(RegMask);\r
3805                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT\r
3806                         | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT\r
3807                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT\r
3808                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT\r
3809                         |  0 ) & RegMask);\r
3810                 Xil_Out32 ( IOU_SLCR_MIO_PIN_55_OFFSET , RegVal);\r
3811 \r
3812         /*############################################################################################################################ */\r
3813 \r
3814                 /*Register : MIO_PIN_56 @ 0XFF1800E0</p>\r
3815 \r
3816                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)\r
3817                 PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0\r
3818 \r
3819                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3820                 ata[0]- (ULPI data bus)\r
3821                 PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1\r
3822 \r
3823                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3824                 PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0\r
3825 \r
3826                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can\r
3827                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
3828                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s\r
3829                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, \r
3830                 utput, tracedq[2]- (Trace Port Databus)\r
3831                 PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0\r
3832 \r
3833                 Configures MIO Pin 56 peripheral interface mapping\r
3834                 (OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  */\r
3835                 RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );\r
3836 \r
3837                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_56_OFFSET);\r
3838                 RegVal &= ~(RegMask);\r
3839                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT\r
3840                         | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT\r
3841                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT\r
3842                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT\r
3843                         |  0 ) & RegMask);\r
3844                 Xil_Out32 ( IOU_SLCR_MIO_PIN_56_OFFSET , RegVal);\r
3845 \r
3846         /*############################################################################################################################ */\r
3847 \r
3848                 /*Register : MIO_PIN_57 @ 0XFF1800E4</p>\r
3849 \r
3850                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)\r
3851                 PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0\r
3852 \r
3853                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3854                 ata[1]- (ULPI data bus)\r
3855                 PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1\r
3856 \r
3857                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3858                 PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0\r
3859 \r
3860                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can\r
3861                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
3862                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0\r
3863                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7\r
3864                  trace, Output, tracedq[3]- (Trace Port Databus)\r
3865                 PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0\r
3866 \r
3867                 Configures MIO Pin 57 peripheral interface mapping\r
3868                 (OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  */\r
3869                 RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );\r
3870 \r
3871                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_57_OFFSET);\r
3872                 RegVal &= ~(RegMask);\r
3873                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT\r
3874                         | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT\r
3875                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT\r
3876                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT\r
3877                         |  0 ) & RegMask);\r
3878                 Xil_Out32 ( IOU_SLCR_MIO_PIN_57_OFFSET , RegVal);\r
3879 \r
3880         /*############################################################################################################################ */\r
3881 \r
3882                 /*Register : MIO_PIN_58 @ 0XFF1800E8</p>\r
3883 \r
3884                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)\r
3885                 PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0\r
3886 \r
3887                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)\r
3888                 PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1\r
3889 \r
3890                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3891                 PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0\r
3892 \r
3893                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can\r
3894                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal\r
3895                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock\r
3896                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- \r
3897                 Trace Port Databus)\r
3898                 PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0\r
3899 \r
3900                 Configures MIO Pin 58 peripheral interface mapping\r
3901                 (OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  */\r
3902                 RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );\r
3903 \r
3904                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_58_OFFSET);\r
3905                 RegVal &= ~(RegMask);\r
3906                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT\r
3907                         | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT\r
3908                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT\r
3909                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT\r
3910                         |  0 ) & RegMask);\r
3911                 Xil_Out32 ( IOU_SLCR_MIO_PIN_58_OFFSET , RegVal);\r
3912 \r
3913         /*############################################################################################################################ */\r
3914 \r
3915                 /*Register : MIO_PIN_59 @ 0XFF1800EC</p>\r
3916 \r
3917                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)\r
3918                 PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0\r
3919 \r
3920                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3921                 ata[3]- (ULPI data bus)\r
3922                 PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1\r
3923 \r
3924                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3925                 PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0\r
3926 \r
3927                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can\r
3928                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa\r
3929                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_\r
3930                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port \r
3931                 atabus)\r
3932                 PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0\r
3933 \r
3934                 Configures MIO Pin 59 peripheral interface mapping\r
3935                 (OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  */\r
3936                 RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );\r
3937 \r
3938                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_59_OFFSET);\r
3939                 RegVal &= ~(RegMask);\r
3940                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT\r
3941                         | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT\r
3942                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT\r
3943                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT\r
3944                         |  0 ) & RegMask);\r
3945                 Xil_Out32 ( IOU_SLCR_MIO_PIN_59_OFFSET , RegVal);\r
3946 \r
3947         /*############################################################################################################################ */\r
3948 \r
3949                 /*Register : MIO_PIN_60 @ 0XFF1800F0</p>\r
3950 \r
3951                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)\r
3952                 PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0\r
3953 \r
3954                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3955                 ata[4]- (ULPI data bus)\r
3956                 PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1\r
3957 \r
3958                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3959                 PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0\r
3960 \r
3961                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can\r
3962                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa\r
3963                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i\r
3964                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)\r
3965                 PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0\r
3966 \r
3967                 Configures MIO Pin 60 peripheral interface mapping\r
3968                 (OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  */\r
3969                 RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );\r
3970 \r
3971                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_60_OFFSET);\r
3972                 RegVal &= ~(RegMask);\r
3973                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT\r
3974                         | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT\r
3975                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT\r
3976                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT\r
3977                         |  0 ) & RegMask);\r
3978                 Xil_Out32 ( IOU_SLCR_MIO_PIN_60_OFFSET , RegVal);\r
3979 \r
3980         /*############################################################################################################################ */\r
3981 \r
3982                 /*Register : MIO_PIN_61 @ 0XFF1800F4</p>\r
3983 \r
3984                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)\r
3985                 PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0\r
3986 \r
3987                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
3988                 ata[5]- (ULPI data bus)\r
3989                 PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1\r
3990 \r
3991                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
3992                 PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0\r
3993 \r
3994                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can\r
3995                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal\r
3996                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]\r
3997                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu\r
3998                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)\r
3999                 PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0\r
4000 \r
4001                 Configures MIO Pin 61 peripheral interface mapping\r
4002                 (OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  */\r
4003                 RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );\r
4004 \r
4005                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_61_OFFSET);\r
4006                 RegVal &= ~(RegMask);\r
4007                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT\r
4008                         | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT\r
4009                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT\r
4010                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT\r
4011                         |  0 ) & RegMask);\r
4012                 Xil_Out32 ( IOU_SLCR_MIO_PIN_61_OFFSET , RegVal);\r
4013 \r
4014         /*############################################################################################################################ */\r
4015 \r
4016                 /*Register : MIO_PIN_62 @ 0XFF1800F8</p>\r
4017 \r
4018                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)\r
4019                 PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0\r
4020 \r
4021                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
4022                 ata[6]- (ULPI data bus)\r
4023                 PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1\r
4024 \r
4025                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
4026                 PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0\r
4027 \r
4028                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c\r
4029                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
4030                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_\r
4031                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp\r
4032                 t, tracedq[8]- (Trace Port Databus)\r
4033                 PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0\r
4034 \r
4035                 Configures MIO Pin 62 peripheral interface mapping\r
4036                 (OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  */\r
4037                 RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );\r
4038 \r
4039                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_62_OFFSET);\r
4040                 RegVal &= ~(RegMask);\r
4041                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT\r
4042                         | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT\r
4043                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT\r
4044                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT\r
4045                         |  0 ) & RegMask);\r
4046                 Xil_Out32 ( IOU_SLCR_MIO_PIN_62_OFFSET , RegVal);\r
4047 \r
4048         /*############################################################################################################################ */\r
4049 \r
4050                 /*Register : MIO_PIN_63 @ 0XFF1800FC</p>\r
4051 \r
4052                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )\r
4053                 PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0\r
4054 \r
4055                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_\r
4056                 ata[7]- (ULPI data bus)\r
4057                 PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1\r
4058 \r
4059                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used\r
4060                 PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0\r
4061 \r
4062                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c\r
4063                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
4064                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s\r
4065                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o\r
4066                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)\r
4067                 PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0\r
4068 \r
4069                 Configures MIO Pin 63 peripheral interface mapping\r
4070                 (OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  */\r
4071                 RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );\r
4072 \r
4073                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_63_OFFSET);\r
4074                 RegVal &= ~(RegMask);\r
4075                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT\r
4076                         | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT\r
4077                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT\r
4078                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT\r
4079                         |  0 ) & RegMask);\r
4080                 Xil_Out32 ( IOU_SLCR_MIO_PIN_63_OFFSET , RegVal);\r
4081 \r
4082         /*############################################################################################################################ */\r
4083 \r
4084                 /*Register : MIO_PIN_64 @ 0XFF180100</p>\r
4085 \r
4086                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)\r
4087                 PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  0\r
4088 \r
4089                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)\r
4090                 PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0\r
4091 \r
4092                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used\r
4093                 PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  1\r
4094 \r
4095                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c\r
4096                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
4097                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s\r
4098                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7\r
4099                  trace, Output, tracedq[10]- (Trace Port Databus)\r
4100                 PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0\r
4101 \r
4102                 Configures MIO Pin 64 peripheral interface mapping\r
4103                 (OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000008U)  */\r
4104                 RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );\r
4105 \r
4106                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_64_OFFSET);\r
4107                 RegVal &= ~(RegMask);\r
4108                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT\r
4109                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT\r
4110                         | 0x00000001U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT\r
4111                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT\r
4112                         |  0 ) & RegMask);\r
4113                 Xil_Out32 ( IOU_SLCR_MIO_PIN_64_OFFSET , RegVal);\r
4114 \r
4115         /*############################################################################################################################ */\r
4116 \r
4117                 /*Register : MIO_PIN_65 @ 0XFF180104</p>\r
4118 \r
4119                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)\r
4120                 PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  0\r
4121 \r
4122                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)\r
4123                 PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0\r
4124 \r
4125                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used\r
4126                 PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  1\r
4127 \r
4128                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c\r
4129                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
4130                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=\r
4131                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac\r
4132                 dq[11]- (Trace Port Databus)\r
4133                 PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0\r
4134 \r
4135                 Configures MIO Pin 65 peripheral interface mapping\r
4136                 (OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000008U)  */\r
4137                 RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );\r
4138 \r
4139                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_65_OFFSET);\r
4140                 RegVal &= ~(RegMask);\r
4141                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT\r
4142                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT\r
4143                         | 0x00000001U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT\r
4144                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT\r
4145                         |  0 ) & RegMask);\r
4146                 Xil_Out32 ( IOU_SLCR_MIO_PIN_65_OFFSET , RegVal);\r
4147 \r
4148         /*############################################################################################################################ */\r
4149 \r
4150                 /*Register : MIO_PIN_66 @ 0XFF180108</p>\r
4151 \r
4152                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)\r
4153                 PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  0\r
4154 \r
4155                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4156                 ata[2]- (ULPI data bus)\r
4157                 PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0\r
4158 \r
4159                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman\r
4160                  Indicator) 2= Not Used 3= Not Used\r
4161                 PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  1\r
4162 \r
4163                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c\r
4164                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
4165                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt\r
4166                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace\r
4167                 Port Databus)\r
4168                 PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0\r
4169 \r
4170                 Configures MIO Pin 66 peripheral interface mapping\r
4171                 (OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000008U)  */\r
4172                 RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );\r
4173 \r
4174                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_66_OFFSET);\r
4175                 RegVal &= ~(RegMask);\r
4176                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT\r
4177                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT\r
4178                         | 0x00000001U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT\r
4179                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT\r
4180                         |  0 ) & RegMask);\r
4181                 Xil_Out32 ( IOU_SLCR_MIO_PIN_66_OFFSET , RegVal);\r
4182 \r
4183         /*############################################################################################################################ */\r
4184 \r
4185                 /*Register : MIO_PIN_67 @ 0XFF18010C</p>\r
4186 \r
4187                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)\r
4188                 PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  0\r
4189 \r
4190                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)\r
4191                 PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0\r
4192 \r
4193                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8\r
4194                 bit Data bus) 2= Not Used 3= Not Used\r
4195                 PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  1\r
4196 \r
4197                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c\r
4198                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
4199                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi\r
4200                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd\r
4201                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)\r
4202                 PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0\r
4203 \r
4204                 Configures MIO Pin 67 peripheral interface mapping\r
4205                 (OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000008U)  */\r
4206                 RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );\r
4207 \r
4208                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_67_OFFSET);\r
4209                 RegVal &= ~(RegMask);\r
4210                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT\r
4211                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT\r
4212                         | 0x00000001U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT\r
4213                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT\r
4214                         |  0 ) & RegMask);\r
4215                 Xil_Out32 ( IOU_SLCR_MIO_PIN_67_OFFSET , RegVal);\r
4216 \r
4217         /*############################################################################################################################ */\r
4218 \r
4219                 /*Register : MIO_PIN_68 @ 0XFF180110</p>\r
4220 \r
4221                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)\r
4222                 PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  0\r
4223 \r
4224                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4225                 ata[0]- (ULPI data bus)\r
4226                 PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0\r
4227 \r
4228                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8\r
4229                 bit Data bus) 2= Not Used 3= Not Used\r
4230                 PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  1\r
4231 \r
4232                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c\r
4233                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
4234                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0\r
4235                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace\r
4236                  Output, tracedq[14]- (Trace Port Databus)\r
4237                 PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0\r
4238 \r
4239                 Configures MIO Pin 68 peripheral interface mapping\r
4240                 (OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000008U)  */\r
4241                 RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );\r
4242 \r
4243                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_68_OFFSET);\r
4244                 RegVal &= ~(RegMask);\r
4245                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT\r
4246                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT\r
4247                         | 0x00000001U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT\r
4248                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT\r
4249                         |  0 ) & RegMask);\r
4250                 Xil_Out32 ( IOU_SLCR_MIO_PIN_68_OFFSET , RegVal);\r
4251 \r
4252         /*############################################################################################################################ */\r
4253 \r
4254                 /*Register : MIO_PIN_69 @ 0XFF180114</p>\r
4255 \r
4256                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)\r
4257                 PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  0\r
4258 \r
4259                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4260                 ata[1]- (ULPI data bus)\r
4261                 PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0\r
4262 \r
4263                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8\r
4264                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used\r
4265                 PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  1\r
4266 \r
4267                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c\r
4268                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
4269                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp\r
4270                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)\r
4271                 7= trace, Output, tracedq[15]- (Trace Port Databus)\r
4272                 PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0\r
4273 \r
4274                 Configures MIO Pin 69 peripheral interface mapping\r
4275                 (OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000008U)  */\r
4276                 RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );\r
4277 \r
4278                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_69_OFFSET);\r
4279                 RegVal &= ~(RegMask);\r
4280                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT\r
4281                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT\r
4282                         | 0x00000001U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT\r
4283                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT\r
4284                         |  0 ) & RegMask);\r
4285                 Xil_Out32 ( IOU_SLCR_MIO_PIN_69_OFFSET , RegVal);\r
4286 \r
4287         /*############################################################################################################################ */\r
4288 \r
4289                 /*Register : MIO_PIN_70 @ 0XFF180118</p>\r
4290 \r
4291                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)\r
4292                 PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  0\r
4293 \r
4294                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)\r
4295                 PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0\r
4296 \r
4297                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8\r
4298                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used\r
4299                 PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  1\r
4300 \r
4301                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c\r
4302                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
4303                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp\r
4304                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not \r
4305                 sed\r
4306                 PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0\r
4307 \r
4308                 Configures MIO Pin 70 peripheral interface mapping\r
4309                 (OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000008U)  */\r
4310                 RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );\r
4311 \r
4312                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_70_OFFSET);\r
4313                 RegVal &= ~(RegMask);\r
4314                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT\r
4315                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT\r
4316                         | 0x00000001U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT\r
4317                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT\r
4318                         |  0 ) & RegMask);\r
4319                 Xil_Out32 ( IOU_SLCR_MIO_PIN_70_OFFSET , RegVal);\r
4320 \r
4321         /*############################################################################################################################ */\r
4322 \r
4323                 /*Register : MIO_PIN_71 @ 0XFF18011C</p>\r
4324 \r
4325                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)\r
4326                 PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  0\r
4327 \r
4328                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4329                 ata[3]- (ULPI data bus)\r
4330                 PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0\r
4331 \r
4332                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8\r
4333                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used\r
4334                 PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  1\r
4335 \r
4336                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c\r
4337                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
4338                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5\r
4339                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used\r
4340                 PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0\r
4341 \r
4342                 Configures MIO Pin 71 peripheral interface mapping\r
4343                 (OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000008U)  */\r
4344                 RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );\r
4345 \r
4346                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_71_OFFSET);\r
4347                 RegVal &= ~(RegMask);\r
4348                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT\r
4349                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT\r
4350                         | 0x00000001U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT\r
4351                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT\r
4352                         |  0 ) & RegMask);\r
4353                 Xil_Out32 ( IOU_SLCR_MIO_PIN_71_OFFSET , RegVal);\r
4354 \r
4355         /*############################################################################################################################ */\r
4356 \r
4357                 /*Register : MIO_PIN_72 @ 0XFF180120</p>\r
4358 \r
4359                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)\r
4360                 PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  0\r
4361 \r
4362                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4363                 ata[4]- (ULPI data bus)\r
4364                 PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0\r
4365 \r
4366                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8\r
4367                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used\r
4368                 PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  1\r
4369 \r
4370                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c\r
4371                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
4372                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N\r
4373                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used\r
4374                 PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0\r
4375 \r
4376                 Configures MIO Pin 72 peripheral interface mapping\r
4377                 (OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000008U)  */\r
4378                 RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );\r
4379 \r
4380                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_72_OFFSET);\r
4381                 RegVal &= ~(RegMask);\r
4382                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT\r
4383                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT\r
4384                         | 0x00000001U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT\r
4385                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT\r
4386                         |  0 ) & RegMask);\r
4387                 Xil_Out32 ( IOU_SLCR_MIO_PIN_72_OFFSET , RegVal);\r
4388 \r
4389         /*############################################################################################################################ */\r
4390 \r
4391                 /*Register : MIO_PIN_73 @ 0XFF180124</p>\r
4392 \r
4393                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)\r
4394                 PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  0\r
4395 \r
4396                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4397                 ata[5]- (ULPI data bus)\r
4398                 PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0\r
4399 \r
4400                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8\r
4401                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used\r
4402                 PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  1\r
4403 \r
4404                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c\r
4405                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
4406                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1\r
4407                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used\r
4408                 PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0\r
4409 \r
4410                 Configures MIO Pin 73 peripheral interface mapping\r
4411                 (OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000008U)  */\r
4412                 RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );\r
4413 \r
4414                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_73_OFFSET);\r
4415                 RegVal &= ~(RegMask);\r
4416                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT\r
4417                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT\r
4418                         | 0x00000001U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT\r
4419                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT\r
4420                         |  0 ) & RegMask);\r
4421                 Xil_Out32 ( IOU_SLCR_MIO_PIN_73_OFFSET , RegVal);\r
4422 \r
4423         /*############################################################################################################################ */\r
4424 \r
4425                 /*Register : MIO_PIN_74 @ 0XFF180128</p>\r
4426 \r
4427                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)\r
4428                 PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  0\r
4429 \r
4430                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4431                 ata[6]- (ULPI data bus)\r
4432                 PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0\r
4433 \r
4434                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8\r
4435                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used\r
4436                 PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  1\r
4437 \r
4438                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c\r
4439                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign\r
4440                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_\r
4441                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used\r
4442                 PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0\r
4443 \r
4444                 Configures MIO Pin 74 peripheral interface mapping\r
4445                 (OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000008U)  */\r
4446                 RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );\r
4447 \r
4448                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_74_OFFSET);\r
4449                 RegVal &= ~(RegMask);\r
4450                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT\r
4451                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT\r
4452                         | 0x00000001U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT\r
4453                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT\r
4454                         |  0 ) & RegMask);\r
4455                 Xil_Out32 ( IOU_SLCR_MIO_PIN_74_OFFSET , RegVal);\r
4456 \r
4457         /*############################################################################################################################ */\r
4458 \r
4459                 /*Register : MIO_PIN_75 @ 0XFF18012C</p>\r
4460 \r
4461                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )\r
4462                 PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  0\r
4463 \r
4464                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_\r
4465                 ata[7]- (ULPI data bus)\r
4466                 PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0\r
4467 \r
4468                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma\r
4469                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used\r
4470                 PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  1\r
4471 \r
4472                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c\r
4473                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig\r
4474                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s\r
4475                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used\r
4476                 PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0\r
4477 \r
4478                 Configures MIO Pin 75 peripheral interface mapping\r
4479                 (OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000008U)  */\r
4480                 RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );\r
4481 \r
4482                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_75_OFFSET);\r
4483                 RegVal &= ~(RegMask);\r
4484                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT\r
4485                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT\r
4486                         | 0x00000001U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT\r
4487                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT\r
4488                         |  0 ) & RegMask);\r
4489                 Xil_Out32 ( IOU_SLCR_MIO_PIN_75_OFFSET , RegVal);\r
4490 \r
4491         /*############################################################################################################################ */\r
4492 \r
4493                 /*Register : MIO_PIN_76 @ 0XFF180130</p>\r
4494 \r
4495                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
4496                 PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0\r
4497 \r
4498                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
4499                 PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0\r
4500 \r
4501                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio\r
4502                 _clk_out- (SDSDIO clock) 3= Not Used\r
4503                 PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  1\r
4504 \r
4505                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c\r
4506                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig\r
4507                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock\r
4508                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used\r
4509                 PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  0\r
4510 \r
4511                 Configures MIO Pin 76 peripheral interface mapping\r
4512                 (OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x00000008U)  */\r
4513                 RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );\r
4514 \r
4515                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_76_OFFSET);\r
4516                 RegVal &= ~(RegMask);\r
4517                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT\r
4518                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT\r
4519                         | 0x00000001U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT\r
4520                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT\r
4521                         |  0 ) & RegMask);\r
4522                 Xil_Out32 ( IOU_SLCR_MIO_PIN_76_OFFSET , RegVal);\r
4523 \r
4524         /*############################################################################################################################ */\r
4525 \r
4526                 /*Register : MIO_PIN_77 @ 0XFF180134</p>\r
4527 \r
4528                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used\r
4529                 PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0\r
4530 \r
4531                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used\r
4532                 PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0\r
4533 \r
4534                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used\r
4535                 PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0\r
4536 \r
4537                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c\r
4538                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign\r
4539                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD\r
4540                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o\r
4541                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used\r
4542                 PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  0\r
4543 \r
4544                 Configures MIO Pin 77 peripheral interface mapping\r
4545                 (OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x00000000U)  */\r
4546                 RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );\r
4547 \r
4548                 RegVal = Xil_In32 (IOU_SLCR_MIO_PIN_77_OFFSET);\r
4549                 RegVal &= ~(RegMask);\r
4550                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT\r
4551                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT\r
4552                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT\r
4553                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT\r
4554                         |  0 ) & RegMask);\r
4555                 Xil_Out32 ( IOU_SLCR_MIO_PIN_77_OFFSET , RegVal);\r
4556 \r
4557         /*############################################################################################################################ */\r
4558 \r
4559                 /*Register : MIO_MST_TRI0 @ 0XFF180204</p>\r
4560 \r
4561                 Master Tri-state Enable for pin 0, active high\r
4562                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0\r
4563 \r
4564                 Master Tri-state Enable for pin 1, active high\r
4565                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0\r
4566 \r
4567                 Master Tri-state Enable for pin 2, active high\r
4568                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0\r
4569 \r
4570                 Master Tri-state Enable for pin 3, active high\r
4571                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0\r
4572 \r
4573                 Master Tri-state Enable for pin 4, active high\r
4574                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0\r
4575 \r
4576                 Master Tri-state Enable for pin 5, active high\r
4577                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0\r
4578 \r
4579                 Master Tri-state Enable for pin 6, active high\r
4580                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0\r
4581 \r
4582                 Master Tri-state Enable for pin 7, active high\r
4583                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0\r
4584 \r
4585                 Master Tri-state Enable for pin 8, active high\r
4586                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0\r
4587 \r
4588                 Master Tri-state Enable for pin 9, active high\r
4589                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0\r
4590 \r
4591                 Master Tri-state Enable for pin 10, active high\r
4592                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            1\r
4593 \r
4594                 Master Tri-state Enable for pin 11, active high\r
4595                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            1\r
4596 \r
4597                 Master Tri-state Enable for pin 12, active high\r
4598                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0\r
4599 \r
4600                 Master Tri-state Enable for pin 13, active high\r
4601                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0\r
4602 \r
4603                 Master Tri-state Enable for pin 14, active high\r
4604                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0\r
4605 \r
4606                 Master Tri-state Enable for pin 15, active high\r
4607                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0\r
4608 \r
4609                 Master Tri-state Enable for pin 16, active high\r
4610                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0\r
4611 \r
4612                 Master Tri-state Enable for pin 17, active high\r
4613                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0\r
4614 \r
4615                 Master Tri-state Enable for pin 18, active high\r
4616                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            0\r
4617 \r
4618                 Master Tri-state Enable for pin 19, active high\r
4619                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0\r
4620 \r
4621                 Master Tri-state Enable for pin 20, active high\r
4622                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0\r
4623 \r
4624                 Master Tri-state Enable for pin 21, active high\r
4625                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            0\r
4626 \r
4627                 Master Tri-state Enable for pin 22, active high\r
4628                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0\r
4629 \r
4630                 Master Tri-state Enable for pin 23, active high\r
4631                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0\r
4632 \r
4633                 Master Tri-state Enable for pin 24, active high\r
4634                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0\r
4635 \r
4636                 Master Tri-state Enable for pin 25, active high\r
4637                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            0\r
4638 \r
4639                 Master Tri-state Enable for pin 26, active high\r
4640                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            0\r
4641 \r
4642                 Master Tri-state Enable for pin 27, active high\r
4643                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0\r
4644 \r
4645                 Master Tri-state Enable for pin 28, active high\r
4646                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0\r
4647 \r
4648                 Master Tri-state Enable for pin 29, active high\r
4649                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0\r
4650 \r
4651                 Master Tri-state Enable for pin 30, active high\r
4652                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0\r
4653 \r
4654                 Master Tri-state Enable for pin 31, active high\r
4655                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0\r
4656 \r
4657                 MIO pin Tri-state Enables, 31:0\r
4658                 (OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x00000C00U)  */\r
4659                 RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );\r
4660 \r
4661                 RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI0_OFFSET);\r
4662                 RegVal &= ~(RegMask);\r
4663                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT\r
4664                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT\r
4665                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT\r
4666                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT\r
4667                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT\r
4668                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT\r
4669                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT\r
4670                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT\r
4671                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT\r
4672                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT\r
4673                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT\r
4674                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT\r
4675                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT\r
4676                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT\r
4677                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT\r
4678                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT\r
4679                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT\r
4680                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT\r
4681                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT\r
4682                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT\r
4683                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT\r
4684                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT\r
4685                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT\r
4686                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT\r
4687                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT\r
4688                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT\r
4689                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT\r
4690                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT\r
4691                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT\r
4692                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT\r
4693                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT\r
4694                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT\r
4695                         |  0 ) & RegMask);\r
4696                 Xil_Out32 ( IOU_SLCR_MIO_MST_TRI0_OFFSET , RegVal);\r
4697 \r
4698         /*############################################################################################################################ */\r
4699 \r
4700                 /*Register : MIO_MST_TRI1 @ 0XFF180208</p>\r
4701 \r
4702                 Master Tri-state Enable for pin 32, active high\r
4703                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0\r
4704 \r
4705                 Master Tri-state Enable for pin 33, active high\r
4706                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0\r
4707 \r
4708                 Master Tri-state Enable for pin 34, active high\r
4709                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0\r
4710 \r
4711                 Master Tri-state Enable for pin 35, active high\r
4712                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0\r
4713 \r
4714                 Master Tri-state Enable for pin 36, active high\r
4715                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0\r
4716 \r
4717                 Master Tri-state Enable for pin 37, active high\r
4718                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0\r
4719 \r
4720                 Master Tri-state Enable for pin 38, active high\r
4721                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0\r
4722 \r
4723                 Master Tri-state Enable for pin 39, active high\r
4724                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0\r
4725 \r
4726                 Master Tri-state Enable for pin 40, active high\r
4727                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0\r
4728 \r
4729                 Master Tri-state Enable for pin 41, active high\r
4730                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0\r
4731 \r
4732                 Master Tri-state Enable for pin 42, active high\r
4733                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0\r
4734 \r
4735                 Master Tri-state Enable for pin 43, active high\r
4736                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0\r
4737 \r
4738                 Master Tri-state Enable for pin 44, active high\r
4739                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            0\r
4740 \r
4741                 Master Tri-state Enable for pin 45, active high\r
4742                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            0\r
4743 \r
4744                 Master Tri-state Enable for pin 46, active high\r
4745                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0\r
4746 \r
4747                 Master Tri-state Enable for pin 47, active high\r
4748                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0\r
4749 \r
4750                 Master Tri-state Enable for pin 48, active high\r
4751                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0\r
4752 \r
4753                 Master Tri-state Enable for pin 49, active high\r
4754                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0\r
4755 \r
4756                 Master Tri-state Enable for pin 50, active high\r
4757                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0\r
4758 \r
4759                 Master Tri-state Enable for pin 51, active high\r
4760                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0\r
4761 \r
4762                 Master Tri-state Enable for pin 52, active high\r
4763                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1\r
4764 \r
4765                 Master Tri-state Enable for pin 53, active high\r
4766                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1\r
4767 \r
4768                 Master Tri-state Enable for pin 54, active high\r
4769                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0\r
4770 \r
4771                 Master Tri-state Enable for pin 55, active high\r
4772                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1\r
4773 \r
4774                 Master Tri-state Enable for pin 56, active high\r
4775                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0\r
4776 \r
4777                 Master Tri-state Enable for pin 57, active high\r
4778                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0\r
4779 \r
4780                 Master Tri-state Enable for pin 58, active high\r
4781                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0\r
4782 \r
4783                 Master Tri-state Enable for pin 59, active high\r
4784                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0\r
4785 \r
4786                 Master Tri-state Enable for pin 60, active high\r
4787                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0\r
4788 \r
4789                 Master Tri-state Enable for pin 61, active high\r
4790                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0\r
4791 \r
4792                 Master Tri-state Enable for pin 62, active high\r
4793                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0\r
4794 \r
4795                 Master Tri-state Enable for pin 63, active high\r
4796                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0\r
4797 \r
4798                 MIO pin Tri-state Enables, 63:32\r
4799                 (OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B00000U)  */\r
4800                 RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );\r
4801 \r
4802                 RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI1_OFFSET);\r
4803                 RegVal &= ~(RegMask);\r
4804                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT\r
4805                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT\r
4806                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT\r
4807                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT\r
4808                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT\r
4809                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT\r
4810                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT\r
4811                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT\r
4812                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT\r
4813                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT\r
4814                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT\r
4815                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT\r
4816                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT\r
4817                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT\r
4818                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT\r
4819                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT\r
4820                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT\r
4821                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT\r
4822                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT\r
4823                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT\r
4824                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT\r
4825                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT\r
4826                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT\r
4827                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT\r
4828                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT\r
4829                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT\r
4830                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT\r
4831                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT\r
4832                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT\r
4833                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT\r
4834                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT\r
4835                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT\r
4836                         |  0 ) & RegMask);\r
4837                 Xil_Out32 ( IOU_SLCR_MIO_MST_TRI1_OFFSET , RegVal);\r
4838 \r
4839         /*############################################################################################################################ */\r
4840 \r
4841                 /*Register : MIO_MST_TRI2 @ 0XFF18020C</p>\r
4842 \r
4843                 Master Tri-state Enable for pin 64, active high\r
4844                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0\r
4845 \r
4846                 Master Tri-state Enable for pin 65, active high\r
4847                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            1\r
4848 \r
4849                 Master Tri-state Enable for pin 66, active high\r
4850                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0\r
4851 \r
4852                 Master Tri-state Enable for pin 67, active high\r
4853                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0\r
4854 \r
4855                 Master Tri-state Enable for pin 68, active high\r
4856                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0\r
4857 \r
4858                 Master Tri-state Enable for pin 69, active high\r
4859                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0\r
4860 \r
4861                 Master Tri-state Enable for pin 70, active high\r
4862                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            0\r
4863 \r
4864                 Master Tri-state Enable for pin 71, active high\r
4865                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            0\r
4866 \r
4867                 Master Tri-state Enable for pin 72, active high\r
4868                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            0\r
4869 \r
4870                 Master Tri-state Enable for pin 73, active high\r
4871                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            0\r
4872 \r
4873                 Master Tri-state Enable for pin 74, active high\r
4874                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            0\r
4875 \r
4876                 Master Tri-state Enable for pin 75, active high\r
4877                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            0\r
4878 \r
4879                 Master Tri-state Enable for pin 76, active high\r
4880                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            1\r
4881 \r
4882                 Master Tri-state Enable for pin 77, active high\r
4883                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0\r
4884 \r
4885                 MIO pin Tri-state Enables, 77:64\r
4886                 (OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00001002U)  */\r
4887                 RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );\r
4888 \r
4889                 RegVal = Xil_In32 (IOU_SLCR_MIO_MST_TRI2_OFFSET);\r
4890                 RegVal &= ~(RegMask);\r
4891                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT\r
4892                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT\r
4893                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT\r
4894                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT\r
4895                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT\r
4896                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT\r
4897                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT\r
4898                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT\r
4899                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT\r
4900                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT\r
4901                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT\r
4902                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT\r
4903                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT\r
4904                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT\r
4905                         |  0 ) & RegMask);\r
4906                 Xil_Out32 ( IOU_SLCR_MIO_MST_TRI2_OFFSET , RegVal);\r
4907 \r
4908         /*############################################################################################################################ */\r
4909 \r
4910                 // : LOOPBACK\r
4911                 /*Register : MIO_LOOPBACK @ 0XFF180200</p>\r
4912 \r
4913                 I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp\r
4914                 ts to I2C 0 inputs.\r
4915                 PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0\r
4916 \r
4917                 CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R\r
4918                 .\r
4919                 PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0\r
4920 \r
4921                 UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1\r
4922                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.\r
4923                 PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0\r
4924 \r
4925                 SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp\r
4926                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.\r
4927                 PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0\r
4928 \r
4929                 Loopback function within MIO\r
4930                 (OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  */\r
4931                 RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );\r
4932 \r
4933                 RegVal = Xil_In32 (IOU_SLCR_MIO_LOOPBACK_OFFSET);\r
4934                 RegVal &= ~(RegMask);\r
4935                 RegVal |= ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT\r
4936                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT\r
4937                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT\r
4938                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT\r
4939                         |  0 ) & RegMask);\r
4940                 Xil_Out32 ( IOU_SLCR_MIO_LOOPBACK_OFFSET , RegVal);\r
4941 \r
4942         /*############################################################################################################################ */\r
4943 \r
4944 \r
4945 }\r
4946 unsigned long psu_peripherals_init_data_3_0() {\r
4947                 // : ENET\r
4948                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>\r
4949 \r
4950                 GEM 0 reset\r
4951                 PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET                                             0\r
4952 \r
4953                 GEM 1 reset\r
4954                 PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET                                             0\r
4955 \r
4956                 GEM 2 reset\r
4957                 PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET                                             0\r
4958 \r
4959                 GEM 3 reset\r
4960                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0\r
4961 \r
4962                 Software controlled reset for the GEMs\r
4963                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x0000000FU ,0x00000000U)  */\r
4964                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK | CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );\r
4965 \r
4966                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU0_OFFSET);\r
4967                 RegVal &= ~(RegMask);\r
4968                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT\r
4969                         | 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT\r
4970                         | 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT\r
4971                         | 0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT\r
4972                         |  0 ) & RegMask);\r
4973                 Xil_Out32 ( CRL_APB_RST_LPD_IOU0_OFFSET , RegVal);\r
4974 \r
4975         /*############################################################################################################################ */\r
4976 \r
4977                 // : QSPI\r
4978                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
4979 \r
4980                 Block level reset\r
4981                 PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0\r
4982 \r
4983                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
4984                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  */\r
4985                 RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );\r
4986 \r
4987                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
4988                 RegVal &= ~(RegMask);\r
4989                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT\r
4990                         |  0 ) & RegMask);\r
4991                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
4992 \r
4993         /*############################################################################################################################ */\r
4994 \r
4995                 // : NAND\r
4996                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
4997 \r
4998                 Block level reset\r
4999                 PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET                                             0\r
5000 \r
5001                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5002                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00010000U ,0x00000000U)  */\r
5003                 RegMask = (CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK |  0 );\r
5004 \r
5005                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5006                 RegVal &= ~(RegMask);\r
5007                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT\r
5008                         |  0 ) & RegMask);\r
5009                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5010 \r
5011         /*############################################################################################################################ */\r
5012 \r
5013                 // : USB\r
5014                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>\r
5015 \r
5016                 USB 0 reset for control registers\r
5017                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0\r
5018 \r
5019                 USB 0 sleep circuit reset\r
5020                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0\r
5021 \r
5022                 USB 0 reset\r
5023                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0\r
5024 \r
5025                 Software control register for the LPD block.\r
5026                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  */\r
5027                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );\r
5028 \r
5029                 RegVal = Xil_In32 (CRL_APB_RST_LPD_TOP_OFFSET);\r
5030                 RegVal &= ~(RegMask);\r
5031                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT\r
5032                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT\r
5033                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT\r
5034                         |  0 ) & RegMask);\r
5035                 Xil_Out32 ( CRL_APB_RST_LPD_TOP_OFFSET , RegVal);\r
5036 \r
5037         /*############################################################################################################################ */\r
5038 \r
5039                 // : SD\r
5040                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5041 \r
5042                 Block level reset\r
5043                 PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET                                            0\r
5044 \r
5045                 Block level reset\r
5046                 PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0\r
5047 \r
5048                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5049                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000060U ,0x00000000U)  */\r
5050                 RegMask = (CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );\r
5051 \r
5052                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5053                 RegVal &= ~(RegMask);\r
5054                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT\r
5055                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT\r
5056                         |  0 ) & RegMask);\r
5057                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5058 \r
5059         /*############################################################################################################################ */\r
5060 \r
5061                 /*Register : CTRL_REG_SD @ 0XFF180310</p>\r
5062 \r
5063                 SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled\r
5064                 PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL                                           0\r
5065 \r
5066                 SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled\r
5067                 PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0\r
5068 \r
5069                 SD eMMC selection\r
5070                 (OFFSET, MASK, VALUE)      (0XFF180310, 0x00008001U ,0x00000000U)  */\r
5071                 RegMask = (IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_MASK | IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );\r
5072 \r
5073                 RegVal = Xil_In32 (IOU_SLCR_CTRL_REG_SD_OFFSET);\r
5074                 RegVal &= ~(RegMask);\r
5075                 RegVal |= ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL_SHIFT\r
5076                         | 0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT\r
5077                         |  0 ) & RegMask);\r
5078                 Xil_Out32 ( IOU_SLCR_CTRL_REG_SD_OFFSET , RegVal);\r
5079 \r
5080         /*############################################################################################################################ */\r
5081 \r
5082                 /*Register : SD_CONFIG_REG2 @ 0XFF180320</p>\r
5083 \r
5084                 Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl\r
5085                 t 11 - Reserved\r
5086                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE                                        0\r
5087 \r
5088                 Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl\r
5089                 t 11 - Reserved\r
5090                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0\r
5091 \r
5092                 1.8V Support 1: 1.8V supported 0: 1.8V not supported support\r
5093                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V                                            1\r
5094 \r
5095                 3.0V Support 1: 3.0V supported 0: 3.0V not supported support\r
5096                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V                                            0\r
5097 \r
5098                 3.3V Support 1: 3.3V supported 0: 3.3V not supported support\r
5099                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V                                            1\r
5100 \r
5101                 1.8V Support 1: 1.8V supported 0: 1.8V not supported support\r
5102                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            1\r
5103 \r
5104                 3.0V Support 1: 3.0V supported 0: 3.0V not supported support\r
5105                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0\r
5106 \r
5107                 3.3V Support 1: 3.3V supported 0: 3.3V not supported support\r
5108                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1\r
5109 \r
5110                 SD Config Register 2\r
5111                 (OFFSET, MASK, VALUE)      (0XFF180320, 0x33803380U ,0x02800280U)  */\r
5112                 RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );\r
5113 \r
5114                 RegVal = Xil_In32 (IOU_SLCR_SD_CONFIG_REG2_OFFSET);\r
5115                 RegVal &= ~(RegMask);\r
5116                 RegVal |= ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT\r
5117                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT\r
5118                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V_SHIFT\r
5119                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V_SHIFT\r
5120                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V_SHIFT\r
5121                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT\r
5122                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT\r
5123                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT\r
5124                         |  0 ) & RegMask);\r
5125                 Xil_Out32 ( IOU_SLCR_SD_CONFIG_REG2_OFFSET , RegVal);\r
5126 \r
5127         /*############################################################################################################################ */\r
5128 \r
5129                 // : CAN\r
5130                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5131 \r
5132                 Block level reset\r
5133                 PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET                                             0\r
5134 \r
5135                 Block level reset\r
5136                 PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0\r
5137 \r
5138                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5139                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000180U ,0x00000000U)  */\r
5140                 RegMask = (CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK | CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );\r
5141 \r
5142                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5143                 RegVal &= ~(RegMask);\r
5144                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT\r
5145                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT\r
5146                         |  0 ) & RegMask);\r
5147                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5148 \r
5149         /*############################################################################################################################ */\r
5150 \r
5151                 // : I2C\r
5152                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5153 \r
5154                 Block level reset\r
5155                 PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0\r
5156 \r
5157                 Block level reset\r
5158                 PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0\r
5159 \r
5160                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5161                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  */\r
5162                 RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );\r
5163 \r
5164                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5165                 RegVal &= ~(RegMask);\r
5166                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT\r
5167                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT\r
5168                         |  0 ) & RegMask);\r
5169                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5170 \r
5171         /*############################################################################################################################ */\r
5172 \r
5173                 // : SWDT\r
5174                 // : SPI\r
5175                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5176 \r
5177                 Block level reset\r
5178                 PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET                                             0\r
5179 \r
5180                 Block level reset\r
5181                 PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET                                             0\r
5182 \r
5183                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5184                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000018U ,0x00000000U)  */\r
5185                 RegMask = (CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK | CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK |  0 );\r
5186 \r
5187                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5188                 RegVal &= ~(RegMask);\r
5189                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT\r
5190                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT\r
5191                         |  0 ) & RegMask);\r
5192                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5193 \r
5194         /*############################################################################################################################ */\r
5195 \r
5196                 // : TTC\r
5197                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5198 \r
5199                 Block level reset\r
5200                 PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0\r
5201 \r
5202                 Block level reset\r
5203                 PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0\r
5204 \r
5205                 Block level reset\r
5206                 PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0\r
5207 \r
5208                 Block level reset\r
5209                 PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0\r
5210 \r
5211                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5212                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  */\r
5213                 RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );\r
5214 \r
5215                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5216                 RegVal &= ~(RegMask);\r
5217                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT\r
5218                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT\r
5219                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT\r
5220                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT\r
5221                         |  0 ) & RegMask);\r
5222                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5223 \r
5224         /*############################################################################################################################ */\r
5225 \r
5226                 // : UART\r
5227                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>\r
5228 \r
5229                 Block level reset\r
5230                 PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0\r
5231 \r
5232                 Block level reset\r
5233                 PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0\r
5234 \r
5235                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.\r
5236                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  */\r
5237                 RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );\r
5238 \r
5239                 RegVal = Xil_In32 (CRL_APB_RST_LPD_IOU2_OFFSET);\r
5240                 RegVal &= ~(RegMask);\r
5241                 RegVal |= ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT\r
5242                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT\r
5243                         |  0 ) & RegMask);\r
5244                 Xil_Out32 ( CRL_APB_RST_LPD_IOU2_OFFSET , RegVal);\r
5245 \r
5246         /*############################################################################################################################ */\r
5247 \r
5248                 /*Register : Baud_rate_divider_reg0 @ 0XFF000034</p>\r
5249 \r
5250                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate\r
5251                 PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0\r
5252 \r
5253                 Baud Rate Divider Register\r
5254                 (OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000000U)  */\r
5255                 RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );\r
5256 \r
5257                 RegVal = Xil_In32 (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET);\r
5258                 RegVal &= ~(RegMask);\r
5259                 RegVal |= ((0x00000000U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT\r
5260                         |  0 ) & RegMask);\r
5261                 Xil_Out32 ( UART0_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);\r
5262 \r
5263         /*############################################################################################################################ */\r
5264 \r
5265                 /*Register : Baud_rate_gen_reg0 @ 0XFF000018</p>\r
5266 \r
5267                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample\r
5268                 PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x0\r
5269 \r
5270                 Baud Rate Generator Register.\r
5271                 (OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x00000000U)  */\r
5272                 RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );\r
5273 \r
5274                 RegVal = Xil_In32 (UART0_BAUD_RATE_GEN_REG0_OFFSET);\r
5275                 RegVal &= ~(RegMask);\r
5276                 RegVal |= ((0x00000000U << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT\r
5277                         |  0 ) & RegMask);\r
5278                 Xil_Out32 ( UART0_BAUD_RATE_GEN_REG0_OFFSET , RegVal);\r
5279 \r
5280         /*############################################################################################################################ */\r
5281 \r
5282                 /*Register : Control_reg0 @ 0XFF000000</p>\r
5283 \r
5284                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a\r
5285                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.\r
5286                 PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0\r
5287 \r
5288                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the\r
5289                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.\r
5290                 PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0\r
5291 \r
5292                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co\r
5293                 pleted.\r
5294                 PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0\r
5295 \r
5296                 Transmit disable: 0: enable transmitter 1: disable transmitter\r
5297                 PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0\r
5298 \r
5299                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.\r
5300                 PSU_UART0_CONTROL_REG0_TXEN                                                     0x1\r
5301 \r
5302                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN\r
5303                 PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0\r
5304 \r
5305                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.\r
5306                 PSU_UART0_CONTROL_REG0_RXEN                                                     0x1\r
5307 \r
5308                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi\r
5309                  bit is self clearing once the reset has completed.\r
5310                 PSU_UART0_CONTROL_REG0_TXRES                                                    0x1\r
5311 \r
5312                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit\r
5313                 is self clearing once the reset has completed.\r
5314                 PSU_UART0_CONTROL_REG0_RXRES                                                    0x1\r
5315 \r
5316                 UART Control Register\r
5317                 (OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  */\r
5318                 RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );\r
5319 \r
5320                 RegVal = Xil_In32 (UART0_CONTROL_REG0_OFFSET);\r
5321                 RegVal &= ~(RegMask);\r
5322                 RegVal |= ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT\r
5323                         | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT\r
5324                         | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT\r
5325                         | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT\r
5326                         | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT\r
5327                         | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT\r
5328                         | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT\r
5329                         | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT\r
5330                         | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT\r
5331                         |  0 ) & RegMask);\r
5332                 Xil_Out32 ( UART0_CONTROL_REG0_OFFSET , RegVal);\r
5333 \r
5334         /*############################################################################################################################ */\r
5335 \r
5336                 /*Register : mode_reg0 @ 0XFF000004</p>\r
5337 \r
5338                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback\r
5339                 PSU_UART0_MODE_REG0_CHMODE                                                      0x0\r
5340 \r
5341                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5\r
5342                 stop bits 10: 2 stop bits 11: reserved\r
5343                 PSU_UART0_MODE_REG0_NBSTOP                                                      0x0\r
5344 \r
5345                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity \r
5346                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity\r
5347                 PSU_UART0_MODE_REG0_PAR                                                         0x4\r
5348 \r
5349                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits\r
5350                 PSU_UART0_MODE_REG0_CHRL                                                        0x0\r
5351 \r
5352                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock\r
5353                 source is uart_ref_clk 1: clock source is uart_ref_clk/8\r
5354                 PSU_UART0_MODE_REG0_CLKS                                                        0x0\r
5355 \r
5356                 UART Mode Register\r
5357                 (OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  */\r
5358                 RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );\r
5359 \r
5360                 RegVal = Xil_In32 (UART0_MODE_REG0_OFFSET);\r
5361                 RegVal &= ~(RegMask);\r
5362                 RegVal |= ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT\r
5363                         | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT\r
5364                         | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT\r
5365                         | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT\r
5366                         | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT\r
5367                         |  0 ) & RegMask);\r
5368                 Xil_Out32 ( UART0_MODE_REG0_OFFSET , RegVal);\r
5369 \r
5370         /*############################################################################################################################ */\r
5371 \r
5372                 /*Register : Baud_rate_divider_reg0 @ 0XFF010034</p>\r
5373 \r
5374                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate\r
5375                 PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x0\r
5376 \r
5377                 Baud Rate Divider Register\r
5378                 (OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000000U)  */\r
5379                 RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );\r
5380 \r
5381                 RegVal = Xil_In32 (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET);\r
5382                 RegVal &= ~(RegMask);\r
5383                 RegVal |= ((0x00000000U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT\r
5384                         |  0 ) & RegMask);\r
5385                 Xil_Out32 ( UART1_BAUD_RATE_DIVIDER_REG0_OFFSET , RegVal);\r
5386 \r
5387         /*############################################################################################################################ */\r
5388 \r
5389                 /*Register : Baud_rate_gen_reg0 @ 0XFF010018</p>\r
5390 \r
5391                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample\r
5392                 PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x0\r
5393 \r
5394                 Baud Rate Generator Register.\r
5395                 (OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x00000000U)  */\r
5396                 RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );\r
5397 \r
5398                 RegVal = Xil_In32 (UART1_BAUD_RATE_GEN_REG0_OFFSET);\r
5399                 RegVal &= ~(RegMask);\r
5400                 RegVal |= ((0x00000000U << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT\r
5401                         |  0 ) & RegMask);\r
5402                 Xil_Out32 ( UART1_BAUD_RATE_GEN_REG0_OFFSET , RegVal);\r
5403 \r
5404         /*############################################################################################################################ */\r
5405 \r
5406                 /*Register : Control_reg0 @ 0XFF010000</p>\r
5407 \r
5408                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a\r
5409                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.\r
5410                 PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0\r
5411 \r
5412                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the\r
5413                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.\r
5414                 PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0\r
5415 \r
5416                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co\r
5417                 pleted.\r
5418                 PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0\r
5419 \r
5420                 Transmit disable: 0: enable transmitter 1: disable transmitter\r
5421                 PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0\r
5422 \r
5423                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.\r
5424                 PSU_UART1_CONTROL_REG0_TXEN                                                     0x1\r
5425 \r
5426                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN\r
5427                 PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0\r
5428 \r
5429                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.\r
5430                 PSU_UART1_CONTROL_REG0_RXEN                                                     0x1\r
5431 \r
5432                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi\r
5433                  bit is self clearing once the reset has completed.\r
5434                 PSU_UART1_CONTROL_REG0_TXRES                                                    0x1\r
5435 \r
5436                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit\r
5437                 is self clearing once the reset has completed.\r
5438                 PSU_UART1_CONTROL_REG0_RXRES                                                    0x1\r
5439 \r
5440                 UART Control Register\r
5441                 (OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  */\r
5442                 RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );\r
5443 \r
5444                 RegVal = Xil_In32 (UART1_CONTROL_REG0_OFFSET);\r
5445                 RegVal &= ~(RegMask);\r
5446                 RegVal |= ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT\r
5447                         | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT\r
5448                         | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT\r
5449                         | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT\r
5450                         | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT\r
5451                         | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT\r
5452                         | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT\r
5453                         | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT\r
5454                         | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT\r
5455                         |  0 ) & RegMask);\r
5456                 Xil_Out32 ( UART1_CONTROL_REG0_OFFSET , RegVal);\r
5457 \r
5458         /*############################################################################################################################ */\r
5459 \r
5460                 /*Register : mode_reg0 @ 0XFF010004</p>\r
5461 \r
5462                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback\r
5463                 PSU_UART1_MODE_REG0_CHMODE                                                      0x0\r
5464 \r
5465                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5\r
5466                 stop bits 10: 2 stop bits 11: reserved\r
5467                 PSU_UART1_MODE_REG0_NBSTOP                                                      0x0\r
5468 \r
5469                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity \r
5470                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity\r
5471                 PSU_UART1_MODE_REG0_PAR                                                         0x4\r
5472 \r
5473                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits\r
5474                 PSU_UART1_MODE_REG0_CHRL                                                        0x0\r
5475 \r
5476                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock\r
5477                 source is uart_ref_clk 1: clock source is uart_ref_clk/8\r
5478                 PSU_UART1_MODE_REG0_CLKS                                                        0x0\r
5479 \r
5480                 UART Mode Register\r
5481                 (OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  */\r
5482                 RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );\r
5483 \r
5484                 RegVal = Xil_In32 (UART1_MODE_REG0_OFFSET);\r
5485                 RegVal &= ~(RegMask);\r
5486                 RegVal |= ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT\r
5487                         | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT\r
5488                         | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT\r
5489                         | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT\r
5490                         | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT\r
5491                         |  0 ) & RegMask);\r
5492                 Xil_Out32 ( UART1_MODE_REG0_OFFSET , RegVal);\r
5493 \r
5494         /*############################################################################################################################ */\r
5495 \r
5496                 // : GPIO\r
5497                 // : ADMA TZ\r
5498                 /*Register : slcr_adma @ 0XFF4B0024</p>\r
5499 \r
5500                 TrustZone Classification for ADMA\r
5501                 PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF\r
5502 \r
5503                 RPU TrustZone settings\r
5504                 (OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  */\r
5505                 RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );\r
5506 \r
5507                 RegVal = Xil_In32 (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET);\r
5508                 RegVal &= ~(RegMask);\r
5509                 RegVal |= ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT\r
5510                         |  0 ) & RegMask);\r
5511                 Xil_Out32 ( LPD_SLCR_SECURE_SLCR_ADMA_OFFSET , RegVal);\r
5512 \r
5513         /*############################################################################################################################ */\r
5514 \r
5515                 // : CSU TAMPERING\r
5516                 // : CSU TAMPER STATUS\r
5517                 /*Register : tamper_status @ 0XFFCA5000</p>\r
5518 \r
5519                 CSU regsiter\r
5520                 PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0\r
5521 \r
5522                 External MIO\r
5523                 PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0\r
5524 \r
5525                 JTAG toggle detect\r
5526                 PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0\r
5527 \r
5528                 PL SEU error\r
5529                 PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0\r
5530 \r
5531                 AMS over temperature alarm for LPD\r
5532                 PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0\r
5533 \r
5534                 AMS over temperature alarm for APU\r
5535                 PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0\r
5536 \r
5537                 AMS voltage alarm for VCCPINT_FPD\r
5538                 PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0\r
5539 \r
5540                 AMS voltage alarm for VCCPINT_LPD\r
5541                 PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0\r
5542 \r
5543                 AMS voltage alarm for VCCPAUX\r
5544                 PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0\r
5545 \r
5546                 AMS voltage alarm for DDRPHY\r
5547                 PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0\r
5548 \r
5549                 AMS voltage alarm for PSIO bank 0/1/2\r
5550                 PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0\r
5551 \r
5552                 AMS voltage alarm for PSIO bank 3 (dedicated pins)\r
5553                 PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0\r
5554 \r
5555                 AMS voltaage alarm for GT\r
5556                 PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0\r
5557 \r
5558                 Tamper Response Status\r
5559                 (OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  */\r
5560                 RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );\r
5561 \r
5562                 RegVal = Xil_In32 (CSU_TAMPER_STATUS_OFFSET);\r
5563                 RegVal &= ~(RegMask);\r
5564                 RegVal |= ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT\r
5565                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT\r
5566                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT\r
5567                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT\r
5568                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT\r
5569                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT\r
5570                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT\r
5571                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT\r
5572                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT\r
5573                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT\r
5574                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT\r
5575                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT\r
5576                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT\r
5577                         |  0 ) & RegMask);\r
5578                 Xil_Out32 ( CSU_TAMPER_STATUS_OFFSET , RegVal);\r
5579 \r
5580         /*############################################################################################################################ */\r
5581 \r
5582                 // : CSU TAMPER RESPONSE\r
5583 \r
5584 }\r
5585 unsigned long psu_post_config() {\r
5586 \r
5587 }\r
5588 unsigned long psu_peripherals_powerdwn_data_3_0() {\r
5589                 // : POWER DOWN REQUEST INTERRUPT ENABLE\r
5590                 // : POWER DOWN TRIGGER\r
5591 \r
5592 }\r
5593 unsigned long psu_security_data_3_0() {\r
5594                 // : DDR XMPU0\r
5595                 // : DDR XMPU1\r
5596                 // : DDR XMPU2\r
5597                 // : DDR XMPU3\r
5598                 // : DDR XMPU4\r
5599                 // : DDR XMPU5\r
5600                 // : FPD XMPU\r
5601                 // : OCM XMPU\r
5602                 // : XPPU\r
5603                 // : MASTER ID LIST\r
5604                 /*Register : MASTER_ID00 @ 0XFF980100</p>\r
5605 \r
5606                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5607                 PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP                                               0\r
5608 \r
5609                 If set, only read transactions are allowed for the masters matching this register\r
5610                 PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR                                               0\r
5611 \r
5612                 Mask to be applied before comparing\r
5613                 PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM                                               0\r
5614 \r
5615                 Predefined Master ID for PMU\r
5616                 PSU_LPD_XPPU_CFG_MASTER_ID00_MID                                                0\r
5617 \r
5618                 Master ID 00 Register\r
5619                 (OFFSET, MASK, VALUE)      (0XFF980100, 0xC3FF03FFU ,0x00000000U)  */\r
5620                 RegMask = (LPD_XPPU_CFG_MASTER_ID00_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID00_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID00_MID_MASK |  0 );\r
5621 \r
5622                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID00_OFFSET);\r
5623                 RegVal &= ~(RegMask);\r
5624                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDP_SHIFT\r
5625                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDR_SHIFT\r
5626                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MIDM_SHIFT\r
5627                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID00_MID_SHIFT\r
5628                         |  0 ) & RegMask);\r
5629                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID00_OFFSET , RegVal);\r
5630 \r
5631         /*############################################################################################################################ */\r
5632 \r
5633                 /*Register : MASTER_ID01 @ 0XFF980104</p>\r
5634 \r
5635                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5636                 PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP                                               0\r
5637 \r
5638                 If set, only read transactions are allowed for the masters matching this register\r
5639                 PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR                                               0\r
5640 \r
5641                 Mask to be applied before comparing\r
5642                 PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM                                               0\r
5643 \r
5644                 Predefined Master ID for RPU0\r
5645                 PSU_LPD_XPPU_CFG_MASTER_ID01_MID                                                0\r
5646 \r
5647                 Master ID 01 Register\r
5648                 (OFFSET, MASK, VALUE)      (0XFF980104, 0xC3FF03FFU ,0x00000000U)  */\r
5649                 RegMask = (LPD_XPPU_CFG_MASTER_ID01_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID01_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID01_MID_MASK |  0 );\r
5650 \r
5651                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID01_OFFSET);\r
5652                 RegVal &= ~(RegMask);\r
5653                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDP_SHIFT\r
5654                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDR_SHIFT\r
5655                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MIDM_SHIFT\r
5656                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID01_MID_SHIFT\r
5657                         |  0 ) & RegMask);\r
5658                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID01_OFFSET , RegVal);\r
5659 \r
5660         /*############################################################################################################################ */\r
5661 \r
5662                 /*Register : MASTER_ID02 @ 0XFF980108</p>\r
5663 \r
5664                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5665                 PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP                                               0\r
5666 \r
5667                 If set, only read transactions are allowed for the masters matching this register\r
5668                 PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR                                               0\r
5669 \r
5670                 Mask to be applied before comparing\r
5671                 PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM                                               0\r
5672 \r
5673                 Predefined Master ID for RPU1\r
5674                 PSU_LPD_XPPU_CFG_MASTER_ID02_MID                                                0\r
5675 \r
5676                 Master ID 02 Register\r
5677                 (OFFSET, MASK, VALUE)      (0XFF980108, 0xC3FF03FFU ,0x00000000U)  */\r
5678                 RegMask = (LPD_XPPU_CFG_MASTER_ID02_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID02_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID02_MID_MASK |  0 );\r
5679 \r
5680                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID02_OFFSET);\r
5681                 RegVal &= ~(RegMask);\r
5682                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDP_SHIFT\r
5683                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDR_SHIFT\r
5684                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MIDM_SHIFT\r
5685                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID02_MID_SHIFT\r
5686                         |  0 ) & RegMask);\r
5687                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID02_OFFSET , RegVal);\r
5688 \r
5689         /*############################################################################################################################ */\r
5690 \r
5691                 /*Register : MASTER_ID03 @ 0XFF98010C</p>\r
5692 \r
5693                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5694                 PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP                                               0\r
5695 \r
5696                 If set, only read transactions are allowed for the masters matching this register\r
5697                 PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR                                               0\r
5698 \r
5699                 Mask to be applied before comparing\r
5700                 PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM                                               0\r
5701 \r
5702                 Predefined Master ID for APU\r
5703                 PSU_LPD_XPPU_CFG_MASTER_ID03_MID                                                0\r
5704 \r
5705                 Master ID 03 Register\r
5706                 (OFFSET, MASK, VALUE)      (0XFF98010C, 0xC3FF03FFU ,0x00000000U)  */\r
5707                 RegMask = (LPD_XPPU_CFG_MASTER_ID03_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID03_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID03_MID_MASK |  0 );\r
5708 \r
5709                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID03_OFFSET);\r
5710                 RegVal &= ~(RegMask);\r
5711                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDP_SHIFT\r
5712                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDR_SHIFT\r
5713                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MIDM_SHIFT\r
5714                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID03_MID_SHIFT\r
5715                         |  0 ) & RegMask);\r
5716                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID03_OFFSET , RegVal);\r
5717 \r
5718         /*############################################################################################################################ */\r
5719 \r
5720                 /*Register : MASTER_ID04 @ 0XFF980110</p>\r
5721 \r
5722                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5723                 PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP                                               0\r
5724 \r
5725                 If set, only read transactions are allowed for the masters matching this register\r
5726                 PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR                                               0\r
5727 \r
5728                 Mask to be applied before comparing\r
5729                 PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM                                               0\r
5730 \r
5731                 Predefined Master ID for A53 Core 0\r
5732                 PSU_LPD_XPPU_CFG_MASTER_ID04_MID                                                0\r
5733 \r
5734                 Master ID 04 Register\r
5735                 (OFFSET, MASK, VALUE)      (0XFF980110, 0xC3FF03FFU ,0x00000000U)  */\r
5736                 RegMask = (LPD_XPPU_CFG_MASTER_ID04_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID04_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID04_MID_MASK |  0 );\r
5737 \r
5738                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID04_OFFSET);\r
5739                 RegVal &= ~(RegMask);\r
5740                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDP_SHIFT\r
5741                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDR_SHIFT\r
5742                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MIDM_SHIFT\r
5743                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID04_MID_SHIFT\r
5744                         |  0 ) & RegMask);\r
5745                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID04_OFFSET , RegVal);\r
5746 \r
5747         /*############################################################################################################################ */\r
5748 \r
5749                 /*Register : MASTER_ID05 @ 0XFF980114</p>\r
5750 \r
5751                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5752                 PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP                                               0\r
5753 \r
5754                 If set, only read transactions are allowed for the masters matching this register\r
5755                 PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR                                               0\r
5756 \r
5757                 Mask to be applied before comparing\r
5758                 PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM                                               0\r
5759 \r
5760                 Predefined Master ID for A53 Core 1\r
5761                 PSU_LPD_XPPU_CFG_MASTER_ID05_MID                                                0\r
5762 \r
5763                 Master ID 05 Register\r
5764                 (OFFSET, MASK, VALUE)      (0XFF980114, 0xC3FF03FFU ,0x00000000U)  */\r
5765                 RegMask = (LPD_XPPU_CFG_MASTER_ID05_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID05_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID05_MID_MASK |  0 );\r
5766 \r
5767                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID05_OFFSET);\r
5768                 RegVal &= ~(RegMask);\r
5769                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDP_SHIFT\r
5770                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDR_SHIFT\r
5771                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MIDM_SHIFT\r
5772                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID05_MID_SHIFT\r
5773                         |  0 ) & RegMask);\r
5774                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID05_OFFSET , RegVal);\r
5775 \r
5776         /*############################################################################################################################ */\r
5777 \r
5778                 /*Register : MASTER_ID06 @ 0XFF980118</p>\r
5779 \r
5780                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5781                 PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP                                               0\r
5782 \r
5783                 If set, only read transactions are allowed for the masters matching this register\r
5784                 PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR                                               0\r
5785 \r
5786                 Mask to be applied before comparing\r
5787                 PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM                                               0\r
5788 \r
5789                 Predefined Master ID for A53 Core 2\r
5790                 PSU_LPD_XPPU_CFG_MASTER_ID06_MID                                                0\r
5791 \r
5792                 Master ID 06 Register\r
5793                 (OFFSET, MASK, VALUE)      (0XFF980118, 0xC3FF03FFU ,0x00000000U)  */\r
5794                 RegMask = (LPD_XPPU_CFG_MASTER_ID06_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID06_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID06_MID_MASK |  0 );\r
5795 \r
5796                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID06_OFFSET);\r
5797                 RegVal &= ~(RegMask);\r
5798                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDP_SHIFT\r
5799                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDR_SHIFT\r
5800                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MIDM_SHIFT\r
5801                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID06_MID_SHIFT\r
5802                         |  0 ) & RegMask);\r
5803                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID06_OFFSET , RegVal);\r
5804 \r
5805         /*############################################################################################################################ */\r
5806 \r
5807                 /*Register : MASTER_ID07 @ 0XFF98011C</p>\r
5808 \r
5809                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5810                 PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP                                               0\r
5811 \r
5812                 If set, only read transactions are allowed for the masters matching this register\r
5813                 PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR                                               0\r
5814 \r
5815                 Mask to be applied before comparing\r
5816                 PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM                                               0\r
5817 \r
5818                 Predefined Master ID for A53 Core 3\r
5819                 PSU_LPD_XPPU_CFG_MASTER_ID07_MID                                                0\r
5820 \r
5821                 Master ID 07 Register\r
5822                 (OFFSET, MASK, VALUE)      (0XFF98011C, 0xC3FF03FFU ,0x00000000U)  */\r
5823                 RegMask = (LPD_XPPU_CFG_MASTER_ID07_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID07_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID07_MID_MASK |  0 );\r
5824 \r
5825                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID07_OFFSET);\r
5826                 RegVal &= ~(RegMask);\r
5827                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDP_SHIFT\r
5828                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDR_SHIFT\r
5829                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MIDM_SHIFT\r
5830                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID07_MID_SHIFT\r
5831                         |  0 ) & RegMask);\r
5832                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID07_OFFSET , RegVal);\r
5833 \r
5834         /*############################################################################################################################ */\r
5835 \r
5836                 /*Register : MASTER_ID08 @ 0XFF980120</p>\r
5837 \r
5838                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5839                 PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP                                               0\r
5840 \r
5841                 If set, only read transactions are allowed for the masters matching this register\r
5842                 PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR                                               0\r
5843 \r
5844                 Mask to be applied before comparing\r
5845                 PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM                                               0\r
5846 \r
5847                 Programmable Master ID\r
5848                 PSU_LPD_XPPU_CFG_MASTER_ID08_MID                                                0\r
5849 \r
5850                 Master ID 08 Register\r
5851                 (OFFSET, MASK, VALUE)      (0XFF980120, 0xC3FF03FFU ,0x00000000U)  */\r
5852                 RegMask = (LPD_XPPU_CFG_MASTER_ID08_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID08_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID08_MID_MASK |  0 );\r
5853 \r
5854                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID08_OFFSET);\r
5855                 RegVal &= ~(RegMask);\r
5856                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDP_SHIFT\r
5857                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDR_SHIFT\r
5858                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MIDM_SHIFT\r
5859                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID08_MID_SHIFT\r
5860                         |  0 ) & RegMask);\r
5861                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID08_OFFSET , RegVal);\r
5862 \r
5863         /*############################################################################################################################ */\r
5864 \r
5865                 /*Register : MASTER_ID09 @ 0XFF980124</p>\r
5866 \r
5867                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5868                 PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP                                               0\r
5869 \r
5870                 If set, only read transactions are allowed for the masters matching this register\r
5871                 PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR                                               0\r
5872 \r
5873                 Mask to be applied before comparing\r
5874                 PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM                                               0\r
5875 \r
5876                 Programmable Master ID\r
5877                 PSU_LPD_XPPU_CFG_MASTER_ID09_MID                                                0\r
5878 \r
5879                 Master ID 09 Register\r
5880                 (OFFSET, MASK, VALUE)      (0XFF980124, 0xC3FF03FFU ,0x00000000U)  */\r
5881                 RegMask = (LPD_XPPU_CFG_MASTER_ID09_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID09_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID09_MID_MASK |  0 );\r
5882 \r
5883                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID09_OFFSET);\r
5884                 RegVal &= ~(RegMask);\r
5885                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDP_SHIFT\r
5886                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDR_SHIFT\r
5887                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MIDM_SHIFT\r
5888                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID09_MID_SHIFT\r
5889                         |  0 ) & RegMask);\r
5890                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID09_OFFSET , RegVal);\r
5891 \r
5892         /*############################################################################################################################ */\r
5893 \r
5894                 /*Register : MASTER_ID10 @ 0XFF980128</p>\r
5895 \r
5896                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5897                 PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP                                               0\r
5898 \r
5899                 If set, only read transactions are allowed for the masters matching this register\r
5900                 PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR                                               0\r
5901 \r
5902                 Mask to be applied before comparing\r
5903                 PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM                                               0\r
5904 \r
5905                 Programmable Master ID\r
5906                 PSU_LPD_XPPU_CFG_MASTER_ID10_MID                                                0\r
5907 \r
5908                 Master ID 10 Register\r
5909                 (OFFSET, MASK, VALUE)      (0XFF980128, 0xC3FF03FFU ,0x00000000U)  */\r
5910                 RegMask = (LPD_XPPU_CFG_MASTER_ID10_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID10_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID10_MID_MASK |  0 );\r
5911 \r
5912                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID10_OFFSET);\r
5913                 RegVal &= ~(RegMask);\r
5914                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDP_SHIFT\r
5915                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDR_SHIFT\r
5916                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MIDM_SHIFT\r
5917                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID10_MID_SHIFT\r
5918                         |  0 ) & RegMask);\r
5919                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID10_OFFSET , RegVal);\r
5920 \r
5921         /*############################################################################################################################ */\r
5922 \r
5923                 /*Register : MASTER_ID11 @ 0XFF98012C</p>\r
5924 \r
5925                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5926                 PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP                                               0\r
5927 \r
5928                 If set, only read transactions are allowed for the masters matching this register\r
5929                 PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR                                               0\r
5930 \r
5931                 Mask to be applied before comparing\r
5932                 PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM                                               0\r
5933 \r
5934                 Programmable Master ID\r
5935                 PSU_LPD_XPPU_CFG_MASTER_ID11_MID                                                0\r
5936 \r
5937                 Master ID 11 Register\r
5938                 (OFFSET, MASK, VALUE)      (0XFF98012C, 0xC3FF03FFU ,0x00000000U)  */\r
5939                 RegMask = (LPD_XPPU_CFG_MASTER_ID11_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID11_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID11_MID_MASK |  0 );\r
5940 \r
5941                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID11_OFFSET);\r
5942                 RegVal &= ~(RegMask);\r
5943                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDP_SHIFT\r
5944                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDR_SHIFT\r
5945                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MIDM_SHIFT\r
5946                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID11_MID_SHIFT\r
5947                         |  0 ) & RegMask);\r
5948                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID11_OFFSET , RegVal);\r
5949 \r
5950         /*############################################################################################################################ */\r
5951 \r
5952                 /*Register : MASTER_ID12 @ 0XFF980130</p>\r
5953 \r
5954                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5955                 PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP                                               0\r
5956 \r
5957                 If set, only read transactions are allowed for the masters matching this register\r
5958                 PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR                                               0\r
5959 \r
5960                 Mask to be applied before comparing\r
5961                 PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM                                               0\r
5962 \r
5963                 Programmable Master ID\r
5964                 PSU_LPD_XPPU_CFG_MASTER_ID12_MID                                                0\r
5965 \r
5966                 Master ID 12 Register\r
5967                 (OFFSET, MASK, VALUE)      (0XFF980130, 0xC3FF03FFU ,0x00000000U)  */\r
5968                 RegMask = (LPD_XPPU_CFG_MASTER_ID12_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID12_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID12_MID_MASK |  0 );\r
5969 \r
5970                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID12_OFFSET);\r
5971                 RegVal &= ~(RegMask);\r
5972                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDP_SHIFT\r
5973                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDR_SHIFT\r
5974                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MIDM_SHIFT\r
5975                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID12_MID_SHIFT\r
5976                         |  0 ) & RegMask);\r
5977                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID12_OFFSET , RegVal);\r
5978 \r
5979         /*############################################################################################################################ */\r
5980 \r
5981                 /*Register : MASTER_ID13 @ 0XFF980134</p>\r
5982 \r
5983                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
5984                 PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP                                               0\r
5985 \r
5986                 If set, only read transactions are allowed for the masters matching this register\r
5987                 PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR                                               0\r
5988 \r
5989                 Mask to be applied before comparing\r
5990                 PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM                                               0\r
5991 \r
5992                 Programmable Master ID\r
5993                 PSU_LPD_XPPU_CFG_MASTER_ID13_MID                                                0\r
5994 \r
5995                 Master ID 13 Register\r
5996                 (OFFSET, MASK, VALUE)      (0XFF980134, 0xC3FF03FFU ,0x00000000U)  */\r
5997                 RegMask = (LPD_XPPU_CFG_MASTER_ID13_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID13_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID13_MID_MASK |  0 );\r
5998 \r
5999                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID13_OFFSET);\r
6000                 RegVal &= ~(RegMask);\r
6001                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDP_SHIFT\r
6002                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDR_SHIFT\r
6003                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MIDM_SHIFT\r
6004                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID13_MID_SHIFT\r
6005                         |  0 ) & RegMask);\r
6006                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID13_OFFSET , RegVal);\r
6007 \r
6008         /*############################################################################################################################ */\r
6009 \r
6010                 /*Register : MASTER_ID14 @ 0XFF980138</p>\r
6011 \r
6012                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6013                 PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP                                               0\r
6014 \r
6015                 If set, only read transactions are allowed for the masters matching this register\r
6016                 PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR                                               0\r
6017 \r
6018                 Mask to be applied before comparing\r
6019                 PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM                                               0\r
6020 \r
6021                 Programmable Master ID\r
6022                 PSU_LPD_XPPU_CFG_MASTER_ID14_MID                                                0\r
6023 \r
6024                 Master ID 14 Register\r
6025                 (OFFSET, MASK, VALUE)      (0XFF980138, 0xC3FF03FFU ,0x00000000U)  */\r
6026                 RegMask = (LPD_XPPU_CFG_MASTER_ID14_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID14_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID14_MID_MASK |  0 );\r
6027 \r
6028                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID14_OFFSET);\r
6029                 RegVal &= ~(RegMask);\r
6030                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDP_SHIFT\r
6031                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDR_SHIFT\r
6032                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MIDM_SHIFT\r
6033                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID14_MID_SHIFT\r
6034                         |  0 ) & RegMask);\r
6035                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID14_OFFSET , RegVal);\r
6036 \r
6037         /*############################################################################################################################ */\r
6038 \r
6039                 /*Register : MASTER_ID15 @ 0XFF98013C</p>\r
6040 \r
6041                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6042                 PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP                                               0\r
6043 \r
6044                 If set, only read transactions are allowed for the masters matching this register\r
6045                 PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR                                               0\r
6046 \r
6047                 Mask to be applied before comparing\r
6048                 PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM                                               0\r
6049 \r
6050                 Programmable Master ID\r
6051                 PSU_LPD_XPPU_CFG_MASTER_ID15_MID                                                0\r
6052 \r
6053                 Master ID 15 Register\r
6054                 (OFFSET, MASK, VALUE)      (0XFF98013C, 0xC3FF03FFU ,0x00000000U)  */\r
6055                 RegMask = (LPD_XPPU_CFG_MASTER_ID15_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID15_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID15_MID_MASK |  0 );\r
6056 \r
6057                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID15_OFFSET);\r
6058                 RegVal &= ~(RegMask);\r
6059                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDP_SHIFT\r
6060                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDR_SHIFT\r
6061                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MIDM_SHIFT\r
6062                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID15_MID_SHIFT\r
6063                         |  0 ) & RegMask);\r
6064                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID15_OFFSET , RegVal);\r
6065 \r
6066         /*############################################################################################################################ */\r
6067 \r
6068                 /*Register : MASTER_ID16 @ 0XFF980140</p>\r
6069 \r
6070                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6071                 PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP                                               0\r
6072 \r
6073                 If set, only read transactions are allowed for the masters matching this register\r
6074                 PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR                                               0\r
6075 \r
6076                 Mask to be applied before comparing\r
6077                 PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM                                               0\r
6078 \r
6079                 Programmable Master ID\r
6080                 PSU_LPD_XPPU_CFG_MASTER_ID16_MID                                                0\r
6081 \r
6082                 Master ID 16 Register\r
6083                 (OFFSET, MASK, VALUE)      (0XFF980140, 0xC3FF03FFU ,0x00000000U)  */\r
6084                 RegMask = (LPD_XPPU_CFG_MASTER_ID16_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID16_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID16_MID_MASK |  0 );\r
6085 \r
6086                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID16_OFFSET);\r
6087                 RegVal &= ~(RegMask);\r
6088                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDP_SHIFT\r
6089                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDR_SHIFT\r
6090                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MIDM_SHIFT\r
6091                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID16_MID_SHIFT\r
6092                         |  0 ) & RegMask);\r
6093                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID16_OFFSET , RegVal);\r
6094 \r
6095         /*############################################################################################################################ */\r
6096 \r
6097                 /*Register : MASTER_ID17 @ 0XFF980144</p>\r
6098 \r
6099                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6100                 PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP                                               0\r
6101 \r
6102                 If set, only read transactions are allowed for the masters matching this register\r
6103                 PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR                                               0\r
6104 \r
6105                 Mask to be applied before comparing\r
6106                 PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM                                               0\r
6107 \r
6108                 Programmable Master ID\r
6109                 PSU_LPD_XPPU_CFG_MASTER_ID17_MID                                                0\r
6110 \r
6111                 Master ID 17 Register\r
6112                 (OFFSET, MASK, VALUE)      (0XFF980144, 0xC3FF03FFU ,0x00000000U)  */\r
6113                 RegMask = (LPD_XPPU_CFG_MASTER_ID17_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID17_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID17_MID_MASK |  0 );\r
6114 \r
6115                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID17_OFFSET);\r
6116                 RegVal &= ~(RegMask);\r
6117                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDP_SHIFT\r
6118                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDR_SHIFT\r
6119                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MIDM_SHIFT\r
6120                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID17_MID_SHIFT\r
6121                         |  0 ) & RegMask);\r
6122                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID17_OFFSET , RegVal);\r
6123 \r
6124         /*############################################################################################################################ */\r
6125 \r
6126                 /*Register : MASTER_ID18 @ 0XFF980148</p>\r
6127 \r
6128                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6129                 PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP                                               0\r
6130 \r
6131                 If set, only read transactions are allowed for the masters matching this register\r
6132                 PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR                                               0\r
6133 \r
6134                 Mask to be applied before comparing\r
6135                 PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM                                               0\r
6136 \r
6137                 Programmable Master ID\r
6138                 PSU_LPD_XPPU_CFG_MASTER_ID18_MID                                                0\r
6139 \r
6140                 Master ID 18 Register\r
6141                 (OFFSET, MASK, VALUE)      (0XFF980148, 0xC3FF03FFU ,0x00000000U)  */\r
6142                 RegMask = (LPD_XPPU_CFG_MASTER_ID18_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID18_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID18_MID_MASK |  0 );\r
6143 \r
6144                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID18_OFFSET);\r
6145                 RegVal &= ~(RegMask);\r
6146                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDP_SHIFT\r
6147                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDR_SHIFT\r
6148                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MIDM_SHIFT\r
6149                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID18_MID_SHIFT\r
6150                         |  0 ) & RegMask);\r
6151                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID18_OFFSET , RegVal);\r
6152 \r
6153         /*############################################################################################################################ */\r
6154 \r
6155                 /*Register : MASTER_ID19 @ 0XFF98014C</p>\r
6156 \r
6157                 Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)\r
6158                 PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP                                               0\r
6159 \r
6160                 If set, only read transactions are allowed for the masters matching this register\r
6161                 PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR                                               0\r
6162 \r
6163                 Mask to be applied before comparing\r
6164                 PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM                                               0\r
6165 \r
6166                 Programmable Master ID\r
6167                 PSU_LPD_XPPU_CFG_MASTER_ID19_MID                                                0\r
6168 \r
6169                 Master ID 19 Register\r
6170                 (OFFSET, MASK, VALUE)      (0XFF98014C, 0xC3FF03FFU ,0x00000000U)  */\r
6171                 RegMask = (LPD_XPPU_CFG_MASTER_ID19_MIDP_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDR_MASK | LPD_XPPU_CFG_MASTER_ID19_MIDM_MASK | LPD_XPPU_CFG_MASTER_ID19_MID_MASK |  0 );\r
6172 \r
6173                 RegVal = Xil_In32 (LPD_XPPU_CFG_MASTER_ID19_OFFSET);\r
6174                 RegVal &= ~(RegMask);\r
6175                 RegVal |= ((0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDP_SHIFT\r
6176                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDR_SHIFT\r
6177                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MIDM_SHIFT\r
6178                         | 0x00000000U << LPD_XPPU_CFG_MASTER_ID19_MID_SHIFT\r
6179                         |  0 ) & RegMask);\r
6180                 Xil_Out32 ( LPD_XPPU_CFG_MASTER_ID19_OFFSET , RegVal);\r
6181 \r
6182         /*############################################################################################################################ */\r
6183 \r
6184                 // : APERTURE PERMISIION LIST\r
6185 \r
6186 }\r
6187 /**\r
6188  * CRL_APB Base Address\r
6189  */\r
6190 #define CRL_APB_BASEADDR      0XFF5E0000U\r
6191 #define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )\r
6192 #define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )\r
6193 #define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )\r
6194 #define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )\r
6195 #define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )\r
6196 \r
6197 /**\r
6198  * CRF_APB Base Address\r
6199  */\r
6200 #define CRF_APB_BASEADDR      0XFD1A0000U\r
6201 \r
6202 #define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )\r
6203 #define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )\r
6204 #define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )\r
6205 \r
6206 void init_ddrc()\r
6207 {\r
6208 \r
6209         Xil_Out32(  0XFD1A0108, 0x0000000F)  ; //#RST_DDR_SS 0xFE500108\r
6210                 Xil_Out32(  0xFD070000, 0x41040001)  ; //#MSTR\r
6211                 Xil_Out32(  0xFD070034, 0x00404310)  ; //#PWRTMG\r
6212                 Xil_Out32(  0xFD070064, 0x0040001E)  ; //#RFSHTMG \r
6213                 Xil_Out32(  0xFD070070, 0x00000010)  ; //#ECCCFG0\r
6214                 Xil_Out32(  0xFD070074, 0x00000000)  ; //#ECCCFG1\r
6215                 Xil_Out32(  0xFD0700C4, 0x10000200)  ; //#CRCPARCTL1\r
6216                 Xil_Out32(  0xFD0700C8, 0x0030051F)  ; //#CRCPARCTL2\r
6217                 Xil_Out32(  0xFD0700D0, 0x40020004)  ; //#INIT0  \r
6218                 Xil_Out32(  0xFD0700D4, 0x00010000)  ; //#INIT1 \r
6219                 Xil_Out32(  0xFD0700D8, 0x00001205)  ; //#INIT2\r
6220                 Xil_Out32(  0xFD0700DC, 0x09300000)  ; //#INIT3\r
6221                 Xil_Out32(  0xFD0700E0, 0x02080000)  ; //#INIT4\r
6222                 Xil_Out32(  0xFD0700E4, 0x00110004)  ; //#INIT5\r
6223                 Xil_Out32(  0xFD070100, 0x090E110A)  ; //#DRAMTMG0\r
6224                 Xil_Out32(  0xFD070104, 0x0007020E)  ; //#DRAMTMG1\r
6225                 Xil_Out32(  0xFD070108, 0x03040407)  ; //#DRAMTMG2\r
6226                 Xil_Out32(  0xFD07010C, 0x00502006)  ; //#DRAMTMG3\r
6227                 Xil_Out32(  0xFD070110, 0x04020205)  ; //#DRAMTMG4\r
6228                 Xil_Out32(  0xFD070114, 0x03030202)  ; //#DRAMTMG5\r
6229                 Xil_Out32(  0xFD070118, 0x01010003)  ; //#DRAMTMG6\r
6230                 Xil_Out32(  0xFD07011C, 0x00000101)  ; //#DRAMTMG7\r
6231                 Xil_Out32(  0xFD070120, 0x03030903)  ; //#DRAMTMG8\r
6232                 Xil_Out32(  0xFD070130, 0x00020608)  ; //#DRAMTMG12\r
6233                 Xil_Out32(  0xFD070180, 0x00800020)  ; //#ZQCTL0\r
6234                 Xil_Out32(  0xFD070184, 0x0200CB52)  ; //#ZQCTL1\r
6235                 Xil_Out32(  0xFD070190, 0x02838204)  ; //#DFITMG0 \r
6236                 Xil_Out32(  0xFD070194, 0x00020404)  ; //#DFITMG1 \r
6237                 Xil_Out32(  0xFD0701A4, 0x00010087)  ; //#DFIUPD1\r
6238                 Xil_Out32(  0xFD0701B0, 0x00000001)  ; //#DFIMISC #change-reset value\r
6239                 Xil_Out32(  0xFD0701B4, 0x00000202)  ; //#DFITMG2\r
6240                 Xil_Out32(  0xFD0701C0, 0x00000000)  ; //#DBICTL\r
6241                 Xil_Out32(  0xFD070200, 0x0000001F)  ; //#ADDRMAP0\r
6242                 Xil_Out32(  0xFD070204, 0x00080808)  ; //#ADDRMAP1\r
6243                 Xil_Out32(  0xFD070208, 0x00000000)  ; //#ADDRMAP2\r
6244                 Xil_Out32(  0xFD07020C, 0x00000000)  ; //#ADDRMAP3\r
6245                 Xil_Out32(  0xFD070210, 0x00000F0F)  ; //#ADDRMAP4\r
6246                 Xil_Out32(  0xFD070214, 0x07070707)  ; //#ADDRMAP5 \r
6247                 Xil_Out32(  0xFD070218, 0x07070707)  ; //#ADDRMAP6\r
6248                 Xil_Out32(  0xFD07021C, 0x00000F0F)  ; //#ADDRMAP7\r
6249                 Xil_Out32(  0xFD070220, 0x00000000)  ; //#ADDRMAP8\r
6250                 Xil_Out32(  0xFD070240, 0x06000604)  ; //#ODTCFG\r
6251                 Xil_Out32(  0xFD070244, 0x00000001)  ; //#ODTMAP\r
6252                 Xil_Out32(  0xFD070250, 0x01002001)  ; //#SCHED\r
6253                 Xil_Out32(  0xFD070264, 0x08000040)  ; //#PERFLPR1\r
6254                 Xil_Out32(  0xFD07026C, 0x08000040)  ; //#PERFWR1\r
6255                 Xil_Out32(  0xFD070294, 0x00000001)  ; //#DQMAP5\r
6256                 Xil_Out32(  0xFD07030C, 0x00000000)  ; //#DBGCMD\r
6257                 Xil_Out32(  0xFD070320, 0x00000000)  ; //#SWCTL\r
6258                 Xil_Out32(  0xFD070400, 0x00000001)  ; //#PCCFG\r
6259                 Xil_Out32(  0xFD070404, 0x0000600F)  ; //#PCFGR_0\r
6260                 Xil_Out32(  0xFD070408, 0x0000600F)  ; //#PCFGW_0\r
6261                 Xil_Out32(  0xFD070490, 0x00000001)  ; //#PCTRL_0\r
6262                 Xil_Out32(  0xFD070494, 0x0021000B)  ; //#PCFGQOS0_0\r
6263                 Xil_Out32(  0xFD070498, 0x004F004F)  ; //#PCFGQOS1_0\r
6264                 Xil_Out32(  0xFD0704B4, 0x0000600F)  ; //#PCFGR_1\r
6265                 Xil_Out32(  0xFD0704B8, 0x0000600F)  ; //#PCFGW_1\r
6266                 Xil_Out32(  0xFD070540, 0x00000001)  ; //#PCTRL_1\r
6267                 Xil_Out32(  0xFD070544, 0x02000B03)  ; //#PCFGQOS0_1\r
6268                 Xil_Out32(  0xFD070548, 0x00010040)  ; //#PCFGQOS1_1\r
6269                 Xil_Out32(  0xFD070564, 0x0000600F)  ; //#PCFGR_2\r
6270                 Xil_Out32(  0xFD070568, 0x0000600F)  ; //#PCFGW_2\r
6271                 Xil_Out32(  0xFD0705F0, 0x00000001)  ; //#PCTRL_2\r
6272                 Xil_Out32(  0xFD0705F4, 0x02000B03)  ; //#PCFGQOS0_2\r
6273                 Xil_Out32(  0xFD0705F8, 0x00010040)  ; //#PCFGQOS1_2\r
6274                 Xil_Out32(  0xFD070614, 0x0000600F)  ; //#PCFGR_3\r
6275                 Xil_Out32(  0xFD070618, 0x0000600F)  ; //#PCFGW_3\r
6276                 Xil_Out32(  0xFD0706A0, 0x00000001)  ; //#PCTRL_3\r
6277                 Xil_Out32(  0xFD0706A4, 0x00100003)  ; //#PCFGQOS0_3\r
6278                 Xil_Out32(  0xFD0706A8, 0x002F004F)  ; //#PCFGQOS1_3\r
6279                 Xil_Out32(  0xFD0706AC, 0x00100007)  ; //#PCFGWQOS0_3\r
6280                 Xil_Out32(  0xFD0706B0, 0x0000004F)  ; //#PCFGWQOS1_3\r
6281                 Xil_Out32(  0xFD0706C4, 0x0000600F)  ; //#PCFGR_4\r
6282                 Xil_Out32(  0xFD0706C8, 0x0000600F)  ; //#PCFGW_4\r
6283                 Xil_Out32(  0xFD070750, 0x00000001)  ; //#PCTRL_4\r
6284                 Xil_Out32(  0xFD070754, 0x00100003)  ; //#PCFGQOS0_4\r
6285                 Xil_Out32(  0xFD070758, 0x002F004F)  ; //#PCFGQOS1_4\r
6286                 Xil_Out32(  0xFD07075C, 0x00100007)  ; //#PCFGWQOS0_4\r
6287                 Xil_Out32(  0xFD070760, 0x0000004F)  ; //#PCFGWQOS1_4\r
6288                 Xil_Out32(  0xFD070774, 0x0000600F)  ; //#PCFGR_5\r
6289                 Xil_Out32(  0xFD070778, 0x0000600F)  ; //#PCFGW_5\r
6290                 Xil_Out32(  0xFD070800, 0x00000001)  ; //#PCTRL_5\r
6291                 Xil_Out32(  0xFD070804, 0x00100003)  ; //#PCFGQOS0_5\r
6292                 Xil_Out32(  0xFD070808, 0x002F004F)  ; //#PCFGQOS1_5\r
6293                 Xil_Out32(  0xFD07080C, 0x00100007)  ; //#PCFGWQOS0_5\r
6294                 Xil_Out32(  0xFD070810, 0x0000004F)  ; //#PCFGWQOS1_5\r
6295                 Xil_Out32(  0xFD070F04, 0x00000000)  ; //#SARBASE0\r
6296                 Xil_Out32(  0xFD070F08, 0x00000000)  ; //#SARSIZE0\r
6297                 Xil_Out32(  0xFD070F0C, 0x00000010)  ; //#SARBASE1\r
6298                 Xil_Out32(  0xFD070F10, 0x0000000F)  ; //#SARSIZE1\r
6299                       \r
6300                 Xil_In32( 0XFD1A0108)  ; //#RST_DDR_SS 0xFE500108\r
6301                 Xil_Out32(  0XFD1A0108, 0x00000000)  ; //#RST_DDR_SS 0xFE500108 0\r
6302                 Xil_In32( 0XFD1A0108           )  ; //#RST_DDR_SS 0xFE500108  \r
6303 \r
6304         /* Take DDR out of reset */\r
6305         Xil_Out32( CRF_APB_RST_DDR_SS, 0x00000000);\r
6306 }\r
6307 \r
6308 void init_peripheral()\r
6309 {\r
6310         unsigned int RegValue;\r
6311 \r
6312         /* Turn on IOU Clock */\r
6313         Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);\r
6314 \r
6315         /* Release all resets in the IOU */\r
6316         Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);\r
6317         Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);\r
6318         Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);\r
6319 \r
6320         /* Activate GPU clocks */\r
6321         Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);\r
6322 \r
6323         /* Take LPD out of reset except R5 */\r
6324         RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);\r
6325         RegValue &= 0x3;\r
6326         Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);\r
6327 \r
6328         /* Take most of FPD out of reset */\r
6329         Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);\r
6330 }\r
6331 int\r
6332 psu_init() \r
6333 {\r
6334     psu_mio_init_data ();\r
6335     psu_pll_init_data ();\r
6336     psu_clock_init_data ();\r
6337     psu_ddr_init_data_3_0 ();\r
6338     init_ddrc();\r
6339     init_peripheral ();\r
6340     psu_peripherals_init_data_3_0 ();\r
6341     psu_peripherals_powerdwn_data_3_0 ();\r
6342     psu_security_data_3_0();\r
6343     return 0;\r
6344 }\r