1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following condition is met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _SAMA5_DBGU_INSTANCE_
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31 #define _SAMA5_DBGU_INSTANCE_
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33 /* ========== Register definition for DBGU peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_DBGU_CR (0xFFFFEE00U) /**< \brief (DBGU) Control Register */
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36 #define REG_DBGU_MR (0xFFFFEE04U) /**< \brief (DBGU) Mode Register */
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37 #define REG_DBGU_IER (0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */
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38 #define REG_DBGU_IDR (0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */
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39 #define REG_DBGU_IMR (0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */
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40 #define REG_DBGU_SR (0xFFFFEE14U) /**< \brief (DBGU) Status Register */
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41 #define REG_DBGU_RHR (0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */
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42 #define REG_DBGU_THR (0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */
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43 #define REG_DBGU_BRGR (0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */
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44 #define REG_DBGU_CIDR (0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */
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45 #define REG_DBGU_EXID (0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */
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46 #define REG_DBGU_FNR (0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */
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48 #define REG_DBGU_CR (*(WoReg*)0xFFFFEE00U) /**< \brief (DBGU) Control Register */
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49 #define REG_DBGU_MR (*(RwReg*)0xFFFFEE04U) /**< \brief (DBGU) Mode Register */
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50 #define REG_DBGU_IER (*(WoReg*)0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */
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51 #define REG_DBGU_IDR (*(WoReg*)0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */
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52 #define REG_DBGU_IMR (*(RoReg*)0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */
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53 #define REG_DBGU_SR (*(RoReg*)0xFFFFEE14U) /**< \brief (DBGU) Status Register */
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54 #define REG_DBGU_RHR (*(RoReg*)0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */
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55 #define REG_DBGU_THR (*(WoReg*)0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */
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56 #define REG_DBGU_BRGR (*(RwReg*)0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */
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57 #define REG_DBGU_CIDR (*(RoReg*)0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */
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58 #define REG_DBGU_EXID (*(RoReg*)0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */
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59 #define REG_DBGU_FNR (*(RwReg*)0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */
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60 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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62 #endif /* _SAMA5_DBGU_INSTANCE_ */
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