1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following condition is met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _SAMA5_LCDC_INSTANCE_
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31 #define _SAMA5_LCDC_INSTANCE_
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33 /* ========== Register definition for LCDC peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_LCDC_LCDCFG0 (0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */
\r
36 #define REG_LCDC_LCDCFG1 (0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */
\r
37 #define REG_LCDC_LCDCFG2 (0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */
\r
38 #define REG_LCDC_LCDCFG3 (0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */
\r
39 #define REG_LCDC_LCDCFG4 (0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */
\r
40 #define REG_LCDC_LCDCFG5 (0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */
\r
41 #define REG_LCDC_LCDCFG6 (0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */
\r
42 #define REG_LCDC_LCDEN (0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */
\r
43 #define REG_LCDC_LCDDIS (0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */
\r
44 #define REG_LCDC_LCDSR (0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */
\r
45 #define REG_LCDC_LCDIER (0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */
\r
46 #define REG_LCDC_LCDIDR (0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */
\r
47 #define REG_LCDC_LCDIMR (0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */
\r
48 #define REG_LCDC_LCDISR (0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */
\r
49 #define REG_LCDC_BASECHER (0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */
\r
50 #define REG_LCDC_BASECHDR (0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */
\r
51 #define REG_LCDC_BASECHSR (0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */
\r
52 #define REG_LCDC_BASEIER (0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */
\r
53 #define REG_LCDC_BASEIDR (0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */
\r
54 #define REG_LCDC_BASEIMR (0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */
\r
55 #define REG_LCDC_BASEISR (0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */
\r
56 #define REG_LCDC_BASEHEAD (0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */
\r
57 #define REG_LCDC_BASEADDR (0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */
\r
58 #define REG_LCDC_BASECTRL (0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */
\r
59 #define REG_LCDC_BASENEXT (0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */
\r
60 #define REG_LCDC_BASECFG0 (0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */
\r
61 #define REG_LCDC_BASECFG1 (0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */
\r
62 #define REG_LCDC_BASECFG2 (0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */
\r
63 #define REG_LCDC_BASECFG3 (0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */
\r
64 #define REG_LCDC_BASECFG4 (0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */
\r
65 #define REG_LCDC_BASECFG5 (0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */
\r
66 #define REG_LCDC_BASECFG6 (0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */
\r
67 #define REG_LCDC_OVR1CHER (0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */
\r
68 #define REG_LCDC_OVR1CHDR (0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */
\r
69 #define REG_LCDC_OVR1CHSR (0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */
\r
70 #define REG_LCDC_OVR1IER (0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */
\r
71 #define REG_LCDC_OVR1IDR (0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */
\r
72 #define REG_LCDC_OVR1IMR (0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */
\r
73 #define REG_LCDC_OVR1ISR (0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */
\r
74 #define REG_LCDC_OVR1HEAD (0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */
\r
75 #define REG_LCDC_OVR1ADDR (0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */
\r
76 #define REG_LCDC_OVR1CTRL (0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */
\r
77 #define REG_LCDC_OVR1NEXT (0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */
\r
78 #define REG_LCDC_OVR1CFG0 (0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */
\r
79 #define REG_LCDC_OVR1CFG1 (0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */
\r
80 #define REG_LCDC_OVR1CFG2 (0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */
\r
81 #define REG_LCDC_OVR1CFG3 (0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */
\r
82 #define REG_LCDC_OVR1CFG4 (0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */
\r
83 #define REG_LCDC_OVR1CFG5 (0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */
\r
84 #define REG_LCDC_OVR1CFG6 (0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */
\r
85 #define REG_LCDC_OVR1CFG7 (0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */
\r
86 #define REG_LCDC_OVR1CFG8 (0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */
\r
87 #define REG_LCDC_OVR1CFG9 (0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */
\r
88 #define REG_LCDC_OVR2CHER (0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */
\r
89 #define REG_LCDC_OVR2CHDR (0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */
\r
90 #define REG_LCDC_OVR2CHSR (0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */
\r
91 #define REG_LCDC_OVR2IER (0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */
\r
92 #define REG_LCDC_OVR2IDR (0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */
\r
93 #define REG_LCDC_OVR2IMR (0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */
\r
94 #define REG_LCDC_OVR2ISR (0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */
\r
95 #define REG_LCDC_OVR2HEAD (0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */
\r
96 #define REG_LCDC_OVR2ADDR (0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */
\r
97 #define REG_LCDC_OVR2CTRL (0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */
\r
98 #define REG_LCDC_OVR2NEXT (0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */
\r
99 #define REG_LCDC_OVR2CFG0 (0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */
\r
100 #define REG_LCDC_OVR2CFG1 (0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */
\r
101 #define REG_LCDC_OVR2CFG2 (0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */
\r
102 #define REG_LCDC_OVR2CFG3 (0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */
\r
103 #define REG_LCDC_OVR2CFG4 (0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */
\r
104 #define REG_LCDC_OVR2CFG5 (0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */
\r
105 #define REG_LCDC_OVR2CFG6 (0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */
\r
106 #define REG_LCDC_OVR2CFG7 (0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */
\r
107 #define REG_LCDC_OVR2CFG8 (0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */
\r
108 #define REG_LCDC_OVR2CFG9 (0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */
\r
109 #define REG_LCDC_HEOCHER (0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */
\r
110 #define REG_LCDC_HEOCHDR (0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */
\r
111 #define REG_LCDC_HEOCHSR (0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */
\r
112 #define REG_LCDC_HEOIER (0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */
\r
113 #define REG_LCDC_HEOIDR (0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */
\r
114 #define REG_LCDC_HEOIMR (0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */
\r
115 #define REG_LCDC_HEOISR (0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */
\r
116 #define REG_LCDC_HEOHEAD (0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */
\r
117 #define REG_LCDC_HEOADDR (0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */
\r
118 #define REG_LCDC_HEOCTRL (0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */
\r
119 #define REG_LCDC_HEONEXT (0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */
\r
120 #define REG_LCDC_HEOUHEAD (0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */
\r
121 #define REG_LCDC_HEOUADDR (0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */
\r
122 #define REG_LCDC_HEOUCTRL (0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */
\r
123 #define REG_LCDC_HEOUNEXT (0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */
\r
124 #define REG_LCDC_HEOVHEAD (0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */
\r
125 #define REG_LCDC_HEOVADDR (0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */
\r
126 #define REG_LCDC_HEOVCTRL (0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */
\r
127 #define REG_LCDC_HEOVNEXT (0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */
\r
128 #define REG_LCDC_HEOCFG0 (0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */
\r
129 #define REG_LCDC_HEOCFG1 (0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */
\r
130 #define REG_LCDC_HEOCFG2 (0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */
\r
131 #define REG_LCDC_HEOCFG3 (0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */
\r
132 #define REG_LCDC_HEOCFG4 (0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */
\r
133 #define REG_LCDC_HEOCFG5 (0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */
\r
134 #define REG_LCDC_HEOCFG6 (0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */
\r
135 #define REG_LCDC_HEOCFG7 (0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */
\r
136 #define REG_LCDC_HEOCFG8 (0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */
\r
137 #define REG_LCDC_HEOCFG9 (0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */
\r
138 #define REG_LCDC_HEOCFG10 (0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */
\r
139 #define REG_LCDC_HEOCFG11 (0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */
\r
140 #define REG_LCDC_HEOCFG12 (0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */
\r
141 #define REG_LCDC_HEOCFG13 (0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */
\r
142 #define REG_LCDC_HEOCFG14 (0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */
\r
143 #define REG_LCDC_HEOCFG15 (0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */
\r
144 #define REG_LCDC_HEOCFG16 (0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */
\r
145 #define REG_LCDC_HEOCFG17 (0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */
\r
146 #define REG_LCDC_HEOCFG18 (0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */
\r
147 #define REG_LCDC_HEOCFG19 (0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */
\r
148 #define REG_LCDC_HEOCFG20 (0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */
\r
149 #define REG_LCDC_HEOCFG21 (0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */
\r
150 #define REG_LCDC_HEOCFG22 (0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */
\r
151 #define REG_LCDC_HEOCFG23 (0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */
\r
152 #define REG_LCDC_HEOCFG24 (0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */
\r
153 #define REG_LCDC_HEOCFG25 (0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */
\r
154 #define REG_LCDC_HEOCFG26 (0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */
\r
155 #define REG_LCDC_HEOCFG27 (0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */
\r
156 #define REG_LCDC_HEOCFG28 (0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */
\r
157 #define REG_LCDC_HEOCFG29 (0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */
\r
158 #define REG_LCDC_HEOCFG30 (0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */
\r
159 #define REG_LCDC_HEOCFG31 (0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */
\r
160 #define REG_LCDC_HEOCFG32 (0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */
\r
161 #define REG_LCDC_HEOCFG33 (0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */
\r
162 #define REG_LCDC_HEOCFG34 (0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */
\r
163 #define REG_LCDC_HEOCFG35 (0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */
\r
164 #define REG_LCDC_HEOCFG36 (0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */
\r
165 #define REG_LCDC_HEOCFG37 (0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */
\r
166 #define REG_LCDC_HEOCFG38 (0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */
\r
167 #define REG_LCDC_HEOCFG39 (0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */
\r
168 #define REG_LCDC_HEOCFG40 (0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */
\r
169 #define REG_LCDC_HEOCFG41 (0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */
\r
170 #define REG_LCDC_HCRCHER (0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */
\r
171 #define REG_LCDC_HCRCHDR (0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */
\r
172 #define REG_LCDC_HCRCHSR (0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */
\r
173 #define REG_LCDC_HCRIER (0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */
\r
174 #define REG_LCDC_HCRIDR (0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */
\r
175 #define REG_LCDC_HCRIMR (0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */
\r
176 #define REG_LCDC_HCRISR (0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */
\r
177 #define REG_LCDC_HCRHEAD (0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */
\r
178 #define REG_LCDC_HCRADDR (0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */
\r
179 #define REG_LCDC_HCRCTRL (0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */
\r
180 #define REG_LCDC_HCRNEXT (0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */
\r
181 #define REG_LCDC_HCRCFG0 (0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */
\r
182 #define REG_LCDC_HCRCFG1 (0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */
\r
183 #define REG_LCDC_HCRCFG2 (0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */
\r
184 #define REG_LCDC_HCRCFG3 (0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */
\r
185 #define REG_LCDC_HCRCFG4 (0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */
\r
186 #define REG_LCDC_HCRCFG6 (0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */
\r
187 #define REG_LCDC_HCRCFG7 (0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */
\r
188 #define REG_LCDC_HCRCFG8 (0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */
\r
189 #define REG_LCDC_HCRCFG9 (0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */
\r
190 #define REG_LCDC_PPCHER (0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */
\r
191 #define REG_LCDC_PPCHDR (0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */
\r
192 #define REG_LCDC_PPCHSR (0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */
\r
193 #define REG_LCDC_PPIER (0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */
\r
194 #define REG_LCDC_PPIDR (0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */
\r
195 #define REG_LCDC_PPIMR (0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */
\r
196 #define REG_LCDC_PPISR (0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */
\r
197 #define REG_LCDC_PPHEAD (0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */
\r
198 #define REG_LCDC_PPADDR (0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */
\r
199 #define REG_LCDC_PPCTRL (0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */
\r
200 #define REG_LCDC_PPNEXT (0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */
\r
201 #define REG_LCDC_PPCFG0 (0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */
\r
202 #define REG_LCDC_PPCFG1 (0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */
\r
203 #define REG_LCDC_PPCFG2 (0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */
\r
204 #define REG_LCDC_PPCFG3 (0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */
\r
205 #define REG_LCDC_PPCFG4 (0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */
\r
206 #define REG_LCDC_PPCFG5 (0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */
\r
207 #define REG_LCDC_BASECLUT (0xF0030600U) /**< \brief (LCDC) Base CLUT Register */
\r
208 #define REG_LCDC_OVR1CLUT (0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */
\r
209 #define REG_LCDC_OVR2CLUT (0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */
\r
210 #define REG_LCDC_HEOCLUT (0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */
\r
211 #define REG_LCDC_HCRCLUT (0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */
\r
213 #define REG_LCDC_LCDCFG0 (*(RwReg*)0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */
\r
214 #define REG_LCDC_LCDCFG1 (*(RwReg*)0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */
\r
215 #define REG_LCDC_LCDCFG2 (*(RwReg*)0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */
\r
216 #define REG_LCDC_LCDCFG3 (*(RwReg*)0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */
\r
217 #define REG_LCDC_LCDCFG4 (*(RwReg*)0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */
\r
218 #define REG_LCDC_LCDCFG5 (*(RwReg*)0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */
\r
219 #define REG_LCDC_LCDCFG6 (*(RwReg*)0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */
\r
220 #define REG_LCDC_LCDEN (*(WoReg*)0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */
\r
221 #define REG_LCDC_LCDDIS (*(WoReg*)0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */
\r
222 #define REG_LCDC_LCDSR (*(RoReg*)0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */
\r
223 #define REG_LCDC_LCDIER (*(WoReg*)0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */
\r
224 #define REG_LCDC_LCDIDR (*(WoReg*)0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */
\r
225 #define REG_LCDC_LCDIMR (*(RoReg*)0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */
\r
226 #define REG_LCDC_LCDISR (*(RoReg*)0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */
\r
227 #define REG_LCDC_BASECHER (*(WoReg*)0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */
\r
228 #define REG_LCDC_BASECHDR (*(WoReg*)0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */
\r
229 #define REG_LCDC_BASECHSR (*(RoReg*)0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */
\r
230 #define REG_LCDC_BASEIER (*(WoReg*)0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */
\r
231 #define REG_LCDC_BASEIDR (*(WoReg*)0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */
\r
232 #define REG_LCDC_BASEIMR (*(RoReg*)0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */
\r
233 #define REG_LCDC_BASEISR (*(RoReg*)0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */
\r
234 #define REG_LCDC_BASEHEAD (*(RwReg*)0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */
\r
235 #define REG_LCDC_BASEADDR (*(RwReg*)0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */
\r
236 #define REG_LCDC_BASECTRL (*(RwReg*)0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */
\r
237 #define REG_LCDC_BASENEXT (*(RwReg*)0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */
\r
238 #define REG_LCDC_BASECFG0 (*(RwReg*)0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */
\r
239 #define REG_LCDC_BASECFG1 (*(RwReg*)0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */
\r
240 #define REG_LCDC_BASECFG2 (*(RwReg*)0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */
\r
241 #define REG_LCDC_BASECFG3 (*(RwReg*)0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */
\r
242 #define REG_LCDC_BASECFG4 (*(RwReg*)0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */
\r
243 #define REG_LCDC_BASECFG5 (*(RwReg*)0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */
\r
244 #define REG_LCDC_BASECFG6 (*(RwReg*)0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */
\r
245 #define REG_LCDC_OVR1CHER (*(WoReg*)0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */
\r
246 #define REG_LCDC_OVR1CHDR (*(WoReg*)0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */
\r
247 #define REG_LCDC_OVR1CHSR (*(RoReg*)0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */
\r
248 #define REG_LCDC_OVR1IER (*(WoReg*)0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */
\r
249 #define REG_LCDC_OVR1IDR (*(WoReg*)0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */
\r
250 #define REG_LCDC_OVR1IMR (*(RoReg*)0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */
\r
251 #define REG_LCDC_OVR1ISR (*(RoReg*)0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */
\r
252 #define REG_LCDC_OVR1HEAD (*(RwReg*)0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */
\r
253 #define REG_LCDC_OVR1ADDR (*(RwReg*)0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */
\r
254 #define REG_LCDC_OVR1CTRL (*(RwReg*)0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */
\r
255 #define REG_LCDC_OVR1NEXT (*(RwReg*)0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */
\r
256 #define REG_LCDC_OVR1CFG0 (*(RwReg*)0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */
\r
257 #define REG_LCDC_OVR1CFG1 (*(RwReg*)0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */
\r
258 #define REG_LCDC_OVR1CFG2 (*(RwReg*)0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */
\r
259 #define REG_LCDC_OVR1CFG3 (*(RwReg*)0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */
\r
260 #define REG_LCDC_OVR1CFG4 (*(RwReg*)0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */
\r
261 #define REG_LCDC_OVR1CFG5 (*(RwReg*)0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */
\r
262 #define REG_LCDC_OVR1CFG6 (*(RwReg*)0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */
\r
263 #define REG_LCDC_OVR1CFG7 (*(RwReg*)0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */
\r
264 #define REG_LCDC_OVR1CFG8 (*(RwReg*)0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */
\r
265 #define REG_LCDC_OVR1CFG9 (*(RwReg*)0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */
\r
266 #define REG_LCDC_OVR2CHER (*(WoReg*)0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */
\r
267 #define REG_LCDC_OVR2CHDR (*(WoReg*)0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */
\r
268 #define REG_LCDC_OVR2CHSR (*(RoReg*)0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */
\r
269 #define REG_LCDC_OVR2IER (*(WoReg*)0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */
\r
270 #define REG_LCDC_OVR2IDR (*(WoReg*)0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */
\r
271 #define REG_LCDC_OVR2IMR (*(RoReg*)0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */
\r
272 #define REG_LCDC_OVR2ISR (*(RoReg*)0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */
\r
273 #define REG_LCDC_OVR2HEAD (*(RwReg*)0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */
\r
274 #define REG_LCDC_OVR2ADDR (*(RwReg*)0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */
\r
275 #define REG_LCDC_OVR2CTRL (*(RwReg*)0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */
\r
276 #define REG_LCDC_OVR2NEXT (*(RwReg*)0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */
\r
277 #define REG_LCDC_OVR2CFG0 (*(RwReg*)0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */
\r
278 #define REG_LCDC_OVR2CFG1 (*(RwReg*)0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */
\r
279 #define REG_LCDC_OVR2CFG2 (*(RwReg*)0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */
\r
280 #define REG_LCDC_OVR2CFG3 (*(RwReg*)0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */
\r
281 #define REG_LCDC_OVR2CFG4 (*(RwReg*)0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */
\r
282 #define REG_LCDC_OVR2CFG5 (*(RwReg*)0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */
\r
283 #define REG_LCDC_OVR2CFG6 (*(RwReg*)0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */
\r
284 #define REG_LCDC_OVR2CFG7 (*(RwReg*)0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */
\r
285 #define REG_LCDC_OVR2CFG8 (*(RwReg*)0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */
\r
286 #define REG_LCDC_OVR2CFG9 (*(RwReg*)0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */
\r
287 #define REG_LCDC_HEOCHER (*(WoReg*)0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */
\r
288 #define REG_LCDC_HEOCHDR (*(WoReg*)0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */
\r
289 #define REG_LCDC_HEOCHSR (*(RoReg*)0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */
\r
290 #define REG_LCDC_HEOIER (*(WoReg*)0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */
\r
291 #define REG_LCDC_HEOIDR (*(WoReg*)0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */
\r
292 #define REG_LCDC_HEOIMR (*(RoReg*)0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */
\r
293 #define REG_LCDC_HEOISR (*(RoReg*)0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */
\r
294 #define REG_LCDC_HEOHEAD (*(RwReg*)0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */
\r
295 #define REG_LCDC_HEOADDR (*(RwReg*)0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */
\r
296 #define REG_LCDC_HEOCTRL (*(RwReg*)0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */
\r
297 #define REG_LCDC_HEONEXT (*(RwReg*)0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */
\r
298 #define REG_LCDC_HEOUHEAD (*(RwReg*)0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */
\r
299 #define REG_LCDC_HEOUADDR (*(RwReg*)0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */
\r
300 #define REG_LCDC_HEOUCTRL (*(RwReg*)0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */
\r
301 #define REG_LCDC_HEOUNEXT (*(RwReg*)0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */
\r
302 #define REG_LCDC_HEOVHEAD (*(RwReg*)0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */
\r
303 #define REG_LCDC_HEOVADDR (*(RwReg*)0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */
\r
304 #define REG_LCDC_HEOVCTRL (*(RwReg*)0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */
\r
305 #define REG_LCDC_HEOVNEXT (*(RwReg*)0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */
\r
306 #define REG_LCDC_HEOCFG0 (*(RwReg*)0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */
\r
307 #define REG_LCDC_HEOCFG1 (*(RwReg*)0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */
\r
308 #define REG_LCDC_HEOCFG2 (*(RwReg*)0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */
\r
309 #define REG_LCDC_HEOCFG3 (*(RwReg*)0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */
\r
310 #define REG_LCDC_HEOCFG4 (*(RwReg*)0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */
\r
311 #define REG_LCDC_HEOCFG5 (*(RwReg*)0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */
\r
312 #define REG_LCDC_HEOCFG6 (*(RwReg*)0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */
\r
313 #define REG_LCDC_HEOCFG7 (*(RwReg*)0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */
\r
314 #define REG_LCDC_HEOCFG8 (*(RwReg*)0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */
\r
315 #define REG_LCDC_HEOCFG9 (*(RwReg*)0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */
\r
316 #define REG_LCDC_HEOCFG10 (*(RwReg*)0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */
\r
317 #define REG_LCDC_HEOCFG11 (*(RwReg*)0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */
\r
318 #define REG_LCDC_HEOCFG12 (*(RwReg*)0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */
\r
319 #define REG_LCDC_HEOCFG13 (*(RwReg*)0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */
\r
320 #define REG_LCDC_HEOCFG14 (*(RwReg*)0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */
\r
321 #define REG_LCDC_HEOCFG15 (*(RwReg*)0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */
\r
322 #define REG_LCDC_HEOCFG16 (*(RwReg*)0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */
\r
323 #define REG_LCDC_HEOCFG17 (*(RwReg*)0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */
\r
324 #define REG_LCDC_HEOCFG18 (*(RwReg*)0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */
\r
325 #define REG_LCDC_HEOCFG19 (*(RwReg*)0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */
\r
326 #define REG_LCDC_HEOCFG20 (*(RwReg*)0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */
\r
327 #define REG_LCDC_HEOCFG21 (*(RwReg*)0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */
\r
328 #define REG_LCDC_HEOCFG22 (*(RwReg*)0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */
\r
329 #define REG_LCDC_HEOCFG23 (*(RwReg*)0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */
\r
330 #define REG_LCDC_HEOCFG24 (*(RwReg*)0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */
\r
331 #define REG_LCDC_HEOCFG25 (*(RwReg*)0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */
\r
332 #define REG_LCDC_HEOCFG26 (*(RwReg*)0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */
\r
333 #define REG_LCDC_HEOCFG27 (*(RwReg*)0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */
\r
334 #define REG_LCDC_HEOCFG28 (*(RwReg*)0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */
\r
335 #define REG_LCDC_HEOCFG29 (*(RwReg*)0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */
\r
336 #define REG_LCDC_HEOCFG30 (*(RwReg*)0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */
\r
337 #define REG_LCDC_HEOCFG31 (*(RwReg*)0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */
\r
338 #define REG_LCDC_HEOCFG32 (*(RwReg*)0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */
\r
339 #define REG_LCDC_HEOCFG33 (*(RwReg*)0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */
\r
340 #define REG_LCDC_HEOCFG34 (*(RwReg*)0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */
\r
341 #define REG_LCDC_HEOCFG35 (*(RwReg*)0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */
\r
342 #define REG_LCDC_HEOCFG36 (*(RwReg*)0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */
\r
343 #define REG_LCDC_HEOCFG37 (*(RwReg*)0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */
\r
344 #define REG_LCDC_HEOCFG38 (*(RwReg*)0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */
\r
345 #define REG_LCDC_HEOCFG39 (*(RwReg*)0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */
\r
346 #define REG_LCDC_HEOCFG40 (*(RwReg*)0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */
\r
347 #define REG_LCDC_HEOCFG41 (*(RwReg*)0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */
\r
348 #define REG_LCDC_HCRCHER (*(WoReg*)0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */
\r
349 #define REG_LCDC_HCRCHDR (*(WoReg*)0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */
\r
350 #define REG_LCDC_HCRCHSR (*(RoReg*)0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */
\r
351 #define REG_LCDC_HCRIER (*(WoReg*)0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */
\r
352 #define REG_LCDC_HCRIDR (*(WoReg*)0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */
\r
353 #define REG_LCDC_HCRIMR (*(RoReg*)0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */
\r
354 #define REG_LCDC_HCRISR (*(RoReg*)0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */
\r
355 #define REG_LCDC_HCRHEAD (*(RwReg*)0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */
\r
356 #define REG_LCDC_HCRADDR (*(RwReg*)0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */
\r
357 #define REG_LCDC_HCRCTRL (*(RwReg*)0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */
\r
358 #define REG_LCDC_HCRNEXT (*(RwReg*)0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */
\r
359 #define REG_LCDC_HCRCFG0 (*(RwReg*)0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */
\r
360 #define REG_LCDC_HCRCFG1 (*(RwReg*)0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */
\r
361 #define REG_LCDC_HCRCFG2 (*(RwReg*)0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */
\r
362 #define REG_LCDC_HCRCFG3 (*(RwReg*)0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */
\r
363 #define REG_LCDC_HCRCFG4 (*(RwReg*)0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */
\r
364 #define REG_LCDC_HCRCFG6 (*(RwReg*)0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */
\r
365 #define REG_LCDC_HCRCFG7 (*(RwReg*)0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */
\r
366 #define REG_LCDC_HCRCFG8 (*(RwReg*)0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */
\r
367 #define REG_LCDC_HCRCFG9 (*(RwReg*)0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */
\r
368 #define REG_LCDC_PPCHER (*(WoReg*)0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */
\r
369 #define REG_LCDC_PPCHDR (*(WoReg*)0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */
\r
370 #define REG_LCDC_PPCHSR (*(RoReg*)0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */
\r
371 #define REG_LCDC_PPIER (*(WoReg*)0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */
\r
372 #define REG_LCDC_PPIDR (*(WoReg*)0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */
\r
373 #define REG_LCDC_PPIMR (*(RoReg*)0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */
\r
374 #define REG_LCDC_PPISR (*(RoReg*)0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */
\r
375 #define REG_LCDC_PPHEAD (*(RwReg*)0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */
\r
376 #define REG_LCDC_PPADDR (*(RwReg*)0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */
\r
377 #define REG_LCDC_PPCTRL (*(RwReg*)0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */
\r
378 #define REG_LCDC_PPNEXT (*(RwReg*)0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */
\r
379 #define REG_LCDC_PPCFG0 (*(RwReg*)0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */
\r
380 #define REG_LCDC_PPCFG1 (*(RwReg*)0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */
\r
381 #define REG_LCDC_PPCFG2 (*(RwReg*)0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */
\r
382 #define REG_LCDC_PPCFG3 (*(RwReg*)0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */
\r
383 #define REG_LCDC_PPCFG4 (*(RwReg*)0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */
\r
384 #define REG_LCDC_PPCFG5 (*(RwReg*)0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */
\r
385 #define REG_LCDC_BASECLUT (*(RwReg*)0xF0030600U) /**< \brief (LCDC) Base CLUT Register */
\r
386 #define REG_LCDC_OVR1CLUT (*(RwReg*)0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */
\r
387 #define REG_LCDC_OVR2CLUT (*(RwReg*)0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */
\r
388 #define REG_LCDC_HEOCLUT (*(RwReg*)0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */
\r
389 #define REG_LCDC_HCRCLUT (*(RwReg*)0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */
\r
390 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
392 #endif /* _SAMA5_LCDC_INSTANCE_ */
\r