1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following condition is met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _SAMA5_PIOA_INSTANCE_
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31 #define _SAMA5_PIOA_INSTANCE_
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33 /* ========== Register definition for PIOA peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_PIOA_PER (0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */
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36 #define REG_PIOA_PDR (0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */
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37 #define REG_PIOA_PSR (0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */
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38 #define REG_PIOA_OER (0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */
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39 #define REG_PIOA_ODR (0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */
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40 #define REG_PIOA_OSR (0xFFFFF218U) /**< \brief (PIOA) Output Status Register */
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41 #define REG_PIOA_IFER (0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
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42 #define REG_PIOA_IFDR (0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
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43 #define REG_PIOA_IFSR (0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */
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44 #define REG_PIOA_SODR (0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */
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45 #define REG_PIOA_CODR (0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */
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46 #define REG_PIOA_ODSR (0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */
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47 #define REG_PIOA_PDSR (0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */
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48 #define REG_PIOA_IER (0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */
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49 #define REG_PIOA_IDR (0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */
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50 #define REG_PIOA_IMR (0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */
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51 #define REG_PIOA_ISR (0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */
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52 #define REG_PIOA_MDER (0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */
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53 #define REG_PIOA_MDDR (0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */
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54 #define REG_PIOA_MDSR (0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */
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55 #define REG_PIOA_PUDR (0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */
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56 #define REG_PIOA_PUER (0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */
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57 #define REG_PIOA_PUSR (0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */
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58 #define REG_PIOA_ABCDSR (0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */
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59 #define REG_PIOA_IFSCDR (0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
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60 #define REG_PIOA_IFSCER (0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
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61 #define REG_PIOA_IFSCSR (0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
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62 #define REG_PIOA_SCDR (0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
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63 #define REG_PIOA_PPDDR (0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */
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64 #define REG_PIOA_PPDER (0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */
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65 #define REG_PIOA_PPDSR (0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */
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66 #define REG_PIOA_OWER (0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */
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67 #define REG_PIOA_OWDR (0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */
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68 #define REG_PIOA_OWSR (0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */
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69 #define REG_PIOA_AIMER (0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
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70 #define REG_PIOA_AIMDR (0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
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71 #define REG_PIOA_AIMMR (0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
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72 #define REG_PIOA_ESR (0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */
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73 #define REG_PIOA_LSR (0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */
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74 #define REG_PIOA_ELSR (0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */
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75 #define REG_PIOA_FELLSR (0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
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76 #define REG_PIOA_REHLSR (0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
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77 #define REG_PIOA_FRLHSR (0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
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78 #define REG_PIOA_LOCKSR (0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */
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79 #define REG_PIOA_WPMR (0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */
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80 #define REG_PIOA_WPSR (0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */
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81 #define REG_PIOA_SCHMITT (0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */
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82 #define REG_PIOA_DRIVER1 (0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */
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83 #define REG_PIOA_DRIVER2 (0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */
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85 #define REG_PIOA_PER (*(WoReg*)0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */
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86 #define REG_PIOA_PDR (*(WoReg*)0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */
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87 #define REG_PIOA_PSR (*(RoReg*)0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */
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88 #define REG_PIOA_OER (*(WoReg*)0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */
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89 #define REG_PIOA_ODR (*(WoReg*)0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */
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90 #define REG_PIOA_OSR (*(RoReg*)0xFFFFF218U) /**< \brief (PIOA) Output Status Register */
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91 #define REG_PIOA_IFER (*(WoReg*)0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
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92 #define REG_PIOA_IFDR (*(WoReg*)0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
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93 #define REG_PIOA_IFSR (*(RoReg*)0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */
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94 #define REG_PIOA_SODR (*(WoReg*)0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */
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95 #define REG_PIOA_CODR (*(WoReg*)0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */
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96 #define REG_PIOA_ODSR (*(RwReg*)0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */
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97 #define REG_PIOA_PDSR (*(RoReg*)0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */
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98 #define REG_PIOA_IER (*(WoReg*)0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */
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99 #define REG_PIOA_IDR (*(WoReg*)0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */
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100 #define REG_PIOA_IMR (*(RoReg*)0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */
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101 #define REG_PIOA_ISR (*(RoReg*)0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */
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102 #define REG_PIOA_MDER (*(WoReg*)0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */
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103 #define REG_PIOA_MDDR (*(WoReg*)0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */
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104 #define REG_PIOA_MDSR (*(RoReg*)0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */
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105 #define REG_PIOA_PUDR (*(WoReg*)0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */
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106 #define REG_PIOA_PUER (*(WoReg*)0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */
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107 #define REG_PIOA_PUSR (*(RoReg*)0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */
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108 #define REG_PIOA_ABCDSR (*(RwReg*)0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */
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109 #define REG_PIOA_IFSCDR (*(WoReg*)0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
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110 #define REG_PIOA_IFSCER (*(WoReg*)0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
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111 #define REG_PIOA_IFSCSR (*(RoReg*)0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
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112 #define REG_PIOA_SCDR (*(RwReg*)0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
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113 #define REG_PIOA_PPDDR (*(WoReg*)0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */
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114 #define REG_PIOA_PPDER (*(WoReg*)0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */
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115 #define REG_PIOA_PPDSR (*(RoReg*)0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */
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116 #define REG_PIOA_OWER (*(WoReg*)0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */
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117 #define REG_PIOA_OWDR (*(WoReg*)0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */
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118 #define REG_PIOA_OWSR (*(RoReg*)0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */
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119 #define REG_PIOA_AIMER (*(WoReg*)0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
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120 #define REG_PIOA_AIMDR (*(WoReg*)0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
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121 #define REG_PIOA_AIMMR (*(RoReg*)0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
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122 #define REG_PIOA_ESR (*(WoReg*)0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */
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123 #define REG_PIOA_LSR (*(WoReg*)0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */
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124 #define REG_PIOA_ELSR (*(RoReg*)0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */
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125 #define REG_PIOA_FELLSR (*(WoReg*)0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
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126 #define REG_PIOA_REHLSR (*(WoReg*)0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
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127 #define REG_PIOA_FRLHSR (*(RoReg*)0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
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128 #define REG_PIOA_LOCKSR (*(RoReg*)0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */
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129 #define REG_PIOA_WPMR (*(RwReg*)0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */
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130 #define REG_PIOA_WPSR (*(RoReg*)0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */
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131 #define REG_PIOA_SCHMITT (*(RwReg*)0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */
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132 #define REG_PIOA_DRIVER1 (*(RwReg*)0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */
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133 #define REG_PIOA_DRIVER2 (*(RwReg*)0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */
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134 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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136 #endif /* _SAMA5_PIOA_INSTANCE_ */
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