1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following condition is met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _SAMA5_PWM_INSTANCE_
\r
31 #define _SAMA5_PWM_INSTANCE_
\r
33 /* ========== Register definition for PWM peripheral ========== */
\r
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
35 #define REG_PWM_CLK (0xF002C000U) /**< \brief (PWM) PWM Clock Register */
\r
36 #define REG_PWM_ENA (0xF002C004U) /**< \brief (PWM) PWM Enable Register */
\r
37 #define REG_PWM_DIS (0xF002C008U) /**< \brief (PWM) PWM Disable Register */
\r
38 #define REG_PWM_SR (0xF002C00CU) /**< \brief (PWM) PWM Status Register */
\r
39 #define REG_PWM_IER1 (0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
\r
40 #define REG_PWM_IDR1 (0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
\r
41 #define REG_PWM_IMR1 (0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
\r
42 #define REG_PWM_ISR1 (0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
\r
43 #define REG_PWM_SCM (0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
\r
44 #define REG_PWM_SCUC (0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
\r
45 #define REG_PWM_SCUP (0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
\r
46 #define REG_PWM_SCUPUPD (0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
\r
47 #define REG_PWM_IER2 (0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
\r
48 #define REG_PWM_IDR2 (0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
\r
49 #define REG_PWM_IMR2 (0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
\r
50 #define REG_PWM_ISR2 (0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
\r
51 #define REG_PWM_OOV (0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */
\r
52 #define REG_PWM_OS (0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */
\r
53 #define REG_PWM_OSS (0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
\r
54 #define REG_PWM_OSC (0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
\r
55 #define REG_PWM_OSSUPD (0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
\r
56 #define REG_PWM_OSCUPD (0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
\r
57 #define REG_PWM_FMR (0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */
\r
58 #define REG_PWM_FSR (0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */
\r
59 #define REG_PWM_FCR (0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */
\r
60 #define REG_PWM_FPV1 (0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */
\r
61 #define REG_PWM_FPE (0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
\r
62 #define REG_PWM_ELMR (0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
\r
63 #define REG_PWM_FPV2 (0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */
\r
64 #define REG_PWM_WPCR (0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
\r
65 #define REG_PWM_WPSR (0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
\r
66 #define REG_PWM_CMPV0 (0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
\r
67 #define REG_PWM_CMPVUPD0 (0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
\r
68 #define REG_PWM_CMPM0 (0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
\r
69 #define REG_PWM_CMPMUPD0 (0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
\r
70 #define REG_PWM_CMPV1 (0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
\r
71 #define REG_PWM_CMPVUPD1 (0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
\r
72 #define REG_PWM_CMPM1 (0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
\r
73 #define REG_PWM_CMPMUPD1 (0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
\r
74 #define REG_PWM_CMPV2 (0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
\r
75 #define REG_PWM_CMPVUPD2 (0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
\r
76 #define REG_PWM_CMPM2 (0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
\r
77 #define REG_PWM_CMPMUPD2 (0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
\r
78 #define REG_PWM_CMPV3 (0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
\r
79 #define REG_PWM_CMPVUPD3 (0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
\r
80 #define REG_PWM_CMPM3 (0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
\r
81 #define REG_PWM_CMPMUPD3 (0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
\r
82 #define REG_PWM_CMPV4 (0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
\r
83 #define REG_PWM_CMPVUPD4 (0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
\r
84 #define REG_PWM_CMPM4 (0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
\r
85 #define REG_PWM_CMPMUPD4 (0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
\r
86 #define REG_PWM_CMPV5 (0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
\r
87 #define REG_PWM_CMPVUPD5 (0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
\r
88 #define REG_PWM_CMPM5 (0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
\r
89 #define REG_PWM_CMPMUPD5 (0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
\r
90 #define REG_PWM_CMPV6 (0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
\r
91 #define REG_PWM_CMPVUPD6 (0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
\r
92 #define REG_PWM_CMPM6 (0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
\r
93 #define REG_PWM_CMPMUPD6 (0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
\r
94 #define REG_PWM_CMPV7 (0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
\r
95 #define REG_PWM_CMPVUPD7 (0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
\r
96 #define REG_PWM_CMPM7 (0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
\r
97 #define REG_PWM_CMPMUPD7 (0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
\r
98 #define REG_PWM_CMR0 (0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
\r
99 #define REG_PWM_CDTY0 (0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
\r
100 #define REG_PWM_CDTYUPD0 (0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
\r
101 #define REG_PWM_CPRD0 (0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
\r
102 #define REG_PWM_CPRDUPD0 (0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
\r
103 #define REG_PWM_CCNT0 (0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
\r
104 #define REG_PWM_DT0 (0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
\r
105 #define REG_PWM_DTUPD0 (0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
\r
106 #define REG_PWM_CMR1 (0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
\r
107 #define REG_PWM_CDTY1 (0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
\r
108 #define REG_PWM_CDTYUPD1 (0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
\r
109 #define REG_PWM_CPRD1 (0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
\r
110 #define REG_PWM_CPRDUPD1 (0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
\r
111 #define REG_PWM_CCNT1 (0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
\r
112 #define REG_PWM_DT1 (0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
\r
113 #define REG_PWM_DTUPD1 (0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
\r
114 #define REG_PWM_CMR2 (0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
\r
115 #define REG_PWM_CDTY2 (0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
\r
116 #define REG_PWM_CDTYUPD2 (0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
\r
117 #define REG_PWM_CPRD2 (0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
\r
118 #define REG_PWM_CPRDUPD2 (0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
\r
119 #define REG_PWM_CCNT2 (0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
\r
120 #define REG_PWM_DT2 (0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
\r
121 #define REG_PWM_DTUPD2 (0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
\r
122 #define REG_PWM_CMR3 (0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
\r
123 #define REG_PWM_CDTY3 (0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
\r
124 #define REG_PWM_CDTYUPD3 (0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
\r
125 #define REG_PWM_CPRD3 (0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
\r
126 #define REG_PWM_CPRDUPD3 (0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
\r
127 #define REG_PWM_CCNT3 (0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
\r
128 #define REG_PWM_DT3 (0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
\r
129 #define REG_PWM_DTUPD3 (0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
\r
130 #define REG_PWM_CMUPD0 (0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */
\r
131 #define REG_PWM_CMUPD1 (0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */
\r
132 #define REG_PWM_CMUPD2 (0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */
\r
133 #define REG_PWM_CMUPD3 (0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */
\r
135 #define REG_PWM_CLK (*(RwReg*)0xF002C000U) /**< \brief (PWM) PWM Clock Register */
\r
136 #define REG_PWM_ENA (*(WoReg*)0xF002C004U) /**< \brief (PWM) PWM Enable Register */
\r
137 #define REG_PWM_DIS (*(WoReg*)0xF002C008U) /**< \brief (PWM) PWM Disable Register */
\r
138 #define REG_PWM_SR (*(RoReg*)0xF002C00CU) /**< \brief (PWM) PWM Status Register */
\r
139 #define REG_PWM_IER1 (*(WoReg*)0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
\r
140 #define REG_PWM_IDR1 (*(WoReg*)0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
\r
141 #define REG_PWM_IMR1 (*(RoReg*)0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
\r
142 #define REG_PWM_ISR1 (*(RoReg*)0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
\r
143 #define REG_PWM_SCM (*(RwReg*)0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
\r
144 #define REG_PWM_SCUC (*(RwReg*)0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
\r
145 #define REG_PWM_SCUP (*(RwReg*)0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
\r
146 #define REG_PWM_SCUPUPD (*(WoReg*)0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
\r
147 #define REG_PWM_IER2 (*(WoReg*)0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
\r
148 #define REG_PWM_IDR2 (*(WoReg*)0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
\r
149 #define REG_PWM_IMR2 (*(RoReg*)0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
\r
150 #define REG_PWM_ISR2 (*(RoReg*)0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
\r
151 #define REG_PWM_OOV (*(RwReg*)0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */
\r
152 #define REG_PWM_OS (*(RwReg*)0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */
\r
153 #define REG_PWM_OSS (*(WoReg*)0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
\r
154 #define REG_PWM_OSC (*(WoReg*)0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
\r
155 #define REG_PWM_OSSUPD (*(WoReg*)0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
\r
156 #define REG_PWM_OSCUPD (*(WoReg*)0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
\r
157 #define REG_PWM_FMR (*(RwReg*)0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */
\r
158 #define REG_PWM_FSR (*(RoReg*)0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */
\r
159 #define REG_PWM_FCR (*(WoReg*)0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */
\r
160 #define REG_PWM_FPV1 (*(RwReg*)0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */
\r
161 #define REG_PWM_FPE (*(RwReg*)0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
\r
162 #define REG_PWM_ELMR (*(RwReg*)0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
\r
163 #define REG_PWM_FPV2 (*(RwReg*)0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */
\r
164 #define REG_PWM_WPCR (*(WoReg*)0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
\r
165 #define REG_PWM_WPSR (*(RoReg*)0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
\r
166 #define REG_PWM_CMPV0 (*(RwReg*)0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
\r
167 #define REG_PWM_CMPVUPD0 (*(WoReg*)0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
\r
168 #define REG_PWM_CMPM0 (*(RwReg*)0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
\r
169 #define REG_PWM_CMPMUPD0 (*(WoReg*)0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
\r
170 #define REG_PWM_CMPV1 (*(RwReg*)0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
\r
171 #define REG_PWM_CMPVUPD1 (*(WoReg*)0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
\r
172 #define REG_PWM_CMPM1 (*(RwReg*)0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
\r
173 #define REG_PWM_CMPMUPD1 (*(WoReg*)0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
\r
174 #define REG_PWM_CMPV2 (*(RwReg*)0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
\r
175 #define REG_PWM_CMPVUPD2 (*(WoReg*)0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
\r
176 #define REG_PWM_CMPM2 (*(RwReg*)0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
\r
177 #define REG_PWM_CMPMUPD2 (*(WoReg*)0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
\r
178 #define REG_PWM_CMPV3 (*(RwReg*)0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
\r
179 #define REG_PWM_CMPVUPD3 (*(WoReg*)0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
\r
180 #define REG_PWM_CMPM3 (*(RwReg*)0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
\r
181 #define REG_PWM_CMPMUPD3 (*(WoReg*)0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
\r
182 #define REG_PWM_CMPV4 (*(RwReg*)0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
\r
183 #define REG_PWM_CMPVUPD4 (*(WoReg*)0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
\r
184 #define REG_PWM_CMPM4 (*(RwReg*)0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
\r
185 #define REG_PWM_CMPMUPD4 (*(WoReg*)0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
\r
186 #define REG_PWM_CMPV5 (*(RwReg*)0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
\r
187 #define REG_PWM_CMPVUPD5 (*(WoReg*)0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
\r
188 #define REG_PWM_CMPM5 (*(RwReg*)0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
\r
189 #define REG_PWM_CMPMUPD5 (*(WoReg*)0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
\r
190 #define REG_PWM_CMPV6 (*(RwReg*)0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
\r
191 #define REG_PWM_CMPVUPD6 (*(WoReg*)0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
\r
192 #define REG_PWM_CMPM6 (*(RwReg*)0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
\r
193 #define REG_PWM_CMPMUPD6 (*(WoReg*)0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
\r
194 #define REG_PWM_CMPV7 (*(RwReg*)0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
\r
195 #define REG_PWM_CMPVUPD7 (*(WoReg*)0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
\r
196 #define REG_PWM_CMPM7 (*(RwReg*)0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
\r
197 #define REG_PWM_CMPMUPD7 (*(WoReg*)0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
\r
198 #define REG_PWM_CMR0 (*(RwReg*)0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
\r
199 #define REG_PWM_CDTY0 (*(RwReg*)0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
\r
200 #define REG_PWM_CDTYUPD0 (*(WoReg*)0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
\r
201 #define REG_PWM_CPRD0 (*(RwReg*)0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
\r
202 #define REG_PWM_CPRDUPD0 (*(WoReg*)0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
\r
203 #define REG_PWM_CCNT0 (*(RoReg*)0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
\r
204 #define REG_PWM_DT0 (*(RwReg*)0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
\r
205 #define REG_PWM_DTUPD0 (*(WoReg*)0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
\r
206 #define REG_PWM_CMR1 (*(RwReg*)0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
\r
207 #define REG_PWM_CDTY1 (*(RwReg*)0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
\r
208 #define REG_PWM_CDTYUPD1 (*(WoReg*)0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
\r
209 #define REG_PWM_CPRD1 (*(RwReg*)0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
\r
210 #define REG_PWM_CPRDUPD1 (*(WoReg*)0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
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211 #define REG_PWM_CCNT1 (*(RoReg*)0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
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212 #define REG_PWM_DT1 (*(RwReg*)0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
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213 #define REG_PWM_DTUPD1 (*(WoReg*)0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
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214 #define REG_PWM_CMR2 (*(RwReg*)0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
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215 #define REG_PWM_CDTY2 (*(RwReg*)0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
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216 #define REG_PWM_CDTYUPD2 (*(WoReg*)0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
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217 #define REG_PWM_CPRD2 (*(RwReg*)0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
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218 #define REG_PWM_CPRDUPD2 (*(WoReg*)0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
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219 #define REG_PWM_CCNT2 (*(RoReg*)0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
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220 #define REG_PWM_DT2 (*(RwReg*)0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
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221 #define REG_PWM_DTUPD2 (*(WoReg*)0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
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222 #define REG_PWM_CMR3 (*(RwReg*)0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
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223 #define REG_PWM_CDTY3 (*(RwReg*)0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
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224 #define REG_PWM_CDTYUPD3 (*(WoReg*)0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
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225 #define REG_PWM_CPRD3 (*(RwReg*)0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
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226 #define REG_PWM_CPRDUPD3 (*(WoReg*)0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
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227 #define REG_PWM_CCNT3 (*(RoReg*)0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
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228 #define REG_PWM_DT3 (*(RwReg*)0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
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229 #define REG_PWM_DTUPD3 (*(WoReg*)0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
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230 #define REG_PWM_CMUPD0 (*(WoReg*)0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */
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231 #define REG_PWM_CMUPD1 (*(WoReg*)0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */
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232 #define REG_PWM_CMUPD2 (*(WoReg*)0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */
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233 #define REG_PWM_CMUPD3 (*(WoReg*)0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */
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234 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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236 #endif /* _SAMA5_PWM_INSTANCE_ */
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