1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following condition is met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _SAMA5_SSC0_INSTANCE_
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31 #define _SAMA5_SSC0_INSTANCE_
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33 /* ========== Register definition for SSC0 peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_SSC0_CR (0xF0008000U) /**< \brief (SSC0) Control Register */
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36 #define REG_SSC0_CMR (0xF0008004U) /**< \brief (SSC0) Clock Mode Register */
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37 #define REG_SSC0_RCMR (0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */
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38 #define REG_SSC0_RFMR (0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */
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39 #define REG_SSC0_TCMR (0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */
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40 #define REG_SSC0_TFMR (0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */
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41 #define REG_SSC0_RHR (0xF0008020U) /**< \brief (SSC0) Receive Holding Register */
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42 #define REG_SSC0_THR (0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */
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43 #define REG_SSC0_RSHR (0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */
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44 #define REG_SSC0_TSHR (0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */
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45 #define REG_SSC0_RC0R (0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */
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46 #define REG_SSC0_RC1R (0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */
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47 #define REG_SSC0_SR (0xF0008040U) /**< \brief (SSC0) Status Register */
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48 #define REG_SSC0_IER (0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */
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49 #define REG_SSC0_IDR (0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */
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50 #define REG_SSC0_IMR (0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */
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51 #define REG_SSC0_WPMR (0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */
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52 #define REG_SSC0_WPSR (0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */
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54 #define REG_SSC0_CR (*(WoReg*)0xF0008000U) /**< \brief (SSC0) Control Register */
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55 #define REG_SSC0_CMR (*(RwReg*)0xF0008004U) /**< \brief (SSC0) Clock Mode Register */
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56 #define REG_SSC0_RCMR (*(RwReg*)0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */
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57 #define REG_SSC0_RFMR (*(RwReg*)0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */
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58 #define REG_SSC0_TCMR (*(RwReg*)0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */
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59 #define REG_SSC0_TFMR (*(RwReg*)0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */
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60 #define REG_SSC0_RHR (*(RoReg*)0xF0008020U) /**< \brief (SSC0) Receive Holding Register */
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61 #define REG_SSC0_THR (*(WoReg*)0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */
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62 #define REG_SSC0_RSHR (*(RoReg*)0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */
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63 #define REG_SSC0_TSHR (*(RwReg*)0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */
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64 #define REG_SSC0_RC0R (*(RwReg*)0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */
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65 #define REG_SSC0_RC1R (*(RwReg*)0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */
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66 #define REG_SSC0_SR (*(RoReg*)0xF0008040U) /**< \brief (SSC0) Status Register */
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67 #define REG_SSC0_IER (*(WoReg*)0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */
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68 #define REG_SSC0_IDR (*(WoReg*)0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */
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69 #define REG_SSC0_IMR (*(RoReg*)0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */
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70 #define REG_SSC0_WPMR (*(RwReg*)0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */
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71 #define REG_SSC0_WPSR (*(RoReg*)0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */
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72 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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74 #endif /* _SAMA5_SSC0_INSTANCE_ */
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