1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2013, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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34 /*----------------------------------------------------------------------------
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36 *----------------------------------------------------------------------------*/
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42 /** \addtogroup dmad_defines DMA Driver Defines
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44 /*----------------------------------------------------------------------------
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46 *----------------------------------------------------------------------------*/
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47 #define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */
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48 #define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */
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50 #define XDMAD_TRANSFER_TX 0
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51 #define XDMAD_TRANSFER_RX 1
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54 #define XDMA_UBC_NDE (0x1u << 24)
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55 #define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
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56 #define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)
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57 #define XDMA_UBC_NSEN (0x1u << 25)
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58 #define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
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59 #define XDMA_UBC_NSEN_UPDATED (0x1u << 25)
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60 #define XDMA_UBC_NDEN (0x1u << 26)
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61 #define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
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62 #define XDMA_UBC_NDEN_UPDATED (0x1u << 26)
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63 #define XDMA_UBC_NVIEW_Pos 27
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64 #define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)
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65 #define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)
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66 #define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)
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67 #define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)
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68 #define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)
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70 /*----------------------------------------------------------------------------
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72 *----------------------------------------------------------------------------*/
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76 /*----------------------------------------------------------------------------
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78 *----------------------------------------------------------------------------*/
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79 /** \addtogroup dmad_structs DMA Driver Structs
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82 /** DMA status or return code */
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83 typedef enum _XdmadStatus {
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84 XDMAD_OK = 0, /**< Operation is sucessful */
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87 XDMAD_BUSY, /**< Channel occupied or transfer not finished */
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88 XDMAD_ERROR, /**< Operation failed */
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89 XDMAD_CANCELED /**< Operation canceled */
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90 } eXdmadStatus, eXdmadRC;
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92 /** DMA state for channel */
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93 typedef enum _XdmadState {
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94 XDMAD_STATE_FREE = 0, /**< Free channel */
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95 XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */
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96 XDMAD_STATE_START, /**< DMA started */
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97 XDMAD_STATE_IN_XFR, /**< DMA in trasfering */
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98 XDMAD_STATE_DONE, /**< DMA transfer done */
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101 /** DMA transfer callback */
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102 typedef void (*XdmadTransferCallback)(uint32_t status, void* pArg);
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104 /** DMA driver channel */
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105 typedef struct _XdmadChannel {
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106 XdmadTransferCallback fCallback; /**< Callback */
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107 void* pArg; /**< Callback argument */
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108 uint8_t bIrqOwner; /**< Uses DMA handler or external one */
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109 uint8_t bSrcPeriphID; /**< HW ID for source */
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110 uint8_t bDstPeriphID; /**< HW ID for destination */
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111 uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */
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112 uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */
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113 uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */
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114 uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */
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115 volatile uint8_t state; /**< DMA channel state */
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118 /** DMA driver instance */
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119 typedef struct _Xdmad {
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121 sXdmadChannel XdmaChannels[2][16];
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122 uint8_t numControllers;
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123 uint8_t numChannels;
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124 uint8_t pollingMode;
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125 uint8_t pollingTimeout;
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128 typedef struct _XdmadCfg {
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129 /** Microblock Control Member. */
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131 /** Source Address Member. */
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133 /** Destination Address Member. */
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135 /** Configuration Register. */
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137 /** Block Control Member. */
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139 /** Data Stride Member. */
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141 /** Source Microblock Stride Member. */
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143 /** Destination Microblock Stride Member. */
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147 /** \brief Structure for storing parameters for DMA view0 that can be
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148 * performed by the DMA Master transfer.*/
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149 typedef struct _LinkedListDescriporView0
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151 /** Next Descriptor Address number. */
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153 /** Microblock Control Member. */
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155 /** Transfer Address Member. */
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157 }LinkedListDescriporView0;
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159 /** \brief Structure for storing parameters for DMA view1 that can be
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160 * performed by the DMA Master transfer.*/
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161 typedef struct _LinkedListDescriporView1
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163 /** Next Descriptor Address number. */
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165 /** Microblock Control Member. */
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167 /** Source Address Member. */
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169 /** Destination Address Member. */
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171 }LinkedListDescriporView1;
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173 /** \brief Structure for storing parameters for DMA view2 that can be
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174 * performed by the DMA Master transfer.*/
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175 typedef struct _LinkedListDescriporView2
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177 /** Next Descriptor Address number. */
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179 /** Microblock Control Member. */
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181 /** Source Address Member. */
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183 /** Destination Address Member. */
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185 /** Configuration Register. */
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187 }LinkedListDescriporView2;
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189 /** \brief Structure for storing parameters for DMA view3 that can be
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190 * performed by the DMA Master transfer.*/
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191 typedef struct _LinkedListDescriporView3
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193 /** Next Descriptor Address number. */
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195 /** Microblock Control Member. */
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197 /** Source Address Member. */
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199 /** Destination Address Member. */
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201 /** Configuration Register. */
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203 /** Block Control Member. */
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205 /** Data Stride Member. */
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207 /** Source Microblock Stride Member. */
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209 /** Destination Microblock Stride Member. */
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211 }LinkedListDescriporView3;
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215 /*----------------------------------------------------------------------------
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216 * Exported functions
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217 *----------------------------------------------------------------------------*/
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218 /** \addtogroup dmad_functions DMA Driver Functionos
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220 extern void XDMAD_Initialize( sXdmad *pXdmad,
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221 uint8_t bPollingMode );
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223 extern void XDMAD_Handler( sXdmad *pDmad);
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225 extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,
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226 uint8_t bSrcID, uint8_t bDstID);
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227 extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel );
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229 extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,
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230 uint32_t dwChannel,
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231 sXdmadCfg *pXdmaParam,
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232 uint32_t dwXdmaDescCfg,
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233 uint32_t dwXdmaDescAddr);
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235 extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel);
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237 extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel );
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239 extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel );
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241 extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad,
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242 uint32_t dwChannel,
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243 XdmadTransferCallback fCallback,
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246 extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel );
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249 #endif //#ifndef _XDMAD_H
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