1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2014, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 //------------------------------------------------------------------------------
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33 //------------------------------------------------------------------------------
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36 #define AIC 0xFC06E000
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37 #define AIC_IVR 0x10
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38 #define AIC_EOICR 0x38
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39 #define SAIC 0xFC068400
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40 #define AIC_FVR 0x14
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42 #define IRQ_STACK_SIZE 8*3*4
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43 #define FIQ_STACK_SIZE 8*3*4
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45 #define MODE_MSK 0x1F
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46 #define ARM_MODE_ABT 0x17
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47 #define ARM_MODE_FIQ 0x11
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48 #define ARM_MODE_IRQ 0x12
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49 #define ARM_MODE_SVC 0x13
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50 #define ARM_MODE_SYS 0x1F
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55 #define REG_SFR_AICREDIR 0xF8028054
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56 #define REG_SFR_UID 0xF8028050
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57 #define AICREDIR_KEY 0x5F67B102
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59 //------------------------------------------------------------------------------
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61 //------------------------------------------------------------------------------
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66 /* Exception vectors
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67 *******************/
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68 .section .vectors, "a", %progbits
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71 ldr pc, =resetHandler /* Reset */
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73 b undefVector /* Undefined instruction */
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75 b swiVector /* Software interrupt */
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76 prefetchAbortVector:
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77 b prefetchAbortVector /* Prefetch abort */
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79 b dataAbortVector /* Data abort */
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81 b reservedVector /* Reserved for future use */
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83 b irqHandler /* Interrupt */
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85 b fiqHandler /* Fast interrupt */
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86 //------------------------------------------------------------------------------
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87 /// Handles a fast interrupt request by branching to the address defined in the
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89 //------------------------------------------------------------------------------
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96 /* Write in the IVR to support Protect Mode */
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98 LDR r0, [r14, #AIC_IVR]
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99 STR lr, [r14, #AIC_IVR]
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101 /* Branch to interrupt handler in Supervisor mode */
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102 MSR CPSR_c, #ARM_MODE_SVC
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103 STMFD sp!, {r1-r3, r4, r12, lr}
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108 LDMIA sp!, {r1-r3, r4, r12, lr}
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109 MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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111 /* Acknowledge interrupt */
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113 STR lr, [r14, #AIC_EOICR]
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115 /* Restore interrupt context and branch back to calling code */
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117 /* MSR SPSR_cxsf, lr*/
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121 //------------------------------------------------------------------------------
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122 /// Handles incoming interrupt requests by branching to the corresponding
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123 /// handler, as defined in the AIC. Supports interrupt nesting.
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124 //------------------------------------------------------------------------------
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126 /* Save interrupt context on the stack to allow nesting */
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127 /* Save interrupt context on the stack to allow nesting */
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131 STMFD sp!, {r0, lr}
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133 /* Write in the IVR to support Protect Mode */
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135 LDR r0, [r14, #AIC_IVR]
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136 STR lr, [r14, #AIC_IVR]
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138 /* Branch to interrupt handler in Supervisor mode */
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139 MSR CPSR_c, #ARM_MODE_SVC
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140 STMFD sp!, {r1-r3, r4, r12, lr}
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142 /* Check for 8-byte alignment and save lr plus a */
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143 /* word to indicate the stack adjustment used (0 or 4) */
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146 STMFD sp!, {r1, lr}
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150 LDMIA sp!, {r1, lr}
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153 LDMIA sp!, {r1-r3, r4, r12, lr}
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154 MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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156 /* Acknowledge interrupt */
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158 STR lr, [r14, #AIC_EOICR]
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160 /* Restore interrupt context and branch back to calling code */
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161 LDMIA sp!, {r0, lr}
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166 //------------------------------------------------------------------------------
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167 /// Initializes the chip and branches to the main() function.
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168 //------------------------------------------------------------------------------
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169 .section .textEntry
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178 /* - Enable access to CP10 and CP11 in CP15.CACR */
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179 //mrc p15, 0, r0, c1, c0, 2
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180 //orr r0, r0, #0xf00000
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181 //mcr p15, 0, r0, c1, c0, 2
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182 /* - Enable access to CP10 and CP11 in CP15.NSACR */
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183 /* - Set FPEXC.EN (B30) */
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185 //orr r0, r0, #0x40000000
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188 /* Useless instruction for referencing the .vectors section */
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189 ldr r0, =resetVector
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191 /* Set pc to actual code location (i.e. not in remap zone) */
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194 /* Initialize the prerelocate segment */
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197 ldr r1, =_sprerelocate
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198 ldr r2, =_eprerelocate
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205 /* Perform low-level initialization of the chip using LowLevelInit() */
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208 ldr r0, =LowLevelInit
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211 /* Initialize the postrelocate segment */
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214 ldr r1, =_spostrelocate
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215 ldr r2, =_epostrelocate
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222 /* Clear the zero segment */
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232 /* Set up the fast interrupt stack pointer.*/
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233 bic r0, r0, #MODE_MSK
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234 orr r0, r0, #ARM_MODE_FIQ
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236 ldr sp, =_fiqstack
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239 /* Set up the normal interrupt stack pointer.*/
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241 bic r0, r0, #MODE_MSK
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242 orr r0, r0, #ARM_MODE_IRQ
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244 ldr sp, =_irqstack
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247 /* Set up the stack pointer.*/
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249 bic r0 ,r0, #MODE_MSK
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250 orr r0 ,r0, #ARM_MODE_SYS
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255 bic r0 ,r0, #MODE_MSK
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256 orr r0 ,r0, #ARM_MODE_SVC
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261 // Redirect FIQ to IRQ
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262 LDR r0, =AICREDIR_KEY
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263 LDR r1, = REG_SFR_UID
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264 LDR r2, = REG_SFR_AICREDIR
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270 /*Initialize the C library */
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271 ldr r3, =__libc_init_array
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275 /* Branch to main()
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276 ******************/
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280 /* Loop indefinitely when program is finished */
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