1 /* ----------------------------------------------------------------------------
\r
2 * SAM Software Package License
\r
3 * ----------------------------------------------------------------------------
\r
4 * Copyright (c) 20143, Atmel Corporation
\r
6 * All rights reserved.
\r
8 * Redistribution and use in source and binary forms, with or without
\r
9 * modification, are permitted provided that the following conditions are met:
\r
11 * - Redistributions of source code must retain the above copyright notice,
\r
12 * this list of conditions and the disclaimer below.
\r
14 * Atmel's name may not be used to endorse or promote products derived from
\r
15 * this software without specific prior written permission.
\r
17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
\r
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
\r
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
\r
23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
\r
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
\r
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
\r
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
27 * ----------------------------------------------------------------------------
\r
30 /** \addtogroup ddrd_module
\r
32 * The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
\r
33 * four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved
\r
34 * to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.
\r
36 * \section ddr2 Configures DDR2
\r
38 * The DDR2-SDRAM devices are initialized by the following sequence:
\r
40 * <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
\r
41 * <li> Step 1: Program the memory device type</li>
\r
43 * -# Program the features of DDR2-SDRAM device into the Configuration Register.
\r
44 * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR.
\r
45 * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR.
\r
46 * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR. </li>
\r
47 * <li> Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock. </li>
\r
48 * <li> Step 4: An NOP command is issued to the DDR2-SDRAM </li>
\r
49 * <li> Step 5: An all banks precharge command is issued to the DDR2-SDRAM. </li>
\r
50 * <li> Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.</li>
\r
51 * <li> Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. </li>
\r
52 * <li> Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.</li>
\r
53 * <li> Step 9: Program DLL field into the Configuration Register.</li>
\r
54 * <li> Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.</li>
\r
55 * <li> Step 11: An all banks precharge command is issued to the DDR2-SDRAM.</li>
\r
56 * <li> Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.</li>
\r
57 * <li> Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).</li>
\r
58 * <li> Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.</li>
\r
59 * <li> Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). </li>
\r
60 * <li> Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.</li>
\r
61 * <li> Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).</li>
\r
62 * <li> Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.</li>
\r
63 * <li> Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.</li>
\r
64 * <li> Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 or 7.81. </li>
\r
70 /** \addtogroup sdram_module
\r
72 * \section sdram Configures SDRAM
\r
74 * The SDR-SDRAM devices are initialized by the following sequence:
\r
76 * <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
\r
77 * <li> Step 1. Program the memory device type into the Memory Device Register</li>
\r
78 * <li> Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.</li>
\r
79 * <li> Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.</li>
\r
80 * <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
\r
81 * set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command.
\r
82 * Now the clock which drives SDR-SDRAM device is enabled.</li>
\r
83 * <li> Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the
\r
84 * Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.</li>
\r
85 * <li> Step 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register.
\r
86 * Once in the idle state, two AUTO REFRESH cycles must be performed.</li>
\r
87 * <li> Step 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM
\r
88 * devices, in particular CAS latency and burst length. </li>
\r
89 * <li> Step 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The write
\r
90 * address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0 </li>
\r
91 * <li> Step 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and perform a write access at any location in the SDRAM to acknowledge this command.</li>
\r
92 * <li> Step 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register </li>
\r
103 * Implementation of memories configuration on board.
\r
108 /*----------------------------------------------------------------------------
\r
110 *----------------------------------------------------------------------------*/
\r
113 /*----------------------------------------------------------------------------
\r
114 * Exported functions
\r
115 *----------------------------------------------------------------------------*/
\r
118 * \brief Changes the mapping of the chip so that the remap area mirrors the
\r
119 * internal ROM or the EBI CS0.
\r
121 void BOARD_RemapRom( void )
\r
123 AXIMX->AXIMX_REMAP = 0;
\r
127 * \brief Changes the mapping of the chip so that the remap area mirrors the
\r
131 void BOARD_RemapRam( void )
\r
133 AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0;
\r
137 * \brief Initialize Vdd EBI drive
\r
138 * \param 0: 1.8V 1: 3.3V
\r
140 void BOARD_ConfigureVddMemSel( uint8_t VddMemSel )
\r
142 ( void ) VddMemSel;
\r
145 #define DDR2_BA0(r) (1 << (26 + r))
\r
146 #define DDR2_BA1(r) (1 << (27 + r))
\r
148 #define H64MX_DDR_SLAVE_PORT0 3
\r
150 static void matrix_configure_slave_ddr(void)
\r
154 /* Disable write protection */
\r
155 MATRIX0->MATRIX_WPMR = MPDDRC_WPMR_WPKEY_PASSWD;
\r
157 /* Partition internal SRAM */
\r
158 MATRIX0->MATRIX_SSR[11] = 0;
\r
159 MATRIX0->MATRIX_SRTSR[11] = 0x05;
\r
160 MATRIX0->MATRIX_SASSR[11] = 0x04;
\r
164 /* Partition external DDR */
\r
165 /* DDR port 0 not used from NWd */
\r
166 for (ddr_port = 1 ; ddr_port < 8 ; ddr_port++) {
\r
167 MATRIX0->MATRIX_SSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x00FFFFFF;
\r
168 MATRIX0->MATRIX_SRTSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000000F;
\r
169 MATRIX0->MATRIX_SASSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000FFFF;
\r
173 #define MATRIX_KEY_VAL (0x4D4154u)
\r
175 static void matrix_configure_slave_nand(void)
\r
177 /* Disable write protection */
\r
178 MATRIX0->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
\r
179 MATRIX1->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
\r
181 /* Partition internal SRAM */
\r
182 MATRIX0->MATRIX_SSR[11] = 0x00010101;
\r
183 MATRIX0->MATRIX_SRTSR[11] = 0x05;
\r
184 MATRIX0->MATRIX_SASSR[11] = 0x05;
\r
186 MATRIX1->MATRIX_SRTSR[3] = 0xBBBBBBBB;
\r
187 MATRIX1->MATRIX_SSR[3] = 0x00FFFFFF;
\r
188 MATRIX1->MATRIX_SASSR[3] = 0xBBBBBBBB;
\r
190 MATRIX1->MATRIX_SRTSR[4] = 0x01;
\r
191 MATRIX1->MATRIX_SSR[4] = 0x00FFFFFF;
\r
192 MATRIX1->MATRIX_SASSR[4] = 0x01;
\r
193 MATRIX1->MATRIX_MEIER = 0x3FF;
\r
197 * \brief Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
\r
198 MT47H64M16HR : 8 Meg x 16 x 8 banks
\r
200 Row address: A[12:0] (8K)
\r
201 Column address A[9:0] (1K)
\r
202 Bank address BA[2:0] a(24,25) (8)
\r
204 void BOARD_ConfigureDdram( void )
\r
206 volatile uint8_t *pDdr = (uint8_t *) DDR_CS_ADDR;
\r
207 volatile uint32_t i;
\r
209 volatile uint32_t dummy_value;
\r
211 matrix_configure_slave_ddr();
\r
213 /* Enable DDR2 clock x2 in PMC */
\r
214 PMC->PMC_PCER0 = (1 << (ID_MPDDRC));
\r
215 PMC->PMC_SCER |= PMC_SCER_DDRCK;
\r
217 /* MPDDRC I/O Calibration Register */
\r
218 dummy_value = MPDDRC->MPDDRC_IO_CALIBR;
\r
219 dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;
\r
220 dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;
\r
221 dummy_value |= MPDDRC_IO_CALIBR_CALCODEP(7);
\r
222 dummy_value |= MPDDRC_IO_CALIBR_CALCODEN(8);
\r
223 dummy_value |= MPDDRC_IO_CALIBR_RDIV_RZQ_60_RZQ_50;
\r
224 dummy_value |= MPDDRC_IO_CALIBR_TZQIO(5);
\r
225 dummy_value |= MPDDRC_IO_CALIBR_EN_CALIB_ENABLE_CALIBRATION;
\r
226 MPDDRC->MPDDRC_IO_CALIBR = dummy_value;
\r
228 /* Step 1: Program the memory device type */
\r
229 /* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/
\r
231 MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM | MPDDRC_MD_DBW_DBW_32_BITS;
\r
233 MPDDRC->MPDDRC_RD_DATA_PATH = MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE;
\r
235 /* Step 2: Program the features of DDR2-SDRAM device into the Timing Register.*/
\r
236 MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_14_ROW_BITS |
\r
237 MPDDRC_CR_NC_10_COL_BITS |
\r
238 MPDDRC_CR_CAS_DDR_CAS3 |
\r
239 MPDDRC_CR_DLL_RESET_DISABLED |
\r
240 MPDDRC_CR_DQMS_NOT_SHARED |
\r
241 MPDDRC_CR_ENRDM_OFF |
\r
242 MPDDRC_CR_NB_8_BANKS |
\r
243 MPDDRC_CR_NDQS_DISABLED |
\r
244 MPDDRC_CR_UNAL_SUPPORTED |
\r
245 MPDDRC_CR_OCD_DDR2_EXITCALIB;
\r
247 MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(8) // 40 ns
\r
248 | MPDDRC_TPR0_TRCD(3) // 12.5 ns
\r
249 | MPDDRC_TPR0_TWR(3) // 15 ns
\r
250 | MPDDRC_TPR0_TRC(10) // 55 ns
\r
251 | MPDDRC_TPR0_TRP(3) // 12.5 ns
\r
252 | MPDDRC_TPR0_TRRD(2) // 8 ns
\r
253 | MPDDRC_TPR0_TWTR(2) // 2 clock cycle
\r
254 | MPDDRC_TPR0_TMRD(2); // 2 clock cycles
\r
257 MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(23)
\r
258 | MPDDRC_TPR1_TXSNR(25)
\r
259 | MPDDRC_TPR1_TXSRD(200)
\r
260 | MPDDRC_TPR1_TXP(2);
\r
262 MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8)
\r
263 | MPDDRC_TPR2_TXARDS(2)
\r
264 | MPDDRC_TPR2_TRPA(3)
\r
265 | MPDDRC_TPR2_TRTP(2)
\r
266 | MPDDRC_TPR2_TFAW(7);
\r
268 /* DDRSDRC Low-power Register */
\r
269 for (i = 0; i < 13300; i++) {
\r
273 /* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
\r
274 the Mode Register, the application must set MODE to 1 in the Mode Register. */
\r
275 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
\r
276 /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
\r
277 *pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/
\r
279 /* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */
\r
280 for (i = 0; i < 13300; i++) {
\r
284 /* Step 4: An NOP command is issued to the DDR2-SDRAM */
\r
285 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
\r
286 /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
\r
287 *pDdr = 0; /* Now CKE is driven high.*/
\r
288 /* wait 400 ns min */
\r
289 for (i = 0; i < 100; i++) {
\r
293 /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
\r
294 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
\r
295 /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
\r
297 /* wait 400 ns min */
\r
298 for (i = 0; i < 100; i++) {
\r
302 /* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations. */
\r
303 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
\r
304 *((uint8_t *)(pDdr + DDR2_BA1(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. */
\r
305 /* wait 2 cycles min */
\r
306 for (i = 0; i < 100; i++) {
\r
310 /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. */
\r
311 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
\r
312 *((uint8_t *)(pDdr + DDR2_BA1(0) + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.*/
\r
313 /* wait 2 cycles min */
\r
314 for (i = 0; i < 100; i++) {
\r
318 /* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. */
\r
319 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
\r
320 *((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. */
\r
321 /* An additional 200 cycles of clock are required for locking DLL */
\r
322 for (i = 0; i < 10000; i++) {
\r
326 /* Step 9: Program DLL field into the Configuration Register.*/
\r
327 MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
\r
329 /* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */
\r
330 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
\r
331 *(pDdr) = 0; /* The write address must be chosen so that BA[1:0] bits are set to 0. */
\r
332 /* wait 2 cycles min */
\r
333 for (i = 0; i < 100; i++) {
\r
337 /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */
\r
338 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
\r
339 *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
\r
340 /* wait 2 cycles min */
\r
341 for (i = 0; i < 100; i++) {
\r
345 /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register. */
\r
346 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
\r
347 *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
\r
348 /* wait 2 cycles min */
\r
349 for (i = 0; i < 100; i++) {
\r
352 /* Configure 2nd CBR. */
\r
353 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
\r
354 *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
\r
355 /* wait 2 cycles min */
\r
356 for (i = 0; i < 100; i++) {
\r
360 /* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */
\r
361 MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED;
\r
363 /* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */
\r
364 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
\r
365 *(pDdr) = 0; /* The write address must be chosen so that BA[1:0] are set to 0. */
\r
366 /* wait 2 cycles min */
\r
367 for (i = 0; i < 100; i++) {
\r
371 /* Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). */
\r
372 MPDDRC->MPDDRC_CR |= MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB;
\r
374 /* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. */
\r
375 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
\r
376 *((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
\r
377 /* wait 2 cycles min */
\r
378 for (i = 0; i < 100; i++) {
\r
382 /* Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit). */
\r
383 MPDDRC->MPDDRC_CR &= ~(MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB);
\r
385 /* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.*/
\r
386 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
\r
387 *((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
\r
388 /* wait 2 cycles min */
\r
389 for (i = 0; i < 100; i++) {
\r
393 /* Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register. */
\r
394 MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;
\r
397 /* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.
\r
398 With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */
\r
399 /* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average
\r
400 refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly
\r
401 refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */
\r
402 /* ((64 x 10(^-3))/8192) x133 x (10^6) */
\r
403 MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(0x2b0); /* Set Refresh timer 7.8125 us*/
\r
404 /* OK now we are ready to work on the DDRSDR */
\r
405 /* wait for end of calibration */
\r
406 for (i = 0; i < 500; i++) {
\r
412 * \brief Configures the EBI for Sdram (LPSDR Micron MT48H8M16) access.
\r
414 void BOARD_ConfigureSdram( void )
\r
418 /** \brief Configures the EBI for NandFlash access at 133Mhz.
\r
420 void BOARD_ConfigureNandFlash( uint8_t busWidth )
\r
422 PMC_EnablePeripheral(ID_HSMC);
\r
423 matrix_configure_slave_nand();
\r
425 HSMC->HSMC_CS_NUMBER[3].HSMC_SETUP = 0
\r
426 | HSMC_SETUP_NWE_SETUP(2)
\r
427 | HSMC_SETUP_NCS_WR_SETUP(2)
\r
428 | HSMC_SETUP_NRD_SETUP(2)
\r
429 | HSMC_SETUP_NCS_RD_SETUP(2);
\r
431 HSMC->HSMC_CS_NUMBER[3].HSMC_PULSE = 0
\r
432 | HSMC_PULSE_NWE_PULSE(7)
\r
433 | HSMC_PULSE_NCS_WR_PULSE(7)
\r
434 | HSMC_PULSE_NRD_PULSE(7)
\r
435 | HSMC_PULSE_NCS_RD_PULSE(7);
\r
437 HSMC->HSMC_CS_NUMBER[3].HSMC_CYCLE = 0
\r
438 | HSMC_CYCLE_NWE_CYCLE(13)
\r
439 | HSMC_CYCLE_NRD_CYCLE(13);
\r
441 HSMC->HSMC_CS_NUMBER[3].HSMC_TIMINGS = HSMC_TIMINGS_TCLR(3)
\r
442 | HSMC_TIMINGS_TADL(27)
\r
443 | HSMC_TIMINGS_TAR(3)
\r
444 | HSMC_TIMINGS_TRR(6)
\r
445 | HSMC_TIMINGS_TWB(5)
\r
446 | HSMC_TIMINGS_RBNSEL(3)
\r
447 |(HSMC_TIMINGS_NFSEL);
\r
448 HSMC->HSMC_CS_NUMBER[3].HSMC_MODE = HSMC_MODE_READ_MODE |
\r
449 HSMC_MODE_WRITE_MODE |
\r
450 ((busWidth == 8 )? HSMC_MODE_DBW_BIT_8 :HSMC_MODE_DBW_BIT_16) |
\r
451 HSMC_MODE_TDF_CYCLES(1);
\r
455 void BOARD_ConfigureNorFlash( uint8_t busWidth )
\r
458 PMC_EnablePeripheral(ID_HSMC);
\r
461 dbw = HSMC_MODE_DBW_BIT_8;
\r
464 dbw = HSMC_MODE_DBW_BIT_16;
\r
466 /* Configure SMC, NCS0 is assigned to a norflash */
\r
467 HSMC->HSMC_CS_NUMBER[0].HSMC_SETUP = 0x00020001;
\r
468 HSMC->HSMC_CS_NUMBER[0].HSMC_PULSE = 0x0B0B0A0A;
\r
469 HSMC->HSMC_CS_NUMBER[0].HSMC_CYCLE = 0x000E000B;
\r
470 HSMC->HSMC_CS_NUMBER[0].HSMC_TIMINGS = 0x00000000;
\r
471 HSMC->HSMC_CS_NUMBER[0].HSMC_MODE = HSMC_MODE_WRITE_MODE
\r
472 | HSMC_MODE_READ_MODE
\r
474 | HSMC_MODE_EXNW_MODE_DISABLED
\r
475 | HSMC_MODE_TDF_CYCLES(1);
\r