1 /*-----------------------------------------------------------------------------
\r
2 * ATMEL Microcontroller Software Support - ROUSSET -
\r
3 *-----------------------------------------------------------------------------
\r
4 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
\r
5 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
6 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
7 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
\r
8 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
9 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
\r
10 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
\r
11 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
\r
12 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
\r
13 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
14 *----------------------------------------------------------------------------
\r
15 * File Name : catb.h
\r
17 * Creation : DAL 21/Jun/2013
\r
18 *----------------------------------------------------------------------------
\r
23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
24 /** \brief Catb hardware registers */
\r
26 __IO uint32_t CATB_CR; /**< \brief (CATB Offset: 0x00) Control Register */
\r
27 __IO uint32_t CATB_CNTCR; /**< \brief (CATB Offset: 0x04) Counter Control Register */
\r
28 __IO uint32_t CATB_IDLE; /**< \brief (CATB Offset: 0x08) Sensor Idle Level */
\r
29 __IO uint32_t CATB_LEVEL; /**< \brief (CATB Offset: 0x0C) Sensor Relative Level */
\r
30 __IO uint32_t CATB_RAW; /**< \brief (CATB Offset: 0x10) Sensor Raw Value */
\r
31 __IO uint32_t CATB_TIMING; /**< \brief (CATB Offset: 0x14) Filter Timing Register */
\r
32 __IO uint32_t CATB_THRESH; /**< \brief (CATB Offset: 0x18) Threshold Register */
\r
33 __IO uint32_t CATB_PINSEL; /**< \brief (CATB Offset: 0x1C) Pin Selection Register */
\r
34 __IO uint32_t CATB_DMA; /**< \brief (CATB Offset: 0x20) Direct Memory Access Register */
\r
35 __IO uint32_t CATB_ISR; /**< \brief (CATB Offset: 0x24) Interrupt Status Register */
\r
36 __IO uint32_t CATB_IER; /**< \brief (CATB Offset: 0x28) Interrupt Enable Register */
\r
37 __IO uint32_t CATB_IDR; /**< \brief (CATB Offset: 0x2C) Interrupt Disable Register */
\r
38 __IO uint32_t CATB_IMR; /**< \brief (CATB Offset: 0x30) Interrupt Mask Register */
\r
39 __IO uint32_t CATB_SCR; /**< \brief (CATB Offset: 0x34) Status Clear Register */
\r
40 __I uint32_t Reserved1[2];
\r
41 __IO uint32_t CATB_INTCHi; /**< \brief (CATB Offset: 0x40) In-Touch Status Register i */
\r
42 __I uint32_t Reserved2[3];
\r
43 __IO uint32_t CATB_INTCHCLRn; /**< \brief (CATB Offset: 0x50) In-Touch Status Clear Register n */
\r
44 __I uint32_t Reserved3[3];
\r
45 __IO uint32_t CATB_OUTTCHi; /**< \brief (CATB Offset: 0x60) Out-of-Touch Status Register i */
\r
46 __I uint32_t Reserved4[3];
\r
47 __IO uint32_t CATB_OUTTCHCLRn; /**< \brief (CATB Offset: 0x70) Out-of-Touch Status Clear Register n */
\r
48 __I uint32_t Reserved5[33];
\r
49 __IO uint32_t CATB_PARAMETER; /**< \brief (CATB Offset: 0xF8) Parameter Register */
\r
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
58 #define CATB_THRESH_RTHRESH 12
\r
59 #define CATB_THRESH_FTHRESH 0
\r
60 #define CATB_ISR_INTCH (0x1u << 1) /**< \brief (CATB_ISR_INTCH) In-touch */
\r
61 #define CATB_ISR_OUTTCH (0x1u<< 2) /**< \brief (CATB_ISR_OUTTCH) Out-touch */
\r
62 #define CATB_IER_INTCH (0x1u << 1) /**< \brief (CATB_IER_INTCH) In-touch */
\r
63 #define CATB_IER_OUTTCH (0x1u<< 2) /**< \brief (CATB_IER_OUTTCH) Out-touch */
\r
64 #define CATB_CR_SWRST (0x1u << 31)
\r
65 #define CATB_CR_EN ( 1u<<0 )
\r
66 #define CATB_CR_CHARGET_Pos 16
\r
67 #define CATB_CR_CHARGET_Msk (0xfu << CATB_CR_CHARGET_Pos) /**< \brief (CATB_CNTCR) Counter Top Value */
\r
68 #define CATB_CR_CHARGET(value) ((CATB_CR_CHARGET_Msk & ((value) << CATB_CR_CHARGET_Pos)))
\r
69 #define CATB_CNTCR_TOP 0
\r
70 #define CATB_SPREAD 24
\r
71 #define CATB_REPEAT 28
\r
72 #define CATB_TIMING_TIDLE 16
\r
73 #define CATB_TIMING_TLEVEL 0
\r
74 #define CATB_ISR_SAMPLE (1 << 0)
\r
75 #define CATB_CR_RUN (0x1u << 1)
\r
76 #define CATB_CR_IIDLE (1<< 2)
\r
77 #define CATB_CR_DMAEN (1 << 7)
\r