1 /* ----------------------------------------------------------------------------
\r
2 * SAM Software Package License
\r
3 * ----------------------------------------------------------------------------
\r
4 * Copyright (c) 2014, Atmel Corporation
\r
6 * All rights reserved.
\r
8 * Redistribution and use in source and binary forms, with or without
\r
9 * modification, are permitted provided that the following conditions are met:
\r
11 * - Redistributions of source code must retain the above copyright notice,
\r
12 * this list of conditions and the disclaimer below.
\r
14 * Atmel's name may not be used to endorse or promote products derived from
\r
15 * this software without specific prior written permission.
\r
17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
\r
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
\r
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
\r
23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
\r
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
\r
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
\r
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
27 * ----------------------------------------------------------------------------
\r
33 * Interface for Level 2 cache (L2CC) controller.
\r
37 /** \addtogroup L2cc_module
\r
39 * \section L2cc_usage Usage
\r
40 * - L2CC_IsEnabled: Check if L2CC is enable
\r
41 * - L2CC_Enable: Enable L2 cache controller with default parameters
\r
42 * - ISI_DisableInterrupt: disable one or more interrupts
\r
43 * - ISI_Enable: enable isi module
\r
44 * - ISI_Disable: disable isi module
\r
45 * - ISI_CodecPathFull: enable codec path
\r
46 * - ISI_SetFrame: set frame rate
\r
47 * - ISI_BytesForOnePixel: return number of byte for one pixel
\r
48 * - ISI_StatusRegister: return ISI status register
\r
49 * - ISI_Reset: make a software reset
\r
55 /*----------------------------------------------------------------------------
\r
57 *----------------------------------------------------------------------------*/
\r
70 #define OFFSET_BIT 5
\r
74 #define DCACHE_CLEAN 0
\r
75 #define DCACHE_INVAL 1
\r
76 #define DCACHE_FLUSH 2
\r
78 #define RESET_EVCOUNTER0 0
\r
79 #define RESET_EVCOUNTER1 1
\r
80 #define RESET_BOTH_COUNTER 3
\r
82 #define FWA_DEFAULT 0
\r
83 #define FWA_NO_ALLOCATE 1
\r
84 #define FWA_FORCE_ALLOCATE 2
\r
85 #define FWA_INTERNALLY_MAPPED 3
\r
86 /*----------------------------------------------------------------------------
\r
88 *----------------------------------------------------------------------------*/
\r
101 }RAMLatencyControl;
\r
103 /** L2CC structur */
\r
106 /** High Priority for SO and Dev Reads Enable */
\r
108 /** Store Buffer Device Limitation Enable */
\r
109 uint32_t SBDLE_Val;
\r
110 /** Shared Attribute Invalidate Enable */
\r
112 /** Event Monitor Bus Enable */
\r
113 uint32_t EMBEN_Val;
\r
114 /** Parity Enable */
\r
116 /** Shared Attribute Override Enable */
\r
117 uint32_t SAOEN_Val;
\r
118 /** Force Write Allocate */
\r
120 /** Cache Replacement Policy */
\r
121 uint32_t CRPOL_Val;
\r
122 /** Non-Secure Lockdown Enable*/
\r
123 uint32_t NSLEN_Val;
\r
124 /** Non-Secure Interrupt Access Control */
\r
125 uint32_t NSIAC_Val;
\r
126 /** Data Prefetch Enable*/
\r
128 /** Instruction Prefetch Enable */
\r
130 /** Prefetch Offset */
\r
131 uint32_t OFFSET_Val;
\r
132 /** Not Same ID on Exclusive Sequence Enable */
\r
133 uint32_t NSIDEN_Val;
\r
134 /** INCR Double Linefill Enable */
\r
135 uint32_t IDLEN_Val;
\r
136 /** Prefetch Drop Enable*/
\r
138 /** Double Linefill on WRAP Read Disable */
\r
139 uint32_t DLFWRDIS_Val;
\r
140 /** Double linefill Enable */
\r
142 /** Standby Mode Enable */
\r
143 uint32_t STBYEN_Val;
\r
144 /** Dynamic Clock Gating Enable */
\r
145 uint32_t DCKGATEN_Val;
\r
146 /** Disable Cache Linefill*/
\r
148 /** Disable Write-back, Force Write-through */
\r
151 /*----------------------------------------------------------------------------
\r
152 * Exported functions
\r
153 *----------------------------------------------------------------------------*/
\r
156 extern unsigned int L2CC_IsEnabled(L2cc* pL2CC);
\r
157 extern void L2CC_Enable(L2cc* pL2CC);
\r
158 extern void L2CC_Disable(L2cc* pL2CC);
\r
159 extern void L2CC_ExclusiveCache(L2cc* pL2CC, uint8_t Enable);
\r
160 extern void L2CC_ConfigLatRAM(L2cc* pL2CC, RAMLatencyControl *pLat);
\r
161 extern void L2CC_Config(L2cc* pL2CC, L2CC_Control L2cc_Config);
\r
162 extern void L2CC_DataPrefetchEnable(L2cc* pL2CC );
\r
163 extern void L2CC_InstPrefetchEnable(L2cc* pL2CC );
\r
164 extern void L2CC_EnableResetCounter(L2cc* pL2CC , uint8_t EvenetCounter);
\r
165 extern void L2CC_EventConfig(L2cc* pL2CC, uint8_t EventCounter, uint8_t Source, uint8_t IntGen);
\r
166 extern unsigned int L2CC_EventCounterValue(L2cc* pL2CC, uint8_t EventCounter);
\r
167 extern void L2CC_EnableIT(L2cc* pL2CC, uint16_t ITSource);
\r
168 extern void L2CC_DisableIT(L2cc* pL2CC, uint16_t ITSource);
\r
169 extern unsigned short L2CC_ITStatusRaw(L2cc* pL2CC, uint16_t ITSource);
\r
170 extern unsigned short L2CC_ITStatusMask(L2cc* pL2CC, uint16_t ITSource);
\r
171 extern void L2CC_ITClear(L2cc* pL2CC, uint16_t ITSource);
\r
172 uint8_t L2CC_PollSPNIDEN(L2cc* pL2CC);
\r
173 extern void L2CC_CacheSync(L2cc* pL2CC);
\r
174 extern void L2CC_InvalidateWay(L2cc* pL2CC, uint8_t Way);
\r
175 extern void L2CC_CleanWay(L2cc* pL2CC, uint8_t Way);
\r
176 extern void L2CC_InvalidatePAL(L2cc* pL2CC, uint32_t P_Address);
\r
177 extern void L2CC_CleanPAL(L2cc* pL2CC, uint32_t P_Address);
\r
178 extern void L2CC_CleanIx(L2cc* pL2CC, uint32_t P_Address);
\r
180 extern void L2CC_CleanIndex(L2cc* pL2CC, uint32_t P_Address, uint8_t Way);
\r
181 extern void L2CC_CleanInvalidateIndex(L2cc* pL2CC, uint32_t P_Address, uint8_t Way);
\r
182 extern void L2CC_DataLockdown(L2cc* pL2CC, uint8_t Way);
\r
183 extern void L2CC_InstructionLockdown(L2cc* pL2CC, uint8_t Way);
\r
184 extern void L2CC_CacheMaintenance(uint8_t Maint_Op);
\r
185 extern void Enable_L2CC(void);
\r
191 #endif /* #ifndef _L2CC_ */
\r