2 FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 * This file initialises three timers as follows:
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73 * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ
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74 * standard demo tasks, which test interrupt nesting and using queues from
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75 * interrupts. As the interrupt is shared the nesting achieved is not as deep
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76 * as normal when this test is executed, but still worth while.
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78 * TC2 channel 0 provides a much higher frequency timer that tests the nesting
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79 * of interrupts that don't use the FreeRTOS API. For convenience, the high
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80 * frequency timer also keeps a count of the number of time it executes, and the
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81 * count is used as the time base for the run time stats (which can be viewed
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84 * All the timers can nest with the tick interrupt - creating a maximum
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85 * interrupt nesting depth of 3 (normally 4, if the first two timers used
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86 * separate interrupts).
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90 /* Scheduler includes. */
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91 #include "FreeRTOS.h"
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93 /* Demo includes. */
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94 #include "IntQueueTimer.h"
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95 #include "IntQueue.h"
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97 /* Library includes. */
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100 /* The frequencies at which the first two timers expire are slightly offset to
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101 ensure they don't remain synchronised. The frequency of the highest priority
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102 interrupt is 20 times faster so really hammers the interrupt entry and exit
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104 #define tmrTIMER_0_FREQUENCY ( 2000UL )
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105 #define tmrTIMER_1_FREQUENCY ( 2003UL )
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106 #define tmrTIMER_2_FREQUENCY ( 20000UL )
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108 /* The channels used in TC0 for generating the three interrupts. */
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109 #define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */
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110 #define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */
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111 #define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */
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113 /* The bit within the RC_SR register that indicates an RC compare. */
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114 #define tmrRC_COMPARE ( 1UL << 4UL )
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116 /* The high frequency interrupt given the highest priority or all. The priority
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117 of the lower frequency timers must still be above the tick interrupt priority. */
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118 #define tmrLOWER_PRIORITY 3
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119 #define tmrHIGHER_PRIORITY 5
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120 /*-----------------------------------------------------------*/
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122 /* Handlers for the two timer peripherals - two channels are used in the TC0
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124 static void prvTC0_Handler( void );
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125 static void prvTC1_Handler( void );
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127 /* Used to provide a means of ensuring the intended interrupt nesting depth is
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128 actually being reached. */
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129 extern uint32_t ulPortInterruptNesting;
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130 static uint32_t ulMaxRecordedNesting = 0;
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132 /* For convenience the high frequency timer increments a variable that is then
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133 used as the time base for the run time stats. */
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134 volatile uint32_t ulHighFrequencyTimerCounts = 0;
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136 /*-----------------------------------------------------------*/
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138 void vInitialiseTimerForIntQueueTest( void )
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140 const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;
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142 /* Enable the TC clocks. */
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143 PMC_EnablePeripheral( ID_TC0 );
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144 PMC_EnablePeripheral( ID_TC1 );
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146 /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger
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147 on RC compare. This is part of the IntQTimer test. */
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148 TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
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149 TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( BOARD_MCK / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider );
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150 TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
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152 /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger
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153 on RC compare. This is part of the IntQTimer test. */
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154 TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );
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155 TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( BOARD_MCK / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider );
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156 TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;
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158 /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on
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159 RC compare. This is the very high frequency timer. */
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160 TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
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161 TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_2_FREQUENCY * ulDivider );
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162 TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
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164 /* First setup TC0 interrupt, in which two channels are used. */
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165 AIC->AIC_SSR = ID_TC0;
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167 /* Ensure the interrupt is disabled before setting mode and handler. */
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168 AIC->AIC_IDCR = AIC_IDCR_INTD;
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169 AIC->AIC_SMR = AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE | tmrLOWER_PRIORITY;
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170 AIC->AIC_SVR = ( uint32_t ) prvTC0_Handler;
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172 /* Start with the interrupt clear. */
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173 AIC->AIC_ICCR = AIC_ICCR_INTCLR;
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175 /* Do the same for TC1 - which is the high frequency timer. */
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176 AIC->AIC_SSR = ID_TC1;
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177 AIC->AIC_IDCR = AIC_IDCR_INTD;
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178 AIC->AIC_SMR = AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE | tmrHIGHER_PRIORITY;
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179 AIC->AIC_SVR = ( uint32_t ) prvTC1_Handler;
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180 AIC->AIC_ICCR = AIC_ICCR_INTCLR;
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182 /* Finally enable the interrupts and start the timers. */
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183 AIC_EnableIT( ID_TC0 );
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184 AIC_EnableIT( ID_TC1 );
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185 TC_Start( TC0, tmrTC0_CHANNEL_0 );
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186 TC_Start( TC0, tmrTC0_CHANNEL_1 );
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187 TC_Start( TC1, tmrTC1_CHANNEL_0 );
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189 /*-----------------------------------------------------------*/
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191 static void prvTC0_Handler( void )
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193 uint32_t ulDidSomething;
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197 ulDidSomething = pdFALSE;
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199 /* Read will clear the status bit. */
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200 if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 )
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202 /* Call the IntQ test function for this channel. */
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203 portYIELD_FROM_ISR( xFirstTimerHandler() );
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204 ulDidSomething = pdTRUE;
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207 if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 )
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209 /* Call the IntQ test function for this channel. */
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210 portYIELD_FROM_ISR( xSecondTimerHandler() );
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211 ulDidSomething = pdTRUE;
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214 } while( ulDidSomething == pdTRUE );
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216 /*-----------------------------------------------------------*/
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218 static void prvTC1_Handler( void )
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220 volatile uint32_t ulDummy;
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222 /* Dummy read to clear status bit. */
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223 ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR;
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225 /* Latch the maximum nesting count. */
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226 if( ulPortInterruptNesting > ulMaxRecordedNesting )
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228 ulMaxRecordedNesting = ulPortInterruptNesting;
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231 /* Keep a count of the number of interrupts to use as a time base for the
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233 ulHighFrequencyTimerCounts++;
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