1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2014, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 IAR startup file for SAMA5D4X microcontrollers.
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36 ;; Forward declaration of sections.
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37 SECTION IRQ_STACK:DATA:NOROOT(2)
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38 SECTION FIQ_STACK:DATA:NOROOT(2)
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39 SECTION UND_STACK:DATA:NOROOT(2)
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40 SECTION ABT_STACK:DATA:NOROOT(2)
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41 SECTION CSTACK:DATA:NOROOT(3)
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43 //------------------------------------------------------------------------------
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45 //------------------------------------------------------------------------------
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47 #define __ASSEMBLY__
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49 //------------------------------------------------------------------------------
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51 //------------------------------------------------------------------------------
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53 #define AIC 0xFC06E000
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54 #define AIC_IVR 0x10
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55 #define AIC_EOICR 0x38
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56 #define L2CC_CR 0x00A00100
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58 #define REG_SFR_AICREDIR 0xF8028054
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59 #define REG_SFR_UID 0xF8028050
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60 #define AICREDIR_KEY 0x5F67B102
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63 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
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64 #define ARM_MODE_ABT 0x17
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65 #define ARM_MODE_FIQ 0x11
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66 #define ARM_MODE_IRQ 0x12
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67 #define ARM_MODE_SVC 0x13
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68 #define ARM_MODE_SYS 0x1F
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69 #define ARM_MODE_UND 0x1B
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75 //------------------------------------------------------------------------------
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77 //------------------------------------------------------------------------------
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82 SECTION .vectors:CODE:NOROOT(2)
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86 EXTERN FreeRTOS_IRQ_Handler
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87 EXTERN Undefined_C_Handler
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88 EXTERN FreeRTOS_SWI_Handler
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89 EXTERN Prefetch_C_Handler
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90 EXTERN Abort_C_Handler
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95 __iar_init$$done: ; The interrupt vector is not needed
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96 ; until after copy initialization is done
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99 ; All default exception handlers (except reset) are
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100 ; defined as weak symbol definitions.
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101 ; If a handler is defined by the application it will take precedence.
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102 LDR pc, =resetHandler ; Reset
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103 LDR pc, Undefined_Addr ; Undefined instructions
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104 LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
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105 LDR pc, Prefetch_Addr ; Prefetch abort
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106 LDR pc, Abort_Addr ; Data abort
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108 LDR PC,IRQ_Addr ; 0x18 IRQ
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109 LDR PC,FIQ_Addr ; 0x1c FIQ
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111 IRQ_Addr: DCD FreeRTOS_IRQ_Handler
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112 Undefined_Addr: DCD Undefined_C_Handler
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113 SWI_Addr: DCD FreeRTOS_SWI_Handler
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114 Abort_Addr: DCD Abort_C_Handler
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115 Prefetch_Addr: DCD Prefetch_C_Handler
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116 ;IRQ_Addr: DCD IRQ_Handler
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117 FIQ_Addr: DCD FIQ_Handler
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119 Handles incoming interrupt requests by branching to the corresponding
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120 handler, as defined in the AIC. Supports interrupt nesting.
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123 /* Save interrupt context on the stack to allow nesting */
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127 STMFD sp!, {r0, lr}
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129 /* Write in the IVR to support Protect Mode */
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131 LDR r0, [r14, #AIC_IVR]
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132 STR lr, [r14, #AIC_IVR]
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134 /* Branch to interrupt handler in Supervisor mode */
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135 MSR CPSR_c, #ARM_MODE_SVC
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136 STMFD sp!, {r1-r3, r4, r12, lr}
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138 /* Check for 8-byte alignment and save lr plus a */
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139 /* word to indicate the stack adjustment used (0 or 4) */
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142 STMFD sp!, {r1, lr}
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146 LDMIA sp!, {r1, lr}
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149 LDMIA sp!, {r1-r3, r4, r12, lr}
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150 MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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152 /* Acknowledge interrupt */
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154 STR lr, [r14, #AIC_EOICR]
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156 /* Restore interrupt context and branch back to calling code */
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157 LDMIA sp!, {r0, lr}
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163 After a reset, execution starts here, the mode is ARM, supervisor
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164 with interrupts disabled.
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165 Initializes the chip and branches to the main() function.
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167 SECTION .cstartup:CODE:NOROOT(2)
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169 PUBLIC resetHandler
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170 EXTERN LowLevelInit
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172 REQUIRE resetVector
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173 EXTERN CP15_InvalidateBTB
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174 EXTERN CP15_InvalidateTranslationTable
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175 EXTERN CP15_InvalidateIcache
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176 EXTERN CP15_InvalidateDcacheBySetWay
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181 LDR r4, =SFE(CSTACK) ; End of SVC stack
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182 BIC r4,r4,#0x7 ; Make sure SP is 8 aligned
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186 ;; Set up the normal interrupt stack pointer.
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188 MSR CPSR_c, #(ARM_MODE_IRQ | F_BIT | I_BIT)
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189 LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
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190 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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193 ;; Set up the fast interrupt stack pointer.
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195 MSR CPSR_c, #(ARM_MODE_FIQ | F_BIT | I_BIT)
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196 LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
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197 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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199 MSR CPSR_c, #(ARM_MODE_ABT | F_BIT | I_BIT)
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200 LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
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201 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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203 MSR CPSR_c, #(ARM_MODE_UND | F_BIT | I_BIT)
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204 LDR sp, =SFE(UND_STACK) ; End of UND_STACK
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205 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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207 MSR CPSR_c, #(ARM_MODE_SYS | F_BIT | I_BIT)
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208 LDR sp, =SFE(CSTACK-0x3000) ; 0x1000 bytes of SYS stack
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209 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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212 MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)
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217 /* - Enable access to CP10 and CP11 in CP15.CACR */
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218 MRC p15, 0, r0, c1, c0, 2
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219 ORR r0, r0, #0xf00000
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220 MCR p15, 0, r0, c1, c0, 2
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221 /* - Enable access to CP10 and CP11 in CP15.NSACR */
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222 /* - Set FPEXC.EN (B30) */
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224 MOV r3, #0x40000000
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228 // Redirect FIQ to IRQ
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229 LDR r0, =AICREDIR_KEY
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230 LDR r1, = REG_SFR_UID
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231 LDR r2, = REG_SFR_AICREDIR
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237 /* Perform low-level initialization of the chip using LowLevelInit() */
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238 LDR r0, =LowLevelInit
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242 MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Regsiter into r0
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243 TST r0, #0x1 ; Is the MMU enabled?
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244 BICNE r0, r0, #0x1 ; Clear bit 0
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245 TST r0, #0x4 ; Is the Dcache enabled?
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246 BICNE r0, r0, #0x4 ; Clear bit 2
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247 MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
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249 // Disbale L2 cache
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255 BL CP15_InvalidateTranslationTable
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256 BL CP15_InvalidateBTB
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257 BL CP15_InvalidateIcache
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258 BL CP15_InvalidateDcacheBySetWay
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263 /* Branch to main() */
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267 /* Loop indefinitely when program is finished */
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273 ;------------------------------------------------------------------------------
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274 ;- Function : FIQ_Handler
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275 ;- Treatments : FIQ Controller Interrupt Handler.
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276 ;- Called Functions : AIC_IVR[interrupt]
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277 ;------------------------------------------------------------------------------
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278 SAIC DEFINE 0xFC068400
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279 AIC_FVR DEFINE 0x14
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281 SECTION .text:CODE:NOROOT(2)
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284 /* Save interrupt context on the stack to allow nesting */
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290 /* Write in the IVR to support Protect Mode */
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292 LDR r0, [r14, #AIC_IVR]
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293 STR lr, [r14, #AIC_IVR]
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295 /* Branch to interrupt handler in Supervisor mode */
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296 MSR CPSR_c, #ARM_MODE_SVC
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297 STMFD sp!, {r1-r3, r4, r12, lr}
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302 LDMIA sp!, {r1-r3, r4, r12, lr}
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303 MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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305 /* Acknowledge interrupt */
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307 STR lr, [r14, #AIC_EOICR]
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309 /* Restore interrupt context and branch back to calling code */
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311 /* MSR SPSR_cxsf, lr */
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