git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c

   1 /******************************************************************************\r
   2  *\r
   3  * alt_address_space.c - API for the Altera SoC FPGA address space.\r
   4  *\r
   5  ******************************************************************************/\r
   6 \r
   7 /******************************************************************************\r
   8  *\r
   9  * Copyright 2013 Altera Corporation. All Rights Reserved.\r
  10  * \r
  11  * Redistribution and use in source and binary forms, with or without\r
  12  * modification, are permitted provided that the following conditions are met:\r
  13  * \r
  14  * 1. Redistributions of source code must retain the above copyright notice,\r
  15  * this list of conditions and the following disclaimer.\r
  16  * \r
  17  * 2. Redistributions in binary form must reproduce the above copyright notice,\r
  18  * this list of conditions and the following disclaimer in the documentation\r
  19  * and/or other materials provided with the distribution.\r
  20  * \r
  21  * 3. The name of the author may not be used to endorse or promote products\r
  22  * derived from this software without specific prior written permission.\r
  23  * \r
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR\r
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
  26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO\r
  27  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
  29  * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
  32  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
  33  * OF SUCH DAMAGE.\r
  34  * \r
  35  ******************************************************************************/\r
  36 \r
  37 #include <stddef.h>\r
  38 #include "alt_address_space.h"\r
  39 #include "socal/alt_l3.h"\r
  40 #include "socal/socal.h"\r
  41 #include "socal/alt_acpidmap.h"\r
  42 #include "hwlib.h"\r
  43 \r
  44 \r
  45 #define ALT_ACP_ID_MAX_INPUT_ID     7\r
  46 #define ALT_ACP_ID_MAX_OUTPUT_ID    4096\r
  47 \r
  48 /******************************************************************************/\r
  49 ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,\r
  50                                      ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,\r
  51                                      ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,\r
  52                                      ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)\r
  53 {\r
  54     uint32_t remap_reg_val = 0;\r
  55 \r
  56     // Parameter checking and validation...\r
  57     if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)\r
  58     {\r
  59         remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);\r
  60     }\r
  61     else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)\r
  62     {\r
  63         remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);\r
  64     }\r
  65     else\r
  66     {\r
  67         return ALT_E_INV_OPTION;\r
  68     }\r
  69 \r
  70     if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)\r
  71     {\r
  72         remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);\r
  73     }\r
  74     else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)\r
  75     {\r
  76         remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);\r
  77     }\r
  78     else\r
  79     {\r
  80         return ALT_E_INV_OPTION;\r
  81     }\r
  82 \r
  83     if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)\r
  84     {\r
  85         remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);\r
  86     }\r
  87     else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)\r
  88     {\r
  89         remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);\r
  90     }\r
  91     else\r
  92     {\r
  93         return ALT_E_INV_OPTION;\r
  94     }\r
  95 \r
  96     if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)\r
  97     {\r
  98         remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);\r
  99     }\r
 100     else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)\r
 101     {\r
 102         remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);\r
 103     }\r
 104     else\r
 105     {\r
 106         return ALT_E_INV_OPTION;\r
 107     }\r
 108 \r
 109     // Perform the remap.\r
 110     alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);\r
 111 \r
 112     return ALT_E_SUCCESS;\r
 113 }\r
 114 \r
 115 /******************************************************************************/\r
 116 // Remap the MPU address space view of address 0 to access the SDRAM controller.\r
 117 // This is done by setting the L2 cache address filtering register start address\r
 118 // to 0 and leaving the address filtering address end address value\r
 119 // unmodified. This causes all physical addresses in the range\r
 120 // address_filter_start <= physical_address < address_filter_end to be directed\r
 121 // to the to the AXI Master Port M1 which is connected to the SDRAM\r
 122 // controller. All other addresses are directed to AXI Master Port M0 which\r
 123 // connect the MPU subsystem to the L3 interconnect.\r
 124 //\r
 125 // It is unnecessary to modify the MPU remap options in the L3 remap register\r
 126 // because those options only affect addresses in the MPU subsystem address\r
 127 // ranges that are now redirected to the SDRAM controller and never reach the L3\r
 128 // interconnect anyway.\r
 129 ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)\r
 130 {\r
 131     uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &\r
 132                               L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);\r
 133     return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);\r
 134 }\r
 135 \r
 136 /******************************************************************************/\r
 137 // Return the L2 cache address filtering registers configuration settings in the\r
 138 // user provided start and end address range out parameters.\r
 139 ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,\r
 140                                            uint32_t* addr_filt_end)\r
 141 {\r
 142     if (addr_filt_start == NULL || addr_filt_end == NULL)\r
 143     {\r
 144         return ALT_E_BAD_ARG;\r
 145     }\r
 146 \r
 147     uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);\r
 148     uint32_t addr_filt_end_reg   = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);\r
 149 \r
 150     *addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);\r
 151     *addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);\r
 152     return ALT_E_SUCCESS;\r
 153 }\r
 154 \r
 155 /******************************************************************************/\r
 156 ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,\r
 157                                            uint32_t addr_filt_end)\r
 158 {\r
 159     // Address filtering start and end values must be 1 MB aligned.\r
 160     if (  (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)\r
 161        || (addr_filt_end   & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )\r
 162     {\r
 163         return ALT_E_ARG_RANGE;\r
 164     }\r
 165 \r
 166     // While it is possible to set the address filtering end value above its\r
 167     // reset value and thereby access a larger SDRAM address range, it is not\r
 168     // recommended. Doing so would potentially obscure any mapped HPS to FPGA\r
 169     // bridge address spaces and peripherals on the L3 interconnect.\r
 170     if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)\r
 171     {\r
 172         return ALT_E_ARG_RANGE;\r
 173     }\r
 174 \r
 175     // NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)\r
 176     // recommends programming the Address Filtering End Register before the\r
 177     // Address Filtering Start Register to avoid unpredictable behavior between\r
 178     // the two writes.\r
 179     alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);\r
 180     // It is recommended that address filtering always remain enabled.\r
 181     addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;\r
 182     alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);\r
 183 \r
 184     return ALT_E_SUCCESS;\r
 185 }\r
 186 \r
 187 /******************************************************************************/\r
 188 ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,\r
 189                                               const uint32_t output_id,\r
 190                                               const ALT_ACP_ID_MAP_PAGE_t page,\r
 191                                               const uint32_t aruser)\r
 192 {\r
 193     if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 194     {\r
 195         return ALT_E_BAD_ARG;\r
 196     }\r
 197 \r
 198     switch (output_id)\r
 199     {\r
 200     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 201         alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,\r
 202                          ALT_ACPIDMAP_VID2RD_MID_SET(input_id)\r
 203                        | ALT_ACPIDMAP_VID2RD_PAGE_SET(page)\r
 204                        | ALT_ACPIDMAP_VID2RD_USER_SET(aruser)\r
 205                        | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));\r
 206         break;\r
 207     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 208         alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,\r
 209                          ALT_ACPIDMAP_VID3RD_MID_SET(input_id)\r
 210                        | ALT_ACPIDMAP_VID3RD_PAGE_SET(page)\r
 211                        | ALT_ACPIDMAP_VID3RD_USER_SET(aruser)\r
 212                        | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));\r
 213         break;\r
 214     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 215         alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,\r
 216                          ALT_ACPIDMAP_VID4RD_MID_SET(input_id)\r
 217                        | ALT_ACPIDMAP_VID4RD_PAGE_SET(page)\r
 218                        | ALT_ACPIDMAP_VID4RD_USER_SET(aruser)\r
 219                        | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));\r
 220         break;\r
 221     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 222         alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,\r
 223                          ALT_ACPIDMAP_VID5RD_MID_SET(input_id)\r
 224                        | ALT_ACPIDMAP_VID5RD_PAGE_SET(page)\r
 225                        | ALT_ACPIDMAP_VID5RD_USER_SET(aruser)\r
 226                        | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));\r
 227         break;\r
 228     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 229         alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,\r
 230                          ALT_ACPIDMAP_VID6RD_MID_SET(input_id)\r
 231                        | ALT_ACPIDMAP_VID6RD_PAGE_SET(page)\r
 232                        | ALT_ACPIDMAP_VID6RD_USER_SET(aruser)\r
 233                        | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));\r
 234         break;\r
 235     default:\r
 236         return ALT_E_BAD_ARG;\r
 237     }\r
 238 \r
 239     return ALT_E_SUCCESS;\r
 240 }\r
 241 \r
 242 /******************************************************************************/\r
 243 ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,\r
 244                                                const uint32_t output_id,\r
 245                                                const ALT_ACP_ID_MAP_PAGE_t page,\r
 246                                                const uint32_t awuser)\r
 247 {\r
 248     if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 249     {\r
 250         return ALT_E_BAD_ARG;\r
 251     }\r
 252 \r
 253     switch (output_id)\r
 254     {\r
 255     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 256         alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,\r
 257                          ALT_ACPIDMAP_VID2WR_MID_SET(input_id)\r
 258                        | ALT_ACPIDMAP_VID2WR_PAGE_SET(page)\r
 259                        | ALT_ACPIDMAP_VID2WR_USER_SET(awuser)\r
 260                        | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));\r
 261         break;\r
 262     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 263         alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,\r
 264                          ALT_ACPIDMAP_VID3WR_MID_SET(input_id)\r
 265                        | ALT_ACPIDMAP_VID3WR_PAGE_SET(page)\r
 266                        | ALT_ACPIDMAP_VID3WR_USER_SET(awuser)\r
 267                        | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));\r
 268         break;\r
 269     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 270         alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,\r
 271                          ALT_ACPIDMAP_VID4WR_MID_SET(input_id)\r
 272                        | ALT_ACPIDMAP_VID4WR_PAGE_SET(page)\r
 273                        | ALT_ACPIDMAP_VID4WR_USER_SET(awuser)\r
 274                        | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));\r
 275         break;\r
 276     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 277         alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,\r
 278                          ALT_ACPIDMAP_VID5WR_MID_SET(input_id)\r
 279                        | ALT_ACPIDMAP_VID5WR_PAGE_SET(page)\r
 280                        | ALT_ACPIDMAP_VID5WR_USER_SET(awuser)\r
 281                        | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));\r
 282         break;\r
 283     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 284         alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,\r
 285                          ALT_ACPIDMAP_VID6WR_MID_SET(input_id)\r
 286                        | ALT_ACPIDMAP_VID6WR_PAGE_SET(page)\r
 287                        | ALT_ACPIDMAP_VID6WR_USER_SET(awuser)\r
 288                        | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)\r
 289             );\r
 290         break;\r
 291     default:\r
 292         return ALT_E_BAD_ARG;\r
 293     }\r
 294 \r
 295     return ALT_E_SUCCESS;\r
 296 }\r
 297 \r
 298 /******************************************************************************/\r
 299 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)\r
 300 {\r
 301     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 302     {\r
 303         return ALT_E_BAD_ARG;\r
 304     }\r
 305 \r
 306     uint32_t aruser, page;\r
 307 \r
 308     switch (output_id)\r
 309     {\r
 310     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 311         aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));\r
 312         page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));\r
 313         break;\r
 314     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 315         aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));\r
 316         page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));\r
 317         break;\r
 318     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 319         aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));\r
 320         page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));\r
 321         break;\r
 322     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 323         aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));\r
 324         page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));\r
 325         break;\r
 326     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 327         aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));\r
 328         page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));\r
 329         break;\r
 330     default:\r
 331         return ALT_E_BAD_ARG;\r
 332     }\r
 333 \r
 334     alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,\r
 335                      ALT_ACPIDMAP_DYNRD_PAGE_SET(page)\r
 336                    | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));\r
 337     return ALT_E_SUCCESS;\r
 338 }\r
 339 \r
 340 /******************************************************************************/\r
 341 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)\r
 342 {\r
 343     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 344     {\r
 345         return ALT_E_BAD_ARG;\r
 346     }\r
 347 \r
 348     uint32_t awuser, page;\r
 349 \r
 350     switch (output_id)\r
 351     {\r
 352     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 353         awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));\r
 354         page   = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));\r
 355         break;\r
 356     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 357         awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));\r
 358         page   = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));\r
 359         break;\r
 360     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 361         awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));\r
 362         page   = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));\r
 363         break;\r
 364     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 365         awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));\r
 366         page   = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));\r
 367         break;\r
 368     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 369         awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));\r
 370         page   = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));\r
 371         break;\r
 372     default:\r
 373         return ALT_E_BAD_ARG;\r
 374     }\r
 375 \r
 376     alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,\r
 377                      ALT_ACPIDMAP_DYNWR_PAGE_SET(page)\r
 378                    | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));\r
 379     return ALT_E_SUCCESS;\r
 380 }\r
 381 \r
 382 /******************************************************************************/\r
 383 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,\r
 384                                                         const uint32_t aruser)\r
 385 {\r
 386     alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,\r
 387                      ALT_ACPIDMAP_DYNRD_PAGE_SET(page)\r
 388                    | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));\r
 389     return ALT_E_SUCCESS;\r
 390 }\r
 391 \r
 392 /******************************************************************************/\r
 393 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,\r
 394                                                          const uint32_t awuser)\r
 395 {\r
 396     alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,\r
 397                      ALT_ACPIDMAP_DYNWR_PAGE_SET(page)\r
 398                    | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));\r
 399     return ALT_E_SUCCESS;\r
 400 }\r
 401 \r
 402 /******************************************************************************/\r
 403 ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,\r
 404                                                 bool * fixed,\r
 405                                                 uint32_t * input_id,\r
 406                                                 ALT_ACP_ID_MAP_PAGE_t * page,\r
 407                                                 uint32_t * aruser)\r
 408 {\r
 409     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 410     {\r
 411         return ALT_E_BAD_ARG;\r
 412     }\r
 413 \r
 414     switch (output_id)\r
 415     {\r
 416     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 417         *aruser   = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));\r
 418         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));\r
 419         *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));\r
 420         *fixed    = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));\r
 421         break;\r
 422     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 423         *aruser   = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));\r
 424         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));\r
 425         *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));\r
 426         *fixed    = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));\r
 427         break;\r
 428     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 429         *aruser   = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));\r
 430         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));\r
 431         *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));\r
 432         *fixed    = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));\r
 433         break;\r
 434     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 435         *aruser   = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));\r
 436         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));\r
 437         *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));\r
 438         *fixed    = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));\r
 439         break;\r
 440     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 441         *aruser   = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));\r
 442         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));\r
 443         *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));\r
 444         *fixed    = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));\r
 445         break;\r
 446     case ALT_ACP_ID_OUT_DYNAM_ID_7:\r
 447         *aruser   = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));\r
 448         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));\r
 449         break;\r
 450     default:\r
 451         return ALT_E_BAD_ARG;\r
 452     }\r
 453 \r
 454     return ALT_E_SUCCESS;\r
 455 }\r
 456 \r
 457 ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,\r
 458                                                  bool * fixed,\r
 459                                                  uint32_t * input_id,\r
 460                                                  ALT_ACP_ID_MAP_PAGE_t * page,\r
 461                                                  uint32_t * awuser)\r
 462 {\r
 463     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)\r
 464     {\r
 465         return ALT_E_BAD_ARG;\r
 466     }\r
 467 \r
 468     switch (output_id)\r
 469     {\r
 470     case ALT_ACP_ID_OUT_FIXED_ID_2:\r
 471         *awuser   = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));\r
 472         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));\r
 473         *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));\r
 474         *fixed    = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));\r
 475         break;\r
 476     case ALT_ACP_ID_OUT_DYNAM_ID_3:\r
 477         *awuser   = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));\r
 478         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));\r
 479         *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));\r
 480         *fixed    = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));\r
 481         break;\r
 482     case ALT_ACP_ID_OUT_DYNAM_ID_4:\r
 483         *awuser   = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));\r
 484         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));\r
 485         *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));\r
 486         *fixed    = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));\r
 487         break;\r
 488     case ALT_ACP_ID_OUT_DYNAM_ID_5:\r
 489         *awuser   = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));\r
 490         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));\r
 491         *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));\r
 492         *fixed    = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));\r
 493         break;\r
 494     case ALT_ACP_ID_OUT_DYNAM_ID_6:\r
 495         *awuser   = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));\r
 496         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));\r
 497         *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));\r
 498         *fixed    = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));\r
 499         break;\r
 500     case ALT_ACP_ID_OUT_DYNAM_ID_7:\r
 501         *awuser   = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));\r
 502         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));\r
 503         break;\r
 504     default:\r
 505         return ALT_E_BAD_ARG;\r
 506     }\r
 507 \r
 508     return ALT_E_SUCCESS;\r
 509 }\r