6 // Disable MMU and enable ICache
\r
7 Reg = __jtagCP15ReadReg(1, 0, 0, 0);
\r
10 __jtagCP15WriteReg(1, 0, 0, 0, Reg);
\r
12 //__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR
\r
13 //__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2
\r
15 // Turn on clock for SPI
\r
16 __writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9
\r
18 // Configure PORTS for SPI (serial flash 1)
\r
19 __writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode
\r
20 __writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode
\r
21 __writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode
\r
23 // Configure PORTS for SPI (serial flash 2)
\r
24 __writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode
\r
25 __writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode
\r
26 __writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode
\r
27 __writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode
\r
29 // Configure SPI for EXTREAD mode
\r
30 __writeMemory32(0x01AA4020, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 1-memory, CPHA=0, CPOL=0, SFDE=1
\r
32 // Configure SPI registers
\r
33 __writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13
\r
34 __writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1
\r
35 __writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst
\r
36 __writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range
\r
39 __writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3
\r
42 Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR_0
\r
43 Reg |= 0x00000200; // Set RCF bit
\r
44 __writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR_0
\r
49 __message "----- Prepare hardware for debug -----\n";
\r