2 ; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
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4 ; FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 ; http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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10 ; * Complete, revised, and edited pdf reference manuals are also *
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14 ; * ensuring you get running as quickly as possible and with an *
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15 ; * in-depth knowledge of how to use FreeRTOS, it will also help *
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27 ; This file is part of the FreeRTOS distribution.
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29 ; FreeRTOS is free software; you can redistribute it and/or modify it under
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30 ; the terms of the GNU General Public License (version 2) as published by the
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31 ; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 ; >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 ; distribute a combined work that includes FreeRTOS without being obliged to
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39 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 ; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 ; details. You should have received a copy of the GNU General Public License
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42 ; and the FreeRTOS license exception along with FreeRTOS; if not itcan be
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43 ; viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 ; writing to Real Time Engineers Ltd., contact details for whom are available
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51 ; * Having a problem? Start by reading the FAQ "My application does *
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52 ; * not run, what could be wrong?" *
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54 ; * http://www.FreeRTOS.org/FAQHelp.html *
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56 ; ***************************************************************************
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59 ; http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 ; license and Real Time Engineers Ltd. contact details.
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62 ; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 ; including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 ; fully thread aware and reentrant UDP/IP stack.
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66 ; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 ; Integrity Systems, who sell the code with commercial support,
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68 ; indemnification and middleware, under the OpenRTOS brand.
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70 ; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 ; engineered and independently SIL3 certified version for use in safety and
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72 ; mission critical applications that require provable dependability.
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75 EXPORT vRegTest1Implementation
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76 EXPORT vRegTest2Implementation
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78 ; This file is built with IAR and ARM compilers. When the ARM compiler
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79 ; is used the compiler options must define __IASMARM__ as 0 using the
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80 ; --predefine "__IASMARM__ SETA 0" command line option. When compiling
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81 ; with IAR __IASMARM__ is automatically set to 1 so no additional assembler
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82 ; options are required.
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84 ; Syntax for IAR compiler.
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85 SECTION .text:CODE:ROOT(2)
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87 ; Syntax for ARM compiler.
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88 AREA RegTest, CODE, READONLY
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92 ; This function is explained in the comments at the top of main-full.c.
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93 vRegTest1Implementation
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96 IMPORT ulRegTest1LoopCounter
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98 ; Fill each general purpose register with a known value.
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114 ; Fill each FPU register with a known value.
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149 ; Loop, checking each itteration that each register still contains the
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152 ; Yield to increase test coverage
\r
155 ; Check all the VFP registers still contain the values set above.
\r
156 ; First save registers that are clobbered by the test.
\r
161 bne reg1_error_loopf
\r
163 bne reg1_error_loopf
\r
166 bne reg1_error_loopf
\r
168 bne reg1_error_loopf
\r
171 bne reg1_error_loopf
\r
173 bne reg1_error_loopf
\r
176 bne reg1_error_loopf
\r
178 bne reg1_error_loopf
\r
181 bne reg1_error_loopf
\r
183 bne reg1_error_loopf
\r
186 bne reg1_error_loopf
\r
188 bne reg1_error_loopf
\r
191 bne reg1_error_loopf
\r
193 bne reg1_error_loopf
\r
196 bne reg1_error_loopf
\r
198 bne reg1_error_loopf
\r
201 bne reg1_error_loopf
\r
203 bne reg1_error_loopf
\r
206 bne reg1_error_loopf
\r
208 bne reg1_error_loopf
\r
211 bne reg1_error_loopf
\r
213 bne reg1_error_loopf
\r
216 bne reg1_error_loopf
\r
218 bne reg1_error_loopf
\r
221 bne reg1_error_loopf
\r
223 bne reg1_error_loopf
\r
226 bne reg1_error_loopf
\r
228 bne reg1_error_loopf
\r
231 bne reg1_error_loopf
\r
233 bne reg1_error_loopf
\r
236 bne reg1_error_loopf
\r
238 bne reg1_error_loopf
\r
242 bne reg1_error_loopf
\r
244 bne reg1_error_loopf
\r
247 bne reg1_error_loopf
\r
249 bne reg1_error_loopf
\r
252 bne reg1_error_loopf
\r
254 bne reg1_error_loopf
\r
257 bne reg1_error_loopf
\r
259 bne reg1_error_loopf
\r
262 bne reg1_error_loopf
\r
264 bne reg1_error_loopf
\r
267 bne reg1_error_loopf
\r
269 bne reg1_error_loopf
\r
272 bne reg1_error_loopf
\r
274 bne reg1_error_loopf
\r
277 bne reg1_error_loopf
\r
279 bne reg1_error_loopf
\r
282 bne reg1_error_loopf
\r
284 bne reg1_error_loopf
\r
287 bne reg1_error_loopf
\r
289 bne reg1_error_loopf
\r
292 bne reg1_error_loopf
\r
294 bne reg1_error_loopf
\r
297 bne reg1_error_loopf
\r
299 bne reg1_error_loopf
\r
302 bne reg1_error_loopf
\r
304 bne reg1_error_loopf
\r
307 bne reg1_error_loopf
\r
309 bne reg1_error_loopf
\r
312 bne reg1_error_loopf
\r
314 bne reg1_error_loopf
\r
317 bne reg1_error_loopf
\r
319 bne reg1_error_loopf
\r
321 ; Restore the registers that were clobbered by the test.
\r
324 ; VFP register test passed. Jump to the core register test.
\r
328 ; If this line is hit then a VFP register value was found to be
\r
334 ; Test each general purpose register to check that it still contains the
\r
335 ; expected known value, jumping to reg1_error_loop if any register contains
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336 ; an unexpected value.
\r
338 bne reg1_error_loop
\r
340 bne reg1_error_loop
\r
342 bne reg1_error_loop
\r
344 bne reg1_error_loop
\r
346 bne reg1_error_loop
\r
348 bne reg1_error_loop
\r
350 bne reg1_error_loop
\r
352 bne reg1_error_loop
\r
354 bne reg1_error_loop
\r
356 bne reg1_error_loop
\r
358 bne reg1_error_loop
\r
360 bne reg1_error_loop
\r
362 bne reg1_error_loop
\r
364 bne reg1_error_loop
\r
366 ; Everything passed, increment the loop counter.
\r
368 ldr r0, =ulRegTest1LoopCounter
\r
378 ; If this line is hit then there was an error in a core register value.
\r
379 ; The loop ensures the loop counter stops incrementing.
\r
383 ;/*-----------------------------------------------------------*/
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385 vRegTest2Implementation
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388 IMPORT ulRegTest2LoopCounter
\r
390 ; Put a known value in each register.
\r
391 mov r0, #0xFF000000
\r
392 mov r1, #0x11000000
\r
393 mov r2, #0x22000000
\r
394 mov r3, #0x33000000
\r
395 mov r4, #0x44000000
\r
396 mov r5, #0x55000000
\r
397 mov r6, #0x66000000
\r
398 mov r7, #0x77000000
\r
399 mov r8, #0x88000000
\r
400 mov r9, #0x99000000
\r
401 mov r10, #0xAA000000
\r
402 mov r11, #0xBB000000
\r
403 mov r12, #0xCC000000
\r
404 mov r14, #0xEE000000
\r
406 ; Likewise the floating point registers
\r
441 ; Loop, checking each itteration that each register still contains the
\r
444 ; Check all the VFP registers still contain the values set above.
\r
445 ; First save registers that are clobbered by the test.
\r
449 cmp r0, #0xFF000000
\r
450 bne reg2_error_loopf
\r
451 cmp r1, #0x11000000
\r
452 bne reg2_error_loopf
\r
454 cmp r0, #0x22000000
\r
455 bne reg2_error_loopf
\r
456 cmp r1, #0x33000000
\r
457 bne reg2_error_loopf
\r
459 cmp r0, #0x44000000
\r
460 bne reg2_error_loopf
\r
461 cmp r1, #0x55000000
\r
462 bne reg2_error_loopf
\r
464 cmp r0, #0x66000000
\r
465 bne reg2_error_loopf
\r
466 cmp r1, #0x77000000
\r
467 bne reg2_error_loopf
\r
469 cmp r0, #0x88000000
\r
470 bne reg2_error_loopf
\r
471 cmp r1, #0x99000000
\r
472 bne reg2_error_loopf
\r
474 cmp r0, #0xAA000000
\r
475 bne reg2_error_loopf
\r
476 cmp r1, #0xBB000000
\r
477 bne reg2_error_loopf
\r
479 cmp r0, #0xFF000000
\r
480 bne reg2_error_loopf
\r
481 cmp r1, #0x11000000
\r
482 bne reg2_error_loopf
\r
484 cmp r0, #0x22000000
\r
485 bne reg2_error_loopf
\r
486 cmp r1, #0x33000000
\r
487 bne reg2_error_loopf
\r
489 cmp r0, #0x44000000
\r
490 bne reg2_error_loopf
\r
491 cmp r1, #0x55000000
\r
492 bne reg2_error_loopf
\r
494 cmp r0, #0x66000000
\r
495 bne reg2_error_loopf
\r
496 cmp r1, #0x77000000
\r
497 bne reg2_error_loopf
\r
499 cmp r0, #0x88000000
\r
500 bne reg2_error_loopf
\r
501 cmp r1, #0x99000000
\r
502 bne reg2_error_loopf
\r
504 cmp r0, #0xAA000000
\r
505 bne reg2_error_loopf
\r
506 cmp r1, #0xBB000000
\r
507 bne reg2_error_loopf
\r
509 cmp r0, #0xFF000000
\r
510 bne reg2_error_loopf
\r
511 cmp r1, #0x11000000
\r
512 bne reg2_error_loopf
\r
514 cmp r0, #0x22000000
\r
515 bne reg2_error_loopf
\r
516 cmp r1, #0x33000000
\r
517 bne reg2_error_loopf
\r
519 cmp r0, #0x44000000
\r
520 bne reg2_error_loopf
\r
521 cmp r1, #0x55000000
\r
522 bne reg2_error_loopf
\r
524 cmp r0, #0x66000000
\r
525 bne reg2_error_loopf
\r
526 cmp r1, #0x77000000
\r
527 bne reg2_error_loopf
\r
530 cmp r0, #0xFF000000
\r
531 bne reg2_error_loopf
\r
532 cmp r1, #0x11000000
\r
533 bne reg2_error_loopf
\r
535 cmp r0, #0x22000000
\r
536 bne reg2_error_loopf
\r
537 cmp r1, #0x33000000
\r
538 bne reg2_error_loopf
\r
540 cmp r0, #0x44000000
\r
541 bne reg2_error_loopf
\r
542 cmp r1, #0x55000000
\r
543 bne reg2_error_loopf
\r
545 cmp r0, #0x66000000
\r
546 bne reg2_error_loopf
\r
547 cmp r1, #0x77000000
\r
548 bne reg2_error_loopf
\r
550 cmp r0, #0x88000000
\r
551 bne reg2_error_loopf
\r
552 cmp r1, #0x99000000
\r
553 bne reg2_error_loopf
\r
555 cmp r0, #0xAA000000
\r
556 bne reg2_error_loopf
\r
557 cmp r1, #0xBB000000
\r
558 bne reg2_error_loopf
\r
560 cmp r0, #0xFF000000
\r
561 bne reg2_error_loopf
\r
562 cmp r1, #0x11000000
\r
563 bne reg2_error_loopf
\r
565 cmp r0, #0x22000000
\r
566 bne reg2_error_loopf
\r
567 cmp r1, #0x33000000
\r
568 bne reg2_error_loopf
\r
570 cmp r0, #0x44000000
\r
571 bne reg2_error_loopf
\r
572 cmp r1, #0x55000000
\r
573 bne reg2_error_loopf
\r
575 cmp r0, #0x66000000
\r
576 bne reg2_error_loopf
\r
577 cmp r1, #0x77000000
\r
578 bne reg2_error_loopf
\r
580 cmp r0, #0x88000000
\r
581 bne reg2_error_loopf
\r
582 cmp r1, #0x99000000
\r
583 bne reg2_error_loopf
\r
585 cmp r0, #0xAA000000
\r
586 bne reg2_error_loopf
\r
587 cmp r1, #0xBB000000
\r
588 bne reg2_error_loopf
\r
590 cmp r0, #0xFF000000
\r
591 bne reg2_error_loopf
\r
592 cmp r1, #0x11000000
\r
593 bne reg2_error_loopf
\r
595 cmp r0, #0x22000000
\r
596 bne reg2_error_loopf
\r
597 cmp r1, #0x33000000
\r
598 bne reg2_error_loopf
\r
600 cmp r0, #0x44000000
\r
601 bne reg2_error_loopf
\r
602 cmp r1, #0x55000000
\r
603 bne reg2_error_loopf
\r
605 cmp r0, #0x66000000
\r
606 bne reg2_error_loopf
\r
607 cmp r1, #0x77000000
\r
608 bne reg2_error_loopf
\r
610 ; Restore the registers that were clobbered by the test.
\r
613 ; VFP register test passed. Jump to the core register test.
\r
617 ; If this line is hit then a VFP register value was found to be
\r
623 cmp r0, #0xFF000000
\r
624 bne reg2_error_loop
\r
625 cmp r1, #0x11000000
\r
626 bne reg2_error_loop
\r
627 cmp r2, #0x22000000
\r
628 bne reg2_error_loop
\r
629 cmp r3, #0x33000000
\r
630 bne reg2_error_loop
\r
631 cmp r4, #0x44000000
\r
632 bne reg2_error_loop
\r
633 cmp r5, #0x55000000
\r
634 bne reg2_error_loop
\r
635 cmp r6, #0x66000000
\r
636 bne reg2_error_loop
\r
637 cmp r7, #0x77000000
\r
638 bne reg2_error_loop
\r
639 cmp r8, #0x88000000
\r
640 bne reg2_error_loop
\r
641 cmp r9, #0x99000000
\r
642 bne reg2_error_loop
\r
643 cmp r10, #0xAA000000
\r
644 bne reg2_error_loop
\r
645 cmp r11, #0xBB000000
\r
646 bne reg2_error_loop
\r
647 cmp r12, #0xCC000000
\r
648 bne reg2_error_loop
\r
649 cmp r14, #0xEE000000
\r
650 bne reg2_error_loop
\r
652 ; Everything passed, increment the loop counter.
\r
654 ldr r0, =ulRegTest2LoopCounter
\r
664 ; If this line is hit then there was an error in a core register value.
\r
665 ; The loop ensures the loop counter stops incrementing.
\r